vampire edl

Tunnel FET or Ferroelectric FET to
achieve a sub-60mV/decade switch
Adrian M. Ionescu, Kathy Boucart
Ecole Polytechnique Fédérale Lausanne
Switzerland
http://nanolab.epfl.ch/
Outline
• Power challenge in nanoelectronics
• Principles for small swing switches
• Tunnel FETs
–
–
–
–
Principle
State-of-the-art: experiments and simulations
Challenges and technology boosters
Sensitivity to technology parameters
• Negative capacitance FETs
– Principle
– Progress in the field
• Conclusions
2
The power challenge
• Power per chip continues increasing.
• Leakage power dominates in advanced technology nodes.
• VT scaling saturated by 60mV/dec physical limit.
• Voltage scaling slowed (90nm:1.2V, 45nm: 1V, 22nm: 0.8V)
Not really
achieved
T. Sakurai, IEICE Trans. Electron., Vol.E87-C, April 2004, pp. 429-436.
3
Drain Current, I DS (A/µ m)
Power challenge due to
kT/q=60mV/dec limit at RT
-3
10
Lower
t
VV
T
-5
10
Incompressible
60mV/dec swing
@RT
-7
10
-9
10
Reducing threshold voltage
by 60mV
increases the leakage
current (power)
by ~10 times
Source: Intel Corporation
Ioff
-11
10
0.0
0.3
0.6
0.9
Gate Voltage, VGS (V)
−
Vt
Id (Vg = 0) = Id (Vg = Vt)e Vs
See also: C. Hu @ INC 2009, UCLA.
4
Why 60mV/dec limit?
• carrier injection by lowering the barrier
• subthreshold current is a diffusion current
Ion
Ioff
dVg
Cdep Css
kT
SS =
= ln 10
(1 +
+
)
d (log10 I d )
q
Cox Cox
kT
→
ln 10 = 60mV / decade @ RT
q
R. Van Overstraeten,G.J. Declerck, P.A. Muls,
IEEE Transactions on Electron Devices, Volume 22,
pp. 282–288, May 1975.
5
Power challenge: rescue strategies
• new softwarehardware techniques
from system to circuit
level dedicated to
power savings
• the identification of
novel power aware or
energy efficient device
architectures: small
swing switches
6
Parallelism to the rescue
CMOS has a fundamental lower
limit in energy per operation due
to subthreshold leakage
Edynamic + Eleakage =
αLdCVdd2 + LdIoffVddtdelay
Parallelism (multi-core) is a key
technique to improve system
performance under a power budget
Source: T.J. King, UC Berkeley.
7
Strategy for digital switches
• Goal
Vdd=0.2V Leakage power reduced by 100
• How?
– Channel engineering to reduce the Vdd-Vt (Ge, III-V,
graphene, etc).
– Nanowire and nanotube FETs for improved electrostatic
(subthreshold leakage) control.
– Operate circuits at low (cryogenic) temperatures.
– Reduce the threshold voltage by achieving a small
swing switch: novel devices.
8
55nm CMOS to beat
Numbers to beat:
Ionn/Ionp = 780/400 µA/µm
Ioff = 3nA/µm
Ion/Ioff = 2.6 x 105 @ 1.2V
NEC @ VLSI 2006
9
Nanowires to the rescue
• NW MOSFET: better electrostatic control, lower Ioff
• L~0.35µm, NW diameter ~30nm
• Ion/Ioff <106, S ~ 62–75 mV/dec and low DIBL (20mV/V)
• Ioff savings compared to bulk CMOS is ~10 times
• Current per NW: ~1µ
µA arrays needed!
W. W. Fang et al, IEEE Electron Device Letts.,
Vol. 28, March 2007.
10
The quasi-ideal switch
ID (log)
Ion
Ioff
• Quasi-ideal binary
switch, what matters:
Quasi-ideal:
SS ~ 0
Ioff ~ 0
VT~0, VDD
0
VG
- 2 stable states (off, on)
- Ion: as high as possible
- Ioff: as low as possible
- Ion/Ioff > 105
- abrupt swing (mV/decade)
- very fast (<ns)
A quasi-ideal nanoelectronic switch has ZERO standby power
and offers all wanted on current. It should be very fast.
11
ID (log)
Sub-kT/q subthreshold slope switch
to the rescue
ideal
Ion
MOSFET Switch:
SS~60mV/dec @ RT
Ioff
Small Swing Switch
VG
• MOSFET is a vampire switch at nanoscale
• New Small Swing Switch = New physics
• SSS: low standby power switch
12
Principles for SS < 60mV/decade
∂Vg
∂Vg
∂ψ S
Cs kT
S=
=
= (1 +
)
ln 10
∂ (log I d ) ∂ψ S ∂ (log I D )
Cins q
{ 1424
3
m
n
m less than 1
n less than (kT/q)ln10
• NEM relay or FET
• positive feedback gate
material (Fe-FET)
• Other ideas?
• Tunnel FETs
• Impact Ionization
• Other ideas?
13
Tunnel FETs
14
Tunnel FET: principle (1)
G
OFF-state
ON-state
S
D
• Vd = positive
n+
i
p+
• Vg = 0
• no current • gated pin junction
• reversed biased, BTBT
flows
1.5
p+
0.5
-0.5
i
n+
-1.5
-2.5
Energy [eV]
Energy [eV]
1.5
• Vd = positive
• Vg = positive
• barrier thin,
current flows
p+
0.5
e-
-0.5
i
n+
-1.5
-2.5
0
0.1
0.2
Location [um]
0
0.1
0.2
Location [um]
15
Tunnel FET: principle (2)
• Barrier control: key for Tunnel FET operation
All-silicon DG Tunnel FET
• gate dielectric
(thickness,
permittivity)
• silicon film thickness
(UTB, NW)
• bandgap
• fringing fields (gate
alignment to the
junction)
16
Tunnel FET: principle (3)
B
I = AVeff ξ ⋅ exp(− )
ξ
VGS2
S=
2VGS + BKane E g3 / 2 / D
S
VGS →0
S = (d log I d / dVgs ) −1
1 dVeff ξ + B d ξ −1
= ln10(
+ 2
)
Veff dVgs
ξ dVgs
• S is gate bias dependent:
lower@ lower VGS
• BKane depends on effective mass
• D depends on tox, L, Vds, dopings
→0
Point swing < 60mV/dec / ln10 = 26mV/dec @ RT
What about average swing?
17
First experimental demonstration:
40mV/dec in CNT Tunnel FETs
• dissipative quantum transport
simulations of CNT FETs using the
non-equilibrium Green’s function
(NEGF) formalism.
M. Lundstrom
On-current: ~1µA/tube
J. Appenzeller, J. Knoch, Phys.
Rev. Lett. 93, (2004).
18
UC Berkeley: experimental
53mV/dec silicon Tunnel FETs
• Ion=12µ
µA/µ
µm, Ioff=5.4nA/µ
µm
• S small in a very limited range
• large drain-to-gate leakage
• Ion/Ioff less than for MOSFET
IEEE EDL 2007, UC Berkeley.
19
MIT staggered heterojunction Tunnel
FETs
• Tunneling Field-Effect Transistors using Strained Silicon/StrainedGermanium Type-II staggered heterojunctions
O. M. Nayfeh et al, IEEE EDL, Vol. 29, Sept. 2008
20
Heterojunction Tunnel FETs: staggered
versus broken band line-up
• High on state
performance
predicted
• minimal S value in
the case of staggered
band line-up
staggered
broken
J. Knoch, Proc. 2009 Internat. Symp. VLSI-TSA, 45 (2009).
21
Stanford: Experimental
Ion=300µA/µm in Ge Tunnel FET
DG TFET with strained
Ge heterostructure
channel:
• high drive currents
(Ion~300uA/um) for Vd=3V
• But the low SS~50mV/dec,
due to small bandgap of sGe and DG electrostatics
and Ioff are for Vd=0.5V.
T. Krishnamohan et al, IEDM 2008.
22
IMEC’s Ge/SiGe-source vertical
Tunnel FET
• Smaller bandgap improved
tunneling but Ioff high
A. Verhulst, Node workshop,
Zurich, 2009.
23
LETI’s experimental Tunnel FETs
GeOI versus SOI Tunnel FETs
F. Mayer et al, IEDM 2008.
24
IBM bottom-up NW Tunnel FETs
VLS grown Si NWs tunnel FETs with different gate stacks (SiO2 and
HfO2); the use of a high-k gate dielectric markedly improves the TFET
performance in terms of average slope and on-current.
Ion~0.3uA/um, Ion/Ioff ~105
K. Moselund et al, ESSDERC 2009.
25
20nm Tunnel FET versus CMOS
Q. Zhang, A. Seabaugh, DRC 2008.
• Solution: heterostructure
transistor
• What about all-silicon Tunnel
FET?
26
Simulation: all-Si Double Gate Tunnel
FET with high-k dielectric
Vg
gate
Vd
Vs
insulator
n+ Si
i Si
p+ Si
insulator
gate
K. Boucart and A.M. Ionescu, IEEE TED 2007.
27
Sub-1V all-silicon Tunnel FET
• Additive technology boosters
Ion~1mA/µ
µm
Ion/Ioff > 1010
Drain current (A/µm)
A) Single gate SOI,
L=100nm, 3nm SiO2
B) stress = 4 GPa
at source junction
C) high-K gate dielectric
D) double gate
E) oxide aligned to
i-region
F) L=30nm
-3
10
-5
10
-7
10
-9
10
-11
10
-13
10
-15
10
-17
10
-19
10
0.0
VD=1V
A
B
C
D
E
F
0.2
0.4
0.6
0.8
1.0
Gate voltage (V)
K. Boucart, W. Riess, A.M. Ionescu, ESSDERC 2009.
28
1V all-silicon asymmetrically
strained Tunnel FET
Boosters
A+B+C+D
•
•
•
•
Avg SS ~ 50mV/dec
Point SS ~15mV/dec
VD=VG=1V
Very low VTD
VTG reduced from 1.5 V
-> 0.5 V
K. Boucart, A.M. Ionescu, IEEE EDL, April 2009.
29
Silicon Tunnel FET: energy
performance comparison
Energy (J)
• For high-performance applications requiring Ion > 100uA/um, TFET
has a larger average subthreshold slope S value and hence would
consume more energy than a MOSFET: Savg very important.
• TFET seems better in energy efficiency for applications <1GHz.
• TFET variability should be addressed.
H. Kam, T.-J. King-Liu, E. Alon, M. Horowitz, IEDM 2008.
30
Energy and performance: Tunnel
FETs versus FinFET & PD SOI
D.J. Frank, IBM, Node Workshop, Zurich, 2009.
31
Negative capacitance FET
32
Negative capacitance FET (NC-FET)
•
step-up voltage
transformer that could
amplify the gate voltage,
thus leading to values of
S lower than 60mV/dec
possible in ferroelectric
gate-stack FET
(Sallahudin & Datta)
Possible to find such insulator and stabilize it?
33
Ferroelectric gate stack NC-FET
• Simulation with ferroelectric in the negative capacitance
region; the subthreshold swing improves significantly,
which unexpected from a typical high-k dielectric.
S. Salahuddin, S. Datta, IEDM 2008.
34
Organic ferroelectric gate stack FET
200
-10
10
13mV/dec
-Source Current,-Is [A]
-9
10
-11
10
-12
10
-13
10
60
mV
/de
c
-8
10
160
120
60mV/dec
limit
80
40
-14
10
SS(mV/dec)
-15
10
0.75
Subthreshold Swing, SS (mV/dec)
• 40nm PVDF / 10nm
SiO2 gate stack FET
shows atypically low SS
@ low currents.
• Due to stabilized
negative capacitance?
More experimental
proof needed. Artifact
of leakage?
-7
10
1.00
1.25
1.50
Gate Voltage, Vg [V]
1.75
G. Salvatore, A.M. Ionescu, IEDM 2008.
35
PVDF gate stack on SOI MOSFET
36
Unique SS(T) in PVDF Fe-FET
500
450
400
temperature:
25°C, step=5°C
350
5
300
250
65°C
200
-1
-0.8
-0.6
-0.4
-0.2
0
Gate voltage, Vg (V)
G. Salvatore et al, ESSDERC 2009.
0.2
∂Vg
∂ (log I d )
=
∂Vg
∂ψ S
=
∂ψ S ∂ (log10 I D )
{ 14243
m
= (1 +
Subthreshold Swing, SS [mV/dec]
Subthreshold swing, dVg/dlog(Id)SS
(mV/decade)
• In Fe-FETs subthreshold swing
appears to decrease with T, in
contrast with traditional MOSFET
SS =
n
Cs
k T
) B ln 10
CoxC Ferro
q
Cox + C Ferro
Cs (T) = Cs
C ox (T) = C ox
C Ferro =
1
1
α (T − T0 ) d
320
2
Y=4628-26T+0.039T
300
Smin?
280
260
240
300
320
340
Temperature, T [°K]
360
37
Conclusions
Main challenges
ly
l
a
nt d
e
im trate
r
pe ns
x
E mo
Tunnel FET
e
d
(non-hysteretic)
• improve Ion
• tunnel junction engineering
• implementation on silicon platforms
r
tr he l
fu nta
s
ed rime
e
N pe
Fe-FET
x
f
e oo
(hysteretic?)
pr
• experimental proof of concept
• identification of most suited gate
stack materials
• Full theory to be developed
38
Acknowledgements
•
•
•
•
•
•
•
Kathy Boucart, Nanolab (Tunnel FET)
Giovanni Salvatore, Nanolab (Fe-FET)
Donato Acquaviva, Nanolab (MEM Diode)
Daniel Grogg, Nanolab (Movable body FET)
Didier Bouvet, Nanolab (Si processing)
Dimitrios Tsamados, Nanolab (SG-FET)
Staff of CMI-EPFL
39