Future of Logic Nano CMOS Technology

Transcription

September 22th, 2014
ESSDERC Tutorial
Venice - Italy
Future of Logic Nano CMOS
Technology
Hiroshi Iwai
Frontier Research Center, Tokyo Institute of Technology
1
Outline
1. Brief history of logic device technology
2. Importance of downsizing
3. Current status of Si-CMOS device technologies
4. Major problems for downsizing
5. Increase of leakage current when downsizing
6. Degradation of on-current when downsizing
7.Emerging technologies
8.Sumamry and conclusions
Acknowledgement
Appendices
2
1. Brief history of logic
device technology
3
1900 “Electronics” started.
4
Electronic Circuits started by the
invention of vacuum tube
(Triode) in 1906
Thermal electrons from cathode
controlled by grid bias
Lee De Forest
Cathode
(heated)
Grid
Anode
(Positive bias)
Same mechanism as that of transistor
1900 “Electronics” started.
Device: Vacuum tube
Device feature size: 10 cm
Major Appl.: Amplifier (Radio, TV, Wireless etc.)
Technology Revolution
because there had been no electronics before
(Vacuum tube new device, new application)
6
First Computer Eniac: made of huge number of vacuum tubes 1946
Big size, huge power, short life time filament
 dreamed of replacing vacuum tube with solid-state device
Today's smart phone
made of semiconductor
has much higher
performance with
extremely low power
consumption
7
1960: First MOSFET
by D. Kahng and M. Atalla
Surface
Source
G
Gate electrode
Gate Oxd
Channel
Drain
S
D
Electron flow
Top View
Al
SiO2
Si
Si/SiO2 Interface is
extraordinarily good
8
1970 “Micro-Electronics” started.
9
1970,71: 1st generation of LSIs (Si-MOSFETs)
1k bit DRAM Intel 1103
MPU Intel 4004
(Clock 750 KHz)
10
1970 “Micro-Electronics” started.
Device: Si MOS integrated circuits
Device feature size: 10 mm
Major Appl.: Digital (Computer, PC, etc.)
Technology Revolution
because there had been no micro-electronics before
(MOS IC new device, new application)
11
2000 “Nano-Electronics” started.
12
180 nm
Intel Pentium 4 : Clock 1 ~ 2 GHz
13
Device: Still, Si CMOS integrated circuits
Device feature size: 180 nm
Major Appl.: Digital (m-processor, cell phone, etc.)
Technology Revolution??
Maybe, just evolution or innovation!
(MOS IC, the same device, similar application)
But very important so many innovations
by reducing the size!
Downsizing increases performance and
decreases the cost and power consumption.
14
Now, 2014 “Nano-Electronics” continued.
Device: Still, Si CMOS integrated circuits
Device feature size: a few 10 nm
Major Appl.: Still Digital (m-processor, cell phone, etc.)
Still evolution and innovation are going on.
Broadwell SoC (Intel)
http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf
15
Downsizing of the components has been
the driving force for circuit evolution
1900
1950
Vacuum
Tube
Transistor
1960
1970
2000
2014
IC
LSI
VLSI
VLSI
10 cm
cm
mm
10 mm
100 nm 14 nm
10-1m
10-2m
10-3m
10-5m
10-7m
10-8m
In 100 years, the size reduced by one million times.
There have been many devices from stone age.
We have never experienced such a tremendous
16
reduction of devices in human history.
Feature Size / Technology Node
(1970) 10 μm  8 μm  6 μm  4 μm  3 μm  2 μm  1.2 μm
0.8 μm  0.5 μm  0.35 μm  0.25 μm  180 nm  130 nm 
90 nm  65 nm  45 nm  32 nm  (28 nm ) 22 nm(2012)
 14 nm (2014)
From 1970 to 2013 (Last year)
43 years
1 generation
18 generations
Line width: 1/450
Area: 1/200,000
2.5 years
Line width: 1/1.43 = 0.70
Area: 1/2 = 0.5
17
2. Importance of downsizing
18
Downsizing
Important for
- Decreasing cost,
and power consumption
- Increasing performance
This is true still for today’s 14 nm !
19
Merit for downsizing to 14 nm
(Intel case)
http://download.intel.com/newsroom/kits/14nm/pdfs/
Intel_14nm_New_uArch.pdf
Merit for cost, power consumption,
and performance
20
In 2012
Most Recent SD Card
128GB (Bite)
= 128G X 8bit
= 1T(Tera)bit
1T = 1012 = １Trillion
World Population：7 Billion
Brain Cell：10～100 Billion
Stars in Galaxy：100 Billion
21
In 2014
Most Recent SD Card
256GB (Bite)
= 256G X 8bit
= 2T(Tera)bit
2T = 1012 = 2Trillion
World Population：7 Billion
Brain Cell：10～100 Billion
Stars in Galaxy：100 Billion
22
128 GB = 1Tbit
2.4cm X 3.2cm X 0.21cm
Volume：1. 6cm³
Weight：2g
Voltage：2.7 - 3.6V
Old Vacuum Tube：
5cm X 5cm X 10cm, 100g, 50W
What are volume, weight, power
consumption for 1Tbit
23
1Tbit = 10,000 X 10,000 X 10,000 bit
Old Vacuum Tube：
5cm X 5cm X 10cm Volume = (5cm X 10,000) X (5cm X 10,000)
X (10cm X 10,000)
= 0.5km X 0.5km X 1km
Pingan Intenational Indian Tower
Finance Center Mumbai, India
Shanghai, China (Year 2016)
(Year 2016)
Burji Khalifa
Dubai, UAE
(Year 2010)
500 m
1,000 m
828 m
700 m
700 m
1Tbit
24
Old Vacuum Tube：
50W/tube (assuming)
1Tbit = 1012bit
Power = 0.05kWX1012=50 TW
Nuclear Power Generator
1MkW=1BW
We need 50,000 Nuclear Power Plant for
just one 128 GB memory
In Japan we have only 54
Nuclear Power Generator
Tokyo Electric Power Company
(TEPCO) can supply only
55BW.
We need 1000 TEPCO just one
128 GB memory
Imagine how many memories
25
are used in the world!
So progress of integrated
circuits by downsizing is
extremely important for
power saving.
26
Various semiconductor devices
Brain is very important
Brain: Integrated Circuits
Ear, Eye：Sensor
Mouth：RF/Opto device
Stomach：PV device
Hands, Legs：Power device
27
Near future smart-society has to treat huge
data.
Demand to high-performance and low power
CMOS become much more stronger.
28
3. Current status of Si-CMOS
device technologies
29
More Moore to More More Moore
Technology node
65nm
45nm
Lg 35nm
Now
32nm
22nm
Future
14nm 10nm, 7nm, 5nm, 3.5nm
Lg 30nm
Main stream
(Fin,Tri, Nanowire)
Si
Planar
Tri-Gate
Si channel
Alternative
(FDSOI)
FD: Fully Depleted
Si is still main stream for future !!
M. Bohr, pp.1, IEDM2011 (Intel)
P. Packan, pp.659, IEDM2009 (Intel)
C. Auth et al., pp.131, VLSI2012 (Intel)
T. B. Hook, pp.115, IEDM2011 (IBM)
S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)
Others
Alternative (III-V/Ge)
Channel FinFET
Emerging
Devices
30
High-k gate dielectrics
Hf-based oxides
45nm
32nm
EOT:1nm EOT:0.95nm
22nm
14nm
EOT:0.9nm EOT:0.?nm
10nm, 7nm, 5nm, 3.5nm,
SiO2 IL (Interfacial Layer)
is used at Si interface to Technology for direct contact of
high-k and Si is necessary
realize good mobility
TiN
EOT=0.9nm
HfO2/SiO2
(IBM)
EOT=0.52 nm
Remote SiO2-IL
scavenging
HfO2 (IBM)
HfO2
SiO2
Si
Continued research
and development
K. Mistry, et al., p.247, IEDM 2007, (Intel)
T.C. Chen, et al., p.8, VLSI 2009, (IBM)
T. Ando, et al., p.423, IEDM2009, (IBM)
T. Kawanago, et al., T-ED, vol. 59, no.
2, p. 269, 2012 (Tokyo Tech.)
K. Kakushima, et al., p.8, IWDTF 2008,
(Tokyo Tech.)
MG
EOT=0.37nm
EOT=0.40nm
EOT=0.48nm
La-silicate
Si
0.48 → 0.37nm Increase of Id at 30%
31
Direct contact with La-silicate (Tokyo.Tech)
High-k is very important, however
very difficult.
Thickness (EOT) decreased only
0.05 nm (or 0.5 Å, or 1 atom
layer) for every generation.
32
Benchmark of device characteristics
Structure
Lg (nm)
Intel
(IEDM2007, 2009)
Intel
(VLSI2012)
Toshiba
(VLSI2012)
IBM
(IEDM2012)
Samsung
(IEDM2012)
IBM
(IEDM2009)
STMicro.
(VLSI2008)
Tokyo Tech
(ESSDERC2010)
Bulk Planar
Tri-Gate NW
ETSOI
Bulk Planar
GAA NW
GAA NW
-gate NW
45nm
32nm
Tri-Gate
22nm
35
30
30
14
22
20
35/25
(nFET/pFET)
22/30
(nFET/pFET)
65
Hf-based
SiO2
HfO2
HfO2 ?
Hf-based
HfZrO2
SiO2
Gate
Dielectrics
Hf-based
EOT (nm)
1
0.95
0.9
3
~1
-
1.5
-
3
Vth (V)
~0.4
~0.3
~0.2
-0.15 (nFET)
0.3~0.4
~0.3
0.3~0.4
~0.5
-0.2 (nFET)
VDD (V)
1
1
0.8
1
0.9
0.9
1
1.1
1
ION (mA/um)
nFET/pFET
1.36/1.07
1.53/1.23
1.26/1.1
0.83 (nFET)
0.59/0.62 (Ieff)
1.2/1.05
0.83/0.95
2.05/1.5
1.32 (nFET)
DIBL
(mV/V)
nFET/pFET
~150
~200
46/50
<50
-
104/115
65/105
56/9
62
SS
(mV/dec)
-
~100
~70
<80
-
87
85
<80
70
33
ION and IOFF benchmark until 2012
NMOS Supply
10000
10000
Intel [1]
Intel [2]
Intel [1]
Bulk 32nm Tri-Gate 22nm Bulk 45nm
VDD=1V
VDD=0.8V VDD=0.8V
Samsung [3]
Bulk 20nm
VDD=0.9V
IBM [10]
ETSOI
VDD=0.9V
Ieff
Toshiba [4]
Tri-Gate NW
VDD=1V
10
IBM [5]
GAA NW
VDD=1V
1000
Tokyo Tech. [9]
-gate NW
VDD=1V
IBM [7]
ETSOI
IBM [7] VDD=1V
ETSOI
IBM [6] VDD=0.9V
FinFET 25nm
STMicro. [8]
VDD=1V
GAA NW
STMicro. [8]
VDD=1.1V
GAA NW
IOFF [nA/mm]
IOFF [nA/mm]
1000
100
voltage affects significantly!
100
Intel [1]
Bulk 32nm
VDD=0.8V
Samsung [3]
Bulk 20nm
VDD=0.9V
0.8
1
1.2
1.4
1.6
ION [mA/mm]
1.8
2
2.2
IBM [7]
ETSOI
VDD=1V
IBM [6]
FinFET 25nm
VDD=1V
STMicro. [8]
GAA NW
IBM [5]
VDD=1.1V
GAA NW
VDD=1V
10
1
0.6
Intel [2]
Intel [1]
Bulk 45nm Tri-Gate 22nm
VDD=1V
VDD=0.8V
IBM [10] IBM [7]
ETSOI
ETSOI
VDD=0.9V VDD=0.9V
Ieff
VDD=0.9V
1
PMOS
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5 1.6
ION [mA/mm]
[1] C. Auth et al., pp.131, VLSI2012 (Intel).
[6] T. Yamashita et al., pp.14, VLSI2011 (IBM).
[2] K. Mistry et al., pp.247, IEDM2007 (Intel).
[7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
[3] H.-J. Cho et al., pp.350, IEDM2011 (Samsung). [8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).
[4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).
[9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
[5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM). [10] K. Cheng et al., pp.419, IEDM2012 (IBM)
34
ION and IOFF benchmark updating
Lower supply voltage degrades the ratio.
NMOS
PMOS
10000
10000
ST [2]
ETSOI 14nm
VDD=0.75V
ST [2]
ETSOI 14nm
VDD=0.75V
Intel [1]
Tri-Gate 22nm
VDD=0.8V
1000
Tokyo Tech. [9]
-gate NW
VDD=1V
IBM [3]
GAA NW
VDD=1V
IBM [7]
ETSOI
IBM [7] VDD=1V
ETSOI
IBM [6] VDD=0.9V
FinFET 25nm
STMicro. [8]
VDD=1V
GAA NW
STMicro. [8]
VDD=1.1V
GAA NW
VDD=0.9V
100
10
Toshiba [4]
Tri-Gate NW
VDD=1V
IOFF [nA/mm]
IOFF [nA/mm]
1000
IBM [7]
ETSOI
VDD=0.9V
0.6
0.8
1
1.2
1.4
1.6
ION [mA/mm]
1.8
2
2.2
IBM [7]
ETSOI
VDD=1V
100
IBM [6]
FinFET 25nm
VDD=1V
STMicro. [8]
GAA NW
IBM [5]
VDD=1.1V
GAA NW
VDD=1V
10
1
1
Intel [1]
Tri-Gate 22nm
VDD=0.8V
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5 1.6
ION [mA/mm]
[6] T. Yamashita et al., pp.14, VLSI2011 (IBM).
[2] Q. Liu et al., pp.228, IEDM2013 (ST).
[7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
[3] S. Bangsaruntip et al., pp.526, IEDM2013 (IBM). [8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).
[4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).
[9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
[5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM).
35
Examples of the state of the art
Current status of Si-CMOS device
technologies
Fin, Tri gate FET
36
Multi-gate structures
G
Tri-gate
Tri-gate
(Variation)
G
G
G
G
G
Fin
-gate
All-around
37
How far can we go for production?
Rather than Ioff value, Ion/Ioff ratio is
important.
Now, Ion/Ioff ratio is typically 106.
However, it degrades significantly
with decrease in Vsupply.
38
ION and IOFF benchmark
NMOS
Intel [a]
Intel [b]
Intel [a]
Bulk 32nm Tri-Gate 22nm Bulk 45nm
VDD=1V
VDD=0.8V VDD=0.8V
Samsung [c]
Bulk 20nm
VDD=0.9V
IBM [j]
ETSOI
VDD=0.9V
Ieff
Toshiba [d]
Tri-Gate NW
VDD=1V
10
IBM [5]
GAA NW
VDD=1V
1000
Tokyo Tech. [i]
-gate NW
VDD=1V
IBM [g]
ETSOI
IBM [g] VDD=1V
ETSOI
IBM [g] VDD=0.9V
FinFET 25nm
STMicro. [h]
VDD=1V
GAA NW
STMicro. [h]
VDD=1.1V
GAA NW
IOFF [nA/mm]
IOFF [nA/mm]
1000
100
PMOS
10000
10000
100
Intel [a]
Bulk 32nm
VDD=0.8V
IBM [j]
IBM [g]
ETSOI
ETSOI
VDD=0.9V VDD=0.9V
Ieff
Samsung [c]
Bulk 20nm
VDD=0.9V
10
1
0.6
0.8
1
1.2
1.4
1.6
ION [mA/mm]
1.8
2
2.2
IBM [g]
ETSOI
VDD=1V
IBM [f]
FinFET 25nm
VDD=1V
STMicro. [h]
GAA NW
IBM [e]
VDD=1.1V
GAA NW
VDD=1V
VDD=0.9V
1
Intel [b]
Intel [a]
Bulk 45nm Tri-Gate 22nm
VDD=1V
VDD=0.8V
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5 1.6
ION [mA/mm]
[a] C. Auth et al., pp.131, VLSI2012 (Intel).
[f] T. Yamashita et al., pp.14, VLSI2011 (IBM).
[b] K. Mistry et al., pp.247, IEDM2007 (Intel).
[g] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
[c] H.-J. Cho et al., pp.350, IEDM2011 (Samsung). [h] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).
[d] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).
[i] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
[e] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM). [j] K. Cheng et al., pp.419, IEDM2012 (IBM)
39
22 nm Tri-gate (Intel)
HP
MP
SP
TOX,E (nm)
0.9
0.9
0.9
LGATE (nm)
30
34
34
20-100
5-20
1-5
IOFF (nA/um)
Tri-gate has been implemented
since 22nm node, enabling
further scaling
40
22 nmTri-gate (Intel)
Intel’s fin is triangle shape!
PMOS channel
under the gate
S/D region showing
the SiGe epitaxy
A fin width of 8nm to balance SCE and Rext
A fin height of 34nm to balance
drive current vs. capacitance
41
22 nmTri-gate (Intel)
C.-H. Jan et al ., pp.44, IEDM2012 (Intel)
Very good Vth control!
・SS of 71 and 72 mV/dec for HP NMOS and PMOS, respectively
・DIBL of 30 and 35 mV/V for NMOS and PMOS, respectively
・Vth of 22 nm is about 0.1 ~0.2 V lower than that of 32nm
42
Low Vccmin16nm node FinFETs (TSMC)
S. Wu et al., pp.224, IEDM2013 (TSMC)
 Fin patterning and formation on bulk
with 48 nm fin pitch (pitch-splitting
technique)
 Poly-silicon deposition and gate
patterning with (gate pitch of 90 nm)
 High-k/Metal gate RPG process
 Raised source/drain with dual epitaxy
Static noise margin of 0.07 um2 high
density SRAM cell at 0.8 V and 0.6 V
Low leakage (SVt : purple)
- Lg = 34 nm
- SS < 65 mV/dec.
- DIBL < 30 mV/V
- Idsat = 520/525 uA/um at 0.75 V
- Ioff = 30 pA/um
43
Advanced RMG for 14 nm FinFETs (GF)
M. Togo et al., pp.112, VLSI2014 (GF)





Dummy gate removal
STI oxide extra recess
WF adjust treatment
W selective etch
Contact formation with
SAC
* No information about Lgate
 STI oxide extra recess during replacement
metal gate (RMG) module increases Ion
 W selective etch improves AC
performance and gate-contact short yield
 Combination of novel work function adjust
treatment and WFM provides Vt turning
44
Intel 14nm Technology by Mark Bohr, August 11. 2014
http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf
Interconnects
SRAM Cell
45
10 nm FinFETs with Multi WF Gate Stack (IBM)
K. –I. Seo et al., pp.12, VLSI2014 (IBM)
DIBL ~ 40 - 50 mV for N/PFET for Lg =
20 nm
=> Controlled short channel effect
I-V performance
 Lg = 20 nm
 SS = 70 mV/dec
SRAM performance
 SNM = 140 mV at 0.75V
 SNM = 120 mV at 0.55 V
46
Si-CMOS device technologies
FD SOI FET
47
Dual STI for Multi-Vt at 20 nm Node (CEA-LETI)
L. Grenouillet et al., pp.64, IEDM2012 (CEA-LETI)
 Wider back bias (BB)
tunability with dual STI
(shallow & deep)
 Successive performance
boost and leakage current
control by BB
48
Extremely Thin SOI (ETSOI) (IBM)
K. Cheng et al., pp.419, IEDM2012 (IBM)
Also, ET-SOI works very good!
・Hybrid CMOS
Si Channel nFET
Strained SiGe Channel pFET
・RO delay improvement over
FinFET with FO = 2
49
Material Selection and RSD for 14 nm FDSOI (ST)
Q. Liu et al., pp.228, IEDM2013 (STMicroelectronics)
nMOS => Si channel/SiC RSD
pMOS => SiGe channel/SiGe RSD
50
14 nm FDSOI Technology (STMicroelectronics)
O. Weber et al., pp.14, VLSI2014 (STMicroelectronics)
New Front-End process elements
 Dual SOI/SiGeOI N/P channel
 Dual workfunction gate-first HKMG
integration scheme
 Dual in-situ doped Si:CP/SiGeB N/P
RSD
 30% speed boost at the same power
 55% power reduction at the same speed
51
Silicon-on-Thin-Buried Oxide CMOS (LEAP)
S. Kamohara et al., pp.154, VLSI2014 (LEAP)
 Very small Vth and Ion variability was
demonstrated for one million transistors.
 High performance due to less S/D doping
and back bias controlling.
 Confirmed 6-T SRAM operation (2 Mbit) at
less than 0.4 V with a 5.5-ps access time.
 Demonstrated that the minimum operating
voltage can be controlled at <0.4 V by
back-bias against temperature variation.
52
Strain Engineered Extremely Thin SOI (IBM)
A. Khakifirooz et al., pp.117, VLSI2012 (IBM)
nFET - Strained SOI (SSDOI)
pFET – SiGe-on-insulator (SGOI)
t ~ 6 nm
Channel
53
technologies
Nanowire FET
54
G
Tri-gate
Tri-gate
(Variation)
G
G
G
G
G
Fin
-gate
All-around
55
Gate All Around Nanowire (GAA NW) (IBM)
・Lg = 25~35nm GAA NW
・Hydrogen anneal provide
smooth channel surface
・Competitive with conventional
CMOS technologies
・Scaling the dimensions of NW
leads to suppressed SCE
56
Gate All Around Nanowire (GAA NW)
G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics)
NiPtSi
SiN
HM
Top
Gate
Channel
Bottom
Gate
・Gate all around structure
・Lg of 22~30nm
・Bulk wafer-based integration
・High drive currents by special stress
and channel orientation design
57
Back gate control Tri-Gate Nanowire
S. Saitoh et al., pp.11, VLSI2012 (Toshiba)
・Lg = 14nm Tri-Gate NW
・High SCE immunity at Lg of 14nm
Vsub
・Vth tuning by applying Vsub with
thin BOX of 20nm
Vth control by
back-gate bias
58
-gate Si Nanowire (TIT)
S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
-3
1.E-03
Poly-Si
SiO2
12 nm
NW
SiN
SiN
19 nm
SiO2
Drain Current (A)
10
Lg=65nm
Vd=-1V
-4
1.E-04
10
Vd=1V
-5
1.E-05
10
-6
1.E-06
10
Vd=-50mV
-7
1.E-07
10
pFET
-8
1.E-08
10
Vd=50mV
nFET
1.E-09
-9
10
-10
1.E-10
10
-11
1.E-11
10
-12
1.E-12
10
-1.5 -1.0 -0.5 0.0 0.5 1.0
Gate Voltage (V)
・Conventional CMOS process
・High drive current
(1.32 mA/mm @ IOFF=117 nA/mm)
Lg=65nm
0
0.5
1
1.5
ION (mA/mm)
2
・DIBL of 62mV/V and SS of 70mV/dec
59
for nFET
technologies
Planar Bulk FET
60
Low Power Planar 20 nm CMOS Bulk (IBM)
H. Shang et al., pp.129, VLSI2012 (IBM)
NFET













PFET
Isolation (wells, Vt)
IO EG gate growth
Dummy gate patterning
Logic SG, IO, SRAM extension/halo
Spacer dep/patterning
eSiGe formation
Raised source/drain formation
Advanced gate stack formation
Tungsten stud (TS) contact formation
CA/CB Tungsten contacts
M1 double patterning
Self Aligned V0
BEOL





Lgate = 20 nm
0.55X density scaling
N/P DIBL = 121/126 mV
SS = 90/86 mV/dec.
SNM = 160mV at 0.9V
61
Process technologies for
State of the art CMOS
Appendix 1
62
4. Major problems for downsizing
63
1. Lithography of sub-10 nm pattern
- Delay in EUV development.
- Process step increase for double, triple, quadruple
patterning as alternate
2. Increase of leakage current
3. Decrease of on-current
4. Interconnect problems
- Increase of R and C
Explained in
this tutorial
5. Variability, reliability, yield.
64
5. Increase of leakage current
when downsizing
65
Leakage components
1. Punch through current between S and D
2. Subthreshold current between S and D
3. Direct-tunneling current between S and D
4. Gate leakage current between G and S/B/D
66
1. Punch-through between S and D
Region governed
by gate bias
Region governed DL touch with S
Region (DL)
0V By drain bias
Gate metal
0V
Source
Gate oxide
0V
1V
Drain
0V
Vdd
1V
Large IOFF
No tox. Vdd 0V
thinning
0V < Vdep＜1V
Channel
0V < Vdep＜1V
Large IOFF
(Electron current)
Substrate 0V
Depletion
Region (DL)
by Drain Bias
0V
0V
0V
Vdd
0.5V
0V
tox and Vdd have to be decreased for better channel
potential control  IOFF Suppression
67
1. Punch-through between S and D
There are 3 solutions to suppress the depletion layer
A. Decrease supply voltage  Very difficult
as explained later
B. Decrease tox to enhance the channel potential
controllability by gate bias
C. Gate/channel configuration change to enhance
the channel potential controllability by gate bias
Also, decrease tSi
68
Fin-FET, ET-SOI, etc.
B.Decrease tox
A. Toriumi (Tokyo Univ), IEDM 2006, Short Course
tox (
(
69
C. Configuration change for channel and
gate structures for better control of
channel potential.
Also, decrease tSi
Fin-FET, ET-SOI, etc.
70
Extremely Thin (or Fully-Depleted) SOI
- Make Si layer thin (decrease tSi)
- Control channel potential also from the bottom
0V
0V
0V
1V
G
0V
S
S
0V ＜V＜1V
0V
G
Drain bias
induced
depletion
1V Extremely
thin Si
0V
D
SiO2
Si
G
0V
Planar
ET (or FD) SOI
71
Surrounding gate structure (Multiple gates)
- Make Si layer thin(decrease tSi)
- Control channel potential also by multiple gates
not only from top & bottom but maybe also
from side
0V
0V
0V
1V
G
S
S
G
0V
Drain bias
induced
depletion
1V
0V
Si fin or
nanowire
D
0V ＜V＜1V
G
0V
0V
Planar
Multi gate
72
G
Tri-gate
Tri-gate
(Variation)
G
G
G
G
G
Fin
-gate
All-around
73
Multi-gate MOSFETs have advantage
not only suppressing Ioff, but also for
increasing Ion over planer MOSFETs
1. Because of higher mobility due to
lower vertical electric field and low
dopant concentration in the channel
2. Because of higher carrier density at
the round corner
74
75
Electron Density
電子濃度(x1019cm-3)
6.E+19
6
角の部分
5.E+19
Edge portion
5
4
4.E+19
平らな部分
Flat portion
3
3.E+19
2
2.E+19
1
1.E+19
0
0.E+00
0
2
4
6
8
Distance from SiNW Surface (nm)
76
2. Direct-tunneling between S and D
Wave function of electron penetrates the
channel potential barriers by quantum
mechanical physics, when the channel length
is around 3 nm.
77
When transistor is at off state
Tunneling
distance
3 nm
Energy or Potential
for Electron
Built-in potential
between Source
and Channel pn
junction < 0.7 V
Direct-tunnel
current
Channel
Source
Drain
There is no solutions!
Downsizing limit is @ Lg 3 nm.
78
3.Subtheshold leakage current of MOSFET
Id
Ion
Subthreshould
Leakage Current
OFF
ON
Vg
Vg=0V
Subthreshold
region
Vth
(Threshold Voltage)
79
Subthreshold leakage current
Id (A/mm)
Ion
Electron Energy
Boltzmann statics
10-5
Exp (qV/kT)
Vd
10-7
Ioff
0.5 V
1.0 V
Vth
10-9
0.15 V 0.3 V
Lg  1/2
Vd, Vg  1/2
Vth  1/2
However
Ioff  103 in this example
10-11
0
0.5
Vg (V)
1
Because of
log-linear dependence
80
Subtheshold leakage current of MOSFET
Id
Subthreshold Current
Is OK at Single Tr. level
Ion
OFF
Subthreshould
Leakage Current
ON
But not OK
For Billions of Trs.
Vg
Vg=0V
Subthreshold
region
Vth
(Threshold Voltage)
81
Solution: however very difficult
Keep Vth as high as possible
- Do not decrease supply voltage, Vd
 However, punchthough enhanced
- Suppress variability in Vth
Thus, subthreshold current will limit the
downsizing, especially for mobile devices
82
4. Gate leakage current
Probably OK using high-k, until EOT=0.4 nm
See Appendix 2
Gate Leakage current
1.E+04
ITRS requirement
Jg at 1 V (A/cm2)
1.E+03
1.E+02
1.E+01
1.E+00
La silicate
Gate dielectrics
1.E-01
1.E-02
0.3
0.4
0.5
0.6
0.7
EOT (nm)
H. Iwai, SBMicro 2013
0.8
83
Our Work at TIT: High-k
Our result at TIT
EOT=0.40nm
Electron Mobility [cm2/Vsec]
L/W = 5/20mm
Vg= 1.0V
0.8
T = 300K
Vg= 0.8V
0.6
Nsub = 3×1016cm-3
0.4
Vg= 0.6V
Vg= 0.4V
0.2
Drain Current (mA)
1.0
140
Vg= 0.2V
120
100
80
EOT = 0.40nm
60
L/W = 5/20mm
40
T = 300K
Nsub = 3×1016cm-3
20
0
Vg= 0 V
0
0.2
0.4
0.6
Drain Voltage (V)
0.8
0
1.0
0.5
1
1.5
Eeff [MV/cm]
2
2.5
84
All the 4 leakage components increase, when downsizing
1. Punch through current between S and D
Solution: Enhance gate bias control to channel potential
 Decrease tox (EOT) for gate oxide, and tSi for SOI & Fin FETs
Solution: Keep as high Vth as possible
 Keep as high Vsupply as possible, but difficult
 This will limit the downsizing depending on application
before Lg = ~ 3 nm
3. Direct-tunneling current between S and D
No solution. Limit the downsizing at Lg = ~ 3 nm
4. Gate leakage current between G and S/B/D
Solution. Introduction of new material for higher k and band offset
85
The limit is deferent depending on application
100
Operation Frequency (a.u.)
e)
10
1
Subthreshold Leakage (A/mm)
Source: 2007 ITRS Winter Public Conf.
86
How far can we go for production?
Past
10mm  8mm  6mm  4mm  3mm  2mm  1.2mm  0.8mm  0.5mm 
0.35mm  0.25mm  180nm  130nm  90nm  65nm  45nm  32nm
Limit depending
on applications
Now
Future
Subthreshold
punchthrough
Fundamental
limit
Direct-tunnel
(28nm)  22nm  14nm  10 nm  7nm  5nm?  3.5nm?  2.5 nm? 
Intermediate
node
87
However, careful about the commercial name of technology!
Recently,
Gate length (Lg) is much larger than the Technology name
22 nm Technology by Intel
Lg (Gate length) = 30 nm (HP), 34 nm (MP), 34 nm or larger (SP)
IEDM 2012, VLSI 2013
14 nm Technology by Global
Lg (Gate length) = 25 nm
Euro SOI 2014
10 nm Technology by Leti (FD-SOI)
Lg (Gate length) = 15 nm
ECS Fall 2013
88
ITRS 2013 (Just published in April 2014)
Year 2013
Year 2027
Commercial name (nm)
X 0.70 / 2 years
14 (nm)
1.3 (nm)
Metal half pitch (nm)
X 0.80 / 2 years
40 (nm)
8 (nm)
Lg (nm)
X 0.83 / 2 years
20.2 (nm)
5.6 (nm)
Vdd (V)
X 0.96 / 2 years
0.86 (nm)
0.65 (nm)
EOT (nm)
X 0.91 / 2 years
0.80 (nm)
0.43 (nm)
TSi (nm)
X 0.84 / 2 years
7.4 (nm)
2.0 (nm)
Only the commercial names decreases X0.7/ 2 years
Difference between the commercial name and
physical parameters becomes larger
1.3 nm technology!
but HP = 8nm
Lg = 5.6 nm
Recently, companies become not to disclose Lg values at conferences
89
ITRS 2013 (Just published in April 2014)
Year
2013
2015
2017
2019
2021
14
10
7
5
3.5
2.5
1.8
1.3
Metal half pitch (HP) (nm)
40
32
25.3
20
15.9
12.6
10
8
20.2
(13)
16.8
(10)
14.0
(8)
11.7
(6)
9.7
8.1
6.7
(5) (4.5 in 2022)
5.6
19
16
13.3
11.1
6.4
Lg (nm)
(Lg for ITRS 2007)
Lg for low stand by power (nm) 23
2023 2025 2027
9.3
7.7
Vdd (V)
(Vdd (V) for ITRS 2007)
0.86 0.83 0.80 0.77 0.74 0.71 0.68 0.65
(0.90) (0.80) (0.70) (0.70) (0.65)(0.65 in 2022)
EOT (nm)
(EOT (nm) for ITRS 2007)
0.80 0.73 0.67 0.61 0.56 0.51 0.47 0.43
(0.60) (0.60) (0.55) (0.50) (0.50)(0.50 in 2022)
TSi (nm)
(TSi (nm) for ITRS 2007)
7.4
(6.0)
6.1
(6.0)
5.1
(4.5)
4.3
(3.8)
3.6
3.0
2.5
(3.2) (3.0 in 2022)
2.0
Before, HP: X 0.70 / 2 years, Lg: X 0.70 / 2 years
Now,
HP: X 0.80 / 2 years, Lg: X 0.83 / 2 years
 Thus, now more generations and more years until reaching limit
90
Shrink rate
Intel kept X ~0.7 for pitch
until 14 nm technology,
but it is not certain for future
SRAM area
Logic area
http://download.intel.com/newsroom/kits/1
4nm/pdfs/Intel_14nm_New_uArch.pdf
91
6. Degradation of on-current
when downsizing
92
When downsizing
1.Mobility degradation
2.Carrier density decrease
1, 2  decrease of on-current
93
m(mobility) degradation
d
Strong interaction between
carriers and Si surface (or interface)
d
tox
tSi
m
Strong interaction between
carriers and metal/oxide interface
d
m
tSi
Si
Si surface
d
SOI
tSi
Gate electrode
tox
d
Gate oxide
d
Si channel
Gate stack
Metal/
Oxide
interface
d
Si
d
d
d
d
tSi
d
d
d d
Si
Nano-wire
Fin / Tri 94
ITRS 2013
Year
EOT (nm)
TSi (nm)
2013
14
0.80
2015
10
0.73
2017
7
0.67
2019
5
0.61
2021
3.5
0.56
7.4
6.1
5.1
4.3
3.6
m
tox
tSi
2023 2025 2027
2.5
1.8
1.3
0.51 0.47 0.43
3.0
2.5
2.0
m
300
Mobility (cm2/Vsec)
at 1 MV/cm
250
200
150
100
50
Solid : La-silicate oxide
Open : Hf-based oxides
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
EOT (nm)
T. Kawanago, et al., (Tokyo Tech.) T-ED, 2012
L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng,. 2011.
T. Ando, et al., (IBM) IEDM 2009
K. Uchida et al., pp.47, IEDM2002 (Toshiba)
95
Carrier density decrease
ITRS 2013
Year
TSi (nm)
tSi
2013
14
2015
10
2017
7
2019
5
2021
3.5
7.4
6.1
5.1
4.3
3.6
Volume
DOS
Diameter 1 nm
2 nm
2023 2025 2027
2.5
1.8
1.3
3.0
2.5
2.0
Carrier density
3 nm
4 nm
6 nm
Si nanowire
band structure
Iwata et al., Journal of Computational Physics 229 (2010) 2339–2363
96
7. Emerging technologies
97
7.1 Alternative channel
technologies
98
Current status
Good research results aiming for low voltage
(= 0.5V) operation.
In general good mobility, but poor S-factor.
CMOS inverter results at primitive stage.
Production starting year predicted at 2018 by
ITRS 2011 and 13, but premature to be ready for
the today’s scale microprocessor production.
No or very few reports for circuits, large wafer,
yield, variability, reliability, production cost etc.
99
Device Structures in III-V
J. Lin, IEDM’12
S.H. Kim, IEDM’11
M. Radosavljevic,
IEDM’11
InAs QW MOSFET
III-V-OI MOSFET
Tri-gate
Recently various device structures have been demonstrated
on InGaAs platform for achieving higher performance at lower
power supply.
Improvement in high-k/III-V interface and III-V growth technology
100
has been a key factor.
Low Voltage CMOS
Source: S. Takagi
101
Multi-gate III-V and Si benchmark
nMOS
1.E-05
1.E-06
IOFF (A/mm)
InGaAs GAA, Lch=50nm, Dielectric: 10nm Al2O3
VDS=0.5V (Purdue Uni.)
J. J. Gu et al., pp.769, IEDM2011 (Purdue).
InGaAs Tri-gate, Lg=60 nm,EOT 12A
VDS=0.5V (Intel)
M. Radosavljevic et al., pp.765, IEDM201(Intel).
0.5V
VDS=0.5V
0.5V
Si-FinFET 32nm
Intel VDD=0.8V [1]
0.5V 0.5V
1.E-07
0.5V 0.5V
Si-FinFET 22nm
Intel VDD=0.8V [1]
0.5V
0.5V
1.E-08
0.5V
Si-bulk 45nm
Intel VDD=1V[2]
0.5V
1.E-09
0
0.4
0.8
1.2
ION (mA/mm)
[2] K. Mistry et al., pp.247,
IEDM2007 (Intel).
LP InGaAs QW MOSFET, Lch=100nm,
Dielectric: Al2O3 VDS=0.5V (IMEC)
X. Zhou, et al., (IMEC) VLSI2014, p.166.
InGaAs FinFET, Lch=130nm EOT 3.8nm
VDS=0.5V (NUS)
H. –C. Chin et al., EDL 32, 2 (2011) (NUS)
InGaAs Nanowire, Lg= 200nm, Tox 14.8nm
VDS=0.5V(Hokkaido Uni.)
K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
Metal S/D InGaAs-OI, Lch= 55nm, EOT 3.5nm
VDS=0.5V(Tokyo Uni.)
S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
InAs Surface channel MOSFET, Lch=130nm,
Dielectric: high-k VDS=0.5V (TSMC)
S. W. Chang, et al., (TSMC) IEDM2013, p.417.
InGaAs QW Tri-gate, Lch=60nm,
Dielectric: Al2O3/HfO2 VDS=0.5V (Sematech)
T. W. Kim, et al., (Sematech) IEDM2013, p.425.
In0.7Ga0.3As FinFET, Lch=120nm,
Dielectric: Al2O3/HfO2 VDS=0.5V (Penn State Uni.)
Arun VT, et al., (Penn State Uni.) VLSI2014, p.72.
Recessed Channel Ge nMOSFET, Lch=60nm,
Dielectric: Al2O3 VDS=0.5V (Purdue Uni.)
H. Wu, et al., (Purdue Uni.) VLSI2014, p.82.
Regrown S/D In0.7Ga0.3As, Lch=40nm,
102
C. –S. Shin, et al., (KANC, Sematch) VLSI2014, p.31.
Multi-gate III-V and Si benchmark(~2012)
1.E-05
IOFF (A/mm)
1.E-06
1.E-07
1.E-05
nMOS
InGaAs GAA
Lch=50nm, Dielectric: 10nm Al2O3
VDS=0.5V (Purdue Uni.) [1]
Si-FinFET 32nm
Intel VDD=0.8V [10]
Si-FinFET 22nm
Intel VDD=0.8V [10]
Ge FinFET
Si-FinFET 32nm
Lg=4.5 mm,
Dielectric: SiON, VDS=-1V Intel VDD=0.8V [10]
(Stanford Uni.)[7]
Si-FinFET 22nm
Intel VDD=0.8V [10]
1.E-07
Si-bulk 45nm
Intel VDD=1V[11]
Ge GAA Lg= 300nm,
dielectric: GeO2(7nm)-HfO2(10nm)
VD= -0.8V (ASTAR Singapore)[8]
InGaAs Nanowire
Lg= 200nm, Tox 14.8nm
VDS=0.5V(Hokkaido Uni.)[4]
1.E-08
GOI Tri-gate
Lg: 65nm. EOT 3.0nm
VD=-1V (AIST Tsukuba)[6]
1.E-06
InGaAs Tri-gate
Lg=60 nm,EOT 12A
VDS=0.5V (Intel) [2]
InGaAs FinFET
Lch=130nm
EOT 3.8nm
VDS=0.5V (NUS)[3]
pMOS
1.E-08
Metal S/D InGaAs-OI
Lch= 55nm, EOT 3.5nm
VDS=0.5V(Tokyo Uni.)[5]
Ge Tri-gate
Lg=183nm, EOT 5.5nm
VD=-1V (NNDL Taiwan)[9]
1.E-09
Si-bulk 45nm
Intel VDD=1V
1.E-09
0
0.4
0.8
ION (mA/mm)
[1] J. J. Gu et al., pp.769, IEDM2011 (Purdue).
[2] M. Radosavljevic et al., pp.765, IEDM201(Intel).
[3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS)
[4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
[5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
1.2
0
0.4
0.8
1.2
ION (mA/mm)
[6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba).
[7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni)
[8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore)
[9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)
IEDM2007 (Intel).
103
III-V/Ge benchmark for various structures
(2013 and 2014)
ETB InGaAs-OI
Tokyo Uni. 2013
Planar InAs
TSMC 2013
Tri-Gate InGaAs
SEMATECH 2013
QW FinFET InGaAs/InP
IMEC 2014
Regrown S/D In0.7Ga0.3As
SEMATECH 2014
FinFET InGaAs (In 70%)
Penn State Uni. 2014
Recessed channel Ge
Purdue Uni. 2014
QW MOSFET InGaAs
IMEC 2014
CMOS InGaAs-OI
GNC 2014
CMOS SGOI
GNC 2014
CMOS La2O3/GaAs nFET
Purdue Uni. 2014
CMOS La2O3/GaAs pFET
Purdue Uni. 2014
ION
DIBL
SS (mV/dec) Lch (nm) Dielectric/EOT Vdd (V)
(mA/μm)
(mV/V)
Al2O3
0.2
187
5μm
1
10nm
0.6
85
130
0.5
77
60
0.36
190
50
1
105
40
1.16
236
120
0.55
-
60
0.55
82
100
0.05
80
10μm
0.02
115
10μm
0.15
74
1μm
0.015
270
1μm
Al2O3/HfO2
0.7nm/1.6nm
HfO2/Al2O3
EOT=1.9nm
HfO2/Al2O3
3nm/0.7nm
HfO2/Al2O3
3nm/1nm
Al2O3
8nm
Al2O3
EOT=1.1nm
Al2O3
7.8nm
HfO2
4.5nm
La2O3/Al2O3
8nm/6nm
La2O3/Al2O3
8nm/6nm
Gm-max
Peak Mobility
(μS/μm)
(cm2/Vs)
1500
(VDS=0.5V)
2700
7100
(VDS=0.5V)
1500
760
(VDS=0.5V)
450
(VDS=0.5V)
2000
5500
(VDS=0.5V)
1900
3000
(VDS=0.5V)
600
(VDS=0.5V)
2000
(VDS=0.5V)
0.5
40
0.5
10
0.5
-
0.5
150
0.5
119
0.5
-
0.5
-
1
-
-
1200
-1
-
-
200
2
-
-
1150
-2
-
-
104
180
(2011 and 2012)
Planar
(metal S/D, Strain, Buffer…)
FinFET
material
InGaAs
Ge
InGaSn
InGaAs
Dieletric
/EOT
Al2O3/
3.5 nm
7.6 Ao
5nm ALD
5nm ALD
Al2O3
Al2O3
HfO2+
Al2O3+GeO2
Gate-all-around
MOSFET
Tri-gate
Ge
SiON
InGaAs
1.2 nm
Ge
InGaAs
5.5 nm
10nmALD
(Al2O3+
GeO2)
Ns: 5e12
Mobility
-
~600
(cm2/Vs)
e: 200
h: 400
(mS/mm)
(cm2/Vs)
~700
-
-
-
Al2O3
701
(mS/mm)
Ge
HfO2:
11nm
-
Nanowire
InGaAs
(multishell)
Ge
HfAlO
14.8 nm
(ALD Al2O3)
~500
~850
(mS/mm)
(cm2/Vs)
3.0 nm
Lch (nm)
55
W/L=
30/5 mm
50 mm
100
4.5 mm
60
183
50
200
200
65
DIBL
(mV/V)
84
-
-
180
-
~50
-
210
-
-
-
-
61pMOS
33nMOS
145
750
90
130
150
160
-
-
10
400
235
180
604
100
731
(VD=0.5V)
(VD=0.5V)
(VD=-1V)
(VD=0.5V)
(VD=-0.5V)
(VD=0.5V)
(VD=-1V)
Stanford
Uni ELD
2007
Intel
IEDM
2011
NNDL
Taiwan
Purdue
Uni IEDM
2011
ASTAR
Singapore
IEDM
2009
Hokkaido
AIST
Uni, IEDM 105
Tsukuba
2011
VLSI 2012
SS
(mV/dec)
150K
105
120K
ION
(mA/mm)
278
3
4 (n,p)
(VD=0.5V)
(VD=-0.2V)
(VD=0.5V)
Research
Group
Tokyo Uni
VLSI 2012
Tokyo Uni
VLSI 2012
Stanford
Uni VLSI
2012
Purdue
Uni IEDM
2009
IEDM 2011
7.2 T-FET technologies
(T: Tunnel)
106
Current status
Very small S-factor (21mV/dec) can be realized depending on the condition.
Very small Ion (on-current) at low Vd (~ 0.5 V) is a big problem.
High Ion can be obtained at high Vd (~ 1 V) , but s-factor was more than 60
mV/dec.
Current problems/concerns
Large variation of Vth is expected, because tunneling current is very
sensitive to the small change of the size and structure of the junction.
Trap assisted tunneling would decreases the range of small s-factor region
in Vg.
Change of Dit (Interface state density) and Qfix (fixed charge) during long
time operation would affect the characteristics  reliability concern.
Difficulty to realize idea structure in experiment, such as abrupt junction etc.
Expect improvement in future and more research reports.
107
Tunnel FET
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)
OFF
Vg = 0V
ON
Vg = 1V
Band to band tunneling
Low IOFF, Low VDD, SS<60mV/decade
108
Tunnel FET (III-V)
K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)
SS=21mV/dec
SS=110mV/dec
VDS=1V
HfAlOx
Gate
Conventional FET limit
SS= 60 mV/dec
VDS= 1V
NW Diameter= 30nm
SS of TFET is function of VG due to Zener tunnel current
Minimum SS= 21 mV/dec is reached due to optimized
series resistance of contact, undoped InAs and InAs/Si
ION/IOFF~106 at VDS= 1.0V (ION= 1Am/mm)
109
ION and IOFF of TFETs
A.M. Ionescu, IEDM2013 Short Course (EPFL)
Q. Liu et al., pp.228, IEDM2013 (ST).
Y. Morita et al., pp. 236, VLSI2013 (AIST)
Si, Ge TFET
Ion (mA/mm)
101
104
Leonelli 2011
Jeon 2011 Si Si, silicides S/D
Ghandi 2011
Si NW
Chang 2013 Si
100
Morita 2013 Si Fin
10-1
Moselund 2011
Si NW
Mayer 2008 Si
10-2
10-3
10-2
10-1
100
Villalon 2014
SiGe NW tri-gate
Knoll 2013
Knoll 2012
strained Si
strained Si
NW GAA
NW tri-gate
Q. Huang 2011 Si
Krishnamohan 2009 GOI
102
Ioff (pA/mm)
Zhou 2012 Dey 2012
Mohata 2012
InAs/GaSb GaSb/InAsSb
GaAsSb/InGaAs
102
101
100
Q. Huang 2012 Si
101
Zhou 2012
InGaAs/InP
104
Zhao 2011
InGaAs
Li 2012
AlGaSb/InAs
Mookerjea 2009 InGaAs
Moseiund (IBM)
2012 Si/InAs
Dewey (Intel) 2011 InGaAs
Tomioka 2012 Si/InAs
Schmid (IBM)
2011 Si/InAs
103
0.3 < VDS < 0.5 V
1.0 < VDS < 1.5 V
III-V TFET
Tri-gate 22nm node SOI 14nm node (Lg=20nm)
(Lg=30nm)
VDD=0.75V (ST)
VDD=0.8V (Intel)
103
SOI 14nm node (Lg=20nm) VDD=0.75V (ST)
Tri-gate 22nm node (Lg=30nm)
VDD=0.8V (Intel)
103
102
0.05 < VDS < 0.6 V
0.9 < VDS < 1.2 V
Ion (mA/mm)
104
L. Knoll et al., pp. 100, IEDM2013 (Jülich)
A. Villalon et al., pp. 66, VLSI2014 (CEA-LETI)
C. Auth et al., pp.131, VLSI2012 (Intel).
10-1
10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101
Ioff (mA/mm)
Si TFETs show the low Ioff, while Ion enhancement is still challenge.
Strain is efficient for Ion enhancement in Si and Ge TFETs.
III-V provide high Ion, however, suffer from unacceptably high Ioff.
110
Strained SiGe nanowire TFETs
Ion enhancement up to 760mA/mm.
Low bandgap of SiGe increase BTBT.
SS lower than 60 mV/dec is
still challenge to be addressed.
111
7.3 2D channel material
technologies
112
Why 2D channels?
 High-drivability FinFET
 Large Weff/Wfootprint
 Taller Fin
 Narrow Fin pitch
 Thinner Fin
K. Uchida, et. al., IEDM, 23.1, 2008.
 Mobility degradation in
thin Si < 10 nm for both
electron & hole.
High-mobility
2D channels
S. Kobayashi, et. al., J. Appl. Phys. 106, 024511 (2009).
113
Family of 2D materials
0
Vacuum
Graphene
family
Oxide
family
Energy [eV]
-1
-2
Graphene
-4
TiO2 RuO2
~ 5.9
1.1
-5
-7
WSe2
MoSe2
-3
-6
Transition metal
dichalcogenide (TMD)
family
MX2
M: Cr, Mo, W, etc.
X: S, Se, Te, etc.
1.6
~ 3 2.7
Silicene
Si
h-BN
1.8
1.2
1.6 0.4
1.4
MoTe2
MoS2
WTe2
WS2
114
Exfoliated single-layer MoS2 nMISFET
 217 cm2/Vs,
electron
 Depletion mode
B. Radisavljevic et al., Nature Nanotech. 6, 147 (2011)
115
7.4 Other emerging
technologies
116
Other Emerging technologies
Carbon-based FET
Carbon nanotube
Graphene
J. P. Colinge et al., Nature Nano. 5(2010)225
Junctionless Transistor
L. Liao, et al., Nature ,Vol.467 p.305.
A. D. Franklin et al., pp.525, IEDM2011 (IBM)
Cut-off frequency ( GHz)
GaAs mHEMT
(20nm)
SiMOSFET GaAs pHEMT
1000
(29nm)
(100nm)
100
All-spin logic device
CNT
Graphene
10
10
1000
100
Gate length (nm)
F. Schwlerz, Nature Nano ,Vol.5 p.487. M. Lemme, Nanotech workshop ,2012
Input and output related via
117
Spin-coherent channel
8. Summary and
conclusions
118
Summary and conclusions
Si-MOSFET is the main component nano-CMOS devices
and will be so in future.
While the shrink rate of commercial node name will keep
0.7 for 2 years, the shrink rates of HP, Lg, Vd, tox, tSi are
expected to be 0.80, 0.83. 0.96, 91 and 0.84, respectively,
according to ITRS. Because of many reasons, the rate of
physical shrinking will be smaller as the downsizing reach
near the limit.
Increase of the Ioff due to subthreshhold leakage and
degradation of Ion due to EOT and tSi reduction would limit
the gate length scaling before Lg reaches its limit of directtunneling (@ Lg = ~3nm).
119
Summary and conclusions (continued)
Problems and cost of the lithography and interconnects
would also limit the downsizing.
There have been good challenges for the emerging
technologies such as alternative channel, T-FET, 2D
material and others. However, none of those technologies
has yet reached the level for the industry to start R&D
assuming mass production, such as yield, variability,
reliability, large wafer production.
120
Acknowledgement
I would like to express appreciation to the following
people for the great support for preparing the
materials for the tutorial.
Slides for the 2D materials were made by Prof.
Hitoshi Wakabayashi, Tokyo Institute of Technology.
Many slides except for the 2D materials were made
by Dr. Takamasa Kawanago, Dr. Darius Zade, and
Mr. Tomoya Shoji of Tokyo Institute of Technology,
and Mr. Jing Neng Yao of National Chio Tung
University.
121
Appendices
122
Appendices
Appendix 1. Process technologies for state of the art CMOS
Appendix 2. Alternative channel technologies
Appendix 3. T-FET technologies
Appendix 4. 2D channel material technologies
Appendix 5. Other emerging technologies
123
Appendix1. Process technologies for
state of the art CMOS
- Source/Drain formation
- Strain
- Gate Stack
- Others
124
- Source/Drain formation
125
Analysis of Implantation to Fin (Panasonic)
T. Noda et al., pp.140, IEDM2013 (Panasonic)
Boron-Interstitial (BnIm)
Kinetic Monte Carlo (KMC) simulation
 Implant temperature has an impact on
amorphization
 Residual defects and dopant-defect
complexes are formed at top-of-Fin
and edge-of-Fin-side after Solid Phase
Epitaxial Regrowth (SPER)
126
Ion Assisted Deposition and Doping (IADD) (IMEC)
Y. Sasaki et al., pp.542, IEDM2013 (IMEC)
 Knock-in Doping Process => Reduce amorphization/damage to Fins
 Deposition layer thickness important
 A single As ion can provide about 6 knockedin As atoms for a 3keV 25 IADD process
 Sidewall doping by simultaneous deposition
and knock-in with small angle implant is the
key of the ION boost
127
Heated Implantation with a-C mask (IMEC)
M. Togo et al., pp.T196, VLSI2013 (IMEC)
 RT implantation (Upper)
 Forms amorphous layer
 Residue twin defects at the
corner after RTA
 Heated implantation (Lower)
 a-Carbon mask (for high temp.)
 No damage to fins after
implantation
a-C
128
Channel Doping to FinFETs for 22 nm (IBM)
C. -H. Lin et al., pp.15, VLSI2012 (IBM)
 Channel doping
 1018 cm-3
Retain a variability
advantage over
planar technology
129
In situ Doped Source Drain Epitaxy for GAA (IBM)
(e) NW formation (f) Gate formation (g) Spacer formation
(h) in situ doped (PH3) S/D epitaxy
Previous (S. Bangsaruntip et al.,
IEDM Tech. Dig., p.297,(2009))
60 nm pitch
LG ~ 15 nm
DNW 8.1 nm
 Dopants placed right next to the spacer
 Equal diffusion distance of dopants to both
the top and bottom of the NW
 Reduced variation
 ~30% enhanced performance
130
- Strain
131
Layout-Induced Stress Effects in FinFETs (IMEC)
Sxx (Mpa)
Mobility (cm2/Vs)
M. G. Bardon et al., pp.T114, VLSI2013 (IMEC)
Number of gate per fin
Sxx (Mpa)
 A strong degradation of the S/D stressors
efficiency in reduced fin length
 Compressive STI keeps the performance
variation
132
Through Silicon Via Induced Mechanical Stress (IMEC)
W. Guo et al., pp.431, IEDM2012 (IMEC)
Cu
4-point bending experiments
 Unlike planar device, the n-FinFET drive
current is also affected by mechanical
stress
 TSV build-in stress affect both n and p-
133
Epitaxial P-SiC Source/Drain Stressor (IMEC)
M. Togo et al., pp.423, IEDM2012 (IMEC)
 Epitaxial Phosphorus doped SiC S/D stressor
 Narrower Fins and SiGe epitaxial growth on the Fins
increase mobility
134
- Gate Stack
135
High-k/Metal Gate Stacks (IBM)
M. M. Frank et al., pp.213, ECS Transactions 2014 (IBM)
Remote oxygen scavenging
 SiO2 interfacial layer helps
optimize high-k/Si or highk/SiGe interface quality.
 Interfacial layer thickness
can be reduced by remote
oxygen scavenging.
136
Simple Gate Metal Anneal Stack (SIGMA) (IBM)
T. Ando et al., pp.44, VLSI2014 (IBM)
nFinFET
Positively charged oxygen
vacancies (Vo) are generated only
when TiN  Tcrit
Optimized
 Metal (TiN)
thickness
 WF-setting
annealing
 9nm more Lg scaling with matched gate resistance
 Aggressive Lg scaling toward the 14 nm node and beyond 137
Work Function Engineering (IMEC)
A. Veloso et al., pp.T194, VLSI2013 (IMEC)
 VT modulation and minimized (Rgate) using
ultra-thin TiN/TaN layers, grown for optimum
Al diffusion control properties on HfO2 and
CoxAly fill-metal
 >500mV VT enabled low-VT FinFET NMOS
with improved mobility, noise and reliability
138
EOT-Scaling with Cubic-phase HfO2 (IMEC)
L. Ragnarsson et al., pp.27, VLSI2012 (IMEC)
35
 Doped the HfO2 by alternating ALD cycles
of HfO2 and metal oxides (MOx)
 EOT-scaling by increasing k-value
 Reduced Jg by 2 to 3 orders of magnitude
at the cost of mobility reduction, however.
139
Low Resistance Co-Al Gate Fill for 20 nm node (IBM)
U. Kwon et al., pp.29, VLSI2012 (IBM)
Co-Al Gate Fill
(Al- Blue, Co-Pink)
Low resistance gate formation
at smaller than Lgate = 25 nm
140
Conduction band offset vs. Dielectric Constant
Oxide
SiO
2
Band
offset
Si
Band Discontinuity [eV]
Leakage Current by Tunneling
4
2
0
-2
-4
-6
0 10 20 30 40
Dielectric Constant
50
XPS measurement by Prof. T. Hattori, INFOS 2003
141
Direct high-k/Si by silicate reaction
HfO2 case
High PO2
Low PO2
VO
VO
VO
Our approach
La2O3 case
VO
HfO2
HfSix
Si substrate
IO
IO
IO
IO
SiO2-IL
(k~4)
High PO2
Low PO2
VO
VO
La2O3
VO
La-rich
LaSix
Si substrate
IO
IO
IO
silicate
Si-rich
SiO2-IL
(k~4)
Direct contact can be achieved with La2O3 by forming silicate at interface
Control of oxygen partial pressure is the key for processing.
PO2: Partial pressure of O2 during
high temperature annealing
142
K. Kakushima, et al., VLSI2010, p.69
SiOx-IL growth at HfO2/Si Interface
Intensity (a.u)
TEM image500 oC 30min
XPS Si1s spectrum
W
o
500 C
SiO2
HfO2k=16
Hf Silicate
Si sub.
SiOx-IL
1846
1843
1840
k=4
1837
Binding energy (eV)
1 nm
Phase separator
HfO2 + Si + O2 → HfO2 + Si + 2O*→HfO2+SiO2
H. Shimizu, JJAP, 44, pp. 6131
Oxygen supplied from W gate electrode
D.J.Lichtenwalner, Tans. ECS 11, 319
SiOx-IL is formed after annealing
Oxygen control is required for optimizing the reaction
143
La-Silicate Reaction at La2O3/Si
Direct contact high-k/Si is possible
XPS Si1s spectra
TEM image 500 oC, 30 min
as depo. La-silicate
W
Intensity (a.u)
Si sub.
La2O3
300 oC
k=23
La-silicate
k=8~14
500 oC
1 nm
1846
1843
1840
Binding energy (eV)
1837
La2O3 + Si + nO2
→ La2SiO5, La2Si2O7,
La9.33Si6O26, La10(SiO4)6O3, etc.
La2O3 can achieve direct contact of high-k/Si
144
Physical mechanisms for small Dit
① silicate-reaction-formed
fresh interface
metal
La2O3
Si Si
metal
② stress relaxation at interface
by glass type structure of La
silicate.
La atom
La-O-Si bonding
La-silicate
Si sub.
Si sub.
Fresh interface with
silicate reaction
J. S. Jur, et al., Appl. Phys. Lett.,
Vol. 87, No. 10, (2007) p. 102908
SiO4
tetrahedron
network
Si sub.
FGA800oC is necessary to
reduce the interfacial stress
145Lett.,
S. D. Kosowsky, et al., Appl. Phys.
Vol. 70, No. 23, (1997) pp. 3119
However, high-temperature anneal is necessary
for the good interfacial property
FGA500oC 30min
1.5
2
1
0.5
0
-1
-0.5
0
0.5
Gate Voltage [V]
1
1
10kHz
100kHz
1MHz
0.5
0
-1.5
-1
-0.5
0
Gate Voltage [V]
2
20 x 20mm
2
10kHz
100kHz
1MHz
2
1.5
2
2
20 x 20mm
Capacitance [mF/cm ]
2
20 x 20mm
FGA800oC 30min
2
FGA700oC 30min
0.5
1.5
10kHz
100kHz
1MHz
1
0.5
0
-1.5
-1
-0.5
0
Gate Voltage [V]
0.5
A fairly nice La-silicate/Si interface can be obtained
with high temperature annealing. (800oC) 146
Our Work at TIT: High-k
Our result at TIT
EOT=0.40nm
Electron Mobility [cm2/Vsec]
L/W = 5/20mm
Vg= 1.0V
0.8
T = 300K
Vg= 0.8V
0.6
Nsub = 3×1016cm-3
0.4
Vg= 0.6V
Vg= 0.4V
0.2
Drain Current (mA)
1.0
140
Vg= 0.2V
120
100
80
EOT = 0.40nm
60
L/W = 5/20mm
40
T = 300K
Nsub = 3×1016cm-3
20
0
Vg= 0 V
0
0.2
0.4
0.6
Drain Voltage (V)
0.8
0
1.0
0.5
1
1.5
Eeff [MV/cm]
2
2.5
147
Benchmark of La-silicate dielectrics
Effective Mobility
Gate Leakage current
1.E+04
300
at 1 MV/cm
ITRS requirement
250
Mobility (cm2/Vsec)
Jg at 1 V (A/cm2)
1.E+03
1.E+02
1.E+01
1.E+00
1.E-01
Our data: La-silicate gate oxide
1.E-02
Solid circle: Our data
La-silicate gate oxide
200
150
100
50
Open square : Hf-based oxides
0
0.3
0.4
0.5
0.6
0.7
0.8
EOT (nm)
0.3
0.4
0.5
0.6
0.7
0.8
0.9
EOT (nm)
L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng, vol. 88, no. 7, pp. 1317–1322, 2011.
T. Ando, et al., (IBM) IEDM 2009, p.423
148
1
Issues in high-k/metal gate stack
Oxygen concentration control
for prevention of EOT increase
and oxygen vacancy
formation in high-k
Suppression of gate
leakage current
Endurance for high
temperature process
Flat metal/high-k
interface for better
mobility
Suppression of
metal diffusion
Suppression of
oxygen vacancy
formation
Small interfacial state
density at high-k/Si
Control of interface reaction
and Si diffusion to high-k
149
Reliability: PBTI,
NBTI, TDDB
O
Metal
Oxygen diffusion control for
prevention of EOT increase
and oxygen vacancy
formation in high-k
Workfunction engineering for
Vth control
Suppression of FLP
High-k
SiO2-IL
Interface dipole control
for Vth tuning
Remove contamination
introduced by CVD
Si-sub.
Thinning or removal of
SiO2-IL for small EOT
- Others
150
Variability and Parameter Correlations in FinFETs (GF)
A. Paul et al., pp.361, IEDM2013 (GF)
Ieff variability is captured by the independent variations in Vtlin, Rext and Gm
Rext: External Resistance
Gmmax: Maximum
Transconductance
Vtlin: Threshold Voltage
Increase in Ieff variability
1X
NFins
12X
Effects on Ieff varitation
 Vtlin: more dominant in nFETs > pFETs
 Gm: Major contributor
=> Improve surface properties (e.g. H2 bake)
 Rext: Increases in larger Nfin
=> Improve S/D contacts
151
Self-Heating Effect in GAA-Si Nanowire FETs (ETH)
R. Rhyner and M. Luisier, pp.790, IEDM2013 (ETH)
The ballisticity, self-heating, and temperature profiles of ultra-scaled Si
NWFETs have been computed through coupled electro-thermal transport
simulation
Large temperature increase at
drain side => Current decrease
Energy (eV)
1.4
0.8
0
x (nm)
40
152
Self Heating in Dielectric Isolated Devices (IBM)
S. Lee et al., pp.T248, VLSI2013 (IBM)
Vgs = 0 to 1 V
Vgs = 0.4 to 1.1 V
Heat flow
 The time constant for self heating is
much longer than characteristic switching
times of CMOS logic and memory
 In special cases (e.g. analog I/O, ESD),
the same design practices as used with
planar devices can be applied
153
RTN in High-k/Metal Gate ETSOI (Hitachi)
H. Miki et al., pp.137, VLSI2012 (Hitachi)
 Cumulative Vt map of RTN Shows that
RTN in high-k/metal gate nFETs tends to
be capture limited at normal supply voltage
 Thermal barrier of capture/emission shows
little correlation to Vg coupling
154
Appendix 2
Alternative channel
technologies
155
Ge,III-V bulk properties
156
S. Takagi., IEDM2011, Short course (Tokyo Uni)
Low Voltage CMOS
Source: S. Takagi
157
ITRS 2011 for III-V/Ge
http://www.itrs.net/Links/2011ITRS/Home2011.htm
2018
Year of Production
Lg (nm)
Vdd (V)
EOT (nm)
Mobility enhancement
factor due to
channel material
III-V
Cg Ideal
(fF/mm)
III-V
Ge
Vt,sat (mV)
III-V
Ge
CV/I (ps)
158
Ge
III-V
Ge
14
0.63
0.68
8
4
0.28
0.41
229
230
0.13
0.21
2020
11.7
0.61
0.62
8
4
0.24
0.36
230
231
0.11
0.17
2022
9.3
0.58
0.56
8
4
0.20
0.30
238
241
0.09
0.13
Manufacturing solutions
are NOT known
2024
7.4
0.56
0.50
8
4
0.16
0.25
245
249
0.07
0.10
2026
5.8
0.54
0.45
8
4
0.13
0.21
251
254
0.06
0.08
ITRS 2011 for III-V/Ge,Contd
Year of Production
Lg (nm)
Equivalent
Injection velocity
Vinj (107 cm/s)
III-V
Id,sat
(mA/mm)
III-V
Ge
Ge
Isd,leak (nA/mm)
159
Rsd
(Ω-mm)
III-V
Ge
CV2
(fJ/mm)
III-V
Ge
2018
2020
2022
14
4.29
2.26
2.200
1.769
100
11.7
9.3
7.4
5.8
4.58 5.32 5.93 6.64
2.44 2.86 3.19 3.63
2.343 2.523 2.703 2.884
1.932 2.121 2.330 2.555
100
100 100
100
131
149
0.18
0.23
113
126
0.15
0.20
96
105
0.13
0.16
Manufacturing solutions
are NOT known
2024
82
85
0.11
0.14
2026
70
72
0.09
0.11
ITRS 2013 for HP logic technology III-V/Ge
Year of Production
Lg (nm)
Vdd (V)
EOT (nm)
Mobility enhancement
factor due to
channel material
III-V
Cg Ideal
(fF/mm)
III-V
Ge
Vt,sat (mV)
III-V
Ge
CV/I (ps)
Ge
III-V
Ge
2018
14
0.63
0.68
8
4
0.28
0.41
229
230
0.13
0.21
2020
11.7
0.61
0.62
8
4
0.24
0.36
230
231
0.11
0.17
2022
9.3
0.58
0.56
8
4
0.20
0.30
238
241
0.09
0.13
2024
7.4
0.56
0.50
8
4
0.16
0.25
245
249
0.07
0.10
2026
5.8
0.54
0.45
8
4
0.13
0.21
251
254
0.06
0.08
Manufacturing solutions Manufacturing solutions Manufacturing solutions
are NOT known
exists or being optimized
are known
160
ITRS 2013 for III-V/Ge
Year of Production
Lg (nm)
Equivalent
Injection velocity
Vinj (107 cm/s)
III-V
Id,sat
(mA/mm)
III-V
Ge
Ge
Isd,leak (nA/mm)
Rsd
(Ω-mm)
III-V
Ge
CV2
(fJ/mm)
III-V
Ge
2018
2020
2022
14
4.29
2.26
2.200
1.769
100
11.7
9.3
7.4
5.8
4.58 5.32 5.93 6.64
2.44 2.86 3.19 3.63
2.343 2.523 2.703 2.884
1.932 2.121 2.330 2.555
100
100 100
100
131
149
0.18
0.23
113
126
0.15
0.20
96
105
0.13
0.16
2024
82
85
0.11
0.14
2026
70
72
0.09
0.11
Manufacturing solutions Manufacturing solutions Manufacturing solutions
are NOT known
exists or being optimized
are known
In span of two years (compared to ITRS 2011)
significant improvements in alternative channel
device performance has been achieved and
161
(2013 and 2014)
ETB InGaAs-OI
Tokyo Uni. 2013
Planar InAs
TSMC 2013
Tri-Gate InGaAs
SEMATECH 2013
QW FinFET InGaAs/InP
IMEC 2014
Regrown S/D In0.7Ga0.3As
SEMATECH 2014
FinFET InGaAs (In 70%)
Penn State Uni. 2014
Recessed channel Ge
Purdue Uni. 2014
QW MOSFET InGaAs
IMEC 2014
CMOS InGaAs-OI
GNC 2014
CMOS SGOI
GNC 2014
CMOS La2O3/GaAs nFET
Purdue Uni. 2014
CMOS La2O3/GaAs pFET
Purdue Uni. 2014
ION
DIBL
SS (mV/dec) Lch (nm) Dielectric/EOT Vdd (V)
(mA/μm)
(mV/V)
Al2O3
0.2
187
5μm
1
10nm
0.6
85
130
0.5
77
60
0.36
190
50
1
105
40
1.16
236
120
0.55
-
60
0.55
82
100
0.05
80
10μm
0.02
115
10μm
0.15
74
1μm
0.015
270
1μm
Al2O3/HfO2
0.7nm/1.6nm
HfO2/Al2O3
EOT=1.9nm
HfO2/Al2O3
3nm/0.7nm
HfO2/Al2O3
3nm/1nm
Al2O3
8nm
Al2O3
EOT=1.1nm
Al2O3
7.8nm
HfO2
4.5nm
La2O3/Al2O3
8nm/6nm
La2O3/Al2O3
8nm/6nm
Gm-max
Peak Mobility
(μS/μm)
(cm2/Vs)
1500
(VDS=0.5V)
2700
7100
(VDS=0.5V)
1500
760
(VDS=0.5V)
450
(VDS=0.5V)
2000
5500
(VDS=0.5V)
1900
3000
(VDS=0.5V)
600
(VDS=0.5V)
2000
(VDS=0.5V)
0.5
40
0.5
10
0.5
-
0.5
150
0.5
119
0.5
-
0.5
-
1
-
-
1200
-1
-
-
200
2
-
-
1150
-2
-
-
162
180
(2011 and 2012)
Planar
(metal S/D, Strain, Buffer…)
FinFET
material
InGaAs
Ge
InGaSn
InGaAs
Dieletric
/EOT
Al2O3/
3.5 nm
7.6 Ao
5nm ALD
5nm ALD
Al2O3
Al2O3
HfO2+
Al2O3+GeO2
Gate-all-around
MOSFET
Tri-gate
Ge
SiON
InGaAs
1.2 nm
Ge
InGaAs
5.5 nm
10nmALD
(Al2O3+
GeO2)
Ns: 5e12
Mobility
-
~600
(cm2/Vs)
e: 200
h: 400
(mS/mm)
(cm2/Vs)
~700
-
-
-
Al2O3
701
(mS/mm)
Ge
HfO2:
11nm
-
Nanowire
InGaAs
(multishell)
Ge
HfAlO
14.8 nm
(ALD Al2O3)
~500
~850
(mS/mm)
(cm2/Vs)
3.0 nm
Lch (nm)
55
W/L=
30/5 mm
50 mm
100
4.5 mm
60
183
50
200
200
65
DIBL
(mV/V)
84
-
-
180
-
~50
-
210
-
-
-
-
61pMOS
33nMOS
145
750
90
130
150
160
-
-
10
400
235
180
604
100
731
(VD=0.5V)
(VD=0.5V)
(VD=-1V)
(VD=0.5V)
(VD=-0.5V)
(VD=0.5V)
(VD=-1V)
Stanford
Uni ELD
2007
Intel
IEDM
2011
NNDL
Taiwan
Purdue
Uni IEDM
2011
ASTAR
Singapore
IEDM
2009
Hokkaido
AIST
Uni, IEDM 163
Tsukuba
2011
VLSI 2012
SS
(mV/dec)
150K
105
120K
ION
(mA/mm)
278
3
4 (n,p)
(VD=0.5V)
(VD=-0.2V)
(VD=0.5V)
Research
Group
Tokyo Uni
VLSI 2012
Tokyo Uni
VLSI 2012
Stanford
Uni VLSI
2012
Purdue
Uni IEDM
2009
IEDM 2011
Multi-gate III-V and Si benchmark
nMOS
1.E-05
1.E-06
IOFF (A/mm)
InGaAs GAA, Lch=50nm, Dielectric: 10nm Al2O3
VDS=0.5V (Purdue Uni.)
J. J. Gu et al., pp.769, IEDM2011 (Purdue).
InGaAs Tri-gate, Lg=60 nm,EOT 12A
VDS=0.5V (Intel)
M. Radosavljevic et al., pp.765, IEDM201(Intel).
0.5V
VDS=0.5V
0.5V
Si-FinFET 32nm
Intel VDD=0.8V [1]
0.5V 0.5V
1.E-07
0.5V 0.5V
Si-FinFET 22nm
Intel VDD=0.8V [1]
0.5V
0.5V
1.E-08
0.5V
Si-bulk 45nm
Intel VDD=1V[2]
0.5V
1.E-09
0
0.4
0.8
1.2
ION (mA/mm)
IEDM2007 (Intel).
LP InGaAs QW MOSFET, Lch=100nm,
Dielectric: Al2O3 VDS=0.5V (IMEC)
InGaAs FinFET, Lch=130nm EOT 3.8nm
VDS=0.5V (NUS)
H. –C. Chin et al., EDL 32, 2 (2011) (NUS)
InGaAs Nanowire, Lg= 200nm, Tox 14.8nm
VDS=0.5V(Hokkaido Uni.)
K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
Metal S/D InGaAs-OI, Lch= 55nm, EOT 3.5nm
VDS=0.5V(Tokyo Uni.)
InAs Surface channel MOSFET, Lch=130nm,
Dielectric: high-k VDS=0.5V (TSMC)
InGaAs QW Tri-gate, Lch=60nm,
In0.7Ga0.3As FinFET, Lch=120nm,
Dielectric: Al2O3/HfO2 VDS=0.5V (Penn State Uni.)
Arun VT, et al., (Penn State Uni.) VLSI2014, p.72.
Recessed Channel Ge nMOSFET, Lch=60nm,
Dielectric: Al2O3 VDS=0.5V (Purdue Uni.)
Regrown S/D In0.7Ga0.3As, Lch=40nm,
164
C. –S. Shin, et al., (KANC, Sematch) VLSI2014, p.31.
Multi-gate III-V and Si benchmark(~2012)
1.E-05
IOFF (A/mm)
1.E-06
1.E-07
1.E-05
nMOS
InGaAs GAA
Lch=50nm, Dielectric: 10nm Al2O3
VDS=0.5V (Purdue Uni.) [1]
Si-FinFET 32nm
Intel VDD=0.8V [10]
Si-FinFET 22nm
Intel VDD=0.8V [10]
Ge FinFET
Si-FinFET 32nm
Lg=4.5 mm,
Dielectric: SiON, VDS=-1V Intel VDD=0.8V [10]
(Stanford Uni.)[7]
Si-FinFET 22nm
Intel VDD=0.8V [10]
1.E-07
Si-bulk 45nm
Intel VDD=1V[11]
Ge GAA Lg= 300nm,
dielectric: GeO2(7nm)-HfO2(10nm)
VD= -0.8V (ASTAR Singapore)[8]
InGaAs Nanowire
Lg= 200nm, Tox 14.8nm
VDS=0.5V(Hokkaido Uni.)[4]
1.E-08
GOI Tri-gate
Lg: 65nm. EOT 3.0nm
VD=-1V (AIST Tsukuba)[6]
1.E-06
InGaAs Tri-gate
Lg=60 nm,EOT 12A
VDS=0.5V (Intel) [2]
InGaAs FinFET
Lch=130nm
EOT 3.8nm
VDS=0.5V (NUS)[3]
pMOS
1.E-08
Metal S/D InGaAs-OI
Lch= 55nm, EOT 3.5nm
VDS=0.5V(Tokyo Uni.)[5]
Ge Tri-gate
Lg=183nm, EOT 5.5nm
VD=-1V (NNDL Taiwan)[9]
1.E-09
Si-bulk 45nm
Intel VDD=1V
1.E-09
0
0.4
0.8
ION (mA/mm)
[1] J. J. Gu et al., pp.769, IEDM2011 (Purdue).
[2] M. Radosavljevic et al., pp.765, IEDM201(Intel).
[3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS)
[4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
[5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
1.2
0
0.4
0.8
1.2
ION (mA/mm)
[6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba).
[7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni)
[8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore)
[9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)
IEDM2007 (Intel).
165
Device Structures in III-V
J. Lin, IEDM’12
S.H. Kim, IEDM’11
M. Radosavljevic,
IEDM’11
InAs QW MOSFET
III-V-OI MOSFET
Tri-gate
Recently various device structures have been demonstrated
on InGaAs platform for achieving higher performance at lower
power supply.
Improvement in high-k/III-V interface and III-V growth technology
166
has been a key factor.
Outline
Alternative channel n-FETs
- Gate Stack
- On Insulator(OI) MOSFETs
- Fin, Tri-Gate, Nanowire (GAA) MOSFET
Ge channel p-FETs
- Planar MOSFET
- Tri-Gate, Nanowire, Recessed Channel
Hybrid CMOS
167
Outline
- Gate Stack
Ge channel p-FETs
- Planar MOSFET
Hybrid CMOS
168
Implementing high-k material to III-V,Ge
III-V (InGaAs, InAs,InGaSb,…)
ALD-Al2O3 is most commonly used as gate dielectric in planar or Multi-gate
HfO2-only stacks have high Dit (combination of Al2O3 or Al or Si is used)
Al2O3
Si-HfO2
Al2O3+HfO2
HfAlOx
TaSiOx
3.4 nm
1.2 nm
In0.7Ga0.3As
E. Kim, et al.,
APL96, 012906
NUS, VLSI 2012
In0.53Ga0.47As
L. Chu, et al.,APL99, 042908
Hokkaido Uni, IEDM 2011
Intel, IEDM 2010
Ge
By controlling the
formation of GeOx
at the interface,
HfO2 and Al2O3
show good results.
169
R. Zhang et al., VLSI2012,p161
Outline
- Gate Stack
Ge channel p-FETs
- Planar MOSFET
Hybrid CMOS
170
Metal S/D InGaAs-OI MOSFET (Tokyo Uni)
Metal S/D and InAs buffer layer are used
as performance boosters.
DIBL=84 mV/V and SS=105 mV/V was
shown for Lch = 55 nm when In-content was
higher.
171
Strained InGaAs-OI MOSFET on Si
S. H. Kim, et al., (Tokyo Uni.) VLSI2013, T50.
Strained InGaAs-OI layer on Si by
DWB(direct wafer bonding) with
optional CMP.
MOSFET with 1.7% tensile strain exhibits
1.65x effective mobility enhancement
against InGaAs without strain with high
Ion/Ioff ration~105.
172
Outline
- Gate Stack
Ge channel p-FETs
- Planar MOSFET
Hybrid CMOS
173
InAs nMOSFET (higher than HEMT)
Using the STI aspect ratio trapping
(ART) technique to introduce high
mobility channel to Si CMOS
platform. Record performance:
Ion=601μA/μm at Ioff=100nA/μm(Vd=0.5V)
gm,ext=2.72mS/μm
S=85mV/dec &DIBL=40mV/V
resulting from breakthroughs in epitaxy and III-V/dielectric interface
174
engineering.
InGaAs FinFET (NSU)
H.C. Chin, et al. (National Uni of Singapore).,
EDL2011,Vol.32 p.146.
LCH= 130nm
DIBL =135 mV/V and drive current
over 840 mA/mm at Lch = 130nm
and Vds = 1.5V was achieved
175
Tri-gate InGaAs QW-FET(Intel)
M. Radosavljevic, et al.(Intel), IEDM2011, p.765.
Tri-gate structure has superiority
electrostatic controllability
compared to ultra-thin body
planar structure
Steepest SS and smallest DIBL
ever reported (Wfin = 30nm)
176
InGaAs/InP QW FinFET (1)
N. Waldron, et al., (IMEC) VLSI2014, p.26.
Process flow of InGaAs fin formation
using the replacement fin process.
A CET value of 1.9nm is extracted
from a MOSCAP test structure.
177
InGaAs/InP QW FinFET (2)
N. Waldron, et al., (IMEC) VLSI2014, p.26.
Performance :
SS=190 mV/dec
gm,ext=558 μS/ μm
EOT=1.9nm
High-k last processing outperforms Highk first processing in an RMG flow.
178
InGaAs QW Tri-Gate (EOT,1.0nm)
Performance at
Vds=0.5V
SS= 77mV/dec
DIBL=10 mV/V
gm,max>1.5mS/μm
BEST balance of gm,max
179
and SS!
Gate last InGaAs QW FET
C. –S. Shin, et al., (KANC, Sematch, GF) VLSI2014, p.30.
Performance :
SS=80mV/dec.
DIBL=22mV/V
μn,eff>5,500 cm2/V-s at 300k
Gate-last (GL)
In0.7Ga0.3As QW
MOSFETs with regrown
Further device optimization in the form
180
of self-aligned S/D contact will improve
gm,max at short-channel devices.
InGaAs QW MOSFET for LP
Best planar InGaAs-channel
MOSFETs attributing to InAlAs
buffer, III-V/oxide interface
engineering and S/D regrowth.
Performance at Vds=0.5V
(Lg=100nm EOT=1.1nm):
Ion=550μA/μm @
Ioff=100nA/μm
gm,ext=2.12mS/μm
SS=82mV/dec
181
Gate all around InGaAs MOSFET(Purdue)
P. D. Ye, et al (Purdue Univ)., IEDM2011,
p.769.
Wfin= 50nm
Wfin= 30nm
Inversion mode In0.53Ga0.47As
MOSFET with ALD Al2O3/WN with
well electrostatic properties
DIBL was suppressed down to
Lch = 50nm and
Gm,max =701mS/mm at Vds = 1V
182
InGaAs nanowire transistor(Hokkaido Uni)
T. Fukui, et al. (Hokkaido Univ), IEDM2011, p.773.
Core-multishell InGaAs nanowires
grown without buffer layer on Si substrate
(bottom up approach)
At Vd = 1 V peak transconductance of
500 mS/mm is achieved
(roughly x3 InGaAs nanowire)
183
Outline
- Gate Stack
Ge channel p-FETs
- Planar MOSFET
Hybrid CMOS
184
Ge pMOSFET EOT=0.6 nm
Y. Shin, et al., (KAIST) VLSI2014, p.82.
Ge pMOSFET with TaN/ZrO2/Zrcap/Ge(100) gate stack.
Performance:
Extremely low leakage:250nA/cm2
Extremely low EOT~0.6nm
Low SS =70mV/dec
185
Low hole mobility
~110cm2/Vs!
Ge triangular pMOSFET (NNDL,Taiwan)
S-H. Hsu, et al. (NNDL,Taiwan), IEDM2011, p. 825.
Lg>2Wfin Lg<2Wfin
Ge Rectangular
Selective etching of high defect
Ge near Ge/Si interface is used which
improves gate controllability.
ION/IOFF = 105 and SS= 130 mV/dec
Ge Triangular
And ION= 235 mm/mm at VD= -1V
186
Ge-nanowire pMOSFET (AIST,Tsukuba)
K. Ikeda, et al. (AIST, Tsukuba), VLSI2012, p.165.
Lg= 65nm Wwire= 20nm
VD= -1V
VD= -0.5V
VD=
-0.05V
Using Ni-Ge alloy as metal S/D
Vg-Vth= -2V
Significantly reduces contact resistance
High saturation current and high mobility
μeff = 855 cm2/Vs at Ns =5x1012cm-2
and saturation drain current of
187
731μA/μm at Vd = -1V
Recessed channel Ge nMOSFET
Test recessed channels, Tch=20nm.
Record performance(at Lch=60nm):
Imax=714mA/mm
gmax=590mS/mm
Ion/Ioff ratio=1E5
188
Outline
- Gate Stack
Ge channel p-FETs
- Planar MOSFET
Hybrid CMOS
189
Common InGaAs-GeSn gate stack (NUS)
X. Gong, et al. (National Uni of Singapore),
VLSI2012, p.99.
VGS-VTH= 0～2.0V
LG= 5mm
Common gate stack (gate metal and
dielectric) were used for both p- and n-type
Si2H6 plasma passivation is employed
which creates Si layer at interface.
SS: nMOS: 90 (mV/decade)
pMOS: 190 (mV/decade)
High intrinsic peak GM,Sat=of ~465
190
μS/μm at VDS=-1.1 V was achieved
for LG=250 nm.
InGaSb as channel material (stanford)
Z. Yuan et al., pp.185, VLSI2012 (Stanford Uni)
Hole Mobility
InGaSb
Si
AlGaSb creates barrier
for both electrons and holes
Electron Mobility
InGaSb
Si
Achieving both N- and P-type MOSFET
on a single channel is possible
In-content of 20-40% improves
perfomance
electron/hole mobility > 4000/900cm2/Vs
was gained in a single channel material
ION at LG = 50 mm pMOS: 4 mA/mm
191
nMOS: 3.8 mA/mm
InGaAs/Ge Dual Channel Inverter
T. Irisawa, et al., (GNC, AIST) VLSI2013, T56.
First dual channel CMOS inverters
composed of InGaAs nFETs and Ge
pFETs ultizing stacked 3D
integration.
Mobility enhancement of 2.6x and
3.0x for InGaAs nFETs and Ge
pFETs against Si FETs respectively.
No degradation of Ge pFETs after
InGaAs nFETs processing !
Inverter, successful down to
Vdd=0.2V !
192
3D InGaAs-OI/SGOI CMOS
Schematic of fabricated
ultimate CMOS structure
composed of InGaAsOI/SGOI wire channel
MOSFET w/ independent
back gate.
T. Irisawa, et al., (GNC, AIST) VLSI2014, p.118.
Mobility enhancement of 2.3x and
2.4x in InGaAs nMOSFET and SGOI pMOSFET against Si MOSFET.
Inverter w/ high gain as Vdd down to
0.2V.
193
Co-integration InGaAs and SiGe ETXOI
L. Czornomaz, et al., (IBM) IEDM2013, p.688.
Using DWB(direct wafer bonding) to
get hybrid dual channel ETXOI
substrate.
First co-integration of co-planar SiGe pFETs(65nm) and
InGaAs nFETs(40nm). Height difference only 17nm !
194
InAs/GaSb CMOS
M. Yokoyama, et al., (Tokyo Uni.) VLSI2014, p.28.
Hole mobility of GaSb-OI PFET can
exceed Si PFET as
(TInAs,TGaSb)=(2.5nm,20nm).
(a) Difficult to integrate due to the
material difference, InGaAs and
GaSb.
(b) Newly proposed single channel
lII-V CMOS on Si with UTB
InAs/GaSb-OI layer.
Electron mobility of InAs-OI NFET
can exceed Si NFET as
(TInAs,TGaSb)=(5nm,20nm).
195
La2O3/GaAs CMOS
L. Dong, et al., (Purdue Uni.) VLSI2014, p.50.
GaAs CMOS invertor: a gain of
Flat and sharp interface. ~12 is achieved with V =3V.
DD
Mobility in moderate Ninv slightly
increased due to less phonon
scattering and the decreasing at
low Ninv is by the influence of
Coulomb scattering.
Dit greatly reduced compared to
amorphous Al2O3/GaAs interface.
Oscillation
frequency
increase from
0.35-3.87MHz
as VDD from 1
– 2.75V.
196
Appendix 3
T-FET technologies
197
Tunnel FET
OFF
Vg = 0V
ON
Vg = 1V
Band to band tunneling
Low IOFF, Low VDD, SS<60mV/decade
198
A.M. Ionescu, IEDM2013 Short Course (EPFL)
Q. Liu et al., pp.228, IEDM2013 (ST).
Si, Ge TFET
Ion (mA/mm)
101
104
Leonelli 2011
Jeon 2011 Si Si, silicides S/D
Ghandi 2011
Si NW
Chang 2013 Si
100
Morita 2013 Si Fin
10-1
Moselund 2011
Si NW
Mayer 2008 Si
10-2
10-3
10-2
10-1
100
Villalon 2014
SiGe NW tri-gate
Knoll 2013
Knoll 2012
strained Si
strained Si
NW GAA
NW tri-gate
Q. Huang 2011 Si
Krishnamohan 2009 GOI
102
Ioff (pA/mm)
Zhou 2012 Dey 2012
Mohata 2012
InAs/GaSb GaSb/InAsSb
GaAsSb/InGaAs
102
101
100
Q. Huang 2012 Si
101
Zhou 2012
InGaAs/InP
104
Zhao 2011
InGaAs
Li 2012
AlGaSb/InAs
Mookerjea 2009 InGaAs
Moseiund (IBM)
2012 Si/InAs
Dewey (Intel) 2011 InGaAs
Schmid (IBM)
2011 Si/InAs
103
0.3 < VDS < 0.5 V
1.0 < VDS < 1.5 V
III-V TFET
Tri-gate 22nm node SOI 14nm node (Lg=20nm)
(Lg=30nm)
VDD=0.75V (ST)
VDD=0.8V (Intel)
103
SOI 14nm node (Lg=20nm) VDD=0.75V (ST)
Tri-gate 22nm node (Lg=30nm)
VDD=0.8V (Intel)
103
102
0.05 < VDS < 0.6 V
0.9 < VDS < 1.2 V
Ion (mA/mm)
104
C. Auth et al., pp.131, VLSI2012 (Intel).
10-1
10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101
Ioff (mA/mm)
Si TFETs show the low Ioff, while Ion enhancement is still challenge.
Strain is efficient for Ion enhancement in Si and Ge TFETs.
III-V provide high Ion, however, suffer from unacceptably high Ioff.
199
Benchmark of TFETs
H. Lu and A. Seabaugh, vol. 2, No. 4, pp. 44, Journal of Electron Device society (Univ. Notre Dame)
The highest current is in the range of 1 ~ 10 nA/mm accompanied by
sub-threshold swing below 60 mV/dec.
200
Tunnel FET performance comparison
measured III-V channel TFETs
Average SS:
SMIN: Most common SS which is
Ith
ID
the inverse of ID-VGS slope
at the steepest part
SEFF: Is the average swing when I
OFF
VTH=VDD/2
VOFF=0
Voff VTH
VGS
VOFF=0
VTH=VDD/2
Effective SS:
201
[1] G. Zhou et al., pp. 782, vol. 33, no. 6, EDL 2012 (University of Notre Dame)
10000
Si MOSFET
IOFF [nA/mm]
1000
100
10
1
TFET
VDS=0.75V
TFET
VDS=1.05V
TFET
VDS=1V
0.1
0.01
0.01
Intel
Bulk 32nm
VDD=0.8V
0.1
Intel
Bulk 45nm
VDD=1V
Intel
Tri-Gate 22nm
VDD=0.8V
1
10
ION [mA/mm]
C. Auth et al., pp.131, VLSI2012
(Intel).
202
K. Mistry et al., pp.247, IEDM2007 (Intel).
Tunnel FET (III-V)
SS=21mV/dec
SS=110mV/dec
VDS=1V
HfAlOx
Gate
Conventional FET limit
SS= 60 mV/dec
VDS= 1V
NW Diameter= 30nm
SS of TFET is function of VG due to Zener tunnel current
Minimum SS= 21 mV/dec is reached due to optimized
series resistance of contact, undoped InAs and InAs/Si
ION/IOFF~106 at VDS= 1.0V (ION= 1Am/mm)
203
Strained SiGe nanowire TFETs
Ion enhancement up to 760mA/mm.
Low bandgap of SiGe increase BTBT.
SS lower than 60 mV/dec is
still challenge to be addressed.
204
Si NW TFET with Silicide S/D
Ni(AlxSi1-x)2 can avoid encroachment
into channel region.
Ion at 64mA/mm at VDD = 1V.
Scaling diameter of NW can
improved performance.
205
Fin-shape Si-TFET
Multi-gate can enhance
electric field, particularly at
the corner, resulting in better
performance.
Scaling Fin-width provide
SS lower than 60 mV/dec.
206
Isoelectronic trap for improving TFET
T. Mori et al., pp. 68, VLSI2014 (AIST)
Al-N complex can introduce
isoelectronic trap (IET) below Si CB.
Tunneling probability is increased
through the intermediary of IET.
207
TFET vs. MOSFET at low VDD
VDD 0.3~0.35V
TFET 8x faster at the same power
“parameter variation is not a
significant factor for differentiation
between MOSFET and TFET”
208
Tunnel FET (Si)
A. Villalon, pp.49, VLSI 2012 (CEA-LETI)
X in Si1-xGex is optimized to allow for efficient BTBT
LG= 200nm
ION/IOFF~105
Reducing SiGe
Body thickness improves
Subthreshold swing.
130mV/dec
Gate Voltage (V)
190mV/dec
209
Device structure
210
Appendix 4.
2D channel material
technologies
211
Why 2D channels?
 High-drivability FinFET
 Large Weff/Wfootprint
 Taller Fin
 Narrow Fin pitch
 Thinner Fin
K. Uchida, et. al., IEDM, 23.1, 2008.
 Mobility degradation in
thin Si < 10 nm for both
electron & hole.
High-mobility
2D channels
S. Kobayashi, et. al., J. Appl. Phys. 106, 024511 (2009).
212
Family of 2D materials
0
Vacuum
Graphene
family
Oxide
family
Energy [eV]
-1
-2
Graphene
-4
TiO2 RuO2
~ 5.9
1.1
-5
-7
WSe2
MoSe2
-3
-6
Transition metal
dichalcogenide (TMD)
family
MX2
M: Cr, Mo, W, etc.
X: S, Se, Te, etc.
1.6
~ 3 2.7
Silicene
Si
h-BN
1.8
1.2
1.6 0.4
1.4
MoTe2
MoS2
WTe2
WS2
213
TMD band structure
 MX2
 MoX2 & WX2
Jun Kang, et. al., Applied Physics Letters 102, 012111 (2013).
Mo
S
MoS2
Mo
S
Tokyo Tech.
MoS2
0.65 nm
214
Dependence on # of layers in MoS2 & WS2
Agnieszka Kuc, et. al., Phys. Rev. B 83,
245213 (2011).
215
Synthesis of MoS2
 Exfoliation
 Dipping & annealing
Scotch tape
Liquid Exfoliation
Valeria Nicolosi et al., Science, 2013: Vol. 340 no. 6139
Keng-Ku Liu et al., Nano Lett., 2012, 12 (3), pp 1538–1544
216
Synthesis of MoS2
 Chemical vapor
deposition (CVD)
 RF magnetron
sputtering
RF
Substrate
Accelerated
Ar ions
Plasma
Ar+
Ar+
MoS2 Target
H. Wang, et. al., IEDM, 4.6, 2012.
Takumi Ohashi, Bachelor thesis, Tokyo Institute of
Technology, 2014.
217
Exfoliated single-layer MoS2 nMISFET
 217 cm2/Vs,
electron
 Depletion mode
B. Radisavljevic et al., Nature Nanotech. 6, 147 (2011)
218
Exfoliated 6-layer MoS2 nMISFET
 ~ 4 nm 6 MLs
 Depletion mode
Lingming Yang, et. al., Symposium on VLSI Technology 2014, T-21.6.
219
CVD-single-layer MoS2 nMISFET
 Mobility
~ 190 cm2/Vs
 Depletion mode
H. Wang, et. al., IEDM, 4.6, 2012.
220
Monolayer-MoS2 nMISFET simulation
 Non-equilibrium Green’s
function
 Heavier electron effective
mass
 m* = 0.45m0
 Immunity to short channel
effects
 DIBL ∼ 10 mV/V
 S-factor: 60 mV/dec.
 Larger Ion/Ioff ratio than
III-V FET
Youngki Yoon, et. al., Nano Lett., 2011, 11 (9), pp 3768–3773.
221
Summary of band-gaps of TMDs
eV
Ti
Zr
Hf
V
S2
1.95 (D),
0.3 (I)
1.68 (D),
2.1(I)
2.7 (D),
1.93 (I)
Se2
1.55 (D),
0.15 (I)
1.20 (D),
1.61(I)
1.77 (D),
1.18 (I)
Metal
Te2
1.0 (D)
Semimetal
Semimetal
Semimetal
Metal
Nb
Ta
Mo
W
Metal
1.8 (SL)
1.72(D)
1.2 (I)
1.93 (SL),
1.77 (D),
1.35 (I)
Metal
Metal
1.49(SL),
1.38 (D),
1.1 (I)
1.6 (D)
1.1 (I)
Metal
Semimetal
1.13 (SL),
Semimetal
Semimetal
Metal
Ian Post, Symposium on VLSI Technology, 2013, Short Course
222
Appendix 5.
Other emerging
technologies
223
ON-state resistance [Ohm]
MEMS relay
ION/IOFF of ~1010
Ultra-low-power digital
logic applications.
Number of Operation Cycles
Frequency of 1, 5, 25kHz under operation
224
T. K. Liu et al., pp. 43, VLSI2012 (UC Berkeley)
Si Junctionless Transistor (Intel)
R. Rios et al., EDL. 32(2011)1170
(Intel)
20
30
Lg (nm)
40 20
40
30
40 20
30
Lg (nm)
Lg (nm)
IM : Conventional Inversion Mode
JAM LD : Janctionless Accumulation Mode with
low dope
JAM HD : Janctionless Accumulation Mode with
high dope
JAM devices have reduced gate control and degraded shortchannel characteristics relative to IM
Not suitable for high-performance logic (high Ion and moderate Ioff)
225
Nanowire Junctionless Transistor
Lg= 1mm
Wwire= 30nm
Lg= 1mm
Silicon nanowire is uniformly doped
Gate material is opposite
polarity polysilicon
Near-ideal subthreshold slope,
close to 60 mV/dec at room
temperature, and extremely low
leakage currents
ION/IOFF~1x106
(-1<Vg<1)
IOFFis smaller than 10-15 A
226
Carbon nanotube and Graphene
K. Banerjee, UC Santa Barbara, G-COE PICE International Symposium on Silicon Nano Devices in 2030
SWCNT : single wall carbon nanotube
GNR : graphene nano ribbon
Carbon materials for FET applications
・ an ultra-thin body for aggressive channel length scaling
・ excellent intrinsic transport properties similar to carbon
nanotubes
・ pattern the desired device structures
227
Sub-10nm carbon nanotube transistor
A. D. Franklin et al., pp.525, IEDM2011 (IBM)
Transistor operation with Lch of 9nm
228
Graphene Field-effect Transistor
Z. Chen et al., pp.509, IEDM2008 (IBM)
J. B. Oostinga et al., Nature Materials 7 (2008) 151
・Ambipolar Characteristics
・Bi-layer graphene and
double gates can open the
gap
229
Spin transfer Torque Switching MOSFET
T. Marukame et al., pp.215, IEDM2009 (Toshiba)
Magnetic tunnel junction on S/D
Lg = 1mm
Read/write are enabled by using ferromagnetic electrodes and
Spin-polarized current
230

Future of Logic Nano CMOS Technology

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