SBC310 3U VPX Single Board Computer

Transcription

GE
Intelligent Platforms
Hardware Reference Manual
SBC310 3U VPX Single Board Computer
Edition 5
Publication No. SBC310-0HH/5
Document History
Edition
First
Second
Third
Fourth
4DF
5
Date
June 2008
March 2009
June 2009
August 2009
March 2010
September 2010
Description
First issue – rev 2 artwork
Minor updates and corrections
Minor update – added environmental Specs & updated MTBF data
Signal name corrections
No technical information changes, rebranding only
Minor amendments to Rev2 information, and introduces Board Rev 3
Waste Electrical and Electronic Equipment (WEEE) Returns
GE Intelligent Platforms Ltd. is registered with an approved Producer Compliance Scheme (PCS) and, subject to suitable contractual arrangements being in place, will ensure WEEE is processed in accordance with the requirements of the WEEE Directive. GE Intelligent Platforms Ltd. will evaluate requests to take back products purchased by our customers before August 13, 2005 on a case by case basis. A WEEE management fee may apply.
2 SBC310 3U VPX Single Board Computer
Contents
1 • Introduction .............................................................................................................................................. 11
1.1 Manual Conventions ......................................................................................................................................................................... 12
1.2 Safety Notices....................................................................................................................................................................................... 13
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
Flammability...............................................................................................................................................................................................13
EMI/EMC Regulatory Compliance ....................................................................................................................................................13
Cooling..........................................................................................................................................................................................................14
Handling.......................................................................................................................................................................................................14
Heatsink .......................................................................................................................................................................................................14
1.3 Associated Documents.................................................................................................................................................................... 15
1.4 Associated Documents.................................................................................................................................................................... 15
1.5 GE Manuals............................................................................................................................................................................................ 16
1.6 Web Sites ................................................................................................................................................................................................ 16
1.7 Technical Support............................................................................................................................................................................... 16
1.8 Returns..................................................................................................................................................................................................... 17
2 • Unpacking.................................................................................................................................................. 18
2.1 Box contents checklist: .................................................................................................................................................................... 18
2.2 Identifying Your Board...................................................................................................................................................................... 19
3 • Configuration – SBC310 Rev2 .......................................................................................................... 20
3.1 Link Settings .......................................................................................................................................................................................... 21
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
P10 (Pins 1-2) JTAG Scanbridge Output Enable Link ...............................................................................................................21
P10 (Pins 3-4) NVMRO Write Enable Link ......................................................................................................................................21
P11 (Pins 1-2) USB/PCI-X mode Link ...............................................................................................................................................21
P11 (Pins 3-4) SMP Mode Link.............................................................................................................................................................21
P12 (Pins 1-2) & P13 (Pins 1-2) Core 0 Boot Area Selection ..................................................................................................22
P13 (Pins 3-4) Flash Protection Unlock Link.................................................................................................................................22
P14 (Pins 1-2) Boot Sequencer Disable..........................................................................................................................................22
P14 (Pins 3-4) External Programming Link...................................................................................................................................23
4 • Configuration – SBC310 From Rev3 .............................................................................................. 24
4.1 Link Settings .......................................................................................................................................................................................... 25
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
P11 (Pins 1-2) USB/PCI-X mode Link ...............................................................................................................................................25
P11 (Pins 3-4) SMP Mode Link.............................................................................................................................................................25
P13 (Pins 1-2) NVMRO Write Enable Link ......................................................................................................................................26
P13 (Pins 3-4) Flash Protection Unlock Link.................................................................................................................................26
P14(Pins 1-2) JTAG Scanbridge Output Enable Link ................................................................................................................26
P14 (Pins 3-4) External Programming Link...................................................................................................................................27
5 • Installation and Power Up/Reset.................................................................................................... 28
5.1 Board Keying......................................................................................................................................................................................... 28
5.2 Board Installation Notes.................................................................................................................................................................. 28
5.3 Connecting to the SBC310 ............................................................................................................................................................. 29
5.4 Reset & Power-up Sequence......................................................................................................................................................... 29
5.4.1
5.4.2
5.4.3
On-board sequencing............................................................................................................................................................................29
Inter-board sequencing........................................................................................................................................................................30
Power-up sequence ...............................................................................................................................................................................30
6 • Functional Description......................................................................................................................... 31
Contents 3
6.1 Features .................................................................................................................................................................................................. 32
6.2 Integrated Host Processor ............................................................................................................................................................. 33
6.2.1
6.2.2
PowerPC Processing Cores .................................................................................................................................................................33
Dual Processing Cores...........................................................................................................................................................................34
6.3 Memory.................................................................................................................................................................................................... 34
6.3.1
6.3.2
6.3.3
Memory Map..............................................................................................................................................................................................34
System RAM................................................................................................................................................................................................34
Flash...............................................................................................................................................................................................................35
6.4 PCI Express Infrastructure.............................................................................................................................................................. 39
6.4.1
6.4.2
6.4.3
PCI Express Switch ..................................................................................................................................................................................40
PCI Express to PCI Bridge .....................................................................................................................................................................41
PCI Bus ..........................................................................................................................................................................................................41
6.5.1
Local Bus Control FPGA.........................................................................................................................................................................43
6.5 Local Bus................................................................................................................................................................................................. 42
6.6 Input/Output ......................................................................................................................................................................................... 43
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
Ethernet........................................................................................................................................................................................................43
Serial Ports ..................................................................................................................................................................................................44
USB .................................................................................................................................................................................................................45
45
Serial ATA.....................................................................................................................................................................................................45
General Purpose I/O ...............................................................................................................................................................................45
6.7 I2C ............................................................................................................................................................................................................... 46
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
Addressing ..................................................................................................................................................................................................47
Real-Time Clock........................................................................................................................................................................................47
Elapsed Time Indicator..........................................................................................................................................................................47
Temperature Sensors ............................................................................................................................................................................47
Power Supply Manager.........................................................................................................................................................................47
MPC8640(D)/MPC8641(D) Configuration EEPROM....................................................................................................................48
I2C Reset .......................................................................................................................................................................................................48
Board Management Microcontroller ..............................................................................................................................................48
6.8 General Purpose Timers .................................................................................................................................................................. 50
6.9 Watchdog Timers ............................................................................................................................................................................... 50
6.10 AXIS Support....................................................................................................................................................................................... 50
6.11 Resets, Interrupts and Error Reporting.................................................................................................................................. 51
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.11.7
6.11.8
Hard Reset ..................................................................................................................................................................................................51
SYSRESET~ Signal ....................................................................................................................................................................................52
Machine Check Exception....................................................................................................................................................................52
Soft Reset.....................................................................................................................................................................................................52
System Management Interrupt (SMI~)...........................................................................................................................................52
External Interrupt (INT~)........................................................................................................................................................................53
Secondary Interrupt Controller .........................................................................................................................................................53
PCI Interrupts.............................................................................................................................................................................................53
6.12 Power Management ....................................................................................................................................................................... 54
6.12.1
6.12.2
Processor.....................................................................................................................................................................................................54
PCI Express..................................................................................................................................................................................................54
6.13 JTAG........................................................................................................................................................................................................ 54
6.14 Mezzanine Sites ................................................................................................................................................................................ 55
6.15 Control and Status Registers...................................................................................................................................................... 58
6.15.1
6.15.2
6.15.3
6.15.4
6.15.5
6.15.6
6.15.7
6.15.8
6.15.9
6.15.10
Board ID Register.....................................................................................................................................................................................59
Address Register ......................................................................................................................................................................................59
Board Frequency Register ...................................................................................................................................................................60
Board Configuration Register ............................................................................................................................................................60
Link Status Register ................................................................................................................................................................................61
Control Register 1 ....................................................................................................................................................................................63
Control Register 2 ....................................................................................................................................................................................64
Flash Control Register............................................................................................................................................................................65
Test Pattern Register 1..........................................................................................................................................................................66
6.15.11
6.15.12
6.15.13
6.15.14
6.15.15
6.15.16
6.15.17
6.15.18
6.15.19
6.15.20
6.15.21
6.15.22
6.15.23
6.15.24
6.15.25
6.15.26
6.15.27
6.15.28
6.15.29
6.15.30
6.15.31
6.15.32
6.15.33
6.15.34
6.15.35
6.15.36
6.15.37
Scratch Register 1 ...................................................................................................................................................................................67
Board Semaphore Registers...............................................................................................................................................................68
Watchdog Control Register (CS4 – Offsets 0x2000 and 0x2010) ......................................................................................68
Watchdog Interrupt Value Registers (CS4 - Offsets 0x2004 and 0x2014) ...................................................................68
Board Interrupt Status Register ........................................................................................................................................................69
Board Interrupt Core 0 INT Mask Register ...................................................................................................................................70
Board Interrupt Core 1 INT Mask Register ...................................................................................................................................71
Board Interrupt Core 0 MCP Mask Register.................................................................................................................................72
Board Interrupt Core 1 MCP Mask Register.................................................................................................................................73
GPIO Direction Register (Read/Write) .............................................................................................................................................74
GPIO Data In Register (Read Only) ...................................................................................................................................................74
GPIO Data Out Register (Read/Write) .............................................................................................................................................74
GPIO Interrupt Generation Mode Register (Read/Write)........................................................................................................75
GPIO Polarity Register A (Read/Write) ............................................................................................................................................75
GPIO Polarity Register B (Read/Write) ............................................................................................................................................76
GPIO Interrupt Status Register (Read/Write) ...............................................................................................................................76
GPIO Output Drive Mode Register (R/W) .......................................................................................................................................77
AXIS Timestamp Low Value Register (CS4 - Offset 0x6000)................................................................................................77
AXIS Timestamp High Value Register (CS4 - Offset 0x6004) ..............................................................................................77
AXIS Timer Control Register (CS4 - Offset 0x6008)...................................................................................................................78
AXIS Semaphore Registers ..................................................................................................................................................................78
FIFO Data Registers ................................................................................................................................................................................79
FIFO Status Registers .............................................................................................................................................................................79
6.16 VPX Port Configuration.................................................................................................................................................................. 80
6.17 LEDs ........................................................................................................................................................................................................ 81
6.17.1
6.17.2
6.17.3
BIT Status LEDs .........................................................................................................................................................................................82
PCI Express Link Status LEDs..............................................................................................................................................................82
Ethernet Link Status LEDs....................................................................................................................................................................82
6.18 Front Panel .......................................................................................................................................................................................... 83
6.18.1
6.18.2
Air-cooled Versions.................................................................................................................................................................................83
Conduction-cooled Versions ..............................................................................................................................................................83
7 • Connectors ................................................................................................................................................ 84
Backplane Connectors ........................................................................................................................................................................... 85
7.1 ...................................................................................................................................................................................................................... 85
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
OpenVPX (VITA65) compatibility........................................................................................................................................................85
P0 (VPX Utility connector) Pin Assignments.................................................................................................................................85
J0 VPX Backplane Pin Assignments ................................................................................................................................................85
P0/J0 Signal Definitions ........................................................................................................................................................................86
P1 Connector Pin Assignments .........................................................................................................................................................87
J1 VPX Backplane Pin Assignments ................................................................................................................................................88
P2 Connector Pin Assignments (PMC P64s config.)..................................................................................................................90
P2 Connector Pin Assignments (XMC X20d24s config.) .........................................................................................................91
J2 VPX Backplane Pin Assignments (PMC P64s config.).........................................................................................................92
J2 VPX Backplane Pin Assignments (XMC X20d24s config.) ................................................................................................93
7.2 PMC Connectors.................................................................................................................................................................................. 95
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
J11 Connector Pin Assignments.......................................................................................................................................................95
PMC Signal Descriptions.......................................................................................................................................................................99
7.3 XMC Connectors................................................................................................................................................................................100
7.3.1
7.3.2
J15 Pin Assignments ........................................................................................................................................................................... 100
J16 Pin Assignments ........................................................................................................................................................................... 100
Contents 5
7.3.3
XMC Signal Descriptions.................................................................................................................................................................... 101
7.4 P17 Connector....................................................................................................................................................................................101
8 • Troubleshooting................................................................................................................................... 102
Appendix A • Specifications................................................................................................................... 103
A.1 Mechanical Construction..............................................................................................................................................................103
A.2 Component Details ..........................................................................................................................................................................103
A.3 Safety Rating.......................................................................................................................................................................................104
A.4 Environmental Specifications .....................................................................................................................................................104
A.4.1 Convection-cooled Boards...................................................................................................................................................................... 104
A.4.2 Conduction-cooled Boards..................................................................................................................................................................... 104
A.5 Electrical Specifications.................................................................................................................................................................105
A.5.1 Voltage Supply Requirements ............................................................................................................................................................... 105
A.5.2 Current Consumption................................................................................................................................................................................ 105
A.5.3 GPIO Electrical Characteristics.............................................................................................................................................................. 106
A.6 Reliability (MTBF)................................................................................................................................................................................106
A.7 Product Codes....................................................................................................................................................................................107
A.8 Software Support..............................................................................................................................................................................108
A.9 Boot Firmware ...................................................................................................................................................................................108
A.10 Built In Test........................................................................................................................................................................................108
A.11 Background Condition Screening ..........................................................................................................................................109
A.12 I/O Module.........................................................................................................................................................................................109
Appendix B • SBC310TST Test Access Board ................................................................................ 110
B.1 Overview ...............................................................................................................................................................................................110
B.2 Configuration......................................................................................................................................................................................110
B.2.1 SW1/SW2 and E1/E2 – JTAG multiplexer control ......................................................................................................................... 111
B.2.2 P1 - JTAG header (Lattice pin-out)....................................................................................................................................................... 111
B.2.3 P2 - JTAG Header (JTAG Technologies Pin-out)............................................................................................................................. 111
B.2.4 P3 – Debug Header..................................................................................................................................................................................... 111
B.2.5 P4 – Scanbridge Link Block ..................................................................................................................................................................... 112
B.2.6 P5 – SBC310 Link Block............................................................................................................................................................................. 112
B.2.7 P5 - External Programming Link pins 1-2 ........................................................................................................................................ 112
B.2.8 P5 - USB/PCI-X mode Link pins 3-4..................................................................................................................................................... 112
B.2.9 P5 - Core1 Disable link pins 5-6 ............................................................................................................................................................ 113
B.2.10 P5 - AMP Mode Link pins 7-8 ............................................................................................................................................................... 113
B.2.11 P5 - EEPROM Recovery Link Pins 9-10 ............................................................................................................................................ 113
B.2.12 P5 - NVMRO Write Enable Link pins 11-12.................................................................................................................................... 114
B.2.13 P5 - Flash Protection Unlock Link pins 13-14 .............................................................................................................................. 114
B.2.14 P5 - Core 0 Boot Area Selection pins 17-18 & pins 15-16...................................................................................................... 114
B.2.15 P5 - Core 1 Boot Area Selection pins 19-20 & pins 15-16...................................................................................................... 115
B.2.16 P6 – BANC Write Enable......................................................................................................................................................................... 115
B.2.17 P7 – BDM header....................................................................................................................................................................................... 115
B.2.18 P8 pins 1-3 Ground .................................................................................................................................................................................. 115
B.2.19 E3 – BANC Write Enable......................................................................................................................................................................... 116
B.2.20 J1 – SBC310 connector .......................................................................................................................................................................... 116
B.3 Installation ...........................................................................................................................................................................................116
B.4 Functional Description ...................................................................................................................................................................116
B.4.1 JTAG Chain...................................................................................................................................................................................................... 116
B.4.2 Reset Switch................................................................................................................................................................................................... 117
B.4.3 LEDs ................................................................................................................................................................................................................... 117
Index ................................................................................................................................................................. 118
List of Tables
Table 3-1 Link Functions............................................................................................................................................................................... 20
Table 3-2 P12 (Pins 1-2) & P13 (Pins 1-2)............................................................................................................................................... 22
Table 4-1 Link Functions............................................................................................................................................................................... 24
Table 6-1 Processor Core Frequency Options ................................................................................................................................... 33
Table 6-2 RAM Configurations................................................................................................................................................................... 34
Table 6-3 Flash Options ................................................................................................................................................................................ 35
Table 6-4 PCI Bus ............................................................................................................................................................................................. 39
Table 6-5 PCI Express Port Configuration ............................................................................................................................................ 40
Table 6-6 PCI Devices..................................................................................................................................................................................... 42
Table 6-7 Flash Memory Allocation......................................................................................................................................................... 42
Table 6-8 Baud Rate Devisors.................................................................................................................................................................... 44
Table 6-9 RS232/422 configuration........................................................................................................................................................ 44
Table 6-10 USB Device Functions ............................................................................................................................................................ 45
Table 6-11 GPIO Functions.......................................................................................................................................................................... 46
Table 6-12 I2C Buses....................................................................................................................................................................................... 47
Table 6-13 BMM Address Allocation ....................................................................................................................................................... 49
Table 6-14 SMB Address Allocation ........................................................................................................................................................ 49
Table 6-15 Processor Interrupts ............................................................................................................................................................... 51
Table 6-16 PCI Interrupts ............................................................................................................................................................................. 54
Table 6-17 JTAG Access Ports.................................................................................................................................................................... 54
Table 6-18 Control & Status Registers ................................................................................................................................................... 58
Table 6-19 Board ID Register ..................................................................................................................................................................... 59
Table 6-20 Address Register....................................................................................................................................................................... 59
Table 6-21 Board Frequency Register ................................................................................................................................................... 60
Table 6-22 Board Configuration Register............................................................................................................................................. 60
Table 6-23 Link Status Register................................................................................................................................................................. 61
Table 6-24 Control Register 1 .................................................................................................................................................................... 63
Table 6-25 Flash Control Register............................................................................................................................................................ 65
Table 6-26 Test Pattern Register 1 .......................................................................................................................................................... 66
Table 6-29 Scratc Register 1 ...................................................................................................................................................................... 67
Table 6-30 Scratch Register 2.................................................................................................................................................................... 67
Table 6-31 Scratc Register 1 ...................................................................................................................................................................... 67
Table 6-32 Scratch Register 2.................................................................................................................................................................... 67
Table 6-33 Board Semaphore Registers............................................................................................................................................... 68
Table 6-34 Watchdog Control Registers (CS4 - Offsets 0x2000 and 0x2010) .................................................................... 68
Table 6-35 Watchdog Interrupt Value Registers (CS4 - Offsets 0x2004 and 0x2014).................................................... 68
Table 6-36 Board Interrupt Status Register ........................................................................................................................................ 69
Table 6-37 Board Interrupt Core 0 INT Mask Register ................................................................................................................... 70
Table 6-38 Board Interrupt Core 1 INT Mask Register ................................................................................................................... 71
List of Tables 7
Table 6-39 Board Interrupt Core 0 MCP Mask Register................................................................................................................. 72
Table 6-40 Board Interrupt Core 1 MCP Mask Register................................................................................................................. 73
Table 6-41 GPIO Direction Register......................................................................................................................................................... 74
Table 6-42 GPIO Data In Register............................................................................................................................................................. 74
Table 6-43 GPIO Data Out Register......................................................................................................................................................... 74
Table 6-44 GPIO Interrupt Generation Mode Register ................................................................................................................... 75
Table 6-45 GPIO Polarity Register A ........................................................................................................................................................ 75
Table 6-46 GPIO Polarity Register B ........................................................................................................................................................ 76
Table 6-47 GPIO Interrupt Status Register........................................................................................................................................... 76
Table 6-48 GPIO Output Drive Mode Register.................................................................................................................................... 77
Table 6-49 Axis Timestamp Low Value Register............................................................................................................................... 77
Table 6-50 AXIS Timestamp High Value Register............................................................................................................................. 77
Table 6-51 AXIS Timer Control Register ................................................................................................................................................ 78
Table 6-52 AXIS Semaphore Registers .................................................................................................................................................. 78
Table 6-53 AXIS Semaphore Register Bits............................................................................................................................................ 78
Table 6-54 FIFO Data Registers................................................................................................................................................................. 79
Table 6-55 FIFO Data Register Bits.......................................................................................................................................................... 79
Table 6-56 FIFO Status Registers ............................................................................................................................................................. 79
Table 6-57 FIFO Status Register Bits....................................................................................................................................................... 79
Table 6-58 LED Functions ............................................................................................................................................................................ 81
Table 6-59 BIT Run State LEDs................................................................................................................................................................... 82
Table 7-1 Connector Functions................................................................................................................................................................. 84
Table 7-2 P0 Pin Assignments.................................................................................................................................................................... 85
Table 7-3 J0 VPX Backplane Pin Assignments................................................................................................................................... 85
Table 7-4 P0 Signal Definitions.................................................................................................................................................................. 86
Table 7-5 P1 Pin Assignments.................................................................................................................................................................... 87
Table 7-6 J1 VPX Backplane Pin Assignments................................................................................................................................... 88
Table 7-7 P1 Signal Definitions.................................................................................................................................................................. 89
Table 7-8 P2 Pin Assignments (PMC P64s Configuration)............................................................................................................. 90
Table 7-9 P2 Connector (XMC X20d24s Configuration) ................................................................................................................. 91
Table 7-10 J2 VPX backplane Pin Assignments (PMC P64s Configuration) ......................................................................... 92
Table 7-11 J2 VPX backplane Pin Assignments (XMC X20d24s Configuration) ................................................................. 93
Table 7-12 P2 Signal Definitions ............................................................................................................................................................... 94
Table 7-13 J11 Pin Assignments............................................................................................................................................................... 95
Table 7-17 PMC Signal Descriptions ....................................................................................................................................................... 99
Table 7-18 J15 Pin Assignments.............................................................................................................................................................100
Table 7-19 J16 Pin Assignments.............................................................................................................................................................100
Table 7-20 XMC Signal Descriptions .....................................................................................................................................................101
Table A-1 Mechanical Construction......................................................................................................................................................103
Table A-2 Component Details ..................................................................................................................................................................103
Table A-3 ............................................................................................................................................................................................................104
Table A-4 ............................................................................................................................................................................................................104
Table A-5 Voltage Requirements............................................................................................................................................................105
Table A-6 VS3 (5V) Current Consumption...........................................................................................................................................105
Table A-7 GPIO Electrical Characteristics...........................................................................................................................................106
Table A-8 GPIO Absolute maximum ratings......................................................................................................................................106
Table A-9 SBC310 Reliability (MTBF)......................................................................................................................................................106
Table A-10 Product Options......................................................................................................................................................................107
Table B-1 JTAG multiplexer control.......................................................................................................................................................111
Table B-2 JTAG header (Lattice pin-out) .............................................................................................................................................111
Table B-3 JTAG Header (JTAG Technologies Pin-out)...................................................................................................................111
Table B-4 Scanbridge Link Block ............................................................................................................................................................112
Table B-5 External Programming Link pins 1-2...............................................................................................................................112
Table B-6 USB/PCI-X mode Link pins 3-4 ...........................................................................................................................................112
Table B-7 Core1 Disable link pins 5-6...................................................................................................................................................113
Table B-8 P11 (Pins 3-4)...............................................................................................................................................................................113
Table B-9 EEPROM Recovery Link Pins 9-10 .....................................................................................................................................113
Table B-10 NVMRO Write Enable Link pins 11-12 ..........................................................................................................................114
Table B-11 Flash Protection Unlock Link pins 13-14 ....................................................................................................................114
Table B-12 Core 0 Boot Area Selection pins 17-18 & pins 15-16 ...........................................................................................114
Table B-13 Core 1 Boot Area Selection pins 19-20 & pins 15-16 ...........................................................................................115
Table B-14 BDM header..............................................................................................................................................................................115
List of Tables 9
List of Figures
Figure 1-1 SBC310 General View (Product with Heatsink Removed)...................................................................................... 11
Figure 1-2 Incorrect Handling method.................................................................................................................................................. 14
Figure 1-3 ESD Label (Present on Board Packaging) ...................................................................................................................... 14
Figure 1-4 Incorrect Heatsink Removal Method............................................................................................................................... 15
Figure 2-1 Box Contents ............................................................................................................................................................................... 18
Figure 2-2 Product Label (Packaging) .................................................................................................................................................... 19
Figure 2-3 Product Label (Product).......................................................................................................................................................... 19
Figure 2-4 Product Label (Conduction-cooled Product)................................................................................................................ 19
Figure 3-1 Link Locations............................................................................................................................................................................. 20
Figure 4-1 Link Locations............................................................................................................................................................................. 24
Figure 6-1 SBC310 Block Diagram .......................................................................................................................................................... 31
Figure 6-2 Flash Memory Structure ........................................................................................................................................................ 35
Figure 6-3 Local Bus CS0 Mapping.......................................................................................................................................................... 36
Figure 6-4 User Flash Chip Select Mapping ........................................................................................................................................ 37
Figure 6-5 Flash Paged Access Mode .................................................................................................................................................... 38
Figure 6-6 I2C Architecture .......................................................................................................................................................................... 46
Figure 6-7 SBC310 Machine Check Exceptions................................................................................................................................. 52
Figure 6-8 SBC310 Interrupts..................................................................................................................................................................... 53
Figure 6-9 PMC/XMC Site Device Clearance Dimensions............................................................................................................. 55
Figure 6-10 XMC VPX I/O Mapping .......................................................................................................................................................... 57
Figure 6-11 PMC VPX I/O Mapping .......................................................................................................................................................... 57
Figure 6-12 VPX Port Configuration ........................................................................................................................................................ 80
Figure 6-13 LED Positions ............................................................................................................................................................................ 81
Figure 7-1 Connector Positions................................................................................................................................................................. 84
Figure 7-2 Example Waveforms ............................................................................................................................................................... 89
Figure 7-3 Example Waveforms ............................................................................................................................................................... 94
Figure B-1 SBC310TST-1BB-1 Layout...................................................................................................................................................110
Figure B-2 JTAG Chain Diagram .............................................................................................................................................................116
1 • Introduction
The SBC310 is a 3U VPX Single Board Computer, and is part of the GE Intelligent Platforms (GEIP) VPXtreme3 range of products. It utilizes the Freescale MPC8641D/MPC8640D Dual‐Core Integrated Host Processor, which contains two e600 PowerPC processing cores running at 1067 MHz with dual memory controllers, serial fabric and I/O interfaces. Also available is the MPC8641/MPC8640 variant which utilizes the single‐core version of the integrated host processor, operating at up to 1.33 GHz. The board offers up to 2 GBytes of DDR2 SDRAM with ECC, up to 512 MByte of Flash memory, two Gigabit Ethernet channels, on‐board serial comms (RS423 or RS422), USB2, Serial ATA and two independent x4 PCI Express links routed to the VPX backplane. The MPC8640(D)/MPC8641(D) is connected to all on‐board PCI devices and mezzanine sites using PCI Express. This is a high‐speed serial interconnect running at 2.5 Gbits/s, providing a total bandwidth of 1 GBytes/s in each direction to/from the processor, through a non‐blocking switch architecture. PCI Express is software compatible with PCI and bridges are used where connection to PCI or PCI‐X components is required. A single 64‐bit PMC site is provided, supporting PCI‐X operation at up to 133 MHz or standard PCI, allowing for off‐the‐shelf or custom mezzanines to be fitted to add further functionality to the board. The site also supports XMC mezzanine cards, allowing for a high‐speed serial interconnect, with a x8 PCI Express link.(VITA 42.3). Figure 1-1 SBC310 General View (Product with Heatsink Removed)
Introduction 11
1.1 Manual Conventions
All numbers are expressed in decimal, except addresses and memory or register data, which are expressed in hexadecimal. Where confusion may occur, decimal numbers have a ‘D’ subscript and binary numbers have a ‘b’ subscript. The prefix ‘0x’ shows a hexadecimal number, following the ‘C’ programming language convention. Thus: One dozen = 12D = 0x0C = 1100b The multipliers ‘k’, ‘M’ and ‘G’ have their conventional scientific and engineering meanings of x103, x106 and x109 respectively. The only exception to this is in the description of the size of memory areas, when ‘K’, ‘M’ and ‘G’ mean x210, x220 and x230 respectively. NOTE
When describing transfer rates, ‘k’ ‘M’ and ‘G’ mean x103, x106 and x109 not x210, x220 and x230.
Multiple bit fields are numbered from 0 to n, where 0 is the LSB and n is the MSB. Signal names ending with a tilde (~) denote active low signals; all other signals are active high. Filenames are shown in bold, e.g. apps/code.exe. System messages and function names are shown in courier typeface, e.g. mapvpx. User input is shown in bold courier typeface, e.g. user input. ‘↵’ represents the Enter, ↵, Return etc. key on your keyboard. This manual uses the following types of notice: 1. Notes call attention to important features or instructions, and are shown as follows:‐ NOTE
This is an example note entry.
2. Cautions, which take the following form, alert you to system danger or loss of data. A Caution is shown as follows:‐ CAUTION
This is an example caution entry.
3. Warnings, which take the following form, alert you to the risk of severe personal injury. A Warning is shown as follows:‐ WARNING
This is an example warning entry.
4. Tips give guidance on procedures that may be tackled in a number of ways, and are shown as follows:‐ TIP
This is an example tip entry.
5. Links to different parts of the same document, other documents or websites are shown as follows:‐ LINK
This is an example Link entry.
The purple link color may also be used to indicate a link (or hyperlink) within a body of text or paragraph. 1.2 Safety Notices
The following general safety precautions represent warnings of certain dangers of which GEIP is aware. Failure to comply with these or with specific Warnings and/or Cautions elsewhere in this manual violates safety standards of design, manufacture and intended use of the equipment. GEIP assumes no liability for the user’s failure to comply with these requirements. Also follow all warning instructions contained in associated system equipment manuals. WARNING
Use extreme caution when handling, testing and adjusting this equipment. This device may operate in
an environment containing potentially dangerous voltages.
Ensure that all system power is removed before installing any device.
To minimize shock hazard, connect the equipment chassis and rack/enclosure to an electrical ground.
If AC power is supplied to the rack/enclosure, the power jack and mating plug of the power cable must
meet IEC safety standards.
1.2.1
Flammability
The SBC310 circuit board is made by a UL‐recognized manufacturer and has a flammability rating of UL94V‐1. 1.2.2
EMI/EMC Regulatory Compliance
CAUTION
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be
susceptible to EMI if not installed and used in a cabinet with adequate EMI protection
The SBC310 is designed using good EMC practices and, when used in a suitably EMC‐compliant chassis, should maintain the compliance of the total system. The SBC310 also complies with EN60950 (product safety), which is essentially the requirement for the Low Voltage Directive (73/23/EEC). Air‐cooled build levels of the SBC310 are designed for use in systems meeting VDE class B, EN and FCC regulations for EMC emissions and susceptibility. Publication No. SBC310-0HH/5
Introduction 13
Conduction‐cooled build levels of the SBC310 are designed for integration into EMC hardened cabinets/boxes. 1.2.3
Cooling
CAUTION
The SBC310 requires air-flow of at least 300 feet/minute for build levels 1 and 2, and at least 600
feet/minute for build level 3. If a conduction-cooled (level 4 or 5) SBC310 is operating on an extender
card, it requires air-flow of at least 300 feet/minute across it.
1.2.4
Handling
CAUTION
Only handle the board by the edges or front panel
Figure 1-2 Incorrect Handling method
Figure 1-3 ESD Label (Present on Board Packaging)
1.2.5
Heatsink
CAUTION
Do not remove the heatsink.
Figure 1-4 Incorrect Heatsink Removal Method
There are no user‐alterable components underneath the heatsink, so users should have no reason to remove it. Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws attaching the heatsink to the PCB. Over‐tightening the screws may cause the heatsink to damage components beneath it. Removal and re‐attachment of the heatsink should only be carried out by the factory. 1.3 Associated Documents
Due to the complexity of some of the parts used on the SBC310, it is not possible to include all the detailed data on all such devices in this manual. The following is a list of the specifications and data sheets that provide any additional information required: VPX Standard, VITA 46.0 – 200x, Draft 0.25 March 2007 (this was the latest version at time of writing; check the web site for later updates), available at http://www.vita.com. NOTE
Registration is required for access to this specification.
1.4 Associated Documents
The GE Intelligent Platforms Technical Manuals CD‐ROM allows privileged access to an Internet resource containing the latest updated documents. Publication No. SBC310-0HH/5
Introduction 15
1.5 GE Manuals
This document is distributed via CD‐ROM and the internet. The CD‐ROM allows privileged access to an Internet resource containing the latest updated documents. Alternatively, you may register for access to all manuals via the website whose link is given below. 1.6 Web Sites
Information regarding all GE Intelligent Platforms (GEIP) products can be found on the following website: LINK
http://www.ge-ip.com/products/family/embedded-systems/
Manufacturers of many of the devices used on the SBC310 maintain FTP or world‐
wide‐web sites. Some useful sites are: LINK
http://www.vita.com
http://www.pcisig.org
http://www.intel.com
http://www.xilinx.com
for VPX (VITA 46) standards
for PCI Bus standards
for processor and chip set information
for CPLD information
NOTE
Registration may be required to access information from external websites.
1.7 Technical Support
Technical assistance contact details can be found on the web site Support Locator page. The appropriate product category is Digital Processing, Multiprocessors and Graphics. LINK
http://www.ge-ip.com/support/embeddedsupport/locator.
Queries will be logged on the Technical Support database and allocated a unique Service Request (SR) number for use in future correspondence. Alternatively, you may also contact GE Intelligent Platforms’ Technical Support via: LINK
support.towcester.ip@ge.com
TELEPHONE
+44 (0) 1327 322760
1.8 Returns
If you need to return a product, there is a Return Materials Authorization (RMA) request form that can be printed out and filled in, available via the web site Support Locator page. LINK
http://www.ge-ip.com/support/embeddedsupport/locator.
Follow the RMA: Request Form (Word Doc) hyperlink under Digital Processing, Multiprocessors and Graphics. Do not return products without first contacting the factory. Publication No. SBC310-0HH/5
Introduction 17
2 • Unpacking
On receipt of the shipping container, if there is any evidence of physical damage, the Terms and Conditions of Sale (provided with your delivery) provide information on what to do. If you need to return the product, please contact your local GEIP Sales Office or Agent. The SBC310 is sealed into an antistatic bag and housed in a padded cardboard box. Failure to use the correct packaging when storing or shipping the board may invalidate the warranty. Figure 2-1 Box Contents
2.1 Box contents checklist:
1. SBC310 in antistatic packaging. 2. Manual CD‐ROM (design may vary). 3. Embedded Software License Agreement (GFJ353). 4. Quick Start Guide (where available) 18 SBC310 3U VPX Single Board Computer
2.2 Identifying Your Board
The SBC310 is identified by labels at strategic positions. These can be cross‐checked against the Advice Note provided with your delivery. Identification labels, similar to this, attached to the shipping box and the antistatic bag provide identical information: SBC310 product code, product description, equipment number and board revision. Figure 2-2 Product Label (Packaging)
On the board within the antistatic bag, there is an identifying label similar to this attached to the PCB. Figure 2-3 Product Label (Product)
On the conduction‐cooled version of the board (build level 4), there is also a label similar to this attached to the front panel. Figure 2-4 Product Label (Conduction-cooled Product)
See the Product Code Information section in Appendix A for more details on the product code (SBC310‐xxxxx). Publication No. SBC310-0HH/5
Unpacking 19
3 • Configuration – SBC310 Rev2
This chapter describes the configuration of links on the SBC310 as seen on Rev2. The board is delivered with push‐on jumper links, but for more rugged or military applications, link pins must be connected using wire wraps and conformal coated. NOTE
The SBC310 is shipped from the factory with no links fitted. Before changing any of the link options,
refer to the appropriate section(s) on the following pages.
Figure 3-1 Link Locations
Table 3-1 Link Functions
Link
Function when link is fitted, or as stated
P10, 1-2
P10, 3-4
P11, 1-2
P12, 1-2
P12, 3-4
P13, 1-2
Enable ScanBridge Tap o/ps
NVRAM Writes enabled when NVMRO signal is LOW
USB enabled
In - SMP Mode – No Offset
Out - AMP Mode – Core 1 has 256 MB Memory Offset
Bootswap (0)
Bootswap (1)
Recovery Boot Select
P13, 3-4
Flash protection unlocked. Persistent Flash sector protection can be altered
P14, 1-2
P14, 3-4
CPU Boot Sequencer disable
External program mode. Factory use only.
P11, 3-4
NOTE
Further functional description for each of the links follows.
3.1 Link Settings
TIP
If you are about to install your board and power-up for the first time, leaving your board in the default
configuration will enable board operation to be proven prior to tackling any further configuration
issues.
3.1.1
P10 (Pins 1-2) JTAG Scanbridge Output Enable Link
The SBC310 uses a JTAG Scanbridge device to connect all of the JTAG‐compliant devices on the board. This link is provided to enable the Scanbridge during boundary scan. It should not normally be fitted in deployed systems and must not be fitted when the BDM Header or PLD Programming Header on the Test Access Board are in use. 3.1.2
P10 (Pins 3-4) NVMRO Write Enable Link
When fitted, this link enable writes to the NVRAM. It also allows writes to the I2C and Serial Configuration EEPROMs to be enabled using Control Register 2. The state of this link is reflected in the Link Status Register. Not fitting this link ensures that software cannot corrupt any of the non‐volatile memory (apart from the Flash, which must be protected separately) during operation NOTE
This link works in conjunction with the NVMRO signal from the VPX backplane. The state of this signal
overrides the state of the link. I.e. The NVRAM is only write enabled when BOTH NVMRO is low AND the
link is fitted.
3.1.3
P11 (Pins 1-2) USB/PCI-X mode Link
The SBC310 includes an optional USB interface which is enabled by fitting this link. When fitted, the board operates in USB mode which restricts the PMC site to 64 bit/33 MHz PCI operation. When USB functionality is not required, the link can be removed and the PMC site operates with a 64 bit/133 MHz PCI‐X bus. 3.1.4
P11 (Pins 3-4) SMP Mode Link
When the two processing cores are running different operating systems, or different instance of the same operating system, the MPC8640(D)/MPC8641(D) provides the ability to offset Core 1 accesses to the bottom of RAM by 256 MBytes (addresses 0x0000000 to0x10000000 are offset to 0x10000000 to 0x20000000). This allows both processing cores to maintain separate stacks and private memory without any software intervention. This is the default mode selected with this link not fitted. When the two processors are operating in Symmetric Multi‐Processing (SMP) mode, this feature is not desirable as both processors need to share the same memory space. In this mode, the link can be fitted at P11 (Pins 3‐4) to disable this feature. The state of this link is reflected in the Link Status Register. Publication No. SBC310-0HH/5
Configuration – SBC310 Rev2 21
NOTE
If a single-core MPC8641 processor is fitted, the setting of this link has no effect.
3.1.5
P12 (Pins 1-2) & P13 (Pins 1-2) Core 0 Boot Area Selection
The Boot Flash for Processing Core 0 is divided into four sections, allowing for three different boot images to be loaded from the Flash. There is also a factory‐
programmed Recovery boot image. These links are used to select which image is used at boot time. The state of these links is reflected in the Link Status Register. Table 3-2 P12 (Pins 1-2) & P13 (Pins 1-2)
P12 (Pins 1-2)
P13 (Pins 1-2)
Active Core 0 Boot Image
Out
Out
Main boot image
In
Out
Alternate boot image
Out
In
Recovery boot image
In
In
2nd Alternate boot image
In normal operation, these links are not fitted and the SBC310 boots from the Main boot image. 3.1.6
Processing Core 1 may boot either from the same Flash image as Processing Core 0 or from its own Boot Flash, which is divided into four sections, allowing for three different boot images along with the factory‐programmed Recovery boot image. These links are used to select which of the Core 1 boot images is used at boot time, if selected. The state of these links is reflected in the Link Status Register. Table 3-3 P12 (Pins 3-4) & P13 (Pins 1-2)
P12 (Pins 3-4)
P13 (Pins 1-2)
Out
Out
Main boot image
In
Out
Out
In
Recovery boot image
In
In
P13 (Pins 3-4) Flash Protection Unlock Link
This link must be fitted to allow software to alter the persistent sector protection, which remains unchanged following a reset or a power‐cycle. See the Flash Sector Protection section for further details. If the link is not fitted, the software is prevented from altering any previously configured sector protection. The state of this link is reflected in the Link Status Register. 3.1.8
P14 (Pins 1-2) Boot Sequencer Disable
Fitting link P14(1‐2) prevents the loading of EEPROM configuration data by the MPC8640(D)/MPC8641(D). 22 SBC310 3U VPX Single Board Computer
3.1.9
P14 (Pins 3-4) External Programming Link
When fitted, this link configures the board at reset time so that all resources are visible to an external master to allow the board to be programmed from an external source. The processor’s cores are disabled allowing an external master to configure the PCI devices and program the FLASH remotely. The state of this link is reflected in the Link Status Register. NOTE
Factory use only
Configuration – SBC310 Rev2 23
4 • Configuration – SBC310 From Rev3
This chapter describes the configuration of links on the SBC310 since Rev3. The board is delivered with push‐on jumper links, but for more rugged or military applications, link pins must be connected using wire wraps and conformal coated. NOTE
The SBC310 is shipped from the factory with no links fitted. Before changing any of the link options,
refer to the appropriate section(s) on the following pages.
Figure 4-1 Link Locations
Table 4-1 Link Functions
Link
P11, 1-2
P11, 3-4
P12, 1-2
P12, 3-4
P13, 1-2
P13, 3-4
P14, 1-2
P14, 3-4
P18, 1-2
Function when link is fitted, or as stated
USB enabled
In - SMP Mode – No Offset
Out - AMP Mode – Core 1 has 256 MB Memory Offset
Bootswap (0)
Bootswap (1)
Flash protection unlocked. Persistent Flash sector protection can be altered
Enable ScanBridge Tap o/ps
External program mode. Factory use only.
Recovery Boot Select
NOTE
Further functional description for each of the links follows.
4.1 Link Settings
TIP
If you are about to install your board and power-up for the first time, leaving your board in the default
configuration will enable board operation to be proven prior to tackling any further configuration
issues.
4.1.1
P11 (Pins 1-2) USB/PCI-X mode Link
The SBC310 includes an optional USB interface which is enabled by fitting this link. When fitted, the board operates in USB mode which restricts the PMC site to 64 bit/33 MHz PCI operation. When USB functionality is not required, the link can be removed and the PMC site operates with a 64 bit/133 MHz PCI‐X bus. 4.1.2
P11 (Pins 3-4) SMP Mode Link
When the two processing cores are running different operating systems, or different instance of the same operating system, the MPC8640(D)/MPC8641(D) provides the ability to offset Core 1 accesses to the bottom of RAM by 256 MBytes (addresses 0x0000000 to 0x10000000 are offset to 0x10000000 to 0x20000000). This allows both processing cores to maintain separate stacks and private memory without any software intervention. This is the default mode selected with this link not fitted. When the two processors are operating in Symmetric Multi‐Processing (SMP) mode, this feature is not desirable as both processors need to share the same memory space. In this mode, the link can be fitted at P11 (Pins 3‐4) to disable this feature. The state of this link is reflected in the Link Status Register. NOTE
4.1.3
The Boot Flash for Processing Core 0 is divided into four sections, allowing for three different boot images to be loaded from the Flash. There is also a factory‐
programmed Recovery boot image. These links are used to select which image is used at boot time. The state of these links is reflected in the Link Status Register. Table 4-2 P12 (Pins 1-2) & P18 (Pins 1-2)
P12 (Pins 1-2)
P18 (Pins 1-2)
Out
Out
Main boot image
In
Out
Out
In
Recovery boot image
In
In
In normal operation, these links are not fitted and the SBC310 boots from the Main boot image. Publication No. SBC310-0HH/5
Configuration – SBC310 From Rev3 25
4.1.4
Processing Core 1 may boot either from the same Flash image as Processing Core 0 or from its own Boot Flash, which is divided into four sections, allowing for three different boot images along with the factory‐programmed Recovery boot image. These links are used to select which of the Core 1 boot images is used at boot time, if selected. The state of these links is reflected in the Link Status Register. Table 4-3 P12 (Pins 3-4) & P18 (Pins 1-2)
P12 (Pins 3-4)
P18 (Pins 1-2)
Out
Out
Main boot image
In
Out
Out
In
Recovery boot image
In
In
P13 (Pins 1-2) NVMRO Write Enable Link
overrides the state of the link. I.e. The NVRAM is only write enabled when BOTH NVMRO is low AND the
link is fitted.
4.1.6
P13 (Pins 3-4) Flash Protection Unlock Link
This link must be fitted to allow software to alter the persistent sector protection, which remains unchanged following a reset or a power‐cycle. See the Flash Sector Protection section for further details. If the link is not fitted, the software is prevented from altering any previously configured sector protection. The state of this link is reflected in the Link Status Register. 4.1.7
P14(Pins 1-2) JTAG Scanbridge Output Enable Link
The SBC310 uses a JTAG Scanbridge device to connect all of the JTAG‐compliant devices on the board. This link is provided to enable the Scanbridge during boundary scan. It should not normally be fitted in deployed systems and must not be fitted when the BDM Header or PLD Programming Header on the Test Access Board are in use. 26 SBC310 3U VPX Single Board Computer
4.1.8
P14 (Pins 3-4) External Programming Link
Factory use only
Configuration – SBC310 From Rev3 27
5 • Installation and Power Up/Reset
Review the Safety Notices section before installing the SBC310. The following notices also apply: CAUTION
The SBC310 has been specifically designed for use with 3U VPX backplanes and is not compatible with
6U backplanes. Plugging the SBC310 into a 6U backplane may cause permanent component damage.
Consult the enclosure documentation to ensure that the SBC310’s power requirements are
compatible with those supplied by the backplane.
The SBC310’s power requirements are up to 8A @ 5V from VS3, operating within VPX Specification limits (5V +5% ‐2.5%). And 2.5A @3.3V from VS2 operating within VPX specification limits (3.3V ‐0.05V/+ 0.15V) 5.1 Board Keying
The 3U VPX backplane specification requires all backplane slots to have two guide pins: one above the J0 connector and one below the J2 connector. As well as providing correct alignment, these pins are keyed to prevent cards being inserted into incorrect backplane slot(s) to avoid electrical incompatibility. The SBC310 has receptacles for these guide pins (see the Connectors section). By default, these are not keyed. Please contact the factory to discuss keying requirements. 5.2 Board Installation Notes
1. Keying may dictate the backplane slot(s) into which the SBC310 can be inserted. Apart from this, as the VPX specification does not specify a standard pinout (except P0), the backplane slot position depends on the system configuration (i.e. unlike VME and CompactPCI, there is no dedicated System Controller position). 2. Air‐cooled versions of the SBC310 have an injector/ejector handle to ensure that the backplane connectors mate properly with the backplane. The captive screws at the top and bottom of the front panel allow the board to be tightly secured in position, which provides continuity with the chassis ground of the system. 3. Conduction‐cooled versions of the SBC310 have screw‐driven wedgelocks at the top and bottom of the board to provide the necessary mechanical/thermal interface. Correct adjustment requires a calibrated torque wrench with a hexagonal head of size 3/32” (2.38 mm), set to between 0.6 and 0.8 Nm. 4. In an air‐cooled development enclosure, when taking I/O connections from the backplane connectors, use of GEIP I/O modules (or some equivalent system) ensures optimum operation of the SBC310 with regard to EMI. See overleaf for more details on the I/O modules. 28 SBC310 3U VPX Single Board Computer
5.3 Connecting to the SBC310
To interact with on‐board firmware requires the SBC310 to have, as a minimum, a control terminal or HyperTerminal connection present on the serial COM1 port. An Ethernet connection may also be required for Host/Target interaction. For development systems, connection to the Serial and Ethernet I/O can be achieved using a Rear Transition Module (RTM). This converts the condensed pin out of the backplane connectors to pinouts suitable for use by industry standard connectors. The following items are required: •
The SBC310 •
A Rear Transition module (VPX3UX600 or VPX3UX300) •
A null‐modem 9‐way D‐type cable for connecting COM1 to a control terminal or HyperTerminal •
For the Ethernet ports, a CAT5 (or better) straight‐through patch cable for 10/100/1000BaseTX The VPX I/O Modules Manual, publication number VPXIOM‐0HH, contains more details on fitting Rear Transition Modules. Similar antistatic and safety precautions apply when handling and/or installing I/O modules as for the SBC310. COM1 is configured as DTE with default settings of 9600 baud, 8 bits/character, 1 stop bit, parity disabled and no flow control. 5.4 Reset & Power-up Sequence
5.4.1
On-board sequencing
Several components on the board have specific power sequencing requirements which need to be met. The SBC310 uses the Lattice ispPAC Power Manager device to sequence the power supplies in the appropriate order. The power manager also monitors the backplane supply voltages and holds the board in reset if these fall below their specified levels. Additionally, when power is first applied, the power manager will not start the on‐
board supplies if the backplane supplies are not within specified limits. The power manager will shut down all on‐board supplies (except VCC and P3V3_AUX) when the BMM_OFF signal is asserted by the Board Management Microcontroller, or when the Test Access board is used to reprogram the power manager device. The power manager is connected to the on‐board I2C Bus 2, allowing software read‐
out of the voltages of all on and off‐board supplies. The 5V supply to the PMC site is switched, under the control of the power manager device, so that the 5V and 3.3V supplies are applied to the PMC card at approximately the same time. Publication No. SBC310-0HH/5
Installation and Power Up/Reset 29
5.4.2
Inter-board sequencing
The SBC310 supports inter‐board power sequencing. This allows for the sequencing of power between a number of boards in a system to be controlled, and as a result, minimises in‐rush current demands on the system power supply. This is achieved by the PSU_SEQ_OUT and PSU_SEQ_IN signals which can be daisy‐chained between boards. The SBC310 drives the PSU_SEQ_OUT signal low when the backplane supplies are out of specification and holds it low until all on‐boards supplies are within specification. The PSU_SEQ_OUT signal is not driven low when the power is removed as a result of the BMM_OFF signal being asserted. The SBC310 holds off all on‐board supplies (except P3V3_AUX) when the PSU_SEQ_IN signal is held low. The power‐on sequence is initiated if the PSU_SEQ_IN signal remains low 500ms after the off‐board supplies are within specification, which may occur if the previous board in the chain fails. 5.4.3
Power-up sequence
The SBC310 power‐on‐reset sequence has the following order. NOTE
Typically, the complete power-up sequence will take approx 100ms.
1. Drive PSU_SEQ_OUT low. 2. Wait for the VS2 and VS3 to reach valid levels. 3. Wait for PSU_SEQ_IN signal to be high, or low for 500 ms. 4. Start Phase 1 on‐board power supplies 5. Wait for all phase one on‐board supplies to become valid. 6. Start phase 2 on‐board supplies 7. Wait for phase 2 on‐board power supplies to become valid. 8. Start phase 3 on‐board power‐supplies 9. Wait for phase 3 on‐board supplies to become valid. 10. Light power‐good LED and drive power‐good signal to on‐board logic. Release PSU_SEQ_OUT. 11. Drive the hard reset signal for a period of 20 ms. (This will proporgate onto the VPX backplane if the board is a system‐controller.) 30 SBC310 3U VPX Single Board Computer
6 • Functional Description
Figure 6-1 SBC310 Block Diagram
NOTE
Due to the increasingly short lifetimes of system components, the I/O devices used on the SBC310 are
not guaranteed to remain fixed in the future.
Hardware should be accessed only through mechanisms provided by the Operating System’s Board
Support Package, and not directly by application software.
If a standard operating system is not being used, then it is recommended that applications are written
in such a way as to minimize direct access to hardware resources, bearing in mind that changes may
be necessary to support future iterations of the hardware.
GEIP supported Operating Systems guarantee compatibility at the application level through hardware
independent mechanisms.
CAUTION
SBC310 Rev2 and Rev3 boards have slightly different confirguration link layout. Please refer to
Chapters 3 and 4 respectively when considering the link information in this chapter.
Functional Description 31
6.1 Features
•
Freescale MPC8641D or MPC8640D Integrated Host Processor with dual processing cores at 1067 MHz OR •
Freescale MPC8641 or MPC8640 Integrated Host Processor at up to 1.33 GHz •
Two x4 PCI Express links •
Up to 2 GBytes dual‐channel DDR2 memory with ECC •
Up to 512 MByte of Flash memory with enhanced write‐protection features •
128 kBytes Non‐Volatile RAM with power‐down AutoStore •
PCI Express board interconnect with non‐blocking switch architecture •
Mezzanine site supporting PMC and XMC modules. The PMC interface has a 64 bit PCI bus which can optionally operate in PCI‐X mode up to 133 MHz. The XMC interface has a x8 PCI Express link. •
Two 10/100/1000BASE‐T Ethernet ports •
Two Serial I/O channels (RS232/422) •
Two optional USB 2.0 ports •
Up to two Serial ATA disk interfaces (up to 3.0 Gbits/s) •
Up to 6 bits of General Purpose I/O with interrupt capability •
Real‐time clock •
Elapsed time indicator •
Watchdog timers •
CPU die and ambient temperature sensors •
Five environmental build levels 32 SBC310 3U VPX Single Board Computer
6.2 Integrated Host Processor
The SBC310 is based around the Freescale MPC8640(D)/MPC8641(D) Integrated Host Processor and fully supports the MPC8641 and the MPC8640 single core versions. The MPC8640(D) are a low power versions of the MPC8641(D)parts, but are otherwise functionally identical. Providing: •
Dual e600 PowerPC processing cores (dual core variants only) •
Internal MPX bus •
Dual DDR2 Memory Controllers •
PCI Express Interface •
Gigabit Ethernet Interfaces •
Local Bus Interface •
I2C Interfaces •
Serial I/O Interfaces •
DMA Engines •
Interrupt Controller 6.2.1
PowerPC Processing Cores
The MPC8640/1D contain two e600 high‐performance, 32‐bit, superscalar, PowerPC processing cores, as used in the MPC7448 processor, clocked at up to 1.33 GHz. Each core includes: •
32 kByte Level 1 instruction and data caches •
1 MByte Level 2 backside cache with ECC •
36‐bit physical addressing •
AltiVec Vector Unit •
Enhanced branch prediction capabilities •
MMU and integral FPU The e600 processing core implements a fully static architecture and offers sophisticated power management capabilities. Table 6-1 Processor Core Frequency Options
Processor Type
Core Frequency (MHz)
MPX Bus Frequency (MHz)
MPC8641D
1000
400
MPC8641
1333
533
MPC8640/D
1067
533
6.2.2
Dual Processing Cores
The MPC8640/1D contains two processing cores. Following reset, Processing Core 1 is prevented from accessing the MPX bus until it is enabled by Core 0. The two processing cores are able to run two different operating systems or two separate instances of the same operating system. This is called Asymmetric Multi‐
Processing (AMP) Mode. This mode is aided by the Low Memory Offset Mode of the MPC8641D, which is able to apply a 256 MByte address offset to accesses by Core 1 to the bottom of RAM (addresses 0x0000000 to 0x10000000 are offset to 0x10000000 to 0x20000000). This allows both processing cores to maintain separate stacks and private memory without any software intervention. The two processor cores are also able to run a single operating system, with tasks divided between them. This is called Symmetric Multi‐Processing (SMP) mode. In this mode, the Low Memory Offset feature is not desirable as both processors need to share the same memory space. MPX Bus
The MPX bus, connecting the processing cores to the host bridge functions, is integrated into the device and therefore is able to run at up to 533 MHz, more than twice as fast as an external implementation. This gives increased memory bandwidth and reduced latency, giving a significant performance increase. 6.3 Memory
6.3.1
Memory Map
The SBC310 supports a fully programmable memory map, defined by the MPC8641D. No memory maps are provided in this manual as no memory locations are fixed in hardware. Refer to the applicable software manual for more information. 6.3.2
System RAM
The MPC8640(D)/MPC8641(D) contains dual 64‐bit DDR2 memory controllers and has the ability to interleave accesses between the two controllers to further increase the available RAM bandwidth. The controllers have full ECC error‐correction support, with the ability to detect multi‐bit errors and correct single‐bit errors within a nibble. The SBC310 provides a total of either 1 GBytes or 2 GBytes of DDR2 SDRAM, split between the two memory controllers. The RAM configurations are defined below. Table 6-2 RAM Configurations
Total RAM
RAM Per Controller
No. of Banks/Controller
Device Size
Bus Speed (MHz)
1 GBytes
512 MBytes
8
64Mx16
266
2 GBytes
1 GByte
8
128Mx16
266
6.3.3
Flash
The SBC310 supports up to 512 Mbyte of Flash memory, with 256 MBytes fitted as standard. The Flash devices are configured as two banks, each with a 16‐bit wide device. The Flash supports page‐mode accesses to allow for maximum bus bandwidth and must be written to as 16‐bits. The Flash in each bank is arranged in 256 kByte sectors, has an erase capacity of 100,000 cycles per sector and typical data retention of 20 years. NOTE
Integrity of Flash data cannot be guaranteed if a hard reset occurs during a Flash write cycle.
The following table shows the Flash options available for the SBC310: Table 6-3 Flash Options
Flash Size (MBytes)
Banks
Flash Bank Organization
256
2
2 x 1024 Mbit
512
2
2 x 2048 Mbit
The Flash is divided into two area types: Boot Flash and User Flash. The top 8 MBytes of each bank are useable as Boot Flash for each of the two processing cores. These each hold four 2 MByte boot images that may be selected using hardware links. The remainder of the Flash memory is allocated as User Flash. Figure 6-2 Flash Memory Structure
Boot Flash
The top 8 MBytes on each of the Flash memory is useable as Boot Flash, and is used to hold initialization and operating system boot routines. Each of the 8 MByte regions are used to hold boot images for one of the processing cores and are divided into four 2 MByte boot images. When a single‐core device is used or a separate boot image for Core 1 is not required, the second 8 MByte region may be utilized as User Flash. The Recovery Boot image contains a 256 kByte factory‐programmed boot image, shared by both processing cores, allowing the Flash to be reprogrammed if other boot images become corrupted. This area is protected by hardware and is not writeable by the user. The remainder of this 2 MByte boot image can be used to store BIT results. The boot flash is accessed using Chip Select 0 on the Local Bus Controller of the MPC8640(D)/MPC8641(D), and is configured as the default boot location for the PowerPC reset vector (0xFFF00100). The boot areas are mapped into a 16 MB window as shown below. Figure 6-3 Local Bus CS0 Mapping
The active boot image for each processing core is selected using the appropriate links, as described in Sections 3.1.5 /3.1.6 and 4.1.3 /4.1.4 . The Core 1 boot region is made active by setting the Core 1 Enable bit in the Flash Control Register. Core 0 should boot normally from its boot region and then, if a separate boot image is required for Core 1, set this bit before allowing the other core to boot. User Flash
Any Flash which is not used as Boot Flash is designated as User Flash and is intended to hold user application code or data. User Flash is accessed using Chip Selects 1 and 2 on the Local Bus Controller of the MPC8640/1D. Chip Select 1 is intended for use by Processing Core 0 and may be used to access all areas of Flash, as required when using a single‐core or SMP system, and Chip Select 2 is intended for use by Processing Core 1 and may only access the lower area of Flash. When Core 1 is using Chip Select 2 to access Flash, Core 0 should not normally use Chip Select 1 to access these same areas to ensure private access for Core 1. 36 SBC310 3U VPX Single Board Computer
The 8 MBytes of Boot Flash appears at the top of the User Flash area, with the four boot images appearing in their physical locations (as shown in Figure 6‐4) unaffected by the state of the Flash Boot Image Select links. Figure 6-4 User Flash Chip Select Mapping
MAC Address
Mirror Mode
The Recovery Boot Area is present in User Flash, only in the top sector of Flash Bank 0 accessed via Chip Select 1. This area also contains the board’s serial number and MAC addresses, which may be required by Processing Core 1. There is a function to “mirror” the top sector of Flash Bank 0 to Flash Bank 1 to allow this to be invisible to software. This mode is controlled by the Flash Control Register and is enabled by default, though it may be disabled as this feature is not desirable in a single processor or SMP mode. Paged Flash
Mode
Due to limitations on the size of the processor memory map, a paged mode is provided where the User Flash area is divided into a number of 128 MByte pages, with separate pages selectable for Chip Select 1 and Chip Select 2. This mode is controlled by two flash page registers located in the Flash Control Register. This is to allow each core to access its bank of flash independently. Because Chip Select 1 needs access to both banks of flash (for SMP operation and to allow core 0 programming of core 1 boot area) then Chip Select 1 needs twice as many pages as Chip Select 2. For this reason, Chip Select 1 page register is one bit larger than the CS2 page register Paged mode is enabled by default, with each Chip Select pointing to the top page of Flash. The diagram below shows how flash paging is organized for the two different device densities. Publication No. SBC310-0HH/5
Figure 6-5 Flash Paged Access Mode
Flash Sector
Protection
The SBC310 uses Spansion S29GLxxGP Flash devices, which provide advanced methods of sector protection to ensure the integrity of code data contained in the Flash array. Protection is defined on a per‐sector basis, where a sector is 256 kBytes in size. Locked sectors cannot be erased or programmed; they may only be read. No write protection of Flash is provided by hardware. Software must be used to configure the Flash devices to protect against corruption of Flash data. The following types of protection are provided: 1. Persistent sector protection provides non‐volatile protection that remains in place when a board is power cycled or reset. Each Flash sector may be set to be locked (write‐protected) or unlocked (write‐enabled) by writing to configuration registers within the Flash. The configuration of this protection is only possible when the Flash Protection Unlock Link is fitted (Sections 3.1.7 /4.1.6 ) and the backplane NVMRO signal is negated. If this link is not fitted, the software is unable to change the sector protection and those sectors that are locked may not be erased or reprogrammed under any circumstances. 2. Non‐persistent protection may also be used. This protection is only present until a power cycle or hardware reset occurs and may be modified by user software. NOTE
Sectors that are locked using the Persistent mode may not be unlocked using this mechanism.
NOTE
Do not rely on non-persistent protection, as it may be subsequently altered by software. If further
protection is required, use the Persistent protection method.
For further details of these protection mechanisms, refer to the S29GL01P 1 Gbit page‐mode Flash data sheet. 38 SBC310 3U VPX Single Board Computer
Non-Volatile
RAM (NVRAM)
The SBC310 has a 128kByte NVRAM device for non‐volatile set‐up and configuration data storage. The NVRAM used is a Simtek STK14CA8, which is configured as an 8‐bit wide device and is accessed using Chip Select 3 on the Local Bus Controller of the MPC8640(D)/MPC8641(D). The NVRAM is write‐protected when the NVMRO Link is removed (Sections 3.1.2 /4.1.5 ) or when the NVMRO backplane signal is asserted. The status of the link and NVMRO backplane signal may be read back in the Link Status Register. 6.4 PCI Express Infrastructure
All on‐board PCI devices and mezzanine sites are connected to the using PCI Express. The PCI Express and PCI structure of the SBC310 is shown in Figure 6‐1. PCI Express is a high‐speed serial, point‐to‐point interconnect running at 2.5 Gbits/s in each direction. PCI Express links are scalable, meaning that multiple lanes can be used between devices to increase the aggregate bandwidth. A comparison of the bandwidth of PCI Express links with PCI implementations are shown in the table below. Table 6-4 PCI Bus
Bus Type
Bus Width
Frequency
Bandwidth
PCI
32-bit
33 MHz
133 MBytes/s
PCI
32-bit
66 MHz
266 MBytes/s
Notes
PCI
64-bit
66 MHz
533 MBytes/s
PCI-X
64-bit
133 MHz
1066 MBytes/s
PCIe
x1
2.5 Gbps
250 MBytes/s
Per Direction
PCIe
X2
2.5 Gbps
500 MBytes/s
Per Direction
PCIe
x4
2.5 Gbps
1000 MBytes/s
Per Direction
PCIe Bandwidths shown include 8b/10b encoding overheads
PCI Express is a packet‐based protocol but uses the same address spaces as standard PCI meaning that the software interfaces are backwards‐compatible. PCIe‐to‐PCI Bridges are used to convert to PCI‐X or standard PCI where connection to these devices is required. The maximum packet payload size for the PCI Express sub‐system is 256 Bytes. CRC error‐checking is performed on each packet transmitted between devices in the system and any corrupted packets are retransmitted. End‐to‐end error‐checking can also be performed by the target device, to ensure integrity of the received data. Publication No. SBC310-0HH/5
MPC8640(D)/MP
C8641(D)
The MPC8640(D)/MPC8641(D) has two high‐speed I/O ports. The SerDes1 port is configured as a x4 PCI Express link and is connected to Port 0 of the PCI Express Switch. The port is able to operate in x1, x2, or x4 modes. This port is normally configured as the system Root Complex but when the External Programming Link is fitted (Sections 3.1.9 /4.1.8 ), the configuration is changed such that this port becomes a PCIe Endpoint. This allows configuration transactions to be accepted, to allow programming of the Boot Flash from a PMC card. The SerDes2 port is configured as a x8 PCI Express link and is routed to the XMC J15 connector. 6.4.1
PCI Express Switch
The SBC310 uses a PLX PEX8518 PCI Express switch to connect all of the various PCI Express devices together. This is a 16‐lane, non‐blocking switch which can support up to 6 PCI Express ports. The device also supports cut‐thru mode to reduce packet latency. Each PCI Express port of the PEX8518 appears to software as a PCI‐to‐PCI bridge, with its own PCI‐ compatible configuration registers. Each port is accessed on the internal virtual PCI bus using a device number equal to its port number. A serial EEPROM is used to configure registers within the device at power‐up. This allows the operating system to reconfigure some properties of the switch, such as non‐transparent‐port selection etc. This EEPROM is write‐protected by default and can be write‐enabled by software only when the NVRMO Link is fitted (Sections 3.1.2 /4.1.5 ) and the NVMRO signal on the VPX backplane is negated. CAUTION
Programming of the configuration EEPROM should only be done under the control of the operation
system. Mis-programming of this part can result in unwanted effects on the SBC310, and can even
stop the board booting.
In the event of this EEPROM device becoming corrupted, it is possible to prevent the EEPROM being loaded at reset by fitting the Recovery Link (Sections 3.1.5 /3.1.6 and 4.1.3 /4.1.4 ) and booting the board from the recovery boot region. In this case, the switch configuration is defined by hardware strapping. The port configuration of the switch is set as follows: Table 6-5 PCI Express Port Configuration
Port No.
Port Width
Lane Nos
Link To
0
X4
0–3
MPC8640(D)/MPC8641(D) SerDes Port 1
1
x4
4–7
VPX port A
2
x4
8 – 11
VPX port B
8
x2
12– 13
PEX8114 PCI-X bridge
9
x1
24 – 31
SIL3132 SATA bridge
Each port is able to negotiate down to smaller link widths if required (such as if a fault occurs on any particular lane). Port widths of x1, x2, and x4 are supported. 40 SBC310 3U VPX Single Board Computer
Port 0 is connected to the MPC8461D and is usually configured as the upstream port. When the External Programming Link is fitted (Sections 3.1.9 /4.1.8 ), the configuration is changed such that an alternate port is the upstream port. This allows configuration transactions to be forwarded from VPX or the PMC site to the processor, to allow programming of the Flash from an external host. The PEX8548 is connected to on‐board I2C Bus 1 (Address 0xB0) to allow configuration by the processor and out‐of‐band monitoring of link status. The status of all of the on‐board links, and the two VPX links can be determined from LEDs on the rear of the board. (See LED section) Further status information (number of active lanes, etc.) can be ascertained from registers within the switch. 6.4.2
PCI Express to PCI Bridge
The SBC310 uses the PLX PEX8114 bridge to connect to it’s PCI bus. The bridge can operate in forward (PCIe‐to‐PCI) or reverse (PCI‐to‐PCIe) mode but is normally used in forward mode on the SBC310. The bridge is connected to the switch via a x2 PCI Express link, allowing a maximum bandwidth of 500 MBytes in each direction. The PCI/PCI‐X interface is 64‐bits wide and can operate at frequencies up to 133 MHz. The bridge generates the clock outputs to external PCI/PCI‐X devices. It samples the PCIXCAP and M66EN signals to determine the correct operating frequency for the PCI bus and drives the PCI‐X initialization pattern during reset. The current operating frequency of each bus may be ascertained by reading registers within the PEX8114. The bridge also contains the arbiter for the PCI bus. This supports up to 4 external masters and the priority of each is programmable. The bridge is initially configured by hardware strapping, but has a serial EEPROM which can also be used to configure registers within the device if required. The EEPROM is write‐enabled by software only when the NVRMO Link is fitted and the NVMRO signal on the VPX backplane is negated. CAUTION
Programming of the configuration EEPROM should only be done under the control of the operation
The PEX8114 is able to report any errors detected to the processor via PCI Express using legacy interrupt messages or Message Signalled Interrupts. 6.4.3
PCI Bus
The PCI bus on the SBC310 is connected to the NEC UPD720101 USB2.0 controller and the PMC site. Because the USB controller is a 33 MHz PCI device, the PCI bus falls back to 33 MHz when this is connected. For this reason, it is possible to disable the USB device by removing the USB Mode Link (Sections 3.1.3 /4.1.1 ) which allows the PCI to operate in PCI‐X mode. Publication No. SBC310-0HH/5
When in PCI‐X mode, the bus will automatically switch to the correct operating frequency (up to 133 MHz) for the PMC card fitted. The current operating frequency of each bus may be ascertained by reading registers within the PEX8114 The device number mapping for the PCI devices are as follows: Table 6-6 PCI Devices
Device No.
IDSEL
Function
0
16
Not implemented
1
17
USB controller
2
18
PMC Device A
3
19
PMC Device B
4
20
PEX8114 Bridge
5 to 15
21 to 31
Not implemented
The PEX8114 bridge is changed into reverse mode when the External Program link is fitted – see Sections 3.1.9 /4.1.8 . This allows configuration transactions to be forwarded from PMC Site 1 to the processor, to allow programming of the Flash from a PMC card. 6.5 Local Bus
The MPC8461D local bus is a 32‐bit multiplexed address/data bus, which is used to access the following devices on the SBC310: •
Local Bus Control FPGA •
FLASH •
NVRAM The Flash and NVRAM address lines are connected to a de‐multiplexed address bus created by the Local Bus Control FPGA. The MPC8640(D)/MPC8641(D) local bus controller provides 8 chip selects, which are allocated to devices as defined in the table below. The minimum possible window size is 32 kBytes. Table 6-7 Flash Memory Allocation
Local Bus Chip Select
CS0
Target
Boot FLASH
Device Width
16-bit
CS1
User FLASH 0
16-bit
CS2
User FLASH 1
16-bit
CS3
NVRAM
Control / Status Registers
Interrupt Controller
Watchdogs
8-bit
Window Size
16 MBytes
128 MBytes in Paged Mode
Up to 512MBytes otherwise
128 MBytes in Paged Mode
Up to 512 MBytes otherwise
128 kBytes
32-bit
32 kBytes
-
-
CS4
CS5-CS7
Unused
6.5.1
Local Bus Control FPGA
The Local Bus Control FPGA is a Lattice MachXO device which provides the following functions: •
Local bus address latching and chip select generation for Flash/NVRAM •
Control/Status registers •
Watchdogs •
GPIO controller •
Secondary interrupt controller 6.6 Input/Output
The SBC310 has a wide variety of possible I/O connectivity, including the following ports: •
Ethernet •
Serial Ports •
USB •
Serial ATA •
General Purpose I/O 6.6.1
Ethernet
The MPC8640(D)/MPC8641(D) has four on‐chip enhanced three‐speed Ethernet Controllers (called eTSECs). These incorporate a media access controller (MAC) which supports 10/100/1000BaseT and half‐ and full‐duplex operation. The eTSECs support a number of TCP offload features (including checksum generation and verification) which reduce the amount of software interaction required. Jumbo frames are also supported. The SBC310 uses two of these controllers to provide external Ethernet interfaces. eTSEC1 and eTSEC3 are used as these have independent connections to the platform bus. The controllers are connected via a GMII interface to Marvell 88E1111 PHYs. The PHYs are isolated from the backplane using transformer‐coupled magnetics. The network (MAC) addresses are factory configured. The phy’s are configured at power‐up to have MDI addresses of 0x1 and 0x3, corresponding to the eTSEC port to which they are connected. Four status LEDs are provided on the rear of the board to allow the status of each Ethernet interface to be monitored. Publication No. SBC310-0HH/5
6.6.2
Serial Ports
COM1 and COM2 , which are available through the P1 and P2 connectors, are provided by the DUART module within the MPC8640(D)/MPC8641(D), and are intended to operate as debug ports for the two processing cores. Each of the two UARTs provide 16‐byte FIFOs and are software‐compatible with the PC16450 and PC16550D UART devices. Hardware flow control (RTS/CTS) is supported. The baud rate is software programmable between, and is derived from, the MPX bus frequency using the following equation: Baud Rate = (1/16) * (MPX Bus Frequency / Divisor Value) The table below shows the divisors used for some commonly used baud rates and the percentage error associated with the use of an integer divider. NOTE
The percentage error will increase significantly at higher baud rates. Different divisors will be required
if a different MPX Bus Frequency is used.
Table 6-8 Baud Rate Devisors
Target Baud
Rate
MPX Bus Freq
(MHz)
Divisor (Dec)
Divisor (Hex)
Actual Baud Rate
Error (%)
9600
400
2604
0A2C
9600.61
0.0064
19200
400
1302
0516
19201.23
0.0064
38400
400
651
028B
38402.46
0.0064
56000
400
446
01BE
56053.81
0.0961
128000
400
195
00C3
128205.13
0.1603
256000
400
98
0062
255102.04
-0.3508
The serial ports are driven by a single ISL41334 bus transceiver and both ports can be software configured through Control Register 1 to operate in RS232 or RS422 mode, though the flow control signals are not available in RS422 mode (seeTable 6‐9). Table 6-9 RS232/422 configuration
Signal
Direction
SBC310 configuration
RS232
RS422 (Rev2)
RS422 (Rev3)
COM1_TXD
Out
COM1_TXD
Not available
COM1_TXD_A
COM1_RXD
In
COM1_RXD
Not available
COM1_RXD_A
COM1_RTS
Out
COM1_RTS
Not available
COM1_TXD_B
COM1_CTS
In
COM1_CTS
Not available
COM1_RXD_B
COM2_TXD
Out
COM2_TXD
COM2_TXD_A
COM2_TXD_A
COM2_RXD
In
COM2_RXD
COM2_RXD_A
COM2_RXD_A
COM2_RTS
Out
COM2_RTS
COM2_TXD_B
COM2_TXD_B
COM2_CTS
In
COM2_CTS
COM2_RXD_B
COM2_RXD_B
The transceivers are capable of up to 400 kbaud operation in RS232 mode and up to 20 Mbaud in RS422 mode. The performance of these ports will be limited by the throughput capability of the software driver. 44 SBC310 3U VPX Single Board Computer
6.6.3
USB
An NEC μPD720101 device is used to provide two USB ports on the SBC310 and is connected to the PCI bus. The device is capable of operation at low‐, full‐ or high‐
speed. The device contains two OHCI controllers (for USB1.1 operation) and one EHCI controller (for USB2.0 operation). Alternate ports use a different OCHI controller for USB1.1 operation and both ports share the EHCI controller for USB2.0 operation. The internal functions are configured as follows: Table 6-10 USB Device Functions
Controller
PCI Function No
Interrupt
SBC310 Connection
OHCI0
0
INTA~
USB port 0
OHCI1
1
INTB~
USB port 1
EHCI
2
INTC~
USB port 0 & 1
An in‐line common‐mode choke is fitted to the USB I/O pairs to filter high frequency noise. This improves signal integrity and helps to reduce EMI emissions. When the board is operating in PCI‐X mode (see Sections 3.1.3 /4.1.1 ) the USB controller is disabled, and is invisible to software. The USB ports are available on the P1 connector. 6.6.4
Serial ATA
A Silicon Image Sil3132 device is used to provide two Serial ATA ports from the SBC310, supporting Generation 2 transfer speeds of at 3.0 Gbits/s. The device is connected to the PEX8518 switch via a x1 PCIe link. Two channels (channel 0 and channel 1) are provided on the SBC310, although channel 1 is a build option and shares pins with some GPIO signals. Channel 0 is present on all variants of the SBC310. When channel 1 is present, the relevant bit in the Board Configuration Register is set. See variant ordering information for more information on how to order this option. An activity LED is provided on the rear of the board, indicating SATA activity on channel 0 and channel 1. 6.6.5
General Purpose I/O
The SBC310 supports up to 6 General Purpose I/O, each with interrupt generation capabilities. These are 3.3V single‐ended signals with 5V tolerance. These signals are controlled by the Local Bus FPGA and can be configured as inputs, with the ability to generate level‐ or edge‐triggered interrupts, or outputs, with totem‐pole or open‐
drain drivers. Each GPIO bit input is protected by quick switch devices, which will limit the input voltage seen by the Local Bus Control FPGA to a safe level. Electrical characteristics of the GPIO pins can be found in the Specifications section. Some GPIO pins are dual function and do not act as GPIO lines in all build options. The table below summarizes which GPIO lines are dual function. Also see Connector and Product Codes sections for more information. Publication No. SBC310-0HH/5
Table 6-11 GPIO Functions
P1 Wafer
GPIO line
Secondary function
D11
0
SATA ch 1 Tx+ (configured by build option)
E11
1
SATA ch 1 Tx- (configured by build option)
B12
2
SATA ch 1 Rx+ (configured by build option)
C12
3
SATA ch 1 Rx- (configured by build option)
E12
4
AXIS Timer Reset (configured by software)
F12
5
BIT Fast-Start input (configured by BIT software)
OR
AXIS Timer Clock (Configured by software)
All GPIO registers are in the Local Bus FPGA, and are defined later in this section. 6.7 I2C
The MPC8640(D)/MPC8641(D) provides two I2C busses. The I2C architecture of the board is shown in the figure below. Figure 6-6 I2C Architecture
I2C Bus 1 connects to the real‐time clock, MPC8640(D)/MPC8641(D) Configuration EEPROM, and the PEX8518 PCIe switch. All other devices with an I2C interface are connected to bus 2 to allow monitoring, either by the processor or by an external device via the Board Management Microcontroller. 46 SBC310 3U VPX Single Board Computer
6.7.1
Addressing
2
Table 6-12 I C Buses
Bus 2
Device
Address (Hex)
PSU Manager
80
Board Temp Sensor
Core Temp Sensor
Elapsed-Time Indicator
BMM
90
98
D6
See Table 6-13
Bus 1
Device
MPC8640(D)/MPC8641(D)
Config EEPROM
Real-Time Clock
PEX8518 PCIe Switch
PCIe Clock Generator
Address (Hex)
A0
A2
E0
DC
The I2C devices connected to the on‐board I2C busses use the addresses shown in the table below. These are the byte addresses that would be used to write to the device on the bus (i.e. the 7‐bit device address and the least significant bit set to ‘0’). 6.7.2
Real-Time Clock
The SBC310 provides an Epson RX8581 real‐time clock device with a minimum of 1 second resolution. The real‐time clock is able to be powered from the VBAT signal when the main power supply is removed. The interrupt output of the real‐time clock is able to generate an interrupt to either processor core, via the Local Bus FPGA. 6.7.3
Elapsed Time Indicator
A Dallas DS1682 elapsed‐time indicator is provided to log the amount of time the board is powered and the number of power cycles. 6.7.4
Temperature Sensors
The SBC310 has two temperature sensors. An ADT7461 temperature sensor remotely monitors the core temperature of the MPC8640(D)/MPC8641(D) and monitors ambient temperature. A LM92 temperature sensor monitors the ambient temperature on the PCB. The temperature sensors are able to generate interrupts to either processor core, via the Local Bus FPGA, at two software‐defined thresholds. Using the Secondary interrupt controller in the Local Bus Control FPGA, these thresholds can optionally be configured to generate a Machine‐Check exception. 6.7.5
Power Supply Manager
The SBC310 uses a Lattice ispPAC‐POWR1014A to monitor and sequence the on‐
board voltages. The device provides an I2C interface which can be used to access an internal A‐to‐D converter to measure the value of each of the on‐board voltage rails. Discrete inputs to and outputs from the device can also be monitored. Publication No. SBC310-0HH/5
6.7.6
MPC8640(D)/MPC8641(D) Configuration EEPROM
Initial configuration of the processor is performed by driving strapping signals to the correct state during reset. An I2C EEPROM is provided, should further configuration information need to be loaded into the device before software boots. The processor’s boot sequencer, which uses the EEPROM, is always enabled and therefore the device must be loaded with valid data (including preamble and CRC) at all times in order for the processor to boot correctly. If valid data is not read, then the device will request a hard reset. The EEPROM is write‐protected by default and can be write‐enabled by clearing the I2C EEPROM Write Protect bit in Control Register 1. This bit may only be cleared when the NVMRO Link is fitted (Sections 3.1.2 /4.1.5 ) and the NVMRO signal from the VPX backplane is negated. CAUTION
Programming of the configuration EEPROM should only be done under the control of the operating
The processor can be prevented from accessing the EEPROM, in the event that the data becomes corrupted and configures the device such that the EEPROM contents cannot be overwritten, by fitting the Recovery Link and booting the SBC310 from the recovery boot region – see Sections 3.1.5 /3.1.6 and 4.1.3 /4.1.4 . The EEPROM should then be reprogrammed with a valid image. 6.7.7
I2C Reset
There is the potential for the I2C bus to become locked‐up if the reset is applied when a slave device (without a reset pin) is driving out data when the I2C clock is stopped. The Local Bus Control FPGA provides logic to recover both I2C busses from this locked‐up state by clocking the bus during reset until the data line is released. 6.7.8
Board Management Microcontroller
The SBC310 contains a Board Management Microcontroller, which provides a proprietary mechanism to share of BIT results between boards in a system and remote monitoring of board status. The BMM is connected to a backplane I2C Serial Management bus (using the SM0 and SM1 connections on the P0 connector) which is bussed between all slots in the system. The BMM on each board is addressed based on its Geographic Address as shown in the table below. These are the byte addresses that would be used to write to the device on the bus (i.e. the 7‐bit device address and the least significant bit set to ‘0’). 48 SBC310 3U VPX Single Board Computer
Table 6-13 BMM Address Allocation
Slot
1
2
3
4
5
6
7
GA[4:0]
11110
11101
11100
11011
11010
11001
11000
I2C Address
0xB0
0xB2
0xB4
0xB6
0xB8
0xBA
0xBC
Slot
8
9
10
11
12
13
14
GA[4:0]
10111
10110
10101
10100
10011
10010
10001
I2C Address
0xBE
0xC0
0xC4
0xC6
0xC8
0xCA
0xCC
Slot
15
16
17
18
19
20
21
GA[4:0]
10000
01111
01110
01101
01100
01011
01010
I2C Address
0xCE
0xD0
0xD2
0xD4
0xD6
0xD8
0xDA
The system management bus of the XMC site is also connected to the backplane Serial Management Bus. The lower 3 bits of its address is also determined by the backplane slot ID. Again, these are the byte addresses that would be used to write to the device on the bus (i.e. the 7‐bit device address and least significant bit set to ‘0’). Table 6-14 SMB Address Allocation
VPX_GA[2:0]
000
001
010
011
100
101
110
111
I2C Address
0xA0
0xA2
0xA4
0xA6
0xA8
0xAA
0xAC
N/A
The local processor communicates with the BMM via the COM2 port from the MPC8640(D)/MPC8641(D). The BMM serial interface is enabled when the BMM COMMS mode bit in control register 1 is set. The BMM is connected to on‐board I2C Bus 2, providing access for out‐of‐band monitoring of board status information such as on‐board voltage rail status by any other board in the system. The BMM is programmed from registers within Control Register 2, though programming may only be performed when the NVMRO Write Link is fitted (Sections 3.1.2 /4.1.5 ) and the NVMRO signal from the backplane is negated. The BMM is powered from the 3.3VAUX rail, meaning that board configuration information or BIT status can be read out of the device without enabling the main on board power. An I2C buffer is sited on the on‐board I2C Bus 1 to allow the BMM to access the Power Manager device when the on‐board supplies are not powered up. Publication No. SBC310-0HH/5
6.8 General Purpose Timers
The 8641D provides eight 31‐bit general‐purpose timers. Each timer is capable of generating interrupts to either or both processing cores and can be programmed to generate periodic interrupts. Each group of 4 timers can be set to operate from a divider of the MPX bus clock (divided by 8, 16, 32, or 64) or from an external 14.318 MHz clock. The minimum resolution of each timer is 15 ns. Each group of timers can be cascaded to form two 63‐bit timers, one 95‐bit timer or one 127‐bit timer, if required. 6.9 Watchdog Timers
The SBC310 provides two independent, programmable 32‐bit watchdog timers. These are count‐down timers which are capable of generating interrupts to the either or both of the two processing cores at a programmable threshold and resetting the board if expired. The watchdog timers are disabled following reset but, once enabled, the watchdog must be serviced periodically to prevent a reset. Further details on the operation of the watchdog can be found in the Watchdog Control Register definition. 6.10 AXIS Support
The SBC310 provides hardware features required to support GEIP’s AXIS software suite. Four 32‐bit wide FIFOs, capable of holding 64 messages each, are provided to support message passing between the two on‐board processing nodes or from other nodes in the system to the on‐board processing nodes. An interrupt can be generated to the receiving processing node when a message is received and remains asserted until the message queue is empty. The SBC310 supports a 48‐bit timer, clocked by the external AXIS_TIMER_CLK signal and reset by the AXIS_TIMER_RST signal. (These signal share pins with GPIO5 and GPIO4 respectively). This allows a number of boards to be connected to these signals and generates a common timestamp for data passed between them. The SBC610 is also able to act as a master on these signals, generating a clock (with programmable frequency) and asserting the reset under software control. Eight hardware semaphores are also provided for use in locking common resources. NOTE
The AXIS timer clock and reset signals are shared with GPIO5 and GPIO4 and there is no hardware
separation of the two functions. Therefore when using AXIS functionality, ensure that the GPIO4 and
GPIO5 are set to INPUT mode, and interrupt generation is disabled (Default state). Likewise, when AXIS
functionality is not being used ensure that the AXIS interrupts are masked. (Default state)
6.11 Resets, Interrupts and Error Reporting
The following table shows the various external interrupt sources to the processor and their relative priorities. It also shows whether the previous state of the processor is recoverable. Table 6-15 Processor Interrupts
Priority
Interrupt
0
System Reset
1
2
Machine Check
System Reset
System
Management
Interrupt
3
4
6.11.1
External Interrupt
Cause
Power on,
Hard Reset Input
MCP~ Input
Soft Reset Input
Recoverability
Non-recoverable
Non-recoverable in most cases
Recoverable unless Machine Check occurs
SMI~ input
Recoverable unless Machine Check or System
Reset occurs
INT~ input
Recoverable unless Machine Check or System
Reset occurs
Hard Reset
A hard reset is used to reset the MPC8640(D)/MPC8641(D) (including the processing cores) and all other devices on the board which require resetting. When released from reset, Processing Core 0 will begin executing from the Boot Flash at address 0xFFF0 0100. A hard reset is initiated when one of the following hardware events occur: 1. Any of the power supplies fall outside specification 2. The SYSRESET~ signal is asserted 3. The processor HRESET_REQ~ output is asserted 4. The reset switch on the Test Access Board is toggled 5. The HRESET~ signal on the BDM Header is asserted 6. The reset output from the PEX8518 switch is asserted 7. The reset output of the BMM is asserted 8. The RESET_OUT~ signal from the XMC site is asserted 9. Either of the two watchdog timers expire The duration of the internal hard reset signal is at least 10 ms. The cause of a hard reset event may be determined from the Link Status Register. The processing cores may be individually reset by software using the Processor Core Reset Register within the MPC8640(D)/MPC8641(D) interrupt controller. Publication No. SBC310-0HH/5
6.11.2
SYSRESET~ Signal
The VPX SYSRESET~ signal is asserted by hardware when a hard reset event occurs and the board is the VPX System Controller (SYSCON~ backplane signal driven low). The duration of the VPX SYSRESET~ signal is at least 10 ms. 6.11.3
Machine Check Exception
When the MCP~ input to the processing core is asserted, it may be configured to take a machine check exception or enter the checkstop state. The MCP~ input to each of the two processing cores can be driven either by interrupts handled by the interrupt controller within the Local Bus Control FPGA being enabled by software to drive the MCP0~ or MCP1~ inputs to the MCP8641D or by software enabling interrupt sources from within the MPC8640(D)/MPC8641(D) interrupt controller to drive the MCP~ input to one of the two processing cores. Figure 6-7 SBC310 Machine Check Exceptions
6.11.4
Soft Reset
A soft reset causes the processing core to reach a recoverable state and then branch to either 0x0000_0100 or 0xFFF0_0100, depending on the state of the IP bit in the core’s Machine State Register. No other on‐board resources are reset. A soft reset is initiated on both processing cores when the SRESET~ signal on the BDM header is asserted. The processing cores may be individually soft reset by software using the Processor Core Initialization Register within the MPC8640(D)/MPC8641(D) interrupt controller. 6.11.5
System Management Interrupt (SMI~)
An SMI~ interrupt to the processing cores can only be generated by asserting the external SMI0~ or SMI1~ pins on the MPC8640(D)/MPC8641(D). These pins are unused on the SBC310. 52 SBC310 3U VPX Single Board Computer
6.11.6
External Interrupt (INT~)
The processing core external interrupt pin (INT~) is asserted for a pending interrupt from the interrupt controller in the MPC8640(D)/MPC8641(D). The MCP8641D interrupt controller supports routing of internal and external interrupt sources to one of the two processing cores, including programmable priority levels. All interrupt routing between source and the processing cores is established by software. 6.11.7
Secondary Interrupt Controller
The Secondary Interrupt Controller within the Local Bus Control FPGA allows all on‐board interrupts to be routed to two of the MPC8640(D)/MPC8641(D) external interrupt inputs and the MCP (Machine Check Exception) inputs. This allows software to configure on‐board devices to interrupt either of the cores independently from the other providing maximum flexibility. Each external interrupt input and MCP input to the MPC8640(D)/MPC8641(D) has associated with it a mask register within the secondary interrupt controller, which determines which on‐board interrupt is routed to that pin. Register definitions can be found in the status/control register section. Figure 6-8 SBC310 Interrupts
6.11.8
PCI Interrupts
PCI Express provides a mechanism for passing interrupts from legacy PCI devices through the PCI Express fabric to the interrupt controller at the Root Complex, using Assert_INTx and Deassert_INTx messages. These messages are, however, subject to the same latency and non‐determinism as any other PCI Express packet. To reduce this latency, the SBC310 takes the interrupts from the USB controller and mezzanines and routes them directly to the interrupt controller, via the Local Bus Control FPGA, bypassing the fabric altogether. The MPC8640(D)/MPC8641(D) PCI Express Root Complex generates internal interrupt signals (equivalent to INTA to INTD) to the Interrupt Controller, which are shared with external interrupt signals (INTA with IRQ0, INTB with IRQ1, etc.) Publication No. SBC310-0HH/5
Mapping the individual device interrupts to the correct external signals allows this mechanism to appear transparent to software. This mapping must account for rotation due to the device number of both the switch port and the device on the PCI bus. The mapping used is shown in the table below. Table 6-16 PCI Interrupts
Interrupt Source
PEX8518 Port
Device
Number
Device Interrupt to MPC8640(D)/MPC8641(D) IRQ Pin Mapping
IRQ 0
IRQ 1
IRQ 2
IRQ 3
PMC site
3
2
INT D
INT A
INT B
INT C
USB
3
1
INT A
INT B
INT C
6.12 Power Management
6.12.1
Processor
All power management features of the processing cores, such as the programmable power states (Doze, Nap, and Sleep), Dynamic Power Management, Instruction Cache Throttling and Dynamic Frequency switching, are available to the software within the 8641D. No external hardware support is required. 6.12.2
PCI Express
All PCI Express links support a number of power management features which are under software control and no hardware support is required. The SBC310 does not support the WAKE* signal and recovery from a D3COLD state under auxiliary power. 6.13 JTAG
The SBC310 provides JTAG boundary scan facilities for all IEEE1149.1 and IEEE1149.6‐compliant devices. The JTAG interface is provided by a Firecron JTS06Bu Scanbridge. This allows the boundary scan path to be partitioned into smaller chains, providing easier fault diagnosis and faster Flash programming. The device supports six Test Access Ports (TAPs), which are allocated as follows: Table 6-17 JTAG Access Ports
TAP
Devices
1
BDM Header MPC8640(D)/MPC8641(D) processor
2
XMC Site (see notes) / PMC Site (see notes)
3
PEX8548 PCIe Switch PMC/PEX8114 PCIe-PCI Bridge
4
88E1111 PHY 1 / 88E1111 PHY 3
5
SiL3132 SATA controller
6
Local Bus FPGA
The JTAG architecture supports the use of the JTAG Technologies Autowrite signal to accelerate flash programming via JTAG. This signal is connected to a user definable single ended pin on P2, and could be disconnected if required. The address of the backplane JTAG scanbridge is set by the VPX geographic address bits (0:4) and indicates the slot number in which the board is fitted. NOTE
The PCI specification requires that if a PMC cannot support JTAG, then it must have TDI connected to
TDO ensuring that the JTAG chain remains intact.
The XMC specification (VITA 42.0) requires that if an XMC cannot support JTAG, then it must have TDI
connected to TDO on the XMC and PMC connectors (if fitted) ensuring that the JTAG chain remains
intact. It also requires that if both connector sets are present, then the XMC connector is used for the
JTAG interface and the PMC connector connects TDI to TDO.
The SBC310 will automatically bypass the PMC and/or the XMC site if the appropriate card is not fitted,
ensuring that the JTAG chain will always be complete.
6.14 Mezzanine Sites
PMC/XMC Site
The SBC310 has a single mezzanine site which supports PMC and XMC modules. The site is compliant with IEEE1386‐2001 for air‐cooled mezzanines and ANSI/VITA20‐2001 for conduction‐cooled mezzanines, with the exception that the front I/O keep‐out area requirement is violated when the board is configured with two banks of memory. In this configuration, PMCs and XMCs with components up to 8.3mm in height in this area can be fitted to the SBC310. The figure below shows the allowable outline of a PMC/XMC when both banks of RAM are fitted. Figure 6-9 PMC/XMC Site Device Clearance Dimensions
PCI Mezzanine
Cards (PMCs)
Each site supports IEEE1386.1‐compliant PMCs and provides Jn1, Jn2, Jn3, and Jn4 connectors. The mezzanine is connected to a 64‐bit bus capable of PCI or PCI‐X operation at frequencies of up to 133 MHz. Each PCI bus is connected to a PEX8114 PCIe‐to‐PCI Bridge, which provides frequency negotiation, clocks and arbitration for the bus. The PEX8114 device is not 5V‐tolerant and so the SBC310 does not support PMCs which use 5V signaling. Publication No. SBC310-0HH/5
CAUTION
The SBC310 PMC site is NOT 5 V tolerant.
Do not fit PMCs that use 5 V signalling
5V and 3V3 Power to the PMC site is switched by the power manager device so that these supplies are switched at the same time. This protects PMC cards that are intolerant to supply rails not being correctly sequenced. PCI Express
Mezzanine
Cards (XMCs)
Each site also supports VITA 42.3‐compliant XMCs and provides J15 and J16 connectors. J15 provides a x8 PCI Express link to the MPC8640(D)/MPC8641(D). I/O Routing
PMC and XMC is routed in accordance with VITA 46.9 X20d24s and P64s standards. The I/O is configurable as a build option such that all I/O is connected to the J14 PMC connector (P64s) OR the P16 XMC connector (X20d24s). See the variant map for details. Where differential signals are required (20 signals to the XMC) the tracks are routed as 100 ohm differential pairs. Where single ended signals are required, the tracks are routed with a target impedance of 50 ohms. NOTE
When configured for PMC routing, 20 of the 64 signals are tracked as differential pairs.
Figure 6‐10 and Figure 6‐11 show the I/O mapping as follows: 56 SBC310 3U VPX Single Board Computer
Figure 6-10 XMC VPX I/O Mapping
Figure 6-11 PMC VPX I/O Mapping
6.15 Control and Status Registers
The control and status registers exist on the SBC310 for controlling or reading the status of the hardware. All registers are accessed using Local Bus Chip Select 4, are configured as 32‐bit wide and must be written as a 32‐bit word. The following table gives the locations of the registers, offset from the Chip Select 4 base address (which is configured by software): Table 6-18 Control & Status Registers
Register
CS
Offset
R/W
Register
CS
Offset
R/W
Board ID Register
4
0x0000
RO
Board Interrupt Core 0 MCP Mask
4
0x4018
RW
Address Register
4
0x0004
RO
Board Interrupt Core 1 MCP Mask
4
0x401C
RW
Board Frequency Register
4
0x0008
RO
GPIO Direction Register
4
0x8000
RW
Board Configuration Register
4
0x000C
RO
GPIO Input Register
4
0x8004
RW
Link Status Register
4
0x0010
RO
GPIO Output Register
4
0x8008
RW
Control Register 1
4
0x0014
RW
GPIO Interrupt Generation Mode Register
4
0x800C
RW
Reserved
4
0x0018
RO
GPIO Polarity Register A
4
0x8010
RW
Flash Control Register
4
0x001C
RW
GPIO Polarity Register B
4
0x8014
RW
Test Pattern Register 1
4
0x0020
RO
GPIO Interrupt Status Register
4
0x8018
RW
4
0x0024
RO
Reserved
4
0x801C
RO
4
0x0028
RO
GPIO Output Drive Mode Register
4
0x8020
RW
Scratch Register 1
4
0x0030
RW
AXIS Timestamp Low Value Registera
4
0x6000
R
Scratch Register 2
4
0x0034
RW
AXIS Timestamp High Value Registera
4
0x6004
R
Scratch Register 3a
4
0x0038
RW
AXIS Timer Control Registera
4
0x6008
RW
Scratch Register 4a
4
0x003C
RW
AXIS Semaphore Register 1a
4
0x6020
RW
Board Semaphore Register 1
4
0x0040
RW
4
0x6024
RW
4
0x0044
RW
4
0x6028
RW
4
0x0048
RW
4
0x602C
RW
4
0x004C
RW
4
0x6030
RW
4
0x0050
RW
4
0x6034
RW
4
0x0054
RW
4
0x6038
RW
4
0x0058
RW
4
0x603C
RW
4
0x005C
RW
FIFO Data Register Aa
4
0x6040
RW
Watchdog 0 Control
4
0x2000
RW
FIFO Data Register Ba
4
0x6044
RW
Watchdog 0 Interrupt Value
4
0x2004
RW
FIFO Data Register Ca
4
0x6048
RW
Watchdog 1 Control
4
0x2010
RW
FIFO Data Register Da
4
0x604C
RW
Watchdog 1 Interrupt Value
4
0x2014
RW
FIFO Status Register Aa
4
0x6050
RW
Board Interrupt Status
4
0x4000
RO
FIFO Status Register Ba
4
0x6054
RW
Board Interrupt Core 0 INT Mask
4
0x4010
RW
FIFO Status Register Ca
4
0x6058
RW
0x4014
RW
FIFO Status Register Da
4
0x605C
RW
Board Interrupt Core 1 INT Mask
4
Where:
RW = Read/Write
RO = Read Only
WO = Write Only
The following sections provide the definitions for the function of each bit within a register. All registers are configured such that Bit 0 is the most‐significant bit and Bit 31 is the least‐significant bit. 6.15.1
Board ID Register
This register contains the board ID and version information, allowing software to identify the specific board type and version. Chip Select Offset Reset Value = CS4 = 0x0000 = N/A Table 6-19 Board ID Register
Bit
0:7
8:15
16:23
24:27
28:31
6.15.2
R/W
R
R
R
R
R
Description
GEIP Board ID
PCB Revision (1,2,3, etc.)
Minor Board Revision (A,B,C, etc.)
Reserved
Register FPGA Revision
Reset Value
0x2F
PCB Rev
Minor Rev
0x0
FPGA Rev
Address Register
This register contains the geographic address of the board as determined from the backplane. Chip Select Offset Reset Value = CS4 = 0x0004 = N/A Table 6-20 Address Register
Bit
0:22
R/W
R
23
R
24:25
R
26
R
27:31
R
Description
Reserved
VPX System Controller
0 = Board is not VPX System Controller
1 = Board is VPX System Controller
Bit is set to 0 if board is not VPX
Reserved
Geographic Address Odd Parity
0 = Odd Number of bits set
1 = Even Number of bits set
Inverted from backplane signal
Geographic Address
Contains VME/VPX Geographic Address
All bits are inverted to present actual address
Reset Value
0x0
N/A
0x0
N/A
N/A
6.15.3
Board Frequency Register
This register contains information on the frequency of the SYSCLK input to the MPC8640(D)/MPC8641(D). Software can then use this in conjunction with the on‐
chip PLL multiplier values to determine Platform and Core operating frequencies. Chip Select Offset Reset Value = CS4 = 0x0008 = N/A Table 6-21 Board Frequency Register
Bit
0:27
R/W
R
28
R
29
R
30:31
R
6.15.4
Description
Reserved
CPU type
0 = MPC8641/D fitted
1 = MPC8640/D fitted
Reserved
SYSCLK Frequency
00 = 66.6MHz
01 = 100.0MHz
10 = Reserved
11 = Reserved
Reset Value
0x0
N/A
0
N/A
Board Configuration Register
This register contains information on the configuration of the board including information on FLASH, number of DRAM banks fitted and whether a PMC/XMC card is fitted. Chip Select Offset Reset Value = CS4 = 0x000C = N/A Table 6-22 Board Configuration Register
Bit
0:3
4
R/W
R
R
5:6
R
7
R
8:12
R
13
R
14
R
15
R
16
R
Description
Reserved
SATA Channel 1 Present
0 = SATA ch 0 only present. Full GPIO available.
1 = SATA ch 0 & 1 present.
PMC/XMC IO routing
00 = PMC 1-64 IO routed to P2 (Vita 46.9 P64s)
01 = Reserved
10 = Reserved
11 = XMC I/O routed to P2 (Vita 46.9 X20d24s)
Dual Gigabit Ethernet Fitted
0 = Dual 10/100 Ethernet
1 = Dual Gigabit Ethernet
Reserved
XMC1 Fitted
0 = XMC1 Not Fitted
1 = XMC1 Fitted
Reserved
PMC1 Fitted
0 = PMC1 Not Fitted
1 = PMC1 Fitted
FLASH Type
0 = Intel FLASH Fitted
1 = Spansion FLASH Fitted
Reset Value
0x0
N/A
N/A
1
0x0
N/A
0
N/A
1
Bit
17:18
R/W
R
19
R
20:21
R
22:23
R
24:25
R
26:27
R
28
R
29:30
R
31
R
6.15.5
Description
Reserved
FLASH Width
0 = 32-bit FLASH
1 = 16-bit FLASH
FLASH Banks
00 = 1 Bank FLASH
01 = 2 Banks FLASH
10 = 4 Banks FLASH
11 = 8 Banks FLASH
FLASH Device Size
00 = Reserved
01 = 512Mbit FLASH Devices
10 = 1Gbit FLASH Devices
11 = 2 Gbit FLASH Devices
Reserved
Number of Ranks per controller
00 = 1
01 = 2
10 = 3
11 = 4
Device width
0 = 16 bits
1 = 8 bits
DRAM Device Density
00 = 1Gbit
01 = 2Gb
10 = 4Gb
11 = Reserved
Number of DRAM controller banks
0 = Both fitted
1 = Memory controller D1 only
Reset Value
0x0
0 – rev 1
1 – rev 2+
00 = rev 1
01 = rev 2+
N/A
0x00
00
‘0’
N/A
N/A
Link Status Register
This register contains information on the links and inputs to the board. It also includes information on the source of the last reset. Chip Select Offset Reset Value = CS4 = 0x0010 = N/A Table 6-23 Link Status Register
Bit
R/W
0
R
1
R
2
R
3
R
4
R
5
R
Description
Backplane Reset
0 = Last Reset not caused by Backplane
1 = Last Reset caused by Backplane
CPU Hard Reset Request Reset
0 = Last Reset not caused by 8641D Hard Reset Request
1 = Last Reset caused by 8641D Hard Reset Request
Watchdog 1 Reset
0 = Last Reset not caused by Watchdog 1
1 = Last Reset caused by Watchdog 1
Watchdog 0 Reset
0 = Last Reset not caused by Watchdog 0
1 = Last Reset caused by Watchdog 0
External Reset
0 = Last Reset not caused by backplane EXT_RESET_N input
1 = Last Reset caused by backplane EXT_RESET_N input
Reserved
Reset Value
0x0
0x0
0x0
0x0
0x0
0x0
Bit
R/W
6
R
7
R
8
R
9
R
10
R
11
R
12
13
R
R
14
R
15
R
16-17
18
19
R
R
R
20
R
21
R
22
R
23
R
24
R
25
R
26
27
28
R
R
R
29
R
30
R
31
R
Description
BMM Reset
0 = Last Reset not caused by BMM
1 = Last Reset caused by BMM
BDM Reset
0 = Last Reset not caused by BDM Header
1 = Last Reset caused by BDM Header
Reserved
XMC1 Reset
0 = Last Reset not caused by PMC/XMC1
1 = Last Reset caused by PMC/XMC1
Reserved
PCI Express Non-Transparent Port Reset
0 = Last Reset not caused by PEX8518 NT PCIe port
1 = Last Reset caused by PEX8518 NT PCIe port
Reserved
Reserved
XMC1 Built-In Self-Test
0 = XMC2 Built-In Self-Test Complete
1 = XMC2 Built-In Self-Test In Progress
EREADY
0 = PMCs/AFIX Ready for Enumeration
1 = PMCs/AFIX Not Ready for Enumeration
Reserved
Reserved
Reserved
Backplane NVMRO status
0 = NVMRO signal high (all NV memory protected)
1 = NVMRO signal low (use on-board NVRAM and FLASH links to set write
protection)
Reserved
SMP Mode Link
0 = Link Not Fitted
1 = Link Fitted
NVRAM Write Enable link
0 = Link Not Fitted (NVRAM write protected)
1 = Link Fitted (NVRAM write enabled)
BANC Area Write Enable Link
0 = Link Not Fitted
1 = Link Fitted
FLASH Password Unlock Link
0 = Link Not Fitted
1 = Link Fitted
Reserved
Reserved
Reserved
Boot Recovery FLASH Area Link
0 = Link Not Fitted
1 = Link Fitted
Boot Alternate FLASH Area core 1 Link (P12 3-4 on board)
0 = Link Not Fitted
1 = Link Fitted
Boot Alternate FLASH Area core 0 Link (P12 1-2 on board)
0 = Link Not Fitted
1 = Link Fitted
Reset Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0
N/A
N/A
N/A
0
0
0
0
N/A
N/A
N/A
N/A
0
0
0
N/A
N/A
N/A
6.15.6
Control Register 1
This register controls various aspects of the board Chip Select Offset Reset Value = CS4 = 0x0014 = 0x002100X2 Table 6-24 Control Register 1
Bit
R/W
0
RW
1
RW
2
RW
3
R
4
RW
5
RW
6
RW
7
RW
8
R
9
RW
10
RW
11
RW
12
RW
13
RW
Description
Board Management Microcontroller Program Enable
0 = BMM_PROGRAM_EN signal inactive
1 = BMM_PROGRAM_EN signal active
This BIT is only writeable if the NVM Write Enable bit is set
Board Management Microcontroller Programming Voltage
0 = BMM Programming Voltage Inactive
1 = BMM Programming Voltage Active
The BMM_PS0_ISP_VPP signal only takes this value when Bit 0 is set high.
Board Management Microcontroller Programming Data Direction Ctrl
0 = Data line is an input
1 = Data line is an output – the value in bit (4) is driven onto the data line
Board Management Microcontroller Programming Data In
0 = BMM Programming Data Line is Low
1 = BMM Programming Data Line is High
This register bit returns the value of the BMM_ISP_DATA pin, regardless of the
value of bit 2.
Board Management Microcontroller Programming Data Out
0 = BMM Programming Data Line driven Low
1 = BMM Programming Data Line driven High
The BMM_ ISP_DATA signal only takes this value when Bit 0 and bit 2 is set high.
Board Management Microcontroller Programming Clock
0 = BMM Programming Clock Line Low
1 = BMM Programming Clock Line High
The BMM_ PS1_ISP_CLK signal only takes this value when Bit 0 is set high.
BMM COMMS mode
0 = Normal COMMS mode (BMM com port disabled)
1 = COM2 connects to BMM only
BIT Flag
0 = BIT Not Run
1 = BIT Run
Reserved
NVMRO Override
0= Backplane NVMRO signal not driven by the SBC310.
1= Backplane NVMRO signal driven low by the SBC310.
This bit can only be set when the SBC310 is configured to be the VPX
System Controller.
Configuration EEPROM write protect
0 = Configuration EEPROM for MC8641/0D is write enabled
1 = Configuration EEPROM for MC8641/0D is write protected
NOTE
Reset Value
0x0
0x0
0x0
N/A
0x0
0x0
0x0
0x0
0
0x0
0x1
This bit can only be cleared to a 0 when the NVMRO link is fitted AND
the backplane NVMRO signal is 0.
Reserved
BIT Pass (Green) LED Status
0 = BIT Pass LED Unlit
1 = BIT Pass LED Lit
BIT LED 2 (Yellow) LED Status
0 = BIT LED 2 Unlit
1 = BIT LED 2 Lit
0x0
0x0
0x0
Bit
R/W
14
RW
15
RW
16:23
R
24
RW
25
R
26
RW
27
RW
28
R
29
RW
30
RW
Description
BIT LED 1 (Yellow) LED Status
0 = BIT LED 1 Unlit
1 = BIT LED 1 Lit
BIT Fail (Red) LED Status
0 = BIT Fail LED Unlit
1 = BIT Fail LED Lit
Reserved
PCI MODE
0=PCI-X mode (no USB)
1=USB mode (USB in scan)
Reserved
COM2 RS232 Mode
0 = COM2 RS422 Mode
1 = COM2 RS232 Mode
COM2 Receiver Enable
0 = COM2 Receiver Disabled
1 = COM2 Receiver Enabled
Reset Value
0x0
0x1
0x0
N/A
0x0
0x1
0x1
NOTE
When in BMM mode, this bit has no function and COM2 controller is
always off.
Reserved
COM1 and COM2 Loopback Enable
0 = COM1 and COM2 Loopback Disabled
1 = COM1 and COM2 Loopback Enabled
COM1 RS232 Mode
0 = COM2 RS422 Mode
1 = COM2 RS232 Mode
0x0
0x0
0x1
NOTE
31
6.15.7
RW
This bit is hardwired to ‘1’ on Rev2 boards.
COM1 and COM2 Transceiver Enable
0 = COM1 and COM2 Transceiver Disabled
1 = COM1 and COM2 Transceiver Enabled
0x0
Control Register 2
This register is reserved. Chip Select Offset Reset Value 64 SBC310 3U VPX Single Board Computer
= CS4 = 0x0018 = 0xx0000000 Publication No. SBC310-0HH/5
6.15.8
Flash Control Register
This register is used to control the flash addressing and data multiplexing. It appears within the control/status register block on CS4 but is placed in this FPGA to avoid routing register signals between the FPGAs to save pins. The addressing bits allowing software to page flash to avoid having to map the entire array into the memory map. Chip Select Offset Reset Value = CS4 = 0x001C = 0x00000913 Table 6-25 Flash Control Register
Bit
0:19
R/W
R
20
RW
21
R
22
RW
Description
Reserved
MAC Mirror Mode
0 = CS2 top sector accesses FLASH Bank 1
1 = CS2 top sector accesses FLASH Bank 0 (BANC Area)
Reserved
Core 1 boot mode
0 = Primary boot area mapped to FF8000000
1 = secondary (core 1) boot area mapped to FF800000
Reset Value
0x0
0x1
0x0
0x0
NOTE
23
RW
24:26
R
27
RW
28:29
R
30:31
RW
Boot area is swapped only when in AMP mode
Page Mode Enable
0 = FLASH Address derived from local bus
1 = FLASH Address Bits 1:4 derived from registers
Reserved
FLASH Address Bit 4 (CS2 space)
When the Page Mode Enable bit is set, these bits are used to provide the most
significant bits of the FLASH address to select a 128MByte page.
NOTE
0x1
0x0
‘1’
With the exception of the BANC area when BANC_MIRROR is set,
It is only possible to access the lower half of the flash using CS2.
Reserved
FLASH Address Bits 3:4 (CS1 space)
When the Page Mode Enable bit is set, these bits are used to provide the most
significant bits of the FLASH address to select a 128MByte page.
0x0
‘11’
6.15.9
This register normally contains an alternate bit test pattern to verify bit ordering and check for stuck bits. When the flash protection unlock link is fitted and the backplane NVMRO signal is negated the register value changes to the first half of the FLASH password. Chip Select Offset Reset Value = CS4 = 0x0020 = N/A Table 6-26 Test Pattern Register 1
Bit
R/W
0:31
R
Description
With the flash protection unlock link removed OR
NVMRO backplane signal = 1 :
0xAAAAAAAA
Reset Value
N/A
With the flash protection unlock link fitted AND
0x44617461 (ascii “Data”)
6.15.10 Test Pattern Register 2
This register normally contains an alternate bit test pattern to verify bit ordering and check for stuck bits. When the flash protection unlock link is fitted and the backplane NVMRO signal is negated the register value changes to the second half of the FLASH password. Chip Select Offset Reset Value = CS4 = 0x0024 = N/A Table 6-27 Test Pattern Register 2
Bit
R/W
0:31
R
Description
With the flash protection unlock link removed OR
0x55555555
Reset Value
N/A
With the flash protection unlock link fitted AND
0x53616665 (ascii “Safe”)
6.15.11 Test Pattern Register 3
This register contains a test pattern to check for byte ordering from the FPGA. Chip Select Offset Reset Value = CS4 = 0x0028 = N/A Table 6-28 Test Pattern Register 3
Bit
0:31
R/W
R
Description
Test Pattern “SBC3” (0x53424333)
Reset Value
N/A
6.15.12 Scratch Register 1
This register has no effect on the system and is provided for software to store status information or data. Chip Select Offset Reset Value = CS4 = 0x0030 = 0x00000000 Table 6-29 Scratc Register 1
Bit
0:31
R/W
RW
Description
Scratch Register 1
Reset Value
0x00000000
This register has no effect on the system and is provided for software to store status information or data. Chip Select Offset Reset Value = CS4 = 0x0034 = 0x00000000 Table 6-30 Scratch Register 2
Bit
0:31
R/W
RW
Description
Scratch Register 2
Reset Value
0x00000000
This register has no effect on the system and is provided for software to store status information or data. Chip Select Offset Reset Value = CS4 = 0x0038 = 0x00000000 Table 6-31 Scratc Register 1
Bit
R/W
Description
Reset Value
0:31
RW
Scratch Register 3
0x00000000
This register has no effect on the system and is provided for software to store status information or data. Chip Select Offset Reset Value = CS4 = 0x003C = 0x00000000 Table 6-32 Scratch Register 2
Bit
0:31
R/W
RW
Description
Scratch Register 4
Reset Value
0x00000000
6.15.16 Board Semaphore Registers
Each register controls one of eight semaphores. Chip Select Offset Reset Value = = = = = = = = = = CS4 0x0040 (Semaphore 1) 0x0044 (Semaphore 2) 0x0048 (Semaphore 3) 0x004C (Semaphore 4) 0x0050 (Semaphore 5) 0x0054 (Semaphore 6) 0x0058 (Semaphore 7) 0x005C (Semaphore 8) 0x00000000 Table 6-33 Board Semaphore Registers
Bit
R/W
0:31
RW
Description
Semaphore Register
Taken by reading register
If value returned is zero then semaphore is currently in use
If value returned is non-zero then semaphore take is successful
Released by writing to register (data value not significant)
Reset Value
0x00000000
6.15.17 Watchdog Control Register
(CS4 – Offsets 0x2000 and 0x2010)
These registers control the operation of Watchdogs 0 and 1 respectively. Table 6-34 Watchdog Control Registers (CS4 - Offsets 0x2000 and 0x2010)
Bit
R/W
Description
0
RO
Watchdog Status
1
RO
Watchdog Expired
2
RO
Watchdog Interrupt
3
RO
Reserved
4:5
RW
Service Watchdog
6:7
RW
Enable Watchdog
8:31
RW
Counter Preset Value
Notes
0 = Watchdog disbaled
1 = Watchdog endabled
0 = Watchdog not expired
1 = Watchdog counter expired (reset)
0 = Watchdog Interrupt Inactive
1 = Watchdog Interrupt Active
A write of ‘01’ followed by ‘10’ to this register services the watchdog
timer
A write of ‘01’ followed by ‘10’ to this register enables/disables the
watchdog timer
24 Most-significant bits of the value which is loaded by the watchdog
counter whenever it is enabled or serviced. 8 least-significant bits are
always 0xFF
6.15.18 Watchdog Interrupt Value Registers
(CS4 - Offsets 0x2004 and 0x2014)
These registers set the count value at which an interrupt is generated for Watchdog 0 and Watchdog 1 respectively. Table 6-35 Watchdog Interrupt Value Registers (CS4 - Offsets 0x2004 and 0x2014)
Bit
0:7
R/W
RO
8:31
RW
Description
Reserved
Interrupt Threshold
Notes
24 Least-significant bits of the count threshold at which an interrupt is
generated to the interrupt controller. The 8 most-significant bits are
always 0x00.
6.15.19 Board Interrupt Status Register
This register reflects the status of all of the on‐board non‐PCI interrupt inputs to the Register FPGA. Chip Select Offset Reset Value = CS4 = 0x4000 = N/A Table 6-36 Board Interrupt Status Register
Bit
0:12
R/W
R
13
R
14
R
15
R
16
R
17
R
18
R
19
R
20
R
21
R
22
R
23
R
24
R
25
R
26
R
27
R
28
R
29
R
30
R
31
R
Description
Reserved
GPIO(5) Interrupt status
0=Interrupt Inactive
1=Interrupt Active
1=Interrupt Active
1=Interrupt Active
1=Interrupt Active
1=Interrupt Active
1=Interrupt Active
Real Time Clock Interrupt Status
0 = Interrupt Inactive
1 = Interrupt Active
Temperature Interrupt Status
Temperature Critical Interrupt Status
Ethernet PHY1 Interrupt Status
Ethernet PHY3 Interrupt Status
PEX8548 Interrupt Status
Reserved
Watchdog 0 Interrupt Status
Watchdog 1 Interrupt Status
AXIS Message FIFO A Interrupt Statusa
AXIS Message FIFO B Interrupt Statusa
AXIS Message FIFO C Interrupt Status
AXIS Message FIFO D Interrupt Status
Reset Value
0x0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
‘0’
N/A
N/A
N/A
N/A
N/A
N/A
6.15.20 Board Interrupt Core 0 INT Mask Register
This register enables active interrupts to drive out the 8641D interrupt PLD_CORE0_INT_N. Chip Select Offset Reset Value = CS4 = 0x4010 = 0x00000000 Table 6-37 Board Interrupt Core 0 INT Mask Register
Bit
0:12
R/W
R
13
RW
14
RW
15
RW
16
RW
17
RW
18
RW
19
RW
20
RW
21
RW
22
RW
23
RW
24
RW
25
R
26
RW
27
RW
28
RW
29
RW
30
RW
31
RW
Description
Reserved
GPIO(5) Interrupt Core 0 INT Mask
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
Real Time Clock Interrupt Core 0 INT Mask
0 = Interrupt Masked
1 = Interrupt Enabled
Temperature Interrupt Core 0 INT Mask
Temperature Critical Interrupt Core 0 INT Mask
Ethernet PHY1 Interrupt Core 0 INT Mask
PEX8548 Interrupt Core 0 INT Mask
Reserved
Watchdog 0 Interrupt Core 0 INT Mask
AXIS Message FIFO 0 Interrupt Core 0 INT Mask
Reset Value
0x0
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
6.15.21 Board Interrupt Core 1 INT Mask Register
This register enables active interrupts to drive out the 8641D interrupt PLD_CORE1_INT_N. Chip Select Offset Reset Value = CS4 = 0x4014 = 0x00000000 Table 6-38 Board Interrupt Core 1 INT Mask Register
Bit
0:12
R/W
R
13
RW
14
RW
15
RW
16
RW
17
RW
18
RW
19
RW
20
RW
21
RW
22
RW
23
RW
24
RW
25
R
26
RW
27
RW
28
RW
29
RW
30
RW
31
RW
Description
Reserved
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
Real Time Clock Interrupt Core 1 INT Mask
Temperature Interrupt Core 1 INT Mask
Temperature Critical Interrupt Core 1 INT Mask
PEX8548 Interrupt Core 1 INT Mask
Reserved
Reset Value
0x0
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
6.15.22 Board Interrupt Core 0 MCP Mask Register
This register enables active interrupts to drive 8641D interrupt PLD_CORE0_MCP_N. Chip Select Offset Reset Value = CS4 = 0x4018 = 0x00000000 Table 6-39 Board Interrupt Core 0 MCP Mask Register
Bit
0:12
R/W
R
13
RW
14
RW
15
RW
16
RW
17
RW
18
RW
19
RW
20
RW
21
RW
22
RW
23
RW
24
RW
25
R
26
RW
27
RW
28
RW
29
RW
30
RW
31
RW
Description
Reserved
GPIO(5) Interrupt Core 0 MCP Mask
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
Real Time Clock Interrupt Core 0 MCP Mask
Temperature Interrupt Core 0 MCP Mask
Temperature Critical Interrupt Core 0 MCP Mask
Ethernet PHY1 Interrupt Core 0 MCP Mask
PEX8548 Interrupt Core 0 MCP Mask
Reserved
Watchdog 0 Interrupt Core 0 MCP Mask
AXIS Message FIFO 0 Interrupt Core 0 MCP Mask
Reset Value
0x0
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
6.15.23 Board Interrupt Core 1 MCP Mask Register
This register enables active interrupts to drive out the 8641D interrupt PLD_CORE1_MCP_N. Chip Select Offset Reset Value = CS4 = 0x401C = 0x00000000 Table 6-40 Board Interrupt Core 1 MCP Mask Register
Bit
0:12
R/W
R
13
RW
14
RW
15
RW
16
RW
17
RW
18
RW
19
RW
20
RW
21
RW
22
RW
23
RW
24
RW
25
R
26
RW
27
RW
28
RW
29
RW
30
RW
31
RW
Description
Reserved
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
0=Interrupt Masked
1=Interrupt Enabled
Real Time Clock Interrupt Core 1 MCP Mask
Temperature Interrupt Core 1 MCP Mask
Temperature Critical Interrupt Core 1 MCP Mask
PEX8548 Interrupt Core 0 MCP Mask
Reserved
Reset Value
0x0
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
6.15.24 GPIO Direction Register (Read/Write)
Chip Select Offset Reset Value = CS4 = 0x8000 = 0x0000003f Table 6-41 GPIO Direction Register
Bit
R/W
31
RW
26:30
0:25
R
Description
GPIO(0) Direction
0= Output
1=Input
GPIO(5):GPIO(1) Direction
0= Output
1=Input
Reserved
Reset Value
0x1
0x1
0x0
6.15.25 GPIO Data In Register (Read Only)
This register returns the value on the pin of the device, regardless of whether the port is set as an input or output. Each bit is triple‐clocked into the device to protect against metastability and to provide an edge‐detection mechanism Chip Select Offset Reset Value = CS4 = 0x8004 = 0x000000xx Table 6-42 GPIO Data In Register
Bit
R/W
31
R
26:30
0:25
R
Description
GPIO(0) Data in
0= Line is low
1=Line is high
GPIO(5):GPIO(1) Data in
0= Line is low
1=Line is high
Reserved
Reset Value
N/A
N/A
0x0
6.15.26 GPIO Data Out Register (Read/Write)
Chip Select Offset Reset Value = CS4 = 0x8008 = 0x00000000 Register containing the value driven to the pins when the direction bit is set to ‘0’. Table 6-43 GPIO Data Out Register
Bit
R/W
31
RW
26:30
RW
0:25
R
Description
GPIO(0) Output Data
0= Line driven low
1=Line driven high
GPIO(5) : GPIO(1) Output Data
0= Line driven low
1=Line driven high
Reserved
Reset Value
0x0
0x0
0x0
6.15.27 GPIO Interrupt Generation Mode Register (Read/Write)
This register is used to configure the interrupt mode of a GPIO line between level sensitive and edge sensitive. Valid when GPIO is input or output, but normal use is with GPIOs set as inputs. Chip Select Offset Reset Value = CS4 = 0x800C = 0x00000000 Table 6-44 GPIO Interrupt Generation Mode Register
Bit
R/W
31
RW
26:30
RW
0:25
R
Description
GPIO(0) interrupt generation mode
0= Level
1= Edge
GPIO(5) :GPIO(1) interrupt generation mode
0= Level
1= Edge
Reserved
Reset Value
0x0
0x0
0x0
6.15.28 GPIO Polarity Register A (Read/Write)
This register is used to configure the polarity of the interrupt mode. Chip Select Offset Reset Value = CS4 = 0x8010 = 0x00000000 Table 6-45 GPIO Polarity Register A
Bit
R/W
31
RW
26:30
RW
0:25
R
Description
GPIO(0) Polarity
Level Mode
0= Active low
1= Active high
Edge Mode
0= As per Polarity B register (0x8014)
1= Both edge interrupt generation
GPIO(5): GPIO(1) Polarity
Level Mode
0= Active low
1= Active high
Edge Mode
0= As per Polarity B register (0x8014)
1= Both edge interrupt generation
Reserved
Reset Value
0x0
0x0
0x0
6.15.29 GPIO Polarity Register B (Read/Write)
Chip Select Offset Reset Value = CS4 = 0x8014 = 0x00000000 This register is used to configure the polarity of the interrupt mode when in Edge Mode. No effect in Level Mode Table 6-46 GPIO Polarity Register B
Bit
R/W
31
RW
26:30
RW
0:25
R
Description
GPIO(0) Edge polarity
Edge Mode
0= low-high edge interrupt generation
1= high-low edge interrupt generation
GPIO(5):GPIO(1) Edge polarity
Edge Mode
0= low-high edge interrupt generation
1= high-low edge interrupt generation
Reserved
Reset Value
0x0
0x0
0x0
6.15.30 GPIO Interrupt Status Register (Read/Write)
This register is used to determine the status of a GPIO interrupt and clear it (Edge Mode). This register is a copy of the bits in the board status register bits 13:18, but an interrupt can only be cleared by writing to this register. Chip Select Offset Reset Value = CS4 = 0x8018 = 0x00000000 Level Mode (Offset 0x0C = ‘0’). Bit is set (‘1’) when: ‐ Offset 0x8010 = ‘0’ and GPIO(x) = ‘0’ or Offset 0x8010 = ‘1’ and GPIO(x) = ‘1’. Writes to this register have no effect when GPIO is configured for Level Mode. Edge Mode (Offset 0x0C = ‘1’). Bit is set (‘1’) when: ‐ Offset 0x10 = ‘0’ and Offset 0x14 = ‘0’ and low to high edge on GPIO(x) or Offset 0x10 = ‘0’ and Offset 0x14 = ‘1’ and high to low edge on GPIO(x) or Offset 0x10 = ‘1’ and any edge on GPIO(x). Edge mode interrupts are latched in this register, and can be cleared by writing a ‘1’ to the corresponding bit of this register. Table 6-47 GPIO Interrupt Status Register
Bit
R/W
31
RW
26:30
RW
0:25
R
Description
GPIO(0) Interrupt Status
0= No interrupt pending
1= Interrupt pending
GPIO(5):GPIO(1) Interrupt Status
0= No interrupt pending
1= Interrupt pending
Reserved
Reset Value
0x0
0x0
0x0
6.15.31 GPIO Output Drive Mode Register (R/W)
This register is used to select the output mode of the GPIO port to either totem‐pole or open‐drain. Effective only when the port is configured as an output. Chip Select Offset Reset Value = CS4 = 0x8020 = 0x00000000 Table 6-48 GPIO Output Drive Mode Register
Bit
R/W
31
RW
26:30
RW
0:25
R
Description
GPIO(0) Output Drive Mode
0=Totem-pole output
1=Open-Drain output
GPIO(5):GPIO(1) Output Drive Mode
0=Totem-pole output
1=Open-Drain output
Reserved
Reset Value
0x0
0x0
0x0
6.15.32 AXIS Timestamp Low Value Register
(CS4 - Offset 0x6000)
This register contains the least‐significant bits of the 48‐bit timer. Table 6-49 Axis Timestamp Low Value Register
Bit
R/W
Description
0:31
RO
Least-significant 32-bits
of the AXIS Timestamp
Notes
Reading this register causes the value of the whole timestamp (including
the high 16 bits) to be latched. It is therefore necessary to read this register
before the high value register.
6.15.33 AXIS Timestamp High Value Register
(CS4 - Offset 0x6004)
This register contains the least‐significant bits of the 48‐bit timer. Table 6-50 AXIS Timestamp High Value Register
Bit
0:15
R/W
RO
16:31
RO
Description
Reserved
Least-significant 16bits of the AXIS
Timestamp
Notes
6.15.34 AXIS Timer Control Register (CS4 - Offset 0x6008)
This register contains the control bits for the 48‐bit AXIS timer when operating in master mode. Table 6-51 AXIS Timer Control Register
Bit
0:23
R/W
RO
Description
Reserved
24:29
RW
Timer Clock
Prescaler
30
RW
Timer Reset
31
RW
Timer Master
Notes
0x000000
This value determines the frequency of the output clock when in master mode.
The clock period is calculated as
Period = (Prescaler + 1) * Local Bus Clock Period (normally 15ns)
Default = 0x07 (Nominally 120ns period)
This determines the state of the Timer Reset output when in master mode
0 = Timer reset output inactive
1 = Timer reset output active
0 = Timer Slave, accepts clock and reset
1 = Timer Master, generates clock and reset
6.15.35 AXIS Semaphore Registers
Register controlling one of eight semaphores. Table 6-52 AXIS Semaphore Registers
Register
0x6020
0x6024
0x6028
0x602C
0x6030
0x6034
0x6038
0x603C
Semaphore
1
2
3
4
5
6
7
8
Table 6-53 AXIS Semaphore Register Bits
Bit
R/W
Description
0:31
RW
Semaphore
Register (1 to 8)
Notes
Taken by reading register
If value returned is zero then semaphore is currently in use
If value returned is non-zero then semaphore take is successful
Released by writing to register (data value not significant)
6.15.36 FIFO Data Registers
These registers form the data path to each FIFO. A write access adds the 32‐bit message onto the back of the queue and a read access removes the first message from the queue. Table 6-54 FIFO Data Registers
Register
0x6040
0x6044
0x6048
0x604C
FIFO
A
B
C
D
Table 6-55 FIFO Data Register Bits
Bit
R/W
Description
0:31
RW
FIFO Data Register
Notes
Write access adds data to queue
Read access removes data from queue
6.15.37 FIFO Status Registers
These registers contain status information on each FIFO. A bit is set if the FIFO is full or empty or has only one message or message space remaining. Table 6-56 FIFO Status Registers
Register
0x6050
0x6054
0x6058
0x605C
FIFO
A
B
C
D
Table 6-57 FIFO Status Register Bits
Bit
0:26
R/W
RO
Description
Reserved
27
RW
FIFO Reset
28
RO
FIFO Full
29
RO
FIFO Almost Full
30
RO
FIFO Almost Empty
31
RO
FIFO Empty
Notes
0 = FIFO Normal Operation
1 = FIFO Reset
0 = FIFO Not Full
1 = FIFO Full
0 = FIFO has more than 1 space
1 = FIFO has only 1 space
0 = FIFO has zero or more than 1 entry
1 = FIFO has only 1 entry
0 = FIFO not empty
1 = FIFO empty
6.16 VPX Port Configuration
The SBC310 has two independent x4 PCIe links connected to P1 in accordance with VITA46.4 (denoted in VITA46.4 as Link A and Link B). The ports are connected to the PEX8518 switch, which allows one port at any time to be non‐transparent (NT). Both links can operate in x4, x2 or x1 modes and will automatically train to use the greatest number of lanes available. Transmit signals have AC coupling capacitors on‐board. It is necessary to make ports NT when connecting to other intelligent boards on the VPX backplane. This is ensure that each intelligent card has it’s own address domain – the NT bridges provide the logical barrier between the address domains. For example, in the diagram below, port A on SBC310 (2) needs to be NT so that each card can be configured by its own processor and operate in its own address domain. In contrast, Port B is connected to a PCIe end‐point, which will appear in SBC310 (2)’s memory map and so needs to be transparent. To make a port non‐transparent, the operating software is required to configure the switch accordingly. This cannot be done under hardware control, although it is possible to re‐program the PEX8518 configuration EEPROM, which will allow the board to boot with the desired switch configuration. The default configuration is for both ports to be transparent. Figure 6-12 VPX Port Configuration
6.17 LEDs
LEDs are mounted on the back of the SBC310 to reflect the status of several different functions: Power Supplies, BIT, PCI Express links, Ethernet links, SATA activity and reset. The following diagram shows the positions of the LEDs. Figure 6-13 LED Positions
Table 6-58 LED Functions
LED/Colour
Function
DS400/RED
BIT Status - Fail
DS401/GREEN
Power Good
DS402/YELLOW
BIT Status LED 1
DS403/ YELLOW
BIT Status LED 2
DS404/ YELLOW
BIT Status - Pass
DS405/ GREEN
On Board PCIe Status
When lit, all on-board PCIe links have initialized and trained successfully on at
least one lane.
DS406/ YELLOW
VPX port A PCIe status
When lit, the PCIe link on VPX port A has initialized and trained successfully on at
least one lane.
DS407/ YELLOW
VPX port B PCIe status
When lit, the PCIe link on VPX port B has initialized and trained successfully on at
least one lane.
DS408/ YELLOW
Ethernet Port 1 Transmit
Ethernet traffic being transmitted
DS409/ YELLOW
Ethernet Port 1
1000BaseT/100BaseT
When lit, Ethernet port operating in 1000BaseT mode. When unlit, Ethernet port
operating in 100BaseT, 10BaseT or not connected.
DS410/ YELLOW
Ethernet Port 0
1000BaseT/100BaseT
When lit, Ethernet port operating in 1000BaseT mode. When unlit, Ethernet port
operating in 100BaseT, 10BaseT or not connected.
DS411/ YELLOW
Ethernet Port 0 Transmit
Ethernet traffic being transmitted
DS412/ YELLOW
SATA Activity
Serial ATA activity on channel 0 or channel 1.
Description
When lit, indicates that on- and off-board power supplies are within
specification
Software programmable LEDs used to indicate
the status of BIT or other software
6.17.1
BIT Status LEDs
DS402 to D404 are used by the software running on the SBC310 (e.g. BIT) to indicate its status. The red BIT Fail LED (DS400) is illuminated following reset and must be turned off by software. The BIT Pass LED (DS404) is used to indicate that the software has completed any power‐up tests and is running correctly. NOTE
BIT LED 2 (DS403) has dual functionality. This LED also denotes that the on-board hard reset signal is
asserted.
Table 6-59 BIT Run State LEDs
BIT Fail LED
(DS400)
BIT Passed LED
(DS404)
Status
ON
OFF
BIT not run (Reset state)
OFF
ON
BIT complete and passed
The yellow BIT LEDs (DS402 and DS403) are used to indicate progress through the boot process and so may provide information for debugging purposes in the event of failure. These LEDs are software‐programmable and may be subsequently reassigned for another purpose. The status of the BIT Fail LED is replicated on the BIT FAIL output signal (connector P2 pin G1). 6.17.2
PCI Express Link Status LEDs
The Link Good LEDs will light if any link has been made between the two devices, even if it is of reduced width (a x1 link on a x8 connection for example). The exact state of each link can only be determined by software interrogation of the device registers. 6.17.3
Ethernet Link Status LEDs
These LEDs are under the control of the 88E1111 PHYs and the descriptions define the default functions of the LED outputs. These are under software control, however, and may be subsequently reassigned. 82 SBC310 3U VPX Single Board Computer
6.18 Front Panel
6.18.1
Air-cooled Versions
PMC/XMC Slot
The SBC310 front panel has provision for front I/O from the PMC/XMC site. If PMCs have not been ordered as part of an assembly with the SBC310, then GEIP will fit a blanking plate in the slot(s) for EMC protection. If fitting a non‐GEIP PMC, it must comply with the P1386 standard for air‐cooled mezzanines to ensure that it mates correctly with the SBC310 mechanics. GEIP PMCs comply with this standard. Before fitting a PMC module, remove the corresponding blanking plate from the desired PMC slot. The PMC’s bezel should fill the slot and may provide front panel connection to the module. GEIP PMCs are delivered with a full kit of parts for mounting, plus fitting instructions. NOTE
The PMC site is not fully compliant when all banks of memory is fitted as the keep-out area is used.
See PMC functionality section.
LEDs
Five LEDs are visible from the front panel. One indicates that all off‐ and on‐board power supplies are within specification and the other four are software‐
programmable and are used to reflect the status of BIT or other software. Refer to the LEDs section below for more details. 6.18.2
Conduction-cooled Versions
PMC/XMC Slot
There is no access to front I/O from PMCs/XMCs in a conduction‐cooled environment. If fitting a non‐GEIP PMC, it must comply with the standard for rugged, conduction‐
cooled PMCs (VITA20‐2001) to ensure that it mates correctly with the SBC310 mechanics. GEIP PMCs comply with this standard. NOTE
The PMC site is not fully compliant when all banks of memory is fitted as the keep-out area is used.
See PMC functionality section.
LEDs
Five LEDs are visible from the front panel. One indicates that all off‐ and on‐board power supplies are within specification and the other four are software‐
programmable and are used to reflect the status of BIT or other software. Refer to the LEDs section below for more details. Publication No. SBC310-0HH/5
7 • Connectors
This section gives the pin assignments and signal descriptions for the connectors on the SBC310. The following table shows the function of the connectors on the SBC310: Table 7-1 Connector Functions
Connector
Function
Connector
Function
P1
VPX P1
J15, J16
XMC Site 1
P2
VPX P2
P17
Test Board Connector
P0
VPX Utility Connector
J11, J12, J13, J14
PMC Site 1
Figure 7-1 Connector Positions
7.1 Backplane Connectors
7.1.1
OpenVPX (VITA65) compatibility
OpenVPX compatibility is supported on the SBC310 by using configuration resistors to change the functionality of pins P1/G15 and P2/G11. When configured for OpenVPX compatibility, P1/G15 is N/C and P2/G11 is “COM2_RXD or COM2_RXD_A”. When configured for VITA46 compatibility, P1/G15 is “COM2_RXD or COM2_RXD_A” and P2/G11 is “JTAG_AUTOWRITE”. The dual functionality is shown in the tables below. OpenVPX compatibility can be selected as a variant option. See “variants” section for more information. 7.1.2
P0 (VPX Utility connector) Pin Assignments
The SBC310 backplane connector conforms to the VITA46.0 standard Table 7-2 P0 Pin Assignments
Pin
1
2
3
4
5
6
7
8
Wafer Type
Power
Power
Power
Singleended
Singleended
Singleended
Differential
Differential
Row G
N/C
N/C
Vs3
Row F
N/C
N/C
Vs3
Row E
N/C
N/C
Vs3
Row D
No Pad
No Pad
No Pad
Row C
Vs2
Vs2
Vs3
Row B
Vs2
Vs2
Vs3
Row A
Vs2
Vs2
Vs3
N/C
N/C
GND
-12V_AUX
GND
SYSRESET~
NVMRO
GAP~
GA4~
GND
3.3V_AUX
GND
SM0
SM1
GA3~
GA2~
GND
+12V_AUX
GND
GA1~
GA0*
TCK
GND
GND
N/C
TDO
N/C
TDI
GND
GND
N/C
TMS
N/C
TRST*
GND
7.1.3
J0 VPX Backplane Pin Assignments
VPX backplane connector. Table 7-3 J0 VPX Backplane Pin Assignments
Pin
Wafer Type
Row I
Row H
RowG
Row F
Row E
Row D
Row C
Row B
Row A
1
Power
Vs1 (n/c)
Vs1 (n/c)
Vs1 (n/c)
Vs1 (n/c)
None
Vs2 (3V3)
Vs2 (3V3)
Vs2 (3V3)
Vs2 (3V3)
2
Power
Vs1 (n/c)
Vs1 (n/c)
Vs1 (n/c)
Vs1 (n/c)
None
Vs2 (3V3)
Vs2 (3V3)
Vs2 (3V3)
Vs2 (3V3)
3
Power
Vs3 (5V)
Vs3 (5V)
Vs3 (5V)
Vs3 (5V)
None
Vs3 (5V)
Vs3 (5V)
Vs3 (5V)
Vs3 (5V)
4
5x2 SE
GND
SM2 (n/c)
SM3 (n/c)
GND
-12V Aux
GND
SYSRST~
NVMRO
GND
5
5x2 SE
GND
GAP~
GA4~
GND
3.3V Aux
GND
SM0
SM1
GND
6
5x2 SE
GND
GA3~
GA2~
GND
+12V Aux
GND
GA1~
GA0~
GND
7
Diff
TCLK
GND
GND
TDO
TDI
GND
GND
TMS
TRST
8
Diff
GND
REFCLK- (n/c)
REFCLK+ (n/c)
GND
GND
RESBUS- (n/c)
RESBUS+ (n/c)
GND
GND
Connectors 85
7.1.4
P0/J0 Signal Definitions
Table 7-4 P0 Signal Definitions
Signal
Signal Description
+12V_AUX
VPX +12V_AUX Power input. Connected to the PMC/XMC site, otherwise unused by the SBC310
-12V_AUX
VPX -12V_AUX Power input. Connected to the PMC/XMC site, otherwise unused by the SBC310
3.3V_AUX
VPX 3.3V_AUX Power Input. See electrical spec for more details
GA0~ to GA4~
Geographical Addressing input bits.
GAP~
Geographical addressing parity bit input. The sum of all GA bits, including the parity bit, should be an odd number.
NVMRO
Non-Volatile Memory Read Only. Driven low by the SBC310 if the NVMRO Override bit in control register 1 is set, and the
SBC310 is configured to be system controller
REF_CLK-
VPX REF_CLK-. Not Connected on the SBC310
REF_CLK+
VPX REF_CLK+. Not Connected on the SBC310
RES_BUS-
VPX RES_BUS-. Defined by Vita46.0 as a reserved bus. Not Connected on the SBC310
RES_BUS+
VPX RES_BUS+. Defined by Vita46.0 as a reserved bus. Not Connected on the SBC310
SM0
SM1
System Management bus 0 CLK. Connects to the on-board Bit Management Microcontroller (BMM) via an I2C buffer.
Allows access to certain on-board resources from an external I2C master.
System Management bus 0 DATA. Connects to the on-board Bit Management Microcontroller (BMM) via an I2C buffer.
Allows access to certain on-board resources from an external I2C master.
SM2
System Management bus 1 CLK. Not connected on the SBC310.
SM3
System Management bus 1 DATA. Not connected on the SBC310.
SYSRESET~
VPX System Reset (Bidirectional). When the SBC310 is configured to be a system controller, this signal is driven low
when an on-board hard reset event occurs. When asserted, it is driven for a minimum of 10ms. In all configurations, the
SBC310 is reset when this signal is asserted by the backplane.
TCK
JTAG TCK input. AC terminated and connects directly to the JTS06 Scan bridge device.
TDI
JTAG TDI input. Connects to the JTS06 Scanbridge device.
TDO
JTAG TDO output. Driven by the JTS06 Scanbridge device through a 20ohm series terminating resistor.
TMS
JTAG TMS input. Connects to the JTS06 Scanbridge device.
TRST~
JTAG TCK input. Connects to the JTS06 Scanbridge device.
VS1
VPX VS1 (12V) power input. Not Connected on the SBC310
VS2
VPX VS2 (3.3V) Power input. See electrical specification for more details
VS3
VPX Vs3 (5V) Power input. See electrical specifications for more details
7.1.5
P1 Connector Pin Assignments
SBC310 backplane connector. Table 7-5 P1 Pin Assignments
Pin
Wafer
Type
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
Diff
N/C
GND
PETA0-
PETA0+
GND
PERA0-
PERA0+
2
Diff
GND
PETA1-
PETA1+
GND
PERA1-
PERA1+
GND
3
Diff
VBAT
GND
PETA2-
PETA2+
GND
PERA2-
PERA2+
4
Diff
GND
PETA3-
PETA3+
GND
PERA3-
PERA3+
GND
5
Diff
SYSCON~
GND
PETB0-
PETB0+
GND
PERB0-
PERB0+
6
Diff
GND
PETB1-
PETB1+
GND
PERB1-
PERB1+
GND
7
Diff
N/C
GND
PETB2-
PETB2+
GND
PERB2-
PERB2+
8
Diff
GND
PETB3-
PETB3+
GND
PERB3-
PERB3+
GND
9
Diff
COM1_TXD/
COM1_TXD_A
GND
SATAT0-
SATAT0+
GND
SATAR0-
SATAR0+
10
Diff
GND
USB1-
USB1+
GND
USB0-
USB0+
GND
11
Diff
COM1_RXD/
COM1_RXD_A
GND
GPIO1/
SATAT1-
GPIO0/
SATAT1+
GND
USB1-5V
USB0-5V
12
Diff
GND
GPIO5/
BIT Fast-Start/
AXIS_TMR_CLK
GPIO4/
AXIS_TMR_RST
GND
GPIO3/
SATAR1-
GPIO2/
SATAR1+
GND
13
Diff
COM2 TXD/
COM2_TXD_A
GND
ETH1B-
ETH1B+
GND
ETH1A-
ETH1A+
14
Diff
GND
ETH1D-
ETH1D+
GND
ETH1C-
ETH1C+
GND
15
Diff
COM2_RXD/
COM2_RXD_A/
No Connect
GND
ETH0B-
ETH0B+
GND
ETH0A-
ETH0A+
16
Diff
GND
ETH0D-
ETH0D+
GND
ETH0C-
ETH0C+
GND
Connectors 87
7.1.6
J1 VPX Backplane Pin Assignments
VPX backplane connector. Table 7-6 J1 VPX Backplane Pin Assignments
Pin
Wafer
Type
Row I
Row H
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
Diff
ResBus0 (n/c)
GND
GND
PETA0-
PETA0+
GND
GND
PERA0-
PERA0+
2
Diff
GND
PETA1-
PETA1+
GND
GND
PERA1-
PERA1+
GND
GND
3
Diff
VBAT
GND
GND
PETA2-
PETA2+
GND
GND
PERA2-
PERA2+
4
Diff
GND
PETA3-
PETA3+
GND
GND
PERA3-
PERA3+
GND
GND
5
Diff
SYSCON~
GND
GND
PETB0-
PETB0+
GND
GND
PERB0-
PERB0+
6
Diff
GND
PETB1-
PETB1+
GND
GND
PERB1-
PERB1+
GND
GND
7
Diff
RFU1 (n/c)
GND
GND
PETB2-
PETB2+
GND
GND
PERB2-
PERB2+
8
Diff
GND
PETB3-
PETB3+
GND
GND
PERB3-
PERB3+
GND
GND
9
Diff
COM1_TXD/
COM1_TXD_A
GND
GND
SATAT0-
SATAT0+
GND
GND
SATAR0-
SATAR0+
10
Diff
GND
USB1-
USB1+
GND
GND
USB0-
USB0+
GND
GND
11
Diff
COM1_RXD/
COM1_RXD_A
GND
GND
GPIO1/
SATAT1-
GPIO0
/SATAT1+
GND
GND
USB1_5V
USB0_5V
12
Diff
GND
GPIO5/BIT faststart
GPIO4
GND
GND
GPIO3/
SATAR1-
GPIO2/
SATAR1+
GND
GND
13
Diff
COM2_TXD/
COM2_TXD_A
GND
GND
ETH1B-
ETH1B+
GND
GND
ETH1A-
ETH1A+
14
Diff
GND
ETH1D-
ETH1D+
GND
GND
ETH1C-
ETH1C+
GND
GND
15
Diff
COM2 RXD/
COM2 RXD_A/ No
Connect
GND
GND
ETH0B-
ETH0B+
GND
GND
ETH0A-
ETH0A+
16
Diff
GND
ETH0D-
ETH0D+
GND
GND
ETH0C-
ETH0C+
GND
GND
7.1.7
Signal
COM1_RXD/
COM1_RXD_A
COM1_TXD/
COM1_TXD_A
COM2_ RXD/
COM2_ RXD_A/
No Connect**
COM2_ TXD/
COM2_ TXD_A
Signal Description
Dual function pin: When COM1 is in RS232 mode, this pin is Receive Data driven to SBC310 COM1. When COM1 is in
RS422 mode, this signal is RXA (Receive data A)
Dual function pin: When COM1 is in RS232 mode, this pin is Transmit Data driven by SBC310 COM1. When COM1 is in
RS422 mode, this signal is TXA (Transmit data A)
Dual function pin: When COM2 is in RS232 mode, this pin is Receive Data driven to SBC310 COM2. When COM2 is in
RS422 mode, this signal is RXB RXA (Receive data BA).
When the SBC310 is configured for OpenVPX compatibility mode, this pin is not connected.**
Dual function pin: When COM2 is in RS232 mode, this pin is Transmit Data driven by SBC310 COM2. When COM2 is in
RS422 mode, this signal is TXB TXA (Transmit data BA)
ETH0n+/-
Gigabit Ethernet differential signal pairs for Ethernet channel port 0
ETH1n+/-
Gigabit Ethernet differential signal pairs for Ethernet channel port 1
GPIO0-3/SATA1xx
Dual function pin. Hardware configurable (variant option) as GPIOn or SATA channel 1 data signal
GPIO4/AXIS_TMR_RST
Configurable by operating system as GPIO5 or AXIS_TMR_RST, which is an output in Master mode, else an input.
GPIO5/BIT Faststart/AXIS_TMR_CLK
Triple function pin. Software configurable (by BIT software) as GPIO5 or BIT Fast Start input. Configurable by operating
system as GPIO5 or AXIS_TMR_CLK, which is an output in Master mode, else an input.
PERAn+/-
PCI-Express link A, lane x Receive data ddifferntial pair
PERBn+/-
PCI-Express link B, lane x Receive data ddifferntial pair
PETAn+/-
PCI-Express link A, lane x transmit data differential pair
PETBn+/-
PCI-Express link B, lane x transmit data differential pair
RFU1
Defined by Vita46.0 as Reserved for Future Use
SATAR0+/-
Serial ATA channel 0 Receive data differential pair
SATAT0+/-
Serial ATA channel 0 Transmit data differential pair
SYSCON~
Drive low to enable the SBC310 as VPX system controller
USB0_5V
Switched +5V Power output to USB port 0
USB0+/-
Differential Signal pairs for USB port 0
USB1_5V
Switched +5V Power output to USB port 1
USB1+/-
Differential Signal pairs for USB port 1
VBAT
VPX Backup supply input (see electrical specs for details)
NOTE
For RS422 signals, the non-inverting output of the differential pair is designated ‘B’ and the inverting
output is designated ‘A’.
* COM1 RS422 mode is not available on PCB revisions 1 & 2.
** OpenVPX compatibility mode not available on PCB revisions 1 & 2.
Figure 7-2 Example Waveforms
Connectors 89
7.1.8
P2 Connector Pin Assignments (PMC P64s config.)
SBC310 backplane connector Table 7-8 P2 Pin Assignments (PMC P64s Configuration)
Pin
Wafer Type
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
Diff
BIT_FAIL~
GND
PMC_IO_01
PMC_IO_03
GND
PMC_IO_02
PMC_IO_04
2
Diff
GND
PMC_IO_05
PMC_IO_07
GND
PMC_IO_06
PMC_IO_08
GND
3
Diff
COM1_RTS/
COM1_TXD_B
GND
PMC_IO_09
PMC_IO_11
GND
PMC_IO_10
PMC_IO_12
4
Diff
GND
PMC_IO_13
PMC_IO_15
GND
PMC_IO_14
PMC_IO_16
GND
5
Diff
COM1_CTS/
COM1_RXD_B
GND
PMC_IO_17
PMC_IO_19
GND
PMC_IO_18
PMC_IO_20
6
Diff
GND
PMC_IO_21
PMC_IO_23
GND
PMC_IO_22
PMC_IO_24
GND
7
Diff
COM2_RTS/
COM2_TXD_B
GND
PMC_IO_25
PMC_IO_27
GND
PMC_IO_26
PMC_IO_28
8
Diff
GND
PMC_IO_29
PMC_IO_31
GND
PMC_IO_30
PMC_IO_32
GND
9
Diff
COM2_CTS/
COM2_RXD_B
GND
PMC_IO_33
PMC_IO_35
GND
PMC_IO_34
PMC_IO_36
10
Diff
GND
PMC_IO_37
PMC_IO_39
GND
PMC_IO_38
PMC_IO_40
GND
11
Diff
AUTO_WR/
COM2_RXD/
COM2_RXD_A
GND
PMC_IO_41
PMC_IO_43
GND
PMC_IO_42
PMC_IO_44
12
Diff
GND
PMC_IO_45
PMC_IO_47
GND
PMC_IO_46
PMC_IO_48
GND
13
Diff
PSU_SEQ_IN
GND
PMC_IO_49
PMC_IO_51
GND
PMC_IO_50
PMC_IO_52
14
Diff
GND
PMC_IO_53
PMC_IO_55
GND
PMC_IO_54
PMC_IO_56
GND
15
Diff
PSU_SEQ_OUT
GND
PMC_IO_57
PMC_IO_59
GND
PMC_IO_58
PMC_IO_60
16
Diff
GND
PMC_IO_61
PMC_IO_63
GND
PMC_IO_62
PMC_IO_64
GND
7.1.9
P2 Connector Pin Assignments (XMC X20d24s config.)
Table 7-9 P2 Connector (XMC X20d24s Configuration)
Pin
Wafer Type
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
Diff
BIT_FAIL~
GND
XMC_IO_C08
XMC_IO_C09
GND
XMC_IO_F08
XMC_IO_F09
2
Diff
GND
XMC_IO_C10
XMC_IO_C11
GND
XMC_IO_F10
XMC_IO_F11
GND
3
Diff
COM1_RTS
GND
XMC_IO_C12
XMC_IO_C13
GND
XMC_IO_F12
XMC_IO_F13
4
Diff
GND
XMC_IO_C14
XMC_IO_C15
GND
XMC_IO_F14
XMC_IO_F15
GND
5
Diff
COM1_CTS
GND
XMC_IO_C16
XMC_IO_C17
GND
XMC_IO_F16
XMC_IO_F17
6
Diff
GND
XMC_IO_C18
XMC_IO_C19
GND
XMC_IO_F18
XMC_IO_F19
GND
7
Diff
COM2_RTS/
COM2_TXD_B
GND
XMC_IO_A01
XMC_IO_B01
GND
XMC_IO_D01
XMC_IO_E01
8
Diff
GND
XMC_IO_A03
XMC_IO_B03
GND
XMC_IO_D03
XMC_IO_E03
GND
9
Diff
COM2_CTS/
COM2 RXD_B
GND
XMC_IO_A11
XMC_IO_B11
GND
XMC_IO_D11
XMC_IO_E11
10
Diff
GND
XMC_IO_A13
XMC_IO_B13
GND
XMC_IO_D13
XMC_IO_E13
GND
11
Diff
AUTO_WR/
COM2_RXD/
COM2_RXD_A
GND
XMC_IO_A05
XMC_IO_B05
GND
XMC_IO_D05
XMC_IO_E05
12
Diff
GND
XMC_IO_A07
XMC_IO_B07
GND
XMC_IO_D07
XMC_IO_E07
GND
13
Diff
PSU_SEQ_IN
GND
XMC_IO_A09
XMC_IO_B09
GND
XMC_IO_D09
XMC_IO_E09
14
Diff
GND
XMC_IO_A15
XMC_IO_B15
GND
XMC_IO_D15
XMC_IO_E15
GND
15
Diff
PSU_SEQ_OUT
GND
XMC_IO_A17
XMC_IO_B17
GND
XMC_IO_D17
XMC_IO_E17
16
Diff
GND
XMC_IO_A19
XMC_IO_B19
GND
XMC_IO_D19
XMC_IO_E19
GND
Connectors 91
7.1.10
J2 VPX Backplane Pin Assignments (PMC P64s config.)
VPX backplane connector. Table 7-10 J2 VPX backplane Pin Assignments (PMC P64s Configuration)
Pin
Wafer
Type
Row I
Row H
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
Diff
BIT_FAIL~
GND
GND
PMC_IO_01
PMC_IO_03
GND
GND
PMC_IO_02
PMC_IO_04
2
Diff
GND
PMC_IO_05
PMC_IO_07
GND
GND
PMC_IO_06
PMC_IO_08
GND
GND
3
Diff
COM1_RTS/
COM1_TXD_B
GND
GND
PMC_IO_09
PMC_IO_11
GND
GND
PMC_IO_10
PMC_IO_12
4
Diff
GND
PMC_IO_13
PMC_IO_15
GND
GND
PMC_IO_14
PMC_IO_16
GND
GND
5
Diff
COM1_CTS/
COM1_RXD_B
GND
GND
PMC_IO_17
PMC_IO_19
GND
GND
PMC_IO_18
PMC_IO_20
6
Diff
GND
PMC_IO_21
PMC_IO_23
GND
GND
PMC_IO_22
PMC_IO_24
GND
GND
7
Diff
COM2_RTS/
COM2_TXD_B
GND
GND
PMC_IO_25
PMC_IO_27
GND
GND
PMC_IO_26
PMC_IO_28
8
Diff
GND
PMC_IO_29
PMC_IO_31
GND
GND
PMC_IO_30
PMC_IO_32
GND
GND
9
Diff
COM2_CTS/
COM2_RXD_B
GND
GND
PMC_IO_33
PMC_IO_35
GND
GND
PMC_IO_34
PMC_IO_36
10
Diff
GND
PMC_IO_37
PMC_IO_39
GND
GND
PMC_IO_38
PMC_IO_40
GND
GND
11
Diff
AUTO_WR/
COM2_RXD/
COM2_RXD_A
GND
GND
PMC_IO_41
PMC_IO_43
GND
GND
PMC_IO_42
PMC_IO_44
12
Diff
GND
PMC_IO_
PMC_IO_
GND
GND
PMC_IO_
PMC_IO_
GND
GND
13
Diff
SEQ_IN
GND
GND
PMC_IO_49
PMC_IO_51
GND
GND
PMC_IO_50
PMC_IO_52
14
Diff
GND
PMC_IO_53
PMC_IO_55
GND
GND
PMC_IO_54
PMC_IO_56
GND
GND
15
Diff
SEQ_OUT
GND
GND
PMC_IO_57
PMC_IO_59
GND
GND
PMC_IO_58
PMC_IO_60
16
Diff
GND
PMC_IO_61
PMC_IO_63
GND
GND
PMC_IO_62
PMC_IO_64
GND
GND
7.1.11
J2 VPX Backplane Pin Assignments (XMC X20d24s config.)
Table 7-11 J2 VPX backplane Pin Assignments (XMC X20d24s Configuration)
Pin
Wafer
Type
Row I
Row H
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
Diff
BIT_FAIL~
GND
GND
XMC_IO_C08
XMC_IO_C09
GND
GND
XMC_IO_F08
XMC_IO_F09
2
Diff
GND
XMC_IO_C10
XMC_IO_C11
GND
GND
XMC_IO_F10
XMC_IO_F11
GND
GND
3
Diff
COM1_RTS/
COM1_TXD_B
GND
GND
XMC_IO_C12
XMC_IO_C13
GND
GND
XMC_IO_F12
XMC_IO_F13
4
Diff
GND
XMC_IO_C14
XMC_IO_C15
GND
GND
XMC_IO_F14
XMC_IO_F15
GND
GND
5
Diff
COM1_CTS/
COM1_RXD_B
GND
GND
XMC_IO_C16
XMC_IO_C17
GND
GND
XMC_IO_F16
XMC_IO_F17
6
Diff
GND
XMC_IO_C18
XMC_IO_C19
GND
GND
XMC_IO_F18
XMC_IO_F19
GND
GND
7
Diff
COM2_RTS/
COM2_TXD_B
GND
GND
XMC_IO_A01
XMC_IO_B01
GND
GND
XMC_IO_D01
XMC_IO_E01
8
Diff
GND
XMC_IO_A03
XMC_IO_B03
GND
GND
XMC_IO_D03
XMC_IO_E03
GND
GND
9
Diff
COM2_CTS/
COM2_RXD_B
GND
GND
XMC_IO_A11
XMC_IO_B11
GND
GND
XMC_IO_D11
XMC_IO_E11
10
Diff
GND
XMC_IO_A13
XMC_IO_B13
GND
GND
XMC_IO_D13
XMC_IO_E13
GND
GND
11
Diff
AUTO_WR/
COM2_RXD/
COM2_RXD_A
GND
GND
XMC_IO_A05
XMC_IO_B05
GND
GND
XMC_IO_D05
XMC_IO_E05
12
Diff
GND
XMC_IO_A07
XMC_IO_B07
GND
GND
XMC_IO_D07
XMC_IO_E07
GND
GND
13
Diff
SEQ_IN
GND
GND
XMC_IO_A09
XMC_IO_B09
GND
GND
XMC_IO_D09
XMC_IO_E09
14
Diff
GND
XMC_IO_A15
XMC_IO_B15
GND
GND
XMC_IO_D15
XMC_IO_E15
GND
GND
15
Diff
SEQ_OUT
GND
GND
XMC_IO_A17
XMC_IO_B17
GND
GND
XMC_IO_D17
XMC_IO_E17
16
Diff
GND
XMC_IO_A19
XMC_IO_B19
GND
GND
XMC_IO_D19
XMC_IO_E19
GND
GND
Connectors 93
7.1.12
Signal
Signal Description
COM1_CTS/
COM1_RXD_B*
COM1_RTS/
COM1_TXD_B*
COM2_CTS/
COM2_RXD_B
COM2_RTS/
COM2_TXD_B
Triple function pin. When the SBC310 is configured for VITA46 compatibility, this pin is JTAG Autowrite. Used by JTAG
boundary scan equipment to directly strobe the flash write enable pin to speed up flash programming times. Since this pin is
classed as user defined by VITA46.0, this signal can be isolated by removing a resistor if required.When the SBC310 is
configured for openVPX compatibility mode, this pin is COM2_RXD/COM2_RXD_A (see Table 6-9 for definition).
Active low TTL compliantopen-drain output driven by the on-board Bit Management Memory Controllerwhich replicates the
state of the BIT FAIL LED. Since this pin is classed as user defined by VITA46.0, this signal can be isolated by removing a
resistor if required.
Dual function pin: When COM1 is in RS232 mode, this pin is CTS (Clear to Send) input signal used by SBC310 COM1. When
COM1 is in RS422 mode, this signal is RXB (Receive data B) .
Dual function pin: When COM1 is in RS232 mode, this pin is RTS (Ready to Send) output signal driven by SBC310 COM1. When
COM1 is in RS422 mode, this signal is TXB (Transmit data B).
Dual function pin: When COM2 is in RS232 mode, this pin is CTS (Clear to Send) intput signal used by SBC310 COM2. When
COM2 is in RS422 mode, this signal is RXB (Receive data B).
Dual function pin: When COM2 is in RS232 mode, this pin is RTS (Ready to Send) output signal driven by SBC310 COM2. When
COM2 is in RS422 mode, this signal is TXB (Transmit data B).
PMC_IO_x
PMC I/O where x=J14 pin number.
AUTO_WR/
COM2_RXD/
COM2_RXD_A**
BIT_FAIL~
PSU_SEQ_IN
SEQ_SEQ_OUT
XMC_IO_x
Used by the power-manager device for inter-board sequencing. When low, the SBC310 will hold off it’s on-board powersupplies until it transitions high, or until it’s been low for 500 ms.
Driven by the power-manager device for inter-board sequencing. When high, it indicates to the system that all on-board
supplies are within regulation.
XMC I/O where x=J16 pin number
NOTE
For RS422 signals, the non-inverting output of the differential pair is designated ‘B’ and the inverting
output is designated ‘A’.
*Note: COM1 RS422 mode is not available on PCB revisions 1 & 2.
**Note: OpenVPX compatibility mode not available on PCB revisions 1 & 2.
Figure 7-3 Example Waveforms
7.2 PMC Connectors
7.2.1
J11 Connector Pin Assignments
Table 7-13 J11 Pin Assignments
Pin
Signal
Pin
Signal
1
TCK
2
-12V
3
GND
4
INTA~
5
INTB~
6
INTC~
7
BUSMODE1~
8
+5V
9
INTD~
10
NC
11
GND
12
NC
13
CLK
14
GND
15
GND
16
GNTA~
17
REQA~
18
+5V
19
VIO (+3.3V)
20
AD31
21
AD28
22
AD27
23
AD25
24
GND
25
GND
26
CBE3~
27
AD22
28
AD21
29
AD19
30
+5V
31
VIO (+3.3V)
32
AD17
33
FRAME~
34
GND
35
GND
36
IRDY~
37
DEVSEL~
38
+5V
39
PCIXCAP
40
LOCK~
41
NC
42
NC
43
PAR
44
GND
45
VIO (+3.3V)
46
AD15
47
AD12
48
AD11
49
AD09
50
+5V
51
GND
52
CBE0~
53
AD06
54
AD05
55
AD04
56
GND
57
VIO (+3.3V)
58
AD03
59
AD02
60
AD01
61
AD00
62
+5V
63
GND
64
REQ64~
Connectors 95
7.2.2
Pin
Signal
Pin
Signal
1
+12V
2
TRST~
3
TMS
4
TDO
5
TDI
6
GND
7
GND
8
NC
9
NC
10
NC
11
BUSMODE2~
12
+3.3V
13
RST~
14
BUSMODE3~
15
+3.3V
16
BUSMODE4~
17
NC
18
GND
19
AD30
20
AD29
21
GND
22
AD26
23
AD24
24
+3.3V
25
IDSELA
26
AD23
27
+3.3V
28
AD20
29
AD18
30
GND
31
AD16
32
CBE2~
33
GND
34
IDSELB
35
TRDY~
36
+3.3V
37
GND
38
STOP~
39
PERR~
40
GND
41
+3.3V
42
SERR~
43
CBE1~
44
GND
45
AD14
46
AD13
47
M66EN
48
AD10
49
AD08
50
+3.3V
51
AD07
52
REQB~
53
+3.3V
54
GNTB~
55
NC
56
GND
57
NC
58
EREADY
59
GND
60
N/C
61
ACK64~
62
+3.3V
63
GND
64
MONARCH~
CAUTION
The SBC310 PMC sites are NOT 5V tolerant.
Do not fit PMCs that use 5V signaling
7.2.3
Pin
Signal
Pin
Signal
1
NC
2
GND
3
GND
4
CBE5~~
5
CBE6~
6
CBE5~
7
CBE4~
8
GND
9
VIO (+3.3V)
10
PAR64
11
AD63
12
AD62
13
AD61
14
GND
15
GND
16
AD60
17
AD59
18
AD58
19
AD57
20
GND
21
VIO (+3.3V)
22
AD56
23
AD55
24
AD54
25
AD53
26
GND
27
GND
28
AD52
29
AD51
30
AD50
31
AD49
32
GND
33
GND
34
AD48
35
AD47
36
AD46
37
AD45
38
GND
39
VIO (+3.3V)
40
AD44
41
AD43
42
AD42
43
AD41
44
GND
45
GND
46
AD40
47
AD39
48
AD38
49
AD37
50
GND
51
GND
52
AD36
53
AD35
54
AD34
55
AD33
56
GND
57
VIO (+3.3V)
58
AD32
59
NC
60
NC
61
NC
62
GND
63
GND
64
NC
Connectors 97
7.2.4
Pin
Signal
Pin
Signal
1
PMC_IO_1
2
PMC_IO_2
3
PMC_IO_3
4
PMC_IO_4
5
PMC_IO_5
6
PMC_IO_6
7
PMC_IO_7
8
PMC_IO_8
9
PMC_IO_9
10
PMC_IO_10
11
PMC_IO_11
12
PMC_IO_12
13
PMC_IO_13
14
PMC_IO_14
15
PMC_IO_15
16
PMC_IO_16
17
PMC_IO_17
18
PMC_IO_18
19
PMC_IO_19
20
PMC_IO_20
21
PMC_IO_21
22
PMC_IO_22
23
PMC_IO_23
24
PMC_IO_24
25
PMC_IO_25
26
PMC_IO_26
27
PMC_IO_27
28
PMC_IO_28
29
PMC_IO_29
30
PMC_IO_30
31
PMC_IO_31
32
PMC_IO_32
33
PMC_IO_33
34
PMC_IO_34
35
PMC_IO_35
36
PMC_IO_36
37
PMC_IO_37
38
PMC_IO_38
39
PMC_IO_39
40
PMC_IO_40
41
PMC_IO_41
42
PMC_IO_42
43
PMC_IO_43
44
PMC_IO_44
45
PMC_IO_45
46
PMC_IO_46
47
PMC_IO_47
48
PMC_IO_48
49
PMC_IO_49
50
PMC_IO_50
51
PMC_IO_51
52
PMC_IO_52
53
PMC_IO_53
54
PMC_IO_54
55
PMC_IO_55
56
PMC_IO_56
57
PMC_IO_57
58
PMC_IO_58
59
PMC_IO_59
60
PMC_IO_60
61
PMC_IO_61
62
PMC_IO_62
63
PMC_IO_63
64
PMC_IO_64
7.2.5
PMC Signal Descriptions
Table 7-17 PMC Signal Descriptions
Signal
Signal Description
+3.3V
+3.3V supply pins
+5V
+5V supply pins
ACK64~
Acknowledge 64 Bit. Driven low by PCI agent in response to REQ64
AD[63:0]
Address/Data bits. Multiplexed address and data bus
BUSMODE1~
Bus Mode 1. Driven low by a PMC if it supports the current bus mode. Used to detect the presence of a PMC on the site.
BUSMODE2~,
BUSMODE3~ and
BUSMODE4~
Bus mode. Driven by the host to indicate the bus mode. On the SBC310 this is always PCI. BUSMODE2~ is pulled-up.
BUSMODE3~ and BUSMODE4~ are connected to GND.
CBE[7:0]~
Command/Byte Enables. During the address phase, these signals specify the type of cycle to carry out on the PCI bus. During
the data phase the signals are byte enables that specify the active bytes on the bus
CLK
Clock. All PCI bus signals except RST~ are synchronous to this clock.
DEVSEL~
Device Select. Driven low by a PCI agent to signal that it has decoded its address as the target of the current access
EREADY
PCI Enumeration Ready. This signal can be held low by the PMC to indicate that it is not yet ready to be enumerated by the
PCI software.
FRAME~
FRAME. Driven low by the current master to signal the start and duration of an access
GNTA/B~
Grant. Driven low by the arbiter to grant PCI bus ownership to a PCI agent
IDSELA/B
Initialisation Device Select. Device chip select during configuration cycles
INTA~ to INTD~
Interrupt lines. Level-sensitive, active-low interrupt requests
IRDY~
Initiator Ready. Driven low by the initiator to signal its ability to complete the current data phase
LOCK~
LOCK. Driven low to indicate an atomic operation that may require multiple transactions to complete
MONARCH~
Monarch. If this signal is low, a processor PMC is expected to enumerate the bus and handle interrupts. It is pulled high on
the SBC310 and monarch mode is not supported.
NC
No connection
PAR
Parity. Parity protection bit for AD31 to AD0 and BE3 to BE0
PAR64
Parity. Parity protection bit for AD63 to AD32
PCIXCAP
PCI-X Capability detect. Used to determine whether a PMC is PCI-X capable.
PERR~
Parity Error. Driven low by a PCI agent to signal a parity error
REQ64~
Request 64 Bit. Driven low by PCI master to request 64 bit transfer
REQA/B~
Request. Driven low by a PCI agent to request ownership of the PCI bus
RESET_OUT~
Reset output. This signal can be driven by a Monarch PMC to reset the host board. This is Not Connected o the SBC310 as
monarch mode is not supported.
RST~
Reset. Driven low to reset the PCI bus
SERR~
System Error. Driven low by a PCI agent to signal a system error
STOP~
STOP. Driven low by a PCI target to signal a disconnect or target-abort
TCK
Test Clock. Clock for the PMC JTAG
TDI
Test Data In. Input data for PMC JTAG chain
TDO
Test Data Out. Data from a PMC JTAG chain
TMS
Test Mode Select. Select Test Mode for PMC JTAG
TRDY~
Target Ready. Driven low by the current target to signal its ability to complete the current data phase
TRST~
Test Reset. Reset any PMC JTAG devices
VIO (+3.3V)
PCI V(I/O) pins. Fixed to +3.3V on the SBC310 as +5V signalling is not supported.
Connectors 99
7.3 XMC Connectors
7.3.1
J15 Pin Assignments
J15 supplies the PCI Express interface for the XMC site. J16 rear I/O connectivity for the XMC Site. Table 7-18 J15 Pin Assignments
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
7.3.2
A
PCIE_TX0P
GND
PCIE_TX2P
GND
PCIE_TX4P
GND
PCIE_TX6P
GND
Reserved
GND
PCIE_RX0P
GND
PCIE_RX2P
GND
PCIE_RX4P
GND
PCIE_RX6P
GND
REFCLK_P
B
PCIE_TX0N
GND
PCIE_TX2N
GND
PCIE_TX4N
GND
PCIE_TX6N
GND
Reserved
GND
PCIE_RX0N
GND
PCIE_RX2N
GND
PCIE_RX4N
GND
PCIE_RX6N
GND
REFCLK_N
C
+3.3V
JTAG_TRST*
+3.3V
JTAG_TCK
+3.3V
JTAG_TMS
+3.3V
JTAG_TDI
Reserved
JTAG_TDO
MBIST~
GA1~
P3V3_AUX
GA2~
Reserved
NVMRO
Reserved
Reserved
Reserved
D
PCIE_TX1P
GND
PCIE_TX3P
GND
PCIE_TX5P
GND
PCIE_TX7P
GND
Reserved
GND
PCIE_RX1P
GND
PCIE_RX3P
GND
PCIE_RX5P
GND
PCIE_RX7P
GND
Wake
E
PCIE_TX1N
GND
PCIE_TX3N
GND
PCIE_TX5N
GND
PCIE_TX7N
GND
Reserved
GND
PCIE_RX1N
GND
PCIE_RX3N
GND
PCIE_RX5N
GND
PCIE_RX7N
GND
Root
F
+5V
RESET_IN~
+5V
RESET_OUT~
+5V
+12V
+5V
-12V
+5V
GA0~
+5V
PRESENT~
+5V
SM_DATA
+5V
SM_CLK
Reserved
Reserved
Reserved
D
XMC_IO_D01
GND
XMC_IO_D03
GND
XMC_IO_D05
GND
XMC_IO_D07
GND
XMC_IO_D09
GND
XMC_IO_D11
GND
XMC_IO_D13
GND
XMC_IO_D15
GND
XMC_IO_D17
GND
XMC_IO_D19
E
XMC_IO_E01
GND
XMC_IO_E03
GND
XMC_IO_E05
GND
XMC_IO_E07
GND
XMC_IO_E09
GND
XMC_IO_E11
GND
XMC_IO_E13
GND
XMC_IO_E15
GND
XMC_IO_E17
GND
XMC_IO_E19
F
NC
NC
NC
NC
NC
NC
NC
NC
XMC_IO_F09
XMC_IO_F10
XMC_IO_F11
XMC_IO_F12
XMC_IO_F13
XMC_IO_F14
XMC_IO_F15
XMC_IO_F16
XMC_IO_F17
XMC_IO_F18
XMC_IO_F19
J16 Pin Assignments
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
XMC_IO_A01
GND
XMC_IO_A03
GND
XMC_IO_A05
GND
XMC_IO_A07
GND
XMC_IO_A09
GND
XMC_IO_A11
GND
XMC_IO_A13
GND
XMC_IO_A15
GND
XMC_IO_A17
GND
XMC_IO_A19
B
XMC_IO_B01
GND
XMC_IO_B03
GND
XMC_IO_B05
GND
XMC_IO_B07
GND
XMC_IO_B09
GND
XMC_IO_B11
GND
XMC_IO_B13
GND
XMC_IO_B15
GND
XMC_IO_B17
GND
XMC_IO_B19
C
NC
NC
NC
NC
NC
NC
NC
NC
XMC_IO_C09
XMC_IO_C10
XMC_IO_C11
XMC_IO_C12
XMC_IO_C13
XMC_IO_C14
XMC_IO_C15
XMC_IO_C16
XMC_IO_C17
XMC_IO_C18
XMC_IO_C19
7.3.3
XMC Signal Descriptions
Table 7-20 XMC Signal Descriptions
Signal
Signal Description
- 12V
-12V supply (from backplane)
+12V
+12V supply (from backplane)
+3.3V
+3.3V supply pins
+5V
+5V supply pins
GA[2:0]~
Geographic Address. Used to identify the address of the XMC on a shared I2C bus.
JTAG_TCK
JTAG Test Clock. Clock for the XMC JTAG
JTAG_TDI
JTAG Test Data In. Input data for XMC JTAG chain
JTAG_TDO
JTAG Test Data Out. Data from an XMC JTAG chain
JTAG_TMS
JTAG Test Mode Select. Select Test Mode for XMC JTAG
JTAG_TRST~
JTAG Test Reset. Reset any XMC JTAG devices
MBIST~
XMC Built-in Self-Test. This signal can be held low by the XMC to indicate that it is not yet ready to be enumerated by
the root complex.
NC
No connection
NVMRO
Non-Volatile Memory Read Only. Used to write protect any non-volatile memory on the XMC. This signal is driven
inactive when the NVRAM Write Enable Link is fitted.
P3V3_AUX
Auxiliary supply (derived from P5VSTDBY or +5V)
PCIE_RX[7:0]P/N
PCI Express Receive Differential Pairs (from switch to XMC)
PCIE_TX[7:0]P/N
PCI Express Transmit Differential Pairs (from XMC to switch)
PRESENT~
XMC Present. Pulled low by the XMC to allow the host card to detect if an XMC is fitted
REFCLK_P/N
PCI Express Reference Clock. 100 MHz Differential clock to XMC.
Reserved
Reserved by VITA42.0 or 42.3 specification
RESET_IN~
XMC Reset In. Reset driven from the host board to the XMC.
RESET_OUT~
XMC Reset Out. Reset signal driven by the XMC to the board (from a front-panel switch for example)
SM_CLK
System Management Bus Clock. Clock line for a two-wire I2C system management bus
SM_DATA
System Management Bus Data. Data line for a two-wire I2C system management bus
XMCx_IO_*
Rear I/O Connection from XMC Site x.
7.4 P17 Connector
P17 is used to connect to the SBC310TST Test Access Board. Fitting this card allows access to the MPC8640(D)/MPC8641(D) COP interface for on‐chip debugging, and provides factory‐level functionality. Pin‐out information is not provided here since access to these signals can only be achieved using the Test Access Board – see Appendix B. Publication No. SBC310-0HH/5
Connectors 101
8 • Troubleshooting
If you are experiencing a problem with your SBC310, there follow some general suggestions of actions you may take, which may resolve the problem without the need to contact GEIP’s technical support. •
Check that there is only one board configured as system controller in a system. •
Check that the terminal is set up for DTE (9.6 kbaud, 8 bits/character, 1 stop bit, parity disabled) •
Ensure that air‐cooled SBC310s receive sufficient air‐flow. If you need to operate your SBC310 on an extender card, this requires an additional fan to supply the necessary air flow •
Ensure that conduction cooled SBC310s are fully installed in the conduction cooled box and that the wedgelocks are correctly tightened. If, for any reason, you need to operate a conduction cooled SBC310 on an extender card, you must maintain an airflow of at least 300 feet/minute over it •
Check the links on the board and the system backplane •
If you are unsure of which link configuration to use, try the default configuration (see the Link Settings section) initially CAUTION
SBC310 Rev2 and Rev3 boards have slightly different confirguration link layout. Please refer to
Chapters 3 and 4 respectively when considering the following suggestions.
•
If the SBC310 boot sequence is not as expected, check which of the 4 available boot images is selected on each node – see Sections 3.1.5 /3.1.6 and 4.1.3 /4.1.4 for further information. •
If the SBC310 is not running software at power‐up or reset, ensure that the External Programming link is out – see Sections 3.1.9 /4.1.8 . This link prevents Processor Core 0 from booting. •
If you are having difficulty programming the Flash, ensure that the Flash Protection Unlock link (Sections 3.1.7 /4.1.6 ) and NVMRO link (Sections 3.1.2 /4.1.5 ) are in and the backplane NVMRO signal is negated. NOTE
Irrespective of the link settings or software settings for Flash write protection, the Recovery Boot area
cannot be write-enabled.
•
If you are having difficulty configuring boot parameters for your operating system, ensure that the NVMRO Write Enable link is in (Sections 3.1.2 /4.1.5 ) and the backplane NVMRO signal is negated. •
If you are not testing the board using JTAG, ensure that the ScanBridge Enable link is out – see Sections 3.1.1 /4.1.7 . 102 SBC310 3U VPX Single Board Computer
Appendix A • Specifications
A.1 Mechanical Construction
Table A-1 Mechanical Construction
Weight
Dimensions
SBC310 Level 4-5 = Approx. 467g
SBC310 Level 1-3 = Approx. 305 g
The air-cooled SBC310 is constructed on a multi-layer 3U Eurocard and conforms to the dimensions
specified in the IEEE1101.1 specification. For layout drawings, refer to the
Standard Interfaces section.
The Conduction-cooled SBC310 is constructed on a multi-layer 3U Eurocard and conforms to the
dimensions specified in the IEEE 1101.2. For layout drawings, refer to the Standard Interfaces section.
A.2 Component Details
Table A-2 Component Details
Features
Integrated Host
Processor
Main Memory
Details
Freescale MPC8641/D,
MPC8640/D
Up to 2 GBytes DDR2 SDRAM with
ECC
Flash Memory
Up to 512 MBytes
Non-Volatile RAM
128 kBytes
On-board
Interconnect
Ethernet Interfaces
PCI Express
USB
Serial ATA
2x 10/100/1000BaseT ports
1x RS232 debug
1 x RS232/422 Async
2 ports
Up to 2 Channels
PMC/XMC Site
Single PMC/XMC Site
DMA Controllers
4
Timers
8 x 31-bit timers
Watchdog Timer
Two 32-bit timers
Real-Time Clock
Time Of Day/Calendar
Elapsed Time
Indicator
Quarter second resolution
Discrete Digital I/O
Up to 6-bits, TTL-compatible
JTAG Interface
On-board Scan bridge
Serial ports
Comments
Containing one or two e600 PowerPC processing cores @
up to 1.33 GHz
Dual memory controllers running at upto 266 MHz
Up to 16 MBytes allocated to Boot Flash and the rest to
User Flash. Advanced sector protection features.
Non-volatile storage for data that must not be lost when
power is removed. Power-down Autostore functionality
High bandwidth serial-interconnect. Non-blocking switch
architecture
Two Gigabit Ethernet ports
MPC8640(D)/MPC8641(D) provides COM1 & COM2 debug
ports
USB 2.0 capable
Supports speeds of up to 3.0Gbps
64-bit PCI-X interface at up to 133 MHz
x8 PCI Express interface
Available in the MPC8640(D)/MPC8641(D) for efficiently
moving large blocks of data
Provided by the MPC8640(D)/MPC8641(D). Programmable
frequency with up to 15ns resolution. Ability to cascade
to form larger timers.
Programmable interrupt and reset thresholds
1 second resolution. Standby power may be connected
from the VBAT pin to maintain data during power down
Logs the total accumulated time the board has been
powered, and the number of power cycles
Able to generate edge- or level-triggered interrupts. Can
be configured as open-drain outputs.
Scan bridge access through P0 connector, or
factory/debug access via Test Access Board
Specifications 103
A.3 Safety Rating
All PCBs are manufactured by UL approved manufacturers and have a flammability rating of 94V‐0. A.4 Environmental Specifications
A.4.1 Convection-cooled Boards
Table A-3
Criterion
Conformal Coat
High Temp Operational
Low Temp Operational
High Temp Storage
Low Temp Storage
Humidity
Vibration Sine
Build Level 1
Optional
55°C @ 300ft/min
0°C
100°C
-50°C
95% non-condensing
5-500Hz 2g
Build Level 2
Standard
65°C @ 300ft/min
-20°C
100°C
-50°C
95% 10cycles 240hrs
5-500Hz 2g
Vibration Random
0.002g2/Hz from 102000Hz
0.002g2/Hz from 102000Hz
Shock
20g Pk Sawtooth
11mSec Duration
20g Pk Sawtooth
11mSec Duration
Build Level 3
Standard
75°C @ 600ft/min
-40°C
100°C
-50°C
95% 10cycles 240hrs
0.04g2/Hz from 20 to 2000 Hz,
with a flat response to 1000Hz.
6dB/Oct roll-off from 10002000Hz
20g Pk Sawtooth 11mSec
Duration
A.4.2 Conduction-cooled Boards
Table A-4
Criterion
Conformal Coat
High Temp Operational
Low Temp Operational
High Temp Storage
Low Temp Storage
Humidity
Vibration Random
Shock
Build Level 4
Standard
75°C at I/F
-40°C
100°C
-50°C
95% 10cycles 240hrs
0.1g2/Hz from 15 to 2000 Hz per MILSTD-810E Fig 514.4 - 8 for high
performance aircraft. 12g RMS
40g Pk Sawtooth 11mSec Duration
Build Level 5
Standard
85°C at I/F
-40°C
100°C
-50°C
95% 10cycles 240hrs
0.1g2/Hz from 15 to 2000 Hz per MILSTD-810E Fig 514.4 - 8 for high
performance aircraft. 12g RMS
40g Pk Sawtooth 11mSec Duration
LINK
For a full explanation of build levels, refer to the Ruggedization Brochure available on our website at:
http://www.ge-ip.com/products/family/embedded-systems/
A.5 Electrical Specifications
A.5.1 Voltage Supply Requirements
The VPX VS3 (+5V) and VPX VS2 (+3.3V) and 3.3V_AUX supplies are required and must remain within the specified as defined below. If any of these supplies is outside of these specifications at power‐up, then the SBC310 will fail to start. If during a powered state these supplies fall outside of these limits then the SBC310 will be held in reset. The VPX ±12V_AUX supplies are not used on the SBC310 but are connected to the PMC/XMC site. Table A-5 Voltage Requirements
Supply
VS2
VS3
3.3V_AUX
The following supplies are
optional:
+12V_AUX
-12V_AUX
VBAT
MIN
+3.25V
+4.88V
+3.14V
NOM
+3.3V
+5.0V
+3.3V
MAX
+3.45V
+5.25V
+3.46V
+11.4V
-11.4V
1.8V
+12.0V
-12.0V
3.3V
+12.6V
-12.6V
5.0V
WARNING
Do not exceed the maximum rated input voltages or apply reversed bias to the assembly. If such
conditions occur, toxic fumes may be produced due to the destruction of components.
A.5.2 Current Consumption
Current consumption figures for SBC310 are shown below. These are given at cold‐
wall temperatures of +25°C and +85°C in a conduction‐cooled environment All figures were measured on a board with 1 GByte of DDR2 SDRAM and 256 MBytes of Flash. All Gigabit Ethernet links were active but idle. Typical consumption was measured whilst running VxWorks shell prompt (on both cores for dual core variants). Maximum consumption was measured whilst running a FFT test (on both cores for dual‐core variants). Table A-6 VS3 (5V) Current Consumption
Temperature (°C)
+25
+85
Operation
MPC8640D @ 1067 MHz
MPC8641 @ 1333 MHz
MPC8640 @ 1067 MHz
Typical
5.3A (26.5W)
5.1A (25.5W)
TBD
Maximum
TBD
TBD
TBD
Typical
7.7A (38.5W)
7.0A (35W)
TBD
Maximum
TBD
TBD
TBD
VS2 (3V3)
Consumption
All boards under all conditions consume a maximum of 0.73A (2.4W) on this supply rail. Publication No. SBC310-0HH/5
Specifications 105
+3.3V_AUX
Consumption
All boards under all conditions consume a maximum of 200mA (0.7W) on this supply rail. NOTE
When using PMCs, ensure that they do not cause the specified maximum supply current to be
exceeded. It may not be possible to support all combinations of PMCs within this limit.
A.5.3 GPIO Electrical Characteristics
Table A-7 GPIO Electrical Characteristics
Parameter
Vinl
Vinh
Voutl
Vouth
Min
-0.3V
2.0V
2.9V
Max
0.8V
3.6V
0.4V
-
GPIO Absolute
maximum
ratings
Table A-8 GPIO Absolute maximum ratings
Pin
Any GPIO pin
Max (V)
-0.5 to +7
A.6 Reliability (MTBF)
The following table shows the predicted values for reliability as Mean Time Between Failures (MTBF) and Failures Per Million Hours (FPMH). The predictions are carried out using MIL‐HDBK‐217F Notice 2, Parts Count method. To complement the 217 failure rates, some manufacturers’ data is included where appropriate; πQ values have been modified according to the ANSI/VITA51.1 Specification. Table A-9 SBC310 Reliability (MTBF)
Environment
Fail Rate
(FPMH)
MTBF
(Hours)
Ground benign 30°c
1.7861
559,868
Ground fixed 40°c
8.3989
119,063
Ground mobile 45°c
21.4554
46,608
Naval sheltered 40°c
11.8625
84,299
Naval unsheltered 45°c
29.9903
33,344
Airborne inhabited cargo 55°c
21.2858
46,980
Airborne inhabited fighter 55°c
29.1683
34,284
Airborne uninhabited cargo 70°c
55.3243
18,075
Airborne uninhabited fighter 70°c
74.0230
13,509
Airborne rotary wing 55°c
62.6316
15,966
Space flight 30°c
1.3536
738,765
Missile flight 45°c
33.48365
29,865
Missile launch 55°c
96.5305
10,359
These failure rates are based only on the components and connectors fitted to the board at delivery and take no account of user fitted PMCs. 106 SBC310 3U VPX Single Board Computer
A.7 Product Codes
Table A-10 Product Options
SBC310
-
X
X
X
X
X
X
X
X
MECHANICS
1 = 0.8” pitch VITA46
A = 0.8” pitch VITA48 (2LM)
2 = 0.85” pitch VITA46
B = 0.85” pitch VITA48 (2LM)
3 = 1” pitch VITA46
C = 1” pitch VITA8 (2LM)
SOFTWARE
3 = VxWorks
4 = BIT/VxWorks
5 = PPCBoot
6 = BIT/PPCBoot
GPIO/SATA OPTIONS
0 = Full GPIO (0-5)
2 = Reserved
1 = Dual SATA / GPIO 4-5
3 = Reserved
PMC I/O AND OPENVPX COMPATIBILITY OPTIONS
0 = PMC I/O fully routed / VPX (VITA46) compatible
1 = XMC I/O fully routed / VPX (VITA46) compatible
X = PMC I/O fully routed /OpenVPX (VITA65) compatible
Y = XMC I/O fully routed /OpenVPX (VITA65) compatible
FLASH
0 = Reserved
1 = 256 MB
2 = 512 MB
MEMORY
0 = 512 MB (single bank)
2 = 1 GB
1 = 1 GB (single bank)
3 = 2 GB
PROCESSOR
1 =8641D @ 1000 MHz
5=8640D @ 1067 MHz
4 =8641 @ 1.33GHz/533 MHz
7 = 8640 @ 1067 MHz
RUGGEDISATION LEVEL
1, 2, 3, 4, 5
Specifications 107
A.8 Software Support
GEIP’s software strategy for PPC boards allows fully integrated system‐level solutions to be realised easily and with confidence. Off‐the‐shelf, layered software modules deliver the most from low‐level hardware features while exploiting the best high level debug and run‐time functionality of popular COTS operating systems and communications modules. The software products described below build on those available for previous generations of the PPCx family, so providing a common interface for technology inserts. GEIP has invested more than 50 man‐years of engineering talent into the PowerX architecture so that customers can develop market‐leading products using the O/S and development environment best suited to their long term program requirements. A.9 Boot Firmware
Developed as an integral part of the GEIP PowerX strategy, the Boot firmware provides a foundation layer to interface between the raw GEIP board hardware, with its highly programmable device set‐ups and flexibility, and the supported Operating Systems, which require a straight‐forward booting and device interface model. The U‐Boot Firmware includes comprehensive configuration facilities, interactive or auto‐boot sequencing from a range of device types, automatic PCI resource allocation at initialisation, PCI display/interrogation utilities and other valuable features for system integrators. Memory or other speed and feature enhancements are seamlessly absorbed by the Boot firmware, giving the same look and feel to the O/S and the user application as the GEIP hardware models advance. This allows the constant use of latest technology in required areas without system impact. Where particular operating systems define the use of alternate boot methods (e.g. VxWorks bootroms), the Boot firmware technology is absorbed into such boot methodology. A.10 Built In Test
PPC BIT probes from the lowest level of discrete on‐board hardware up to Line Replaceable Unit level within a system, ensuring the highest degree of confidence in system integrity. BIT includes comprehensive configuration facilities, allowing automatic initialisation tests to be defined for the desired mix of system functionality and options. Further tests can be invoked interactively, giving BIT a valuable role as a field service tool. Both object and source code products are available. 108 SBC310 3U VPX Single Board Computer
A.11 Background Condition Screening
BCS supplements the BIT initialisation test coverage with further health screening that can co‐exist with a standard COTS Operating System. In contrast to a traditional BIT‐style test, the intensity and coverage of which makes it destructive to operating systems, the configurable BCS package allows functions such as periodic check‐summing, memory scrubbing, and others to be tailored for operation alongside the application in on‐line conditions. Results are stored in Flash in the same format as BIT results. Code is available for reading out BIT/BCS results under LynxOS and VxWorks. A.12 I/O Module
The Rear Transition Modules (RTMs) for the SBC310 are the VPX3UX600 and VPX3UX300. Publication No. SBC310-0HH/5
Specifications 109
Appendix B • SBC310TST Test Access Board
B.1 Overview
The SBC310 Test Access Board provides additional connectivity to the SBC310 Single Board Computer and is used to aid development and debug. It is designed as a development aid, and is not intended for use in deployed systems. In brief, the SBC310TST provides the following functions: •
BDM header for Wind River Probes •
JTAG Programming header for Lattice Programmable devices •
JTAG header for access to the main JTAG chain onboard the SBC310. (primary input to the JTS06 Scan bridge) •
Duplication of all on‐board links •
Reset switch B.2 Configuration
Figure B-1 SBC310TST-1BB-1 Layout
B.2.1 SW1/SW2 and E1/E2 – JTAG multiplexer
control
Switches SW1 and SW2 provide control for the onboard JTAG multiplexer. Links E1 and E2 duplicate these functions. See Section B.4.1 for more information on the JTAG chain. Table B-1 JTAG multiplexer control
SW2/E2
ON/IN
ON/IN
OFF/OUT
OFF/OUT
SW1/E1
ON/IN
OFF/OUT
ON/IN
OFF/OUT
JTAG connection
JTAG chain connected to SBC310 power-manager device.
JTAG chain connected to SBC310 power-manager device.
JTAG chain connected to SBC310 Local Bus Control FPGA
JTAG chain connected to SBC310 scan bridge
B.2.2 P1 - JTAG header (Lattice pin-out)
Provides connection to the on‐board JTAG chain using a pinout compatible with the Lattice download cable. Table B-2 JTAG header (Lattice pin-out)
PIN
1
2
3
4
5
6
7
8
Function
3V3 power. Provides power for the programming buffers
TDO – JTAG Test Data Out
TDI – JTAG Test Data In
N/C
N/C
TMS – JTAG Test Mode Select
GND
TCK – JTAG Test Clock
B.2.3 P2 - JTAG Header (JTAG Technologies Pin-out)
Provides connection to the on‐board JTAG chain using a pinout compatible with JTAG Technologies test equipment. Table B-3 JTAG Header (JTAG Technologies Pin-out)
PIN
1
3
5
7
9
11
13
15,17,19
2,4,6,8,10,12,14,16,18,20
Function
TRST~ - JTAG Test Reset
N/C
AUTO_WRITE – JTAG Auto-write pin
N/C
GND
B.2.4 P3 – Debug Header
NOTE
Factory use only.
SBC310TST Test Access Board 111
B.2.5 P4 – Scanbridge Link Block
Links to control the SBC310’s scanbridge. Links fit between active pin and GND. Table B-4 Scanbridge Link Block
Pin
Function
SCAN_OE~ Fit this link to Enable the SBC310 scan bridge. This link should be removed when using the
BDM header P7, or the JTAG headers P1 and P2
PASS_THRU. Fit this link to enable Pass Through mode on the SBC310 scanbridge. This directly
connects the primary chain to one of the six local TAPs, selected by the links below.
PASS_THRU(0) – Pass Through Select bit 0 (LSB). Use these links to select the TAP (1-6) that will
connect to the primary chain when the scanbridge is in pass-through mode.
PASS_THRU(1) – Pass Through Select bit 1Use these links to select the TAP (1-6) that will connect to
the primary chain when the scanbridge is in pass-through mode.
PASS_THRU(2) – Pass Through Select bit 2 (MSB). Use these links to select the TAP (1-6) that will
connect to the primary chain when the scanbridge is in pass-through mode.
GND
1
3
5
7
9
2,4,6,8,10
B.2.6 P5 – SBC310 Link Block
Duplication of the SBC310 links. Links fit between link pin and GND. B.2.7 P5 - External Programming Link pins 1-2
Factory use only.
Table B-5 External Programming Link pins 1-2
Setting
Function
Out
Normal Operation
In
External Programming mode
B.2.8 P5 - USB/PCI-X mode Link pins 3-4
The SBC310 includes an optional USB interface which is enabled by fitting this link. When fitted, the board operates in USB mode which restricts the PMC site to 64 bit/33 MHz PCI operation. When USB functionality is not required, the link can be removed and the PMC site operates with a 64 bit/133 MHz PCI‐X bus. Table B-6 USB/PCI-X mode Link pins 3-4
Setting
Function
Out
PCI-X mode enabled
In
USB mode enabled
B.2.9 P5 - Core1 Disable link pins 5-6
When fitted on a dual core board, core one is disabled, and the MPC8640/1D will report it’s self as a single core device in its System Version Register (SVR) by returning a value of 0x809000xx. Table B-7 Core1 Disable link pins 5-6
Setting
Function
Out
Core 1 enabled
In
Core 1 disabled
NOTE
B.2.10 P5 - AMP Mode Link pins 7-8
Fitting this link disables Asymmetrical Multi‐Processing (AMP) mode, which instructs the MPC8640/1D to offset all Core 1 accesses to the bottom of RAM by 256Mbytes (addresses 0x0000000 to 0x10000000 are offset to 0x10000000 to 0x20000000). This allows both processing cores to maintain separate stacks and private memory without any software intervention, which is desirable when the two cores are running separate operating systems. With the link removed, the processor is operating in Symmetric Multi‐Processing (SMP) mode. This feature is not desirable when each core needs to run separate operating systems, as both cores share the same memory space. The state of this link is reflected in the Link Status Register. Table B-8 P11 (Pins 3-4)
Setting
In
Function
SMP Mode – No Offset
Out
AMP Mode – Core 1 has 256MB Memory Offset
NOTE
B.2.11 P5 - EEPROM Recovery Link Pins 9-10
Fitting link 9‐10 prevents the loading of EEPROM configuration data by the MPC8640(D)/MPC8641(D)and the PEX8518 PCIe switch. This is necessary in the event that EEPROM data becomes corrupted and needs to be reprogrammed. Table B-9 EEPROM Recovery Link Pins 9-10
Setting
Out
In
Function
Normal Operation
EEPROM Load Disabled
B.2.12 P5 - NVMRO Write Enable Link pins 11-12
overrides the state of the link. I.e. The NVRAM is only write enabled when BOTH NVRMO is low AND the
link is fitted.
Table B-10 NVMRO Write Enable Link pins 11-12
Setting
Out
Function
NVRAM Writes disabled.
When board is configured as system controller:
NVMRO signal driven low to the VPX backplane
In
B.2.13 P5 - Flash Protection Unlock Link pins 13-14
This link must be fitted to allow software to alter the persistent sector protection, which remains unchanged following a reset or a power‐cycle. See the Flash Sector Protection section for further details. If the link is not fitted, the software is prevented from altering any previously configured sector protection. The state of this link is reflected in the Link Status Register. Table B-11 Flash Protection Unlock Link pins 13-14
Setting
Out
In
Function
Persistent Flash sector protection cannot be altered
Persistent Flash sector protection can be altered
B.2.14 P5 - Core 0 Boot Area Selection pins 17-18 &
pins 15-16
The Boot Flash for Processing Core 0 is divided into four sections, allowing for three different boot images to be loaded into the Flash. There is also a factory‐
programmed Recovery boot image. These links are used to select which image is used at boot time. The state of these links is reflected in the Link Status Register. Table B-12 Core 0 Boot Area Selection pins 17-18 & pins 15-16
Pins 17-18
Pins 15-16
Out
Out
Main boot image
In
Out
Out
In
Recovery boot image
In
In
In normal operation, these links are not fitted and the SBC310 boots from the Main boot image. 114 SBC310 3U VPX Single Board Computer
B.2.15 P5 - Core 1 Boot Area Selection pins 19-20 &
pins 15-16
Processing Core 1 may boot either from the same Flash image as Processing Core 0 or from its own Boot Flash, which is divided into four sections, allowing for three different boot images along with the factory‐programmed Recovery boot image. These links are used to select which of the Core 1 boot images is used at boot time, if selected. The state of these links is reflected in the Link Status Register. Table B-13 Core 1 Boot Area Selection pins 19-20 & pins 15-16
Pins 19-20
pins 15-16
Out
Out
Main boot image
In
Out
Out
In
Recovery boot image
In
In
In normal operation, these links are not fitted and the SBC310 boots from the Main Boot image. B.2.16 P6 – BANC Write Enable
NOTE
Factory use only.
B.2.17 P7 – BDM header
Connects directly to the MPC8640(D)/MPC8641(D) JTAG port to provide access for a Background Debug Monitor probe. The pin‐out is compatible with Windriver probes. Table B-14 BDM header
PIN
1
2
3
4
5
6
7
8
9
11
13
15
16
10,12,14
Function
N/C
TRST – JTAG port reset.
STOP~ Pulled to 3v3 via 4k7 resistor
VDD_SENSE - Pulled to 3v3 via 4k7 resistor
CKSTP_IN~ - Connects to processor Checkstop-In line.
SRESET~ – connects to Core 0 and Core 1 soft-reset inputs
HRESET~– Connects to the Processor hard-reset input.
CKSTOP_OUT~ Connects to the processor checkstop-out output.
GND
N/C
B.2.18 P8 pins 1-3 Ground
Provides a general‐purpose ground point for attaching oscilloscope or logic‐analyzer probe grounds. Publication No. SBC310-0HH/5
B.2.19 E3 – BANC Write Enable
NOTE
Factory use only.
B.2.20 J1 – SBC310 connector
This 80‐way connector is used to connect to the SBC310. B.3 Installation
The SBC310TST Test Access Board is designed to be fitted directly to the SBC310 with minimal additional hardware. To attach the Test Access Board, carefully connect J1 to P17 on the SBC310 and use screws and nuts though the available holes to provide mechanical support. B.4 Functional Description
B.4.1 JTAG Chain
The SBC310TST Test Access Card has an on‐board JTAG chain that can be connected to one of three destinations on‐board the SBC310 by means of a multiplexer. The multiplexer is controlled by switches (and links) as described in Chapters 3 •and 4 •. A functional diagram of the JTAG chain can be seen below. Figure B-2 JTAG Chain Diagram
NOTE
Full backplane power needs to be provided in order for the JTAG multiplexer to function.
When the multiplexer is configured for Power‐manager programming, the SBC310 on‐board power supplies are automatically disabled. This is to ensure that the board powers up in a controlled manor, and is not affected by programming activity. 116 SBC310 3U VPX Single Board Computer
B.4.2 Reset Switch
A momentary‐action toggle switch is used to provide a reset signal to the SBC310. Activating the switch in either direction generates a de‐bounced reset pulse, which is used by the SBC310 to generate a board level hard‐reset. B.4.3 LEDs
There are two LEDs on‐board that are used to indicate board power and reset status. DS1 (green) when on, indicates that all power‐supplies on‐board the SBC310 are within specification. DS2 (red) when on, indicates that the SBC310 is in reset. This LED is lit regardless of the reset source. Publication No. SBC310-0HH/5
Index
A
Airflow....................................................................................... 14
Associated Documents .................................................... 16
B
BCS ...........................................................................................109
BIT.............................................................................................108
Board ID
Register.................................................................................77, 78
Board Identification ........................................................... 19
Board Installation................................................................ 28
Boot Firmware....................................................................108
Boot Flash ............................................................................... 36
C
Caution Heading.................................................................. 40
Cautions................................................................................... 13
Chassis Ground.................................................................... 28
Configuration
Link Rev2
P10(1-2) .............................................................................................21
P10(3-4) .............................................................................................21
P11 (1-2) ............................................................................................21
P11(3-4) .............................................................................................21
P12(1-2) .............................................................................................22
P12(3-4) .............................................................................................22
P13 (3-4) ............................................................................................22
P13(1-2) .............................................................................................22
P13(1-2) .............................................................................................22
P14(1-2) .............................................................................................23
P14(3-4) .............................................................................................23
Link Rev3
P11 (1-2) ............................................................................................25
P11(3-4) .............................................................................................25
P12(1-2) .............................................................................................25
P12(3-4) .............................................................................................26
P13 (3-4) ............................................................................................26
P13(1-2) .............................................................................................26
P14(1-2) .............................................................................................26
P14(3-4) .............................................................................................27
P18(1-2) ......................................................................................25, 26
Link SBC310TST
E3 ...................................................................................................... 116
P4(1-10) .......................................................................................... 112
P5(11-12)........................................................................................ 114
P5(1-2)............................................................................................. 112
P5(13-14)........................................................................................ 114
P5(15-16).............................................................................. 114, 115
P5(17-18)........................................................................................ 114
P5(19-20)........................................................................................ 115
P5(3-4)............................................................................................. 112
P5(5-6)............................................................................................. 113
P5(7-8)............................................................................................. 113
P5(9-10) .......................................................................................... 113
P6 ...................................................................................................... 115
Rev2 ...............................................................................................20
Rev3 ...............................................................................................24
Connecting to SBC310...................................................... 29
Connectors............................................................................. 84
J0.....................................................................................................85
J1.....................................................................................................88
J11 ..................................................................................................95
J12 ..................................................................................................96
J13 ..................................................................................................97
J14 ..................................................................................................98
J2.....................................................................................................92
P0 ....................................................................................................85
P1 ....................................................................................................87
P15............................................................................................... 100
P16............................................................................................... 100
P17............................................................................................... 101
P2 ....................................................................................................90
Cooling ..................................................................................... 14
Current Consumption .....................................................105
D
Dimensions...........................................................................103
Documentation Conventions ........................................ 12
E
EMI/EMC................................................................................... 28
Regulatory Compliance ........................................................13
Environment ........................................................................107
Ethernet ................................................................................... 43
F
Flammability.......................................................................... 13
Flash .......................................................................................... 35
Boot................................................................................................36
Sector Protection .....................................................................38
User................................................................................................36
I
I/O Capabilities ..................................................................... 43
I/O Modules..........................................................................109
Interrupts ................................................................................ 51
External ........................................................................................53
Handling ................................................................................... 104
Interrupter................................................................................ 104
SMI..................................................................................................52
J
JTAG........................................................................................... 54
L
LEDs ........................................................................................... 81
M
Machine Check
Exception .................................................................................... 52
Memory
Maps ............................................................................................. 34
MTBF........................................................................................106
N
Problems ................................................................................. 16
Product Identification ....................................................... 19
R
Related Documents ........................................................... 15
Reset Sequence and Timing .......................................... 29
Resets
Soft .................................................................................................52
S
NVRAM...................................................................................... 39
Safety Notices....................................................................... 13
Software Support ..............................................................108
System ROM........................................................................... 35
O
U
Ordering Information ......................................................107
Unpacking .............................................................................. 18
User Flash ............................................................................... 36
Write Enabling .........................................................21, 26, 114
P
PMC
Signal Descriptions................................................................. 99
Site ................................................................................................. 55
W
Warnings................................................................................. 13
Web Sites ................................................................................ 16
Index 119
© 2010 GE Intelligent Platforms Embedded ©
2010 GE Intelligent Platforms Embedded
Systems, Inc. All rights reserved.
GE Intelligent Platforms
Information Centers
* indicates a trademark of GE Intelligent
Platforms, Inc. and/or its affiliates. All other
trademarks are the property of their respective
owners.
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Confidential Information - This document
contains Confidential/Proprietary Information
of GE Intelligent Platforms, Inc. and/or its
suppliers or vendors. Distribution or
reproduction prohibited without permission.
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EXPRESSLY DISCLAIMED.

SBC310 3U VPX Single Board Computer

Transcription

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