Micro Electro Mechanical Systems: LTCC

Transcription

4th Round Table on M/NT – ESTEC Noordwijk 20/5/2003
Contents:
Micro Electro Mechanical Systems
l Alenia interest in the field of MEMS
l Present activity on SPDT RF Switches
LTCC-Packaged Single Pole Double Through
(SPDT) Switch in MEMS technology for high
reliability application
Technical and quality requirements
Design approach
Technology
Measurements
Simulations relevant to the next design and foundry iteration
LTCC micropackage
l Conclusions
–
–
–
–
–
–
Presented by Francesco Vitulli – Alenia Spazio, Rome Italy
Alenia interest in field of MEMS
l As a Company dedicated to space equipment for telecom, our main
interest is toward those MEMS promising good RF performance, like
Cavity Resonators, Varactors , RF Switches.
l RF Switches have been studied for several years; many Electrostatically
actuated SPST (Single Pole Single Through) Switches have been realized
in IC technology.
l RF Switches offer good performance in respect of: linearity, power
consumption, mass.
l RF Switches are of interest if, in addition to electrical performance, they
can achieve a high level of reliability and competitive cost.
l A SPDT (Single Pole Double Through) RF Switch is being developed by
Alenia in the frame of contract NR. 14628/NL/CK with ESTEC.
Work organization for the development of a
SPDT RF Switch
l Alenia Spazio S.p.A. (ALS): prime contractor, also in charge of package
assembly
l Technische Universität München (TUM), Istitüt für Hochfrequenztechnik:
switch and switch matrix design, wafer layers design
l Università di Perugia (UNI-PG), Department
electromagnetic simulation and design support
Electronics:
l Istituto di Ricerca Scientifica e Tecnologica del Trentino (IRST),
Microsystem Division: fabrication process development, foundry service,
mechanical simulation
l Consiglio Nazionale delle Ricerche (CNR), Microwave and Microsystem
Laboratory : electrical testing and design support
Technical requirement for the SPDT RF Switch
of
Quality Requirements for the SPDT RF Switch
l Number of cycles : 106 minimum
l Frequency range : 1 to 30 GHz
l Lifetime by design : 10 years minimum
l Input RF power : 10 W minimum
l Sine vibration : 20Hz -2000Hz at 20g, 3-axis, 4 minutes each axis
l Insertion loss : 0.4 dB maximum
l Random Vibration :
l Isolation : 50 dB minimum
l Return loss : 20 dB minimum
l Actuation voltage : 50 V maximum
–
–
–
–
20-100Hz +3dB/octave
100-200Hz 1 g2 /Hz
200-2000Hz -4dB/octave
Duration : 2.5 minutes
l Temperature range : -25°C to 75°C
l Mechanical Shock : n. 5, 1500 g, 0.5 ms, y1 axis
l Switching time, power consumption : to be minimized
l Thermal Vacuum : 7 cycles, below 1.3x10-6 hPa (PSS-01-802)
l Radiation tolerance : up to 100 krads (target)
1
Design aspects:
1) Parallel, classical SPST Switch:
l The SPDT design must take into account the present technology
availability, in order to have a final product which can be manufactured
without critical and costly processes. We have avoided to choose “state of
the art” technology.
l This Switch has a metallic membrane shaped like a bridge, which is
placed above the central conductor and connects both ground electrodes.
The membrane can be attracted to the central (underpass) conductor if a
DC voltage is applied between the central conductor and the membrane
itself (ground). The underpass conductor is covered by a thin passivation
layer (capacitor dielectric) to avoid the sticking of the electrodes.
l While SPST Switches have been already demonstrated to be realized as
single devices, SPDT Switches are much more difficult to be made as
single devices.
l Our choice has been to obtain SPDT Switch as a combination of SPST
Switches but still in a monolithic form.
l Therefore the first step was to design and characterize SPST cells, within
the technology domain and the layout rules offered by the foundry IRST.
2) Series SPST Switch:
SPDT RF Switch:
l The central conductor is interrupted, the gap will be closed by the metal
bridge when the switch is actuated. The contact is ohmic with a low
resistance value; this will insure a low insertion loss when the switch is
actuated.
l None of the above described switches can meet the technical
requirements, in particular RF isolation between input and output port in
“off” condition, therefore a concatenation of series and shunt switches is
needed for each branch. To reduce the insertion loss one series and one
parallel switch only are used.
l To avoid sticking problems the center conductor is not used as an
actuation pad. Separate (two) pads are added instead.
l The same approach of having separate pads from the center conductor is
used for the parallel switch.
l Care has to be taken to achieve a good isolation of the RF signal path
from the DC actuation pads and biasing lines. To this scope the biasing
lines are made of polysilicon (230Ω/ ).
Fabrication process requirements
Basic device structures of the RF-switch process
l Electrical specification:
– Actuation voltage < 50V
– Max input RF power >10W
l Structural requirements:
– HF sections: Air Bridges, CPW lines
– LF sections: 50kohm resistors, DC block capacitors, connection ilnes
for actuation signals
2
Fabrication Process 1
Mechanical Design
3
Vp =
The pull-in voltage
8kg 0
27ε0 A
k = spring constant
g 0 = air-gap
ε0 = permittivity of vacuum
A = area of the actuation pad
1) 1000 nm isolation oxide growth, 300 nmpolysilicon deposition, Boron
implantation, poly definition, Boron diffusion 925 °° C, 300 nm TEOS
oxide and contact holes opening.
k calculated by FEM simulation program ANSYS.
Bridge Stress Pressurepull-in
[MPa]
[MPa]
53
1.3*10-3
53+9
1.5*10-3
53-9
1.1*10-3
xm a x
[µm]
1.023
1.016
1.033
V pull-in
[V]
34.3
36.8
31.5
50µ
m
400
µm
320
µm
80
35
µm
µm
2) Ti/TiN/Al/Ti/TiN 60/200/400/60/100 nm deposition and definition
(underpass)
Silicon
3) 100 nm LPCVD oxide (or PECVD nitride) and Via definition
5) Cr/Au 10/150 nm seed layer deposition, plating mould definitio n and
first Au (1.5 µm) electroplating (Bridge and pads)
6) Second Au (3.5 µm) electroplating (CPW lines), seed layer removal,
and final release
4) 3 µm Resist Spacer deposition and definition
Silicon
Oxide
Poly-Si
Oxide
Poly-Si
TiN
Oxide
Si-nitride
Silicon
TiN
Actuation test results
Process statistics
7 mask-layers
~ 130 process steps
20 product wafers (4”) per run
9 weeks cycle time
Capacitance [pF]
12
10
49.5
37.0
33.0 43.75
28.75
39.25
25.25
21.75
35.5
8
6
4
Advantages
No need for planarization steps
High isolation of the actuation electrodes
High Con – Coff ratio, mostly break-down independent
Next improvements
Polysilicon and underpass multilayer of same height
Poly-Si
Resist Spacer
2
0
0
20
33.
54 0
60
w20 g=3µm
w09 g=2µm
80
100
Bias Voltage [V]
W=150 µm
L= 850, 750, 650, 550, 450 µm
g 0= 3 µm ∆ C=2.1 pF
g 0= 2 µm ∆C=1.4 pF
3
CPW lines Insertion Loss
Presently, an acceptable figure of merit
for the CPW losses is 0.1 dB/mm at 30
l
Insertion Loss [dB] @ 20 GHz
Finished devices
GHz and ≤0.2 dB/mm at 40 GHz
The measured insertion loss is in the
order of 0.17 to 0.27 dB for a CPW
having a length of 2.1 mm, i.e. 0.11
l
dB/mm
In order to improve the insertion loss of
the Shunt Switch a triple layer: TiN-AlTiN has been used for the underpass of
shunt switches
l
Classical shunt switch
2,0
2,2
I.L. @ 20
GHz [dB]
I.L. @ 30
GHz [dB]
0.14
0.20
0.22
1
0
0
0
0
0
0
0
0
0
0
Shunt Switch Response (ON state)
0
,0
,9
,8
,7
,6
,5
,4
,3
,2
,1
,0
1000
S - p a r a m e t e r s
I.L. @ 10
GHz [dB]
L o s s
The effect on the I.L. is in the order of
0.1 dB @ 30 GHz, by using polysilicon
actuation lines and pads
I n s e r t i o n
to determine their contribution
[ d B ]
CPW lines with biasing lines and
actuation pads have been manufactured
Line loss
[dB/mm]
1,8
C P W l e n g t h [ m m ]
[ d B ]
l
1,6
SPDT prototype
Insertion Loss due to biasing lines and actuation pads
l
W5
W6
W7
W8
W9
W10
1,0
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0,0
F 1 0
F 2 0
F 3 0
D a t a 5 F 1 0
D a t a 5 F 2 0
D a t a 5 F 3 0
2000
S
- 2 0
- 3 0
S
- 4 0
- 6 0
0
1 0
2 0
[ d B ]
20 GHz
30 GHz
-0.31
-0.58
-0.60
2
-1.25
-1.48
-1.30
6
-0.33
-0.58
-0.53
11
-0.28
-0.43
-0.58
l Wafer #1, 6, 11 have been realized by using the multilayer for the underpass
conductor: TiN/Al/TiN; while wafer #2 is TiN.
l The triple layer has been demonstrated suitable for this application
Shunt Switch Response (OFF state)
l The actuation voltage is about
50V. Note that a voltage
between 10 to 20% higher is
necessary after the first
actuation to switch
0
10 GHz
1
4 0
[ G H z ]
@ 10 GHz, 0.43 @ 20 GHz and 0.58 @ 30 GHz. The line is included (1.5mm),
so the switch alone is expected to contribute no more than 0.25 dB @30 GHz
Inserion Loss [dB]
3 0
F r e q u e n c y
l The return loss is better than 20 dB up to more than 35 GHz. Los ses are 0.28
C P W l e n g t h [ µ m ]
Wafer #
1 1
- 5 0
3000
Shunt Switch Response (ON state)
2 1
- 1 0
- 1 0
l The peak in the isolation does
- 2 0
S
2 1
- 3 0
S
- 4 0
1 1
- 5 0
0
1 0
2 0
F r e q u e n c y
3 0
[ G H z ]
4 0
not match with the simulation
prediction (6Ghz vs 36.5Ghz
measured!). This is likely
caused by the bridge position
which is not flat on the bottom
electrode of the underpass, as
the bottom electrode is not in
the same plane as the
actuation pads
l This explanation is confirmed
by the test shown in the
following chart.
4
l In addition to the actuation voltage,
an extra voltage has been applied
between the central conductor of the
CPW and the mobile bridge by using
a bias tee
W1_Cell_1_IV_C3_BiasTee_S21
10
DB(|S[2,1]|)
DD_STD1
DB(|S[2,1]|)
DD_C34005
DB(|S[2,1]|)
DD_C3
DB(|S[2,1]|)
DD_C34010
DB(|S[2,1]|)
DD_C340
DB(|S[2,1]|)
DD_C34015
DB(|S[2,1]|)
DD_C30020
DB(|S[2,1]|)
DD_C34020
DB(|S[2,1]|)
DD_C30025
DB(|S[2,1]|)
DD_C34025
0
-10
-20
-30
-40
DB(|S[2,1]|)
DD_C32525
capacitance in Off state and,
consequently, the reduction in
frequency of the isolation peak, in
the direction of the simulated
behavior
l Comparison between the red curve
DB(|S[2,1]|)
DD_STD
10
Wafer #
d [µm]
εr
Fres
[GHz]
I.L.
[dB]
F’res
[GHz]
I.L. ’
[dB]
1
100
3.94
11.2
-37
35.7
-26
2
100
3.94
10
-32.7
28.9
-30
6
30
3.94
6
-46
36.4
-25
11
200
7
14.5
-40
34.34
-27
l The result is the increasing of the
-50
0.045
20
Frequency (GHz)
30
40
(only 20V through the bias tee) and
the yellow one (20V -bias teen plus
40V-actuation pads), shows that the
voltage given by the bias tee in
much more effective (the curves are
practically superimposed)
•
Comparison between the insertion loss peak (IL) and frequency (Fres) of
actuated by design switches with IL ’ and F’res of voltage actuated swithes over
different wafers. d is the thickness of the dielectric.
l The insertion loss is in
the order of 3.5 to 4
dB. This is due to the
poor ohmic contact of
the
bridge
with
underpass conductor.
0
- 1 0
Series Switch Response (ON state)
electrical contact:
l The idea is to grow a array
of dimples (by using the
polysilicon layer) in the
underpass area of contact
with the mobile bridge
chromium oxide layer
in the bottom part of
the bridge is likely the
root cause.
- 3 0
- 4 0
l The size of such dimples is
to be minimized to get
higher pressure
l An higher contact force is
l This layer must be
- 5 0
l Improvement of the
l The formation of a
- 2 0
0
1 0
2 0
F r e q u e n c y
3 0
4 0
[ G H z ]
also preferable
broken
when
the
bridge goes down to
ensure
a
good
electrical contact
[ d B ]
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
2 0
3 0
4 0
F r e q u e n c y [ G H z ]
l The OFF behavior is satisfactory, better at low frequency as expected. An
isolation of 20dB is obtained up to 35 GHz.
[ d B ]
0
1 0
one plane to allow for a
larger contact area
Shunt switch performance after 1000 ON/OFF cycles
- 1 0
0
l The beam must flex only in
Modified Series Switch
Series Switch Response (OFF state)
S
- p a r a m e t e r s
[ d B ]
Series Switch Response (ON state)
0
- 1 0
- 2 0
S
2 1
c h a n g e
i n
1 0 0 0
a c t u a t i o n s
- 3 0
- 4 0
S
1 1
c h a n g e
i n
1 0 0 0
a c t u a t i o n s
- 5 0
0
1 0
2 0
F r e q u e n c y
3 0
4 0
[ G H z ]
l OFF state performance (wafer 6)
5
[ d B ]
W1_Cell_1_V_C3_rel_S21
0
0
- 1 0
S
2 1
c h a n g e
i n
1 0 0 0
a c t u a t i o n s
-5
- 2 0
-10
- 3 0
- 4 0
S
1 1
c h a n g e
i n
1 0 0 0
DB(|S[2,1]|)
DD_C3
DB(|S[2,1]|)
DD_C3MD
DB(|S[2,1]|)
DD_C350
DB(|S[2,1]|)
DD_C3MD50
-15
a c t u a t i o n s
- 5 0
-20
- 6 0
-25
S
0
1 0
2 0
F r e q u e n c y
3 0
4 0
0.045
10
20
[ G H z ]
l ON state performance (wafer 6)
[ d B ]
Shunt+series switch performance over 1000 ON/OFF cycles
0
W1_Cell_1_V_C3_rel_S11
-10
-20
-30
-40
-50
DB(|S[1,1]|)
DD_C3
DB(|S[1,1]|)
DD_C3MD
DB(|S[1,1]|)
DD_C350
DB(|S[1,1]|)
DD_C3MD50
-60
0.045
10
20
30
40
l ON/OFF state performance (wafer 1)
0
30
Frequency (GHz)
40
S
S
- 2 0
S
S
S
S
- 3 0
- 4 0
0
S
Frequency (GHz)
- 1 0
1
2
1
2
1
1
1
1
1
,
,
,
,
0
1
1
a
a
s
s
f
f
2 1
1 1
t a c t u a
t a c t u a
t e r 1 0 0
t e r 1 0 0
2 0
3 0
F r e q u e n c y
t i
t i
0
0
o n
o n
c y c l e s
c y c l e s
4 0
[ G H z ]
l ON state behavior: the high insertion loss is due to the series switch. Note the
l ON/OFF state performance (wafer 1)
incremental reduction of the insertion loss over cycling, corres ponding to the
improvement of the mechanical contact between bridge and underpass
Next foundry run – SPDT design: shunt-shunt
Next foundry run – SPDT design: shunt-shunt (On state)
d2=1000 um
d1=1700 um
2
3
500 um
1
Au
d1=1700 um
2
500 um
1
3
TiN/Al/TiN
SPDT 1
l
Narrow band design: the transmission frequency depends on D1
Bridge down
SPDT 2
l
Bridge up
SPST
Simulation: ADS Momentum; the underpass triple layer has been
simulated as a unique layer, the actuation pads an biasing lines are
proved to be not influent and therefore not considered in the simulation.
6
Next foundry run – SPDT design: shunt-shunt (Off state)
Next foundry run – SPDT design: series-shunt
l
220 um
The series and shunt switches are closer
together, resulting in a large band
behavior in comparison to the shunt -shunt
switch
100 um
l
The T-junction is made of underpass, so
no blocking capacitors are necessary
l
l
SPDT 1
SPDT 2
SPST
The isolation behavior depends on the resonant frequency of the switch.
The mobile bridge has been assumed flat on the bottom electrode
(actuation pads having the same height as the bottom electrode). An
additional layer of chromium oxide has been considered (5um) plus 10um
of air to account for the roughness of the metals in contact.
140 um
d
200 um
TiN/Al/TiN
Bridge down
Bridge up
Next foundry run – SPDT design: shunt-series (Off state)
D=50um
l
Simulation has been carried out by using Sonnet
D=50um
D=130um
l
The On behavior still needs some optimization at high frequency
D=130um
The Off behavior still requires further optimization at high frequency
l
LTCC 3D Micropackage
Au
d: anchorground
distance
Next foundry run – SPDT design: shunt-series (On state)
The contact resistance of the bridge with
the underpass is the critical point.
Microstrip to CPW transition
l The need for packaging comes from several reasons:
microstrip
side
– The SPDT Switch, as contains mobile parts, requires to be protec ted by
particles and pollution to ensure good reliability
– The CPW is better to be transformed to microstrip line to interface with
other circuits
microstrip
line
coupling
via
coplanar
line
Dielectric
MS-CPW coupling via
l Advantages of the LTCC technology :
–
–
–
–
Alenia Spazio have this technology in house
The LTCC package is inherently low cost
The CPW to MS transition is embedded in the package itself
The control circuitry can be embedded in the package as long as the control
lines and pads
MS and
CPW
ground
coplanar
side
side
view
7
Micropackage - Assembly
Micropackage - Assembly
RF out (chip side)
cavity for the
accommodation of the
switch chip
RF out
RF in
DC actuation controls(chip
side)
top side
RF out (chip side)
RF in (chip side)
MS and CPW ground
DC actuation controls
RF out
metallized cover (back side)
backside view
topside view
Micropackage – Electrical behaviour
Micropackage – Assembly components
0
dB(S(1,1))
dB(S(2,2))
-10
-20
S 21
20 point smoothing of S2 1
0,0
-30
-0,4
-40
-0,8
-50
0
5
10
15
20
25
freq,GHz
30
35
40
-1,2
-1,6
-2,0
0
10
20
Frequency [GHz]
30
Conclusion:
l The achieved results on the insertion loss of the shunt switch gives
good confidence the requirements can be encountered; the third design
and foundry iteration, now underway, is needed to verify if the switch
resonance (Off state) can be predicted, proving that the fabrication
process and simulation match together
l The series switch is also expected to improve its insertion loss
performance by using polysilicon dimples to help in obtaining a good
electrical contact
l The LTCC micropackage shows satisfactory performance
l The SPDT Switch will be finally assembled in the package and
subjected to a qualification program to assess the robustness of the
design and developed technology
8

Micro Electro Mechanical Systems: LTCC

Transcription

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