GR-TMTC-0002 Data Sheet and User`s Manual

Transcription

CCSDS Telemetry and Telecommand
CCSDS TM / TC and SpaceWire FPGA
Data Sheet and User’s Manual
GAISLER
Features
Description
• CCSDS/ECSS compatible Telemetry Encoder
and Telecommand Decoder
• Telemetry encoder implements in hardware
part of protocol sub-layer, synchronization &
channel coding sub-layer, and part of physical
layer
• Telemetry input via multiple SpaceWire links
• Reed-Solomon and Convolutional encoding
• Telecommand decoder implements in
hardware synchronization & channel coding
sub-layer, and part of physical layer
• Software telecommands via SpaceWire link
• Hardware telecommands via parallel port
• At least 2 Mbit/s downlink & 100 kbit/s uplink
The telemetry encoder and telecommand decoder
are implemented in an Actel RTAX FPGA. The
lower layers of the encoder and decoder are
implemented in hardware with the higher layers
externally in software. Support is provided for
additional hardware encoded telemetry and
hardware decoded command outputs and pulses.
Specification
• RTAX2000S-CQ352
• Total Ionizing Dose Up to 300 krad (Si)
• Single-Event Latch-Up Immunity (SEL) to
LETTH > 104 MeV-cm2/mg
• Immune to Single-Event Upsets (SEU) to
LETTH > 37 MeV-cm2/mg
Data Link Protocol Sub-Layer
Configuration
4k
Memory
AHB
Slave
SpaceWire
(Science)
GRSPW
RMAP
AHB
Master
All Frames Recept.
VC Demux
MC Demux
VC Reception
2k FIFO
Telemetry Encoder
VC3
AHB
Slave
VC
Generate
AMBA
AHB
Master
VC4
AHB
Slave
VC
Generate
AMBA
AHB
Master
VC5
AHB
Slave
VC
Generate
AMBA
AHB
Master
Idle
Frame
Sync Marker
AMBA
AHB
Master
All Frames Generation
Coding Sub-Layer
VC
Generate
AHB
Slave
Master Channel Generation
AMBA
Virtual Channel Frame Service
AMBA
(Science)
GRSPW
RMAP
AHB
Master
VC0
VC1
VC2
DMA
Physical Layer
NRZ-L/M
16k Buffer
Memory
AHB
Slave
Configuration
Pseudo Randomizer
AMBA
AHB
Master
Convolutional
Descriptor
Memory
AHB
Slave
SpaceWire
Path Recovery
CLCW
AMBA
APB
Slave
Virtual Channel Multiplexer
Interrupt
Hardware
Commands
Interrupt
Controller
Telecommand
CLTU
Telecommand Decoder
VC Pkt Extraction
HW Cmd
AMBA
AHB
Slave
Packet Extraction
(LEON3)
GRSPW
RMAP
AHB
Master
AMBA
SpaceWire
NRZ-L/M
FIFO
BCH Decoder
DMA
Physical Layer
Start sequence search
AMBA
AHB
Master
Coding Sub-Layer
Pseudo-Derandomizer
Memory
Controller
AHB
Slave
Reed-Solomon
SRAM
MRAM
Telemetry
CADU
VC6
VC7
TMTC FPGA
Applications
The telemetry encoder and telecommand decoder can be used in systems where CCSDS/ECSS
compatible communication services are required. The software implementation of the higher layers
of the telemetry encoder and the telecommand decoder allows for implementation flexibility and
accommodation of future standard enhancements. The hardware encoded telemetry and decoded
command outputs do not require software and can be used for critical operations.
Copyright Aeroflex Gaisler AB
GR-TMTC-0002
December 2009, Version 1.5
GAISLER
2
Table of contents
1
Introduction.............................................................................................................................. 8
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
Architecture............................................................................................................................ 15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Specification .......................................................................................................................................... 15
Interfaces ............................................................................................................................................... 16
Clock and reset ...................................................................................................................................... 16
Performance........................................................................................................................................... 16
IP cores .................................................................................................................................................. 17
Interrupts ............................................................................................................................................... 17
Memory map ......................................................................................................................................... 17
Signals ................................................................................................................................................... 19
Abbreviations and acronyms ................................................................................................................. 21
Conventions ........................................................................................................................... 24
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
4
Overview ................................................................................................................................................. 8
Hierarchy ................................................................................................................................................. 8
Telemetry encoder ................................................................................................................................... 9
1.3.1
Telemetry encoder specification ............................................................................................... 9
1.3.2
Virtual Channels 0, 1 and 2..................................................................................................... 10
1.3.3
Virtual Channels 3, 4, 5 and 6................................................................................................. 10
1.3.4
Virtual Channel 7 .................................................................................................................... 10
Telecommand decoder........................................................................................................................... 11
1.4.1
Telecommand decoder specification ....................................................................................... 11
1.4.2
Software Virtual Channel........................................................................................................ 11
1.4.3
Hardware Virtual Channel ...................................................................................................... 12
Memory Interface .................................................................................................................................. 12
SpaceWire Link Interfaces .................................................................................................................... 12
On-chip Memory ................................................................................................................................... 13
Interrupt Controller................................................................................................................................ 13
Signal overview..................................................................................................................................... 14
Consultative Committee for Space Data Systems ................................................................................. 24
Galois Field ........................................................................................................................................... 24
Telemetry Transfer Frame format.......................................................................................................... 25
Reed-Solomon encoder data format ...................................................................................................... 26
Attached Synchronization Marker......................................................................................................... 26
Telecommand Transfer Frame format ................................................................................................... 27
Command Link Control Word............................................................................................................... 27
Space Packet.......................................................................................................................................... 28
Asynchronous bit serial data format...................................................................................................... 28
SpaceWire Remote Memory Access Protocol (RMAP)........................................................................ 28
Command Link Control Word interface (CLCW) ................................................................................ 29
Waveform formats ................................................................................................................................. 29
Telemetry Encoder ................................................................................................................. 30
4.1
4.2
Overview ............................................................................................................................................... 30
Layers .................................................................................................................................................... 31
4.2.1
Introduction............................................................................................................................. 31
4.2.2
Data Link Protocol Sub-layer ................................................................................................. 31
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4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
5
5.4
4.2.3
Synchronization and Channel Coding Sub-Layer................................................................... 31
4.2.4
Physical Layer......................................................................................................................... 31
Data Link Protocol Sub-Layer .............................................................................................................. 31
4.3.1
Physical Channel..................................................................................................................... 31
4.3.2
Virtual Channel Frame Service ............................................................................................... 32
4.3.3
Virtual Channel Generation - Virtual Channels 3, 4, 5 and 6 ................................................. 32
4.3.4
Virtual Channel Generation - Idle Frames - Virtual Channel 7 .............................................. 32
4.3.5
Virtual Channel Multiplexing ................................................................................................. 33
4.3.6
Master Channel Generation .................................................................................................... 33
4.3.7
Master Channel Frame Service ............................................................................................... 33
4.3.8
Master Channel Multiplexing ................................................................................................. 34
4.3.9
All Frame Generation ............................................................................................................. 34
Synchronization and Channel Coding Sub-Layer ................................................................................. 34
4.4.1
Attached Synchronization Marker .......................................................................................... 34
4.4.2
Reed-Solomon Encoder .......................................................................................................... 34
4.4.3
Pseudo-Randomiser ................................................................................................................ 36
4.4.4
Convolutional Encoder ........................................................................................................... 36
Physical Layer ....................................................................................................................................... 36
4.5.1
Non-Return-to-Zero Level encoder ........................................................................................ 36
4.5.2
Clock Divider.......................................................................................................................... 37
Connectivity .......................................................................................................................................... 38
Operation ............................................................................................................................................... 39
4.7.1
Introduction............................................................................................................................. 39
4.7.2
Descriptor setup ...................................................................................................................... 39
4.7.3
Starting transmissions ............................................................................................................. 40
4.7.4
Descriptor handling after transmission ................................................................................... 40
4.7.5
Auto start................................................................................................................................. 41
Registers ................................................................................................................................................ 42
Signal definitions and reset values ........................................................................................................ 48
Timing ................................................................................................................................................... 48
Overview ............................................................................................................................................... 49
Interrupts ............................................................................................................................................... 49
Registers ................................................................................................................................................ 49
5.3.1
Status Register (R) .................................................................................................................. 50
5.3.2
Control Register (R/W)........................................................................................................... 50
AHB I/O area......................................................................................................................................... 50
Telemetry Encoder - Virtual Channel Generation.................................................................. 52
6.1
6.2
6.3
6.4
7
Telemetry Encoder - Virtual Channel Generation function input interface ........................... 49
5.1
5.2
5.3
6
3
Overview ............................................................................................................................................... 52
Registers ................................................................................................................................................ 52
Timing ................................................................................................................................................... 52
Telemetry Encoder - Descriptor............................................................................................. 53
7.1
7.2
7.3
7.4
Overview ............................................................................................................................................... 53
Operation ............................................................................................................................................... 53
7.2.1
Introduction............................................................................................................................. 53
7.2.2
Descriptor definition ............................................................................................................... 53
Registers ................................................................................................................................................ 54
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7.5
8
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
Timing ................................................................................................................................................... 54
Overview ............................................................................................................................................... 55
8.1.1
Concept ................................................................................................................................... 55
8.1.2
Functions and options ............................................................................................................. 56
Data formats .......................................................................................................................................... 56
8.2.1
Reference documents .............................................................................................................. 56
8.2.2
Waveforms .............................................................................................................................. 57
Coding Layer (CL) ................................................................................................................................ 57
8.3.1
Synchronisation and selection of input channel...................................................................... 57
8.3.2
Codeblock decoding................................................................................................................ 58
8.3.3
De-Randomiser ....................................................................................................................... 58
8.3.4
Non-Return-to-Zero – Mark ................................................................................................... 58
8.3.5
Design specifics ...................................................................................................................... 58
8.3.6
Direct Memory Access (DMA) .............................................................................................. 59
Transmission.......................................................................................................................................... 59
8.4.1
Data formatting ....................................................................................................................... 62
8.4.2
CLTU Decoder State Diagram ................................................................................................ 62
8.4.3
Nominal................................................................................................................................... 62
8.4.4
CASE 1 ................................................................................................................................... 63
8.4.5
CASE 2 ................................................................................................................................... 63
8.4.6
Abandoned .............................................................................................................................. 63
Relationship between buffers and FIFOs .............................................................................................. 64
8.5.1
Buffer full................................................................................................................................ 64
8.5.2
Buffer full interrupt................................................................................................................. 65
Command Link Control Word interface (CLCW)................................................................................. 66
Configuration Interface (AMBA AHB slave) ....................................................................................... 66
Interrupts ............................................................................................................................................... 67
Registers ................................................................................................................................................ 68
8.9.1
Interrupt registers .................................................................................................................... 74
Timing ................................................................................................................................................... 76
Telecommand Decoder - Hardware Commands .................................................................... 77
9.1
9.2
9.3
9.4
9.5
10
Telecommand Decoder - Software Commands ..................................................................... 55
8.1
9
4
Overview ............................................................................................................................................... 77
9.1.1
Concept ................................................................................................................................... 77
Operation ............................................................................................................................................... 77
9.2.1
All Frames Reception ............................................................................................................. 77
9.2.2
Master Channel Demultiplexing ............................................................................................. 78
9.2.3
Virtual Channel Demultiplexing ............................................................................................. 78
9.2.4
Virtual Channel Reception ...................................................................................................... 78
9.2.5
Virtual Channel Packet Extraction.......................................................................................... 79
9.2.6
Path Recovery ......................................................................................................................... 79
9.2.7
Packet Extraction .................................................................................................................... 79
9.2.8
Application Layer ................................................................................................................... 80
Telecommand Transfer Frame format - Hardware Commands............................................................. 81
Timing ................................................................................................................................................... 82
SpaceWire Interface with RMAP target................................................................................. 83
10.1
Overview ............................................................................................................................................... 83
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10.2
10.3
10.4
10.5
10.6
11
11.3
11.4
11.5
11.6
13.3
Overview ............................................................................................................................................. 104
Operation ............................................................................................................................................. 104
Registers .............................................................................................................................................. 106
Overview ............................................................................................................................................. 107
Operation ............................................................................................................................................. 107
13.2.1 Errors..................................................................................................................................... 107
13.2.2 Correctable errors.................................................................................................................. 107
13.2.3 Interrupts ............................................................................................................................... 107
Registers .............................................................................................................................................. 107
Serial Debug Interface ......................................................................................................... 109
14.1
14.2
14.3
14.4
14.5
15
Overview ............................................................................................................................................... 93
Operation ............................................................................................................................................... 93
11.2.1 Access errors ........................................................................................................................... 94
11.2.2 Using bus ready signalling...................................................................................................... 95
PROM/SRAM/IO waveforms ............................................................................................................... 95
Registers .............................................................................................................................................. 101
Signal definitions and reset values ...................................................................................................... 102
Timing ................................................................................................................................................. 103
Status Registers .................................................................................................................... 107
13.1
13.2
14
Operation ............................................................................................................................................... 83
10.2.1 Overview................................................................................................................................. 83
10.2.2 Protocol support ...................................................................................................................... 83
Link interface ........................................................................................................................................ 84
10.3.1 Link interface FSM ................................................................................................................. 84
10.3.2 Transmitter .............................................................................................................................. 84
10.3.3 Receiver .................................................................................................................................. 85
RMAP.................................................................................................................................................... 86
10.4.1 Fundamentals of the protocol.................................................................................................. 86
10.4.2 Implementation ....................................................................................................................... 86
10.4.3 Write commands ..................................................................................................................... 87
10.4.4 Read commands ...................................................................................................................... 87
10.4.5 RMW commands .................................................................................................................... 88
10.4.6 Control .................................................................................................................................... 88
Timing ................................................................................................................................................... 92
On-chip Memory with EDAC Protection ............................................................................ 104
12.1
12.2
12.3
13
Fault Tolerant PROM/SRAM Memory Interface .................................................................. 93
11.1
11.2
12
5
Overview ............................................................................................................................................. 109
Operation ............................................................................................................................................. 109
14.2.1 Transmission protocol........................................................................................................... 109
14.2.2 Baud rate generation ............................................................................................................. 110
Registers .............................................................................................................................................. 110
Timing ................................................................................................................................................. 111
Interrupt Controller .............................................................................................................. 112
15.1
15.2
Overview ............................................................................................................................................. 112
Operation ............................................................................................................................................. 112
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15.3
15.4
15.5
16
18.3
18.4
19.3
Overview ............................................................................................................................................. 119
Operation ............................................................................................................................................. 119
18.2.1 Arbitration............................................................................................................................. 119
18.2.2 Decoding ............................................................................................................................... 119
18.2.3 Plug&play information ......................................................................................................... 119
Registers .............................................................................................................................................. 120
Debug print-out ................................................................................................................................... 120
Overview ............................................................................................................................................. 122
Operation ............................................................................................................................................. 122
19.2.1 Decoding ............................................................................................................................... 122
19.2.2 Plug&play information ......................................................................................................... 122
Debug print-out ................................................................................................................................... 122
Electrical description ........................................................................................................... 124
20.1
20.2
20.3
20.4
20.5
20.6
21
Overview ............................................................................................................................................. 118
Timing ................................................................................................................................................. 118
AMBA AHB/APB bridge with plug&play support............................................................. 122
19.1
19.2
20
Overview ............................................................................................................................................. 117
Timing ................................................................................................................................................. 117
AMBA AHB controller with plug&play support ................................................................ 119
18.1
18.2
19
15.2.1 Interrupt prioritization........................................................................................................... 112
15.2.2 Extended interrupts ............................................................................................................... 113
15.2.3 Processor status monitoring .................................................................................................. 113
15.2.4 Irq broadcasting .................................................................................................................... 113
Registers .............................................................................................................................................. 114
15.3.1 Interrupt level register........................................................................................................... 114
15.3.2 Interrupt pending register...................................................................................................... 114
15.3.3 Interrupt force register (NCPU = 0)...................................................................................... 115
15.3.4 Interrupt clear register........................................................................................................... 115
15.3.5 Multiprocessor status register ............................................................................................... 115
15.3.6 Processor interrupt mask register.......................................................................................... 115
15.3.7 Broadcast register (NCPU > 0) ............................................................................................. 116
15.3.8 Processor interrupt force register (NCPU > 0) ..................................................................... 116
15.3.9 Extended interrupt acknowledge register.............................................................................. 116
Timing ................................................................................................................................................. 116
Reset generation................................................................................................................... 118
17.1
17.2
17.3
18
Clock generation .................................................................................................................. 117
16.1
16.2
16.3
17
6
Absolute maximum ratings ................................................................................................................. 124
Operating conditions ........................................................................................................................... 124
Input voltages, leakage currents and capacitances .............................................................................. 124
Output voltages, leakage currents and capacitances ........................................................................... 124
Clock Input voltages, leakage currents and capacitances.................................................................... 124
Power supplies..................................................................................................................................... 124
Mechanical description ........................................................................................................ 125
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21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
7
Package................................................................................................................................................ 125
Pin assignment..................................................................................................................................... 125
RTAX2000S specific pins - CQ352 package ...................................................................................... 132
RTAX2000S specific pins - CG624 package ...................................................................................... 133
Package figure ..................................................................................................................................... 134
Mechanical drawing ............................................................................................................................ 134
Weight.................................................................................................................................................. 134
Package materials ................................................................................................................................ 134
Thermal characteristics........................................................................................................................ 134
22
Reference documents ........................................................................................................... 135
23
Ordering information ........................................................................................................... 136
24
Change record ...................................................................................................................... 137
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1
Introduction
1.1
Overview
The CCSDS/ECSS Telemetry Encoder and Telecommand Decoder can be used in systems where
CCSDS/ECSS compatible communication services are required. The Telemetry and Telecommand
concept is based on implementing the associated protocols partly in hardware and partly in software.
The lower layers, such as physical layer and the channel coding sub-layer, are implemented in hardware, whereas high levels such as data link - protocol sub-layer are implemented in software.
1.2
Hierarchy
Figure 1 shows a simple block diagram of the device. Note that all cores with AHB master interfaces
also have APB slave interfaces for configuration and status monitoring, although not shown in the
block diagram. The following sub-sections briefly describe the functionality of the blocks.
Configuration
4k
Memory
AHB
Slave
AMBA
AHB
Master
16k Buffer
Memory
AHB
Slave
SpaceWire
(Science)
GRSPW
RMAP
AHB
Master
All Frames Recept.
MC Demux
Configuration
VC0
VC1
VC2
DMA
2k FIFO
Telemetry Encoder
AMBA
AHB
Master
VC4
AHB
Slave
VC
Generate
AMBA
AHB
Master
VC5
AHB
Slave
VC
Generate
AMBA
AHB
Master
VC6
Idle
Frame
Physical Layer
NRZ-L/M
VC
Generate
Pseudo Randomizer
AHB
Slave
Convolutional
VC3
Sync Marker
AMBA
AHB
Master
All Frames Generation
VC
Generate
AHB
Slave
Virtual Channel Multiplexer
AMBA
Coding Sub-Layer
AMBA
(Science)
GRSPW
RMAP
AHB
Master
VC Demux
CLCW
AMBA
APB
Slave
Descriptor
Memory
AHB
Slave
SpaceWire
VC Reception
Interrupt
Controller
VC Pkt Extraction
Interrupt
Hardware
Commands
Path Recovery
HW Cmd
Telecommand
CLTU
Telecommand Decoder
Packet Extraction
(LEON3)
GRSPW
RMAP
AHB
Master
AMBA
SpaceWire
AMBA
AHB
Slave
NRZ-L/M
FIFO
Physical Layer
DMA
BCH Decoder
AMBA
AHB
Master
Pseudo-Derandomizer
Memory
Controller
AHB
Slave
Coding Sub-Layer
Reed-Solomon
SRAM
MRAM
Telemetry
CADU
VC7
TMTC FPGA
Figure 1. Block diagram
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1.3
9
Telemetry encoder
The CCSDS Telemetry Encoder implements part of the Data Link Layer, covering the Protocol Sublayer and the Synchronization and Coding Sub-layer and part of the Physical Layer of the packet
telemetry encoder protocol.
The Telemetry Encoder comprises several encoders and modulators implementing the Consultative
Committee for Space Data Systems (CCSDS) recommendations, European Cooperation on Space
Standardization (ECSS) and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding.
The Telemetry Encoder implements seven Virtual Channels accessible via SpaceWire links. Three of
the Virtual Channels accept partial Telemetry Frames from software implementing higher protocol
layers such as Virtual Channel Generation function. The other four Virtual Channels accept CCSDS
Space Packet data [CCSDS-133.0] as input via the SpaceWire RMAP protocol. An eighth Virtual
Channel is implemented for Idle Frames only.
1.3.1
Telemetry encoder specification
This Data Link - Protocol Sub-layer [CCSDS-132.0] functionality is not implemented in hardware:
•
Packet Processing
•
Virtual Channel Frame Service (DMA functionality only) (see also Virtual Channel 3, 4, 5 and 6)
•
Master Channel Frame Service (only single Spacecraft Identifier supported)
•
Master Channel Multiplexing (only single Spacecraft Identifier supported)
This Data Link - Protocol Sub-layer [CCSDS-132.0] functionality is implemented in hardware:
•
Virtual Channel Generation (for Virtual Channels 3, 4, 5 and 6)
•
Virtual Channel Generation (for Idle Frame generation only, e.g. Virtual Channel 7)
•
Virtual Channel Multiplexing (for all frames)
•
Master Channel Generation (for all frames)
•
All Frame Generation (for all frames)
•
Multiplexing of four CLCW sources, of which two external via asynchronous bit serial interfaces
This Synchronization and Channel Coding Sub-Layer [CCSDS-131.0] functionality is implemented
in hardware:
•
Attached Synchronization Marker
•
Reed-Solomon coding
•
Pseudo-Randomiser
•
Convolutional coding
This Physical Layer [ECSS-50-05A] functionality is implemented in hardware:
•
Non-Return-to-Zero Mark/Level modulation (NRZ-M/L)
The Telemetry Encoder fixed configuration is as follows:
•
fixed transfer frame format, version 00b, Packet Telemetry
•
fixed transfer frame length of 1115 octets
•
common Master Channel Frame Counter for all Virtual Channels
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•
fixed nominal Attached Synchronization Marker usage
•
fixed 2 kByte telemetry transmit FIFO
•
fixed 4 kByte on-chip EDAC protected RAM memory per Virtual Channel 3, 4, 5 and 6
The Telemetry Encoder programmability is as follows:
•
telemetry Spacecraft Identifier
•
telemetry OCF/CLCW enable
•
telemetry No RF Available and No Bit Lock bits in CLCW overwriting from input pins
•
telemetry Frame Error Control Field (FECF/CRC) enable
•
telemetry Reed-Solomon enable (E=16 coding, interleave depth 5, 160 check symbols)
•
telemetry Pseudo Randomization enable
•
telemetry Convolutional Encoder enable and rate
•
telemetry NRZ-L/ NRZ-M modulation
•
telemetry transfer rate
The Telemetry Encoder does not implement the following:
•
no Advanced Orbiting Systems (AOS) support (also no Insert Zone (AOS) and no Frame Header
Error Control (FHEC))
•
no Transfer Frame Secondary Header (also no Extended Virtual Channel Frame Counter)
•
no Turbo Encoding
•
no Split-Phase Level modulation
•
no Sub-carrier modulation
1.3.2
Virtual Channels 0, 1 and 2
Virtual Channels 0, 1 and 2 are implemented by means of software support from an external processor
via SpaceWire RMAP commands. The input is a partial Transfer Frame. See section 4 for details.
1.3.3
Virtual Channels 3, 4, 5 and 6
Virtual Channels 3, 4, 5 and 6 are implemented in hardware without any software support being
required. Data are input via SpaceWire RMAP commands. See sections 5 and 10 for details.
The following Data Link - Protocol Sub-layer [CCSDS-132.0] functionality is implemented:
•
Virtual Channel Generation
•
Transfer Frame Primary Header insertion
•
Transfer Frame Data Field insertion
•
First Header Pointer (FHP) handling and insertion
•
Buffering of two complete Transfer Frames per Virtual Channel
•
CCSDS Space Packet [CCSDS-133.0] data input (or user-defined data-blocks).
1.3.4
Virtual Channel 7
Idle Frames are generated on a separate Virtual Channel, using identifier 7. See section 4.3.4.
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1.4
11
Telecommand decoder
The CCSDS Telecommand Decoder implements part of the Data Link Layer, covering the Protocol
Sub-layer and the Synchronization and Coding Sub-layer and part of the Physical Layer of the packet
telecommand decoder protocol.
The Telecommand Decoder supports decoding of higher protocol layers in software, being accessible
via a SpaceWire link. It also supports decoding in hardware for bit-parallel output with pulse generation, for which CLCW is produced to on-chip Telemetry Encoder.
1.4.1
Telecommand decoder specification
The following Data Link - Synchronization and Channel Coding Sub-Layer [CCSDS-231.0] functionality is implemented in hardware:
•
Pseudo-De-randomization
•
BCH codeblock decoding
•
Start Sequence Search
The following Physical Layer functionality [ECSS-50-05A] is implemented in hardware:
•
Non-Return-to-Zero Mark/Level de-modulation (NRZ-M/L)
The telecommand decoder fixed configuration is as follows:
•
fixed telecommand decoder support for CCSDS/ECSS functionality, not ESA PSS
The telecommand decoder provide the following pin programmability:
•
telecommand (hardware commands) Spacecraft Identifier (10 pins)
•
telecommand (hardware commands) Virtual Channel Identifier (6 pins)
•
telecommand Pseudo De-randomization enable
•
telecommand NRZ-L / NRZ-M modulation selection
•
telecommand RF available indicator polarity selection
•
telecommand active signal (bit lock) polarity selection
•
telecommand bit clock active edge selection
The Telecommand Decoder has multiple separate serial input streams from transponders etc., comprising serial data, clock, channel active indicator (bit lock) and RF carrier available. The input
streams are possible to individually disable or enable. The input stream is auto-adaptable.
1.4.2
Software Virtual Channel
The interface between the Telecommand Decoder hardware and software is a SpaceWire link with
RMAP protocol. The CLCW produced by the software is input to the Telemetry Encoder via the Telecommand Decoder CLCW Registers (CLCWRn), see section 8.9 for details, using the SpaceWire link
with RMAP protocol, with the same information being output on an asynchronous bit serial output
suitable for cross-strapping.
The higher protocol levels are implemented in software. These software telecommands are stored in
external memory and can be accessed via a SpaceWire interfaces. The software implementation of the
higher layers of the telecommand decoder allows for implementation flexibility and accommodation
of future standard enhancements. See sections 8 and 10 for details.
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1.4.3
Hardware Virtual Channel
A separate Virtual Channel for hardware commands is implemented in hardware, without the need of
software support. The hardware commands control an external bit-parallel output port, setting or
clearing bits individually, or generating pulses. The hardware commands are carried inside the Transfer Frame Data Field, and the Transfer Frame includes the Frame Error Control Field (FECF/CRC).
This Application Layer functionality is implemented in hardware:
•
Hardware command decoding and execution:
•
Individually controlled parallel outputs
•
Static logical 0 or 1, or pulsed output
•
Command controlled pulse length
This Space Packet Protocol layer [CCSDS-133.0] functionality is implemented in hardware:
•
Packet Extraction
•
Path Recovery
This Data Link - Protocol Sub-Layer [CCSDS-232.0] functionality is implemented in hardware:
•
Virtual Channel Packet Extraction
•
Virtual Channel Reception:
•
Support for Command Link Control Word (CLCW)
•
Virtual Channel Demultiplexing
•
Master Channel Demultiplexing
•
All Frames Reception:
•
Frame Delimiting and Fill Removal Procedure; and
•
Frame Validation Check Procedure, in this order.
The CLCW is automatically transferred to the on-chip Telemetry Encoder, with the same information
being output on an asynchronous bit serial output suitable for cross-strapping.
The hardware telecommands are implemented entirely in hardware and do not require any software
and can therefore be used for critical operations. See section 9 for details.
1.5
Memory Interface
The memory interface support external volatile and non-volatile memory (e.g. MRAM), supporting
32-bit data and 8-bit EDAC check sum, with multiple chip select signals.
1.6
SpaceWire Link Interfaces
The SpaceWire links provide an interface between the on-chip bus and a SpaceWire network. They
implement the SpaceWire standard [ECSS-E-ST-50-12C] with the protocol identification extension
[ECSS-E-ST-50-11C]. The Memory Access Protocol (RMAP) command handler implements the
ECSS standard [ECSS-E-ST-50-11C].
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1.7
13
On-chip Memory
16 kByte of on-chip volatile memory is provided for temporary storage of two telemetry transfer
frames for each of the Telemetry Virtual Channels 3 through 6, together with a dedicated hard coded
descriptor memory containing two descriptors for each channel. Additional general purpose 4 kByte
of on-chip volatile memory is provided and can for example be used for telemetry or telecommand
descriptor. All memory is protected by EDAC. Neither automatic scrubbing nor error counter are
implemented.
1.8
Interrupt Controller
The Interrupt Controller is used to prioritize and propagate interrupt requests from internal devices to
a single interrupt output.
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1.9
14
Signal overview
The signal overview of the telemetry encoder and telecommand decoder is shown in figure 2.
clk
resetn
Clock & Reset &
Interrupt
dsurx
Debug UART
transclk
clcwin[0:1]
Telemetry
Encoder
tcscid[0:9]
tcvcid[0:5]
tcrfpos
irq
dsutx
caduclk[0:3]
caduout[0:3]
clcwout[0:1]
Telecommand
Decoder
tcgpio[0:31]
tchigh
tcrise
tcpseudo
tcmark
tcrfa[0:3]
tcactive[0:3]
tcclk[0:3]
tcdata[0:3]
spw_clk
spw_rxd[]
spw_rxdn[]
spw_rxs[]
spw_rxsn[]
data[31:0]
cb[7:0]
SpaceWire Links
Memory Interface
spw_txd[]
spw_txdn[]
spw_txs[]
spw_txsn[]
address[27:0]
ramsn[7:0]
ramoen[7:0]
ramben[3:0]
rwen[3:0]
romsn[7:0]
oen
writen
Figure 2. Signal overview
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2
Architecture
2.1
Specification
15
The Telemetry and Telecommand FPGA specification comprises the following elements.
CCSDS compliant Telemetry encoder:
•
Input:
•
7 Virtual Channels
•
Input access via SpaceWire link
•
CCSDS Space Packet data (or any custom data block)
•
CLCW
•
Input via SpaceWire link
•
CLCW internally from hardware commands
•
CLCW externally from two dedicated asynchronous bit serial inputs
•
Output:
•
CADU / encoded CADU
•
NRZ-L / NRZ-M encoding
•
Pseudo-Randomization
•
Reed-Solomon and/or Convolutional encoding
•
Bit synchronous output: clock and data
CCSDS compliant Telecommand decoder (software commands):
•
Layers in hardware:
•
Coding layer
•
Input:
•
Auto adaptable bit rate
•
Bit synchronous input: clock, qualifier and data
•
Output:
•
Output access via SpaceWire link
•
CLTU (Telecommand Transfer Frame and Filler Data)
•
CLCW internally connected to Telemetry encoder
•
CLCW on dedicated asynchronous bit serial output
CCSDS compliant Telecommand decoder (hardware commands):
•
Layers in hardware:
•
Coding layer
•
Transfer layer (BD frames only)
•
Space Packet Protocol
•
CLCW internally connected to Telemetry encoder
•
Input:
•
Auto adaptable bit rate
•
Bit synchronous input: clock, qualifier and data
•
Telecommand Frame with Space Packet
•
Output:
•
Bit-parallel output with pulse generation
•
CLCW on dedicated asynchronous bit serial output
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2.2
16
Interfaces
The following interfaces are provided:
•
Telemetry
•
Telemetry transmitter clock input
•
CLCW externally from two dedicated asynchronous bit serial inputs
•
Physical layer output:
•
Two sets of bit synchronous output: clock and data
•
One set of bit synchronous output: clock and data for EGSE
•
One set of Manchester encoded data output for EGSE
(Manchester as per IEEE 803.2 when GRTM physical layer register bit SF=0)
(Manchester as per G.E. Thomas when GRTM physical layer register bit SF=1)
•
Telecommand
•
Physical layer input:
•
Four sets of bit synchronous input: data, qualifier (bit lock), clock and RF status
•
Hardware commands:
•
Bit-parallel output
•
CLCW on dedicated asynchronous bit serial output (hardware commands)
•
CLCW on dedicated asynchronous bit serial output (software commands)
•
2.3
System level
•
Memory interface (SRAM and PROM chip selects, read and write strobes, 32-bit data, 8bit checksum, at least 21 bit address)
•
Interrupt output
•
System clock and reset
•
SpaceWire link with RMAP support for software telemetry and telecommand
•
SpaceWire link with RMAP support for hardware telemetry (VC3 - VC4)
•
SpaceWire link with RMAP support for hardware telemetry (VC5 - VC6)
•
SpaceWire transmitter clock input
Clock and reset
The system clock is taken directly from a separate external input.
The telemetry transmitter clock is derived from a separate external input.
The SpaceWire transmitter clock is derived from a separate external input.
The device is reset with a single external reset input that need not be synchronous with the system
clock input.
2.4
Performance
Telemetry downlink rate is programmable up to at least 2 Mbit/s, based on a 8 MHz input clock.
Telecommand uplink rate up to at least 100 kbit/s is supported.
SpaceWire links rate up to at least 10 Mbit/s is supported, based on a 10 MHz input clock.
System clock frequency up to at least 20 MHz is supported, based on a 20 MHz input clock.
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2.5
17
IP cores
The architecture is based on cores from the GRLIB IP library. The vendor and device identifiers for
each core can be extracted from the plug & play information. The used IP cores are listed in table 1.
Table 1. Used IP cores
2.6
Core
Function
Vendor
Device
AHBCTRL
AHB Arbiter & Decoder
0x01
-
APBCTRL
AHB/APB Bridge
0x01
0x006
AHBUART
Serial/AHB debug interface
0x01
0x007
FTSRCTRL
PROM/SRAM/IO Memory Interface
0x01
0x051
FTAHBRAM
On-chip SRAM with EDAC
0x01
0x050
AHBSTAT
AHB failing address register
0x01
0x052
IRQMP
Interrupt controller
0x01
0x00D
GRSPW
SpaceWire link with RMAP
0x01
0x01F
GRTC
CCSDS TC Decoder
0x01
0x031
GRTM
CCSDS TM Encoder
0x01
0x030
GRTM_PAHB
CCSDS TM Encoder Virtual Channel Generation Input
0x01
0x088
GRTM_VC
CCSDS TM Encoder Virtual Channel Generation
0x01
0x085
GRTM_DESC
CCSDS TM Encoder Descriptors
0x01
0x084
GRTC HW
CCSDS TC Decoder - Hardware Commands
-
-
Interrupts
See the description of the individual cores for how and when the interrupts are raised.
Table 2. Interrupt assignment
Core
2.7
Interrupt
Comment
AHBSTAT
4
GRTM_PAHB
7-8, 9-10, 11-12, 13-14 CCSDS TM Encoder Virtual Channel Generation Input (VC3-6)
GRTC
5
CCSDS TC Decoder
GRTM
6
CCSDS TM Encoder
Memory map
The internal architecture is based on three sets of AMBA AHB and AMBA ABP buses. The three sets
are separated from each other. See figure 1 for details.
The memory map shown in tables 3, 5 and 7 is based on the AMBA AHB address space. Access to
addresses outside the ranges will return an AHB error response. The detailed register layout is defined
in the description of each individual core.
The control registers of most on-chip peripherals are accessible via the AHB/APB bridge, which is
mapped at address 0x80000000. The memory map shown in tables 4, 6 and 8 is based on the AMBA
AHB address space.
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Table 3. AMBA AHB address range - primary bus
Core
Address range
Area
FTSRCTRL
0x00000000 - 0x20000000
PROM area
0x40000000 - 0x60000000
SRAM area
APBCTRL
0x80000000 - 0x80100000
APB bridge
FTAHBRAM
0xA0000000 - 0xB0000000
On-chip RAM, 4 kByte
FTAHBRAM
0xB0000000 - 0xC0000000
GRTM_DESC
0xC0000000 - 0xD0000000
CCSDS TM Encoder Descriptors (VC3 - VC6)
GRTC
0xFFF00000 - 0xFFF10000
CCSDS TC Decoder
AHB plug&play
0xFFFFF000 - 0xFFFFFFFF
Plug & Play
Table 4. APB address range - primary bus
Core
Address range
Comment
IRQMP
0x80000000 - 0x80010000
Interrupt controller
FTSRCTRL
0x80010000 - 0x80020000
Memory controller
AHBSTAT
0x80020000 - 0x80030000
FTAHBRAM
0x80030000 - 0x80040000
FTAHBRAM
0x80040000 - 0x80050000
AHBUART
0x80050000 - 0x80060000
Serial/AHB debug interface
GRTM
0x80060000 - 0x80070000
CCSDS TM Encoder
APB plug&play
0x800FF000 - 0x80100000
Plug & Play
Table 5. AMBA AHB address range - secondary bus
Core
Address range
Area
GRTM_PAHB
0xFFF70000 - 0xFFF80000
CCSDS TM Encoder VC Generation Input VC3
GRTM_PAHB
0xFFF80000 - 0xFFF90000
AHB plug&play
Plug & Play
Table 6. APB address range - secondary bus
Core
Address range
Comment
GRTM_PAHB
0x80070000 - 0x80080000
GRTM_PAHB
0x80080000 - 0x80090000
APB plug&play
0x800FF000 - 0x80100000
Plug & Play
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Table 7. AMBA AHB address range - third bus
Core
Address range
Area
GRTM_PAHB
0xFFF90000 - 0xFFFA0000
GRTM_PAHB
0xFFFA0000 - 0xFFFB0000
AHB plug&play
Plug & Play
Table 8. APB address range - third bus
2.8
Core
Address range
Comment
GRTM_PAHB
0x80090000 - 0x800A0000
GRTM_PAHB
0x800A0000 - 0x800B0000
APB plug&play
0x800FF000 - 0x80100000
Plug & Play
Signals
The functional signals are shown in table 9. Note that index 0 is MSB for TM/TC signals.
Table 9. External signals
Name
Usage
Direction
Polarity
Reset
clk
System and telemetry transmitter clock
In
Rising
-
resetn
System reset
In
Low
-
irq
System interrupt
Out
High
Low
dsutx
Debug UART transmit data
Out
Low
-
dsurx
Debug UART receive data
In
Low
-
transclk
Telemetry transmitter clock
In
High
-
caduclk[0:2]
Telemetry CADU serial bit clock output
Out
-
Low
caduout[0:2]
Telemetry CADU serial bit data output
Out
-
Low
caduclk[3]
Telemetry CADU serial bit clock output
Out
-
Low
caduout[3]
Telemetry CADU serial bit data output, Manchester coded
Out
-
Low
tcscid[0:9]
Telecommand Spacecraft identifier
In
-
-
tcvcid[0:5]
Telecommand (hardware command) Virtual Channel identifier
In
-
-
tcrfpos
Telecommand RF Available positive level selection
In
High
-
tchigh
Telecommand input active (bit lock) positive level selection
In
High
-
tcrise
Telecommand serial bit clock rising edge selection
In
High
-
tcpseudo
Telecommand Pseudo-Derandomiser decoder enable
In
High
-
tcmark
Telecommand NRZ-M de-modulation enable
In
High
-
tcrfa[0:3]
Telecommand CLTU RF available indicator
In
-
-
tcactive[0:3]
Telecommand CLTU input active indicator (bit lock)
In
-
-
tcclk[0:3]
Telecommand CLTU serial bit clock input
In
-
-
tcdata[0:3]
Telecommand CLTU serial bit data input
In
-
-
tcgpio[0:31]
Telecommand (hardware command) parallel output
Out
High
Low
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Table 9. External signals
Name
Usage
Direction
Polarity
Reset
clcwin[0:1]
Telemetry CLCW asynchronous bit serial inputs
In
-
-
clcwout[0:1]
Telecommand CLCW asynchronous bit serial outputs
Out
-
High
spw_clk
Transmitter default run-state clock
In
Rising
-
spw_rxd[0:2]
Data input, positive
In
High
-
spw_rxdn[0:2]
Data input, negative {spare}
In, LVDS
Low
-
spw_rxs[0:2]
Strobe input, positive
In
High
-
spw_rxsn[0:2]
Strobe input, negative {spare}
In, LVDS
Low
-
spw_txd[0:2]
Data output, positive
Out
High
Low
spw_txdn[0:2]
Data output, negative {spare}
Out, LVDS
Low
Low
spw_txs[0:2]
Strobe output, positive
Out
High
Low
spw_txsn[0:2]
Strobe output, negative {spare}
Out, LVDS
Low
Low
address[27:0]
Memory word address
Out
High
-
data[31:0]
Memory data bus
BiDir
High
Tristate
cb[7:0]
Memory checkbits
BiDir
High
Tristate
ramsn[7:0]
SRAM chip selects
Out
Low
High
ramoen[7:0]
SRAM output enable
Out
Low
High
ramben[3:0]
SRAM read/write byte enable
Out
Low
High
rwen[3:0]
SRAM write enable strobe
Out
Low
High
romsn[7:0]
PROM chip select
Out
Low
High
oen
PROM output enable
Out
Low
High
writen
PROM write strobe
Out
Low
High
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2.9
21
Abbreviations and acronyms
AHB
AMBA Advanced High-Speed Bus
AHBCTRL
AMBA AHB Controller with plug&play support (IP core)
AMBA
Advanced Microcontroller Bus Architecture
AOS
Advanced Orbiting Systems
APB
AMBA Advanced Peripheral Bus
APBCTRL
AMBA AHB/APB Bridge with plug&play support (IP core)
ARM
Advanced RISC Machine
ASIC
Application Specific Integrated Circuit
ASM
BCH
Bose Chaudhuri Hocquenghem
CADU
Channel Access Data Unit
CCSDS
Consultative Committee for Space Data Systems
CLCW
Command Link Control Word
CLTU
Command Link Transfer Unit
CMOS
Complementary Metal-Oxide Semiconductor
COP-1
Communications Operation Procedure-1
CQFP
Ceramic Quad Flat Package
CRC
Cyclic Redundancy Code
DMA
Direct Memory Access
ECSS
European Cooperation on Space Standardization
EDAC
Error Detection And Correction
EGSE
Electrical Ground Support Equipment
EM
Engineering Model
ESA
European Space Agency
FARM
Frame Acceptance and Reporting Mechanism
FECF
Frame Error Control Field
FHEC
Frame Header Error Control
FHP
First Header Pointer
FIFO
First In First Out
FM
Flight Model
FPGA
Field Programmable Gate Array
FSH
Frame Secondary Header
FTAHBRAM
On-chip SRAM with EDAC and AHB interface (IP core)
FTMCTRL
Memory Controller with EDAC (IP core)
FTSRCTRL
Fault Tolerant 32-bit PROM/SRAM/IO Controller (IP core)
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GF
Galois Field
GPIO
General Purpose Input Output
GRLIB
Aeroflex Gaisler VHDL IP Core Library
GRSPW
SpaceWire codec with AHB host Interface and RMAP support (IP core)
GRTC
Telecommand Decoder
GRTM
Telemetry Encoder
HDL
Hardware Description Language
ID
Identifier
I/O
Input/Output
IP
Intellectual Property
IRQMP
Interrupt Controller (IP core)
JTAG
Joint Test Action Group
kbit/s
Thousand bits per second
kbps
Thousand bits per second
kByte
1024 bytes
LET
Linear Energy Transfer
LFSR
Linear Feedback Shift Register
LSB
Least Significant Bit/Byte
LVTTL
Low Voltage Transistor Transistor Logic
Mbit/s
Million bits per second
Mbps
Million bits per second
MByte
1048576 bytes
MC
Master Channel
MC_OCF
Master Channel associated Operation Control Field
MHz
Million Hertz
MRAM
Magneto-resistive Random Access Memory
MSB
Most Significant Bit/Byte
NRZ-L
Non Return to Zero - Level encoding
NRZ-M
Non Return to Zero - Mark encoding
OCF
Operational Control Field
PROM
Programmable Ready Only Memory
PSR
Pseudo Randomiser
PSS
Procedures, Standards and Specifications
RF
Radio Frequency
RISC
Reduced Instruction Set Computing
RMAP
Remote Memory Access Protocol
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RS
Reed-Solomon
SCID
Spacecraft Identifier
SEL
Single Event Latch-up
SEU
Single Event Upsets
SRAM
Static Random Access Memory
TBD
To Be Defined
TC
Telecommand
TM
Telemetry
UART
Universal Asynchronous Receiver Transmitter
VC
Virtual Channel
VHDL
VHSIC Hardware Description Language
VHSIC
Very High Speed Integrated Circuit
XOR
Exclusive-or
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24
3
Conventions
3.1
Consultative Committee for Space Data Systems
Convention according to the Consultative Committee for Space Data Systems (CCSDS) recommendations, applying to all relevant structures:
•
The most significant bit of an array is located to the left, carrying index number zero, and is
transmitted first.
•
An octet comprises eight bits.
General convention, applying to signals and interfaces:
•
Signal names are in mixed case.
•
An upper case '_N' suffix in the name indicates that the signal is active low.
CCSDS n-bit field
most significant
least significant
0
1 to n-2
n-1
Table 10. CCSDS n-bit field definition
3.2
Galois Field
Convention according to the Consultative Committee for Space Data Systems (CCSDS) recommendations, applying to all Galois Field GF(28) symbols:
•
A Galois Field GF(28) symbol comprises eight bits.
•
The least significant bit of a symbol is located to the left, carrying index number zero, and is
transmitted first.
Galois Field GF(28) symbol
least significant
most significant
0
1 to 6
7
GR-TMTC-0002
Table 11. Galois Field GF(28) symbol definition
GAISLER
3.3
25
Telemetry Transfer Frame format
The Telemetry Transfer Frame specified in [CCSDS-132.0] and [ECSS-50-03A] is composed of a Primary Header, a Secondary Header, a Data Field and a Trailer with the following structures.
Transfer Frame
Transfer Frame Data Field
Transfer Frame Trailer
Primary
Transfer Frame Header
Secondary (optional)
ket | Packet | Pa
OCF / FECF (optional)
6 octets
variable
variable
0 / 2 /4 / 6 octets
up to 2048 octets
Table 12. Telemetry Transfer Frame format
Transfer Frame Primary Header
Frame Identification
Version
VC
S/C
Id
OCF
Id
Master Channel Virtual Channel
Frame
Frame
Count
Flag
Frame
Data
Count
Field
Status
2 bits
0:1
10 bits
2:11
3 bits
1 bit
12:14
15
2 octets
8 bits
8 bits
16 bits
1 octet
1 octet
2 octets
Table 13. Telemetry Transfer Frame Primary Header format
Frame Data Field Status
Secondary Header Flag
Sync Flag
Packet Order Flag
Segment Length Id
First Header Pointer
1 bit
1 bit
1 bit
2 bits
11 bits
0
1
2
3:4
5:15
2 octets
Table 14. Part of Telemetry Transfer Frame Primary Header format
Transfer Frame Secondary Header (optional)
Secondary Header Identification
Secondary Header Data Field
Secondary Header Version
Secondary Header Length
2 bits
0:1
6 bits
2:7
Custom data
1 octet
up to 63 octets
Table 15. Telemetry Transfer Frame Secondary Header format
Transfer Frame Trailer (optional)
Operational Control Field (optional)
Frame Error Control Field (optional)
0 / 4 octets
0 / 2 octets
Table 16. Telemetry Transfer Frame Trailer format
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3.4
26
Reed-Solomon encoder data format
The applicable standards [CCSDS-131.0] and [ECSS-50-01A] specify a Reed-Solomon E=16 (255,
223) code resulting in the frame lengths and codeblock sizes listed in table 17.
Interleave depth
1
4 octets
Transfer Frame
Reed-Solomon Check Symbols
223 octets
32 octets
2
446 octets
64 octets
3
669 octets
96 octets
4
892 octets
128 octets
5
1115 octets
160 octets
8
1784 octets
256 octets
Table 17. Reed-Solomon E=16 codeblocks with Attached Synchronisation Marker
The applicable standards [CCSDS-131.0] also specifies a Reed-Solomon E=8 (255, 239) code resulting in the frame lengths and codeblock sizes listed in table 18.
Interleave depth
Transfer Frame
Reed-Solomon Check Symbols
1
4 octets
239 octets
16 octets
2
478 octets
32 octets
3
717 octets
48 octets
4
956 octets
64 octets
5
1195 octets
80 octets
8
1912 octets
128 octets
Table 18. Reed-Solomon E=8 codeblocks with Attached Synchronisation Marker
3.5
The Attached Synchronization Marker pattern depends on the encoding scheme in use, as specified in
[CCSDS-131.0] and [ECSS-50-01A] as shown in table 19.
Mode
Hexadecimal stream (left to right)
Nominal
1ACFFC1Dh
Table 19. Attached Synchronization Marker hexadecimal pattern
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3.6
27
Telecommand Transfer Frame format
The Telecommand Transfer Frame specified in [CCSDS-232.0] and [ECSS-50-04A] is composed of a
Primary Header, a Data Field and a trailer with the following structures.
Transfer Frame
Transfer Frame Primary
Header
Segment Header (optional)
ket | Packet | Pa
Frame Error Control Field
FECF (optional)
5 octets
variable
variable
2 octets
up to 1024 octets
Table 20. Telecommand Transfer Frame format
Version
Bypass
Control
Reserved
S/C
Virtual
Frame
Frame
Flag
Command
Spare
Id
Channel
Length
Sequence
Flag
Id
Number
2 bits
1 bit
1 bit
2 bits
10 bits
6 bits
10 bits
8 bits
0:1
3
4
5
6:15
16:21
22:31
32:39
2 octets
2 octets
1 octet1
Table 21. Telecommand Transfer Frame Primary Header format
Segment Header (optional)
Sequence Flags
Multiplexer Access Point (MAP) Id
2 bits
6 bits
40:41
42:47
1 octet
Table 22. Transfer Frame Secondary Header format
3.7
The Command Link Control Word (CLCW) can be transmitted as part of the Operation Control Field
(OCF) in a Transfer Frame Trailer. The CLCW is specified in [CCSDS-232.0] and [ECSS-50-04A]
and is listed in table 23.
Control Word Type
Version Number
Status Field
COP in Effect
Virtual Channel Identifier
Reserved Spare
0
1:2
3:5
6:7
8:13
14:15
1 bit
2 bits
3 bits
2 bits
6 bits
2 bits
No RF Available
No Bit Lock
Lock Out
Wait
Retransmit FARM B Reserved
Counter
Spare
Report Value
16
17
18
19
20
21:22
23
1 bit
1 bit
1 bit
1 bit
1 bit
2 bits
1 bit
24:31
Table 23. Command Link Control Word
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3.8
28
Space Packet
The Space Packet defined in the CCSDS [CCSDS-133.0] recommendation and is listed in table 24.
Space Packet
Primary Header
Packet Packet Identification
Version Type Secondary
Application
Number
Header Flag
Process Id
Packet Data Field
Packet Sequence Control
Packet
Secondary
User
Packet
Sequence
Flags
Sequence
Count
Data
Header
Data
Error
Length
(optional)
Field
Control
(optional)
variable
variable
variable
0:2
3
4
5:15
16:17
18:31
32:47
3 bits
1 bit
1 bit
11 bits
2 bits
14 bits
16 bits
Table 24. CCSDS Space Packet format
3.9
Asynchronous bit serial data format
The asynchronous bit serial interface complies to the data format defined in [EIA232]. It also complies to the data format and waveform shown in table 25 and figure 3. The interface is independent of
the transmitted data contents. Positive logic is considered for the data bits. The number of stop bits
can optionally be either one or two. The parity bit can be optionally included.
Asynchronous
bit serial format
start
D0
first
lsb
General data format
i = {0, n}
D1
D2
D3
D4
D5
D6
D7
parity stop
msb
stop
last
8*i+7 8*i+6 8*i+5 8*i+4 8*i+3 8*i+2 8*i+1 8*i
last
first
Table 25. Asynchronous bit serial data format
3.10
SpaceWire Remote Memory Access Protocol (RMAP)
A general definition of RMAP commands is specified in [RMAP].
For Telemetry Virtual Channels 3 through 6, a complete CCSDS Space Packet [CCSDS-133.0] is carried inside an RMAP write command [RMAP], which in turn is carried inside a SpaceWire packet
[SPW], as shown in the table 26.
SpaceWire
Packet
RMAP
Write
Command
Destination
Address
Target
SpaceWire
Address
Target
Logical
Address
Cargo
Protocol
Identifier
Instruction
Key
Reply
Address
Initiator
Logical
Address
Transaction
Identifier
Extended
Address
EOP
Address
Data
Length
Header
CRC
CCSDS
Space
Packet
Data
Data
CRC
EOP
1 byte
token
CCSDS
Space
Packet
optional,
variable
1 byte
1 byte
1 byte
1 byte
optional,
variable
1 byte
2 bytes
1 byte
4 bytes
3 bytes
1 byte
variable
Table 26. CCSDS Space Packet, inside RMAP write command, inside SpaceWire packet
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Command Link Control Word interface (CLCW)
Table 27. CLCW transmission protocol
3.12
Byte
Number
CLCW
register bits
CLCW contents
First
[31:24]
Control Word Type
CLCW
Version Number
Second
[23:16]
Virtual Channel ID
Reserved Field
Third
[15:8]
No RF Available
No Bit Lock
Fourth
[7:0]
Report Value
Fifth
N/A
[RS232 Break Command]
Status
Field
COP In Effect
Lock
Out
Wait
Retransmit
Farm B
Counter
Report
Type
Waveform formats
The design receives and generates the waveform formats shown in the following figures.
Start
bit
Data
Stop
bits
Start LSB
MSB Stop
Start LSB
MSB Stop Stop
Start
bit
Parity Stop
bits
Data
Start LSB
Start LSB
MSB
P
Stop
MSB
P
Stop Stop
Break
Start
Stop
Figure 3. Asynchronous bit serial protocol / waveform
Delimiter
Clock
Data
0
MSB
1
2
3
4
5
6
7
n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1
LSB
Figure 4. Telecommand input protocol / waveform
1
0
0
1
1
Data:
Clock
Manchester
Figure 5. Manchester encoded waveform (IEEE 802.3) (when GRTM physical layer register bit SF=0)
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4
Telemetry Encoder
4.1
Overview
The CCSDS/ECSS/PSS Telemetry Encoder implements part of the Data Link Layer, covering the
Protocol Sub-layer and the Frame Synchronization and Coding Sub-layer and part of the Physical
Layer of the packet telemetry encoder protocol. The operation of the Telemetry Encoder is highly programmable by means of control registers. The Telemetry Encoder comprises several encoders and
modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations, European Cooperation on Space Standardization (ECSS) and the European Space Agency
(ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding.
The encoder comprises the following:
•
Packet Telemetry Encoder (TM)
•
Reed-Solomon Encoder
•
Pseudo-Randomiser (PSR)
•
Non-Return-to-Zero Level / Mark encoder (NRZ-L/NRZ-M)
•
Convolutional Encoder (CE)
•
Clock Divider (CD)
Virtual Channel
Generation
AMBA
AHB
Master
DMA
FIFO
Master Channel
Generation
Idle Frame
Generation
OCF
Master Channel Mux
AMBA
APB
Slave
All Frame Generation
Coding Sub-Layer
AMBA APB
Virtual Channel & Master Channel
Frame Services
Attached Sync Mark
System clock domain
Reed-Solomon
Pseudo-Randomiser
NRZ-L
Convolutional
-
GRTM
Octet clock domain
Transponder
clock domain
Clock
Divider
Physical Layer
AMBA AHB
Virtual Channel Mux
Note that the SpaceWire input interface is described separately. The SpaceWire interfaces and corresponding Virtual Channel Generation function and buffer memories are not shown in the block diagram below, as is the case for the CLCW multiplexing function.
Telemetry output
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Layers
4.2.1
Introduction
The relationship between Packet Telemetry standard and the Open Systems Interconnection (OSI) reference model is such that the OSI Data Link Layer corresponds to two separate layer, namely the Data
Link Protocol Sub-layer and Synchronization and Channel Coding Sub-Layer.
4.2.2
Data Link Protocol Sub-layer
The following functionality is not implemented in the core:
•
Packet Processing
•
Virtual Channel Frame Service (DMA functionality only) (see also Virtual Channel 3, 4, 5 and 6)
•
Master Channel Frame Service (only single Spacecraft Identifier supported)
•
Master Channel Multiplexing (only single Spacecraft Identifier supported)
The following functionality is implemented in the core:
•
Virtual Channel Generation (for Virtual Channels 3, 4, 5 and 6)
•
Virtual Channel Generation (for Idle Frame generation only, e.g. Virtual Channel 7)
•
Master Channel Generation (for all frames)
•
All Frame Generation (for all frames)
4.2.3
Synchronization and Channel Coding Sub-Layer
•
•
Reed-Solomon coding
•
Pseudo-Randomiser
•
Convolutional coding
4.2.4
Physical Layer
•
4.3
Non-Return-to-Zero Level / Mark modulation
4.3.1
Physical Channel
The configuration of a Physical Channel covers the following parameters:
•
Transfer Frame Length is fixed to 1115 octets
•
Transfer Frame Version Number is fixed to 0, i.e. Packet Telemetry
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4.3.2
The Virtual Channel Frame Service is implemented by means of a DMA interface, providing the user
with a means for inserting Transfer Frames into the Telemetry Encoder. Transfer Frames are automatically fetched from memory, for which the user configures a descriptor table with descriptors that
point to each individual Transfer Frame. For each individual Transfer Frame the descriptor also provides means for bypassing functions in the Telemetry Encoder. This includes the following:
•
Virtual Channel Counter generation can be enabled in the Virtual Channel Generation function
(this function is normally only used for Idle Frame generation but can be used for the Virtual
Channel Frame Service when sharing a Virtual Channel, e.g. Virtual Channel 7)
•
Master Channel Counter generation can be bypassed in the Master Channel Generation function
•
Operational Control Field (OCF) generation can be bypassed in the Master Channel Generation
function
•
Frame Error Control Field (FECF) generation can be bypassed in the All Frame Generation function
Note that the above features can only be bypassed for each Transfer Frame, the overall enabling of the
features is done for the corresponding functions in the Telemetry Encoder, as described in the subsequent sections. The detailed operation of the DMA interface is described in section 4.7.
4.3.3
Virtual Channel Generation - Virtual Channels 3, 4, 5 and 6
There is a Virtual Channel Generation function for each of Virtual Channels 3, 4, 5 and 6. The channels have each an on-chip memory buffer to store two complete Transfer Frames (see section 12).
Each Virtual Channel Generation function receives data from the SpaceWire interface that are stored
in the on-chip memory buffer that is EDAC protected (see section 5).
The function supports:
•
•
Transfer Frame Data Field insertion (with support for different lengths due to OCF and FECF)
•
The function keeps track of the number of octets received and the packet boundaries in order to calculated the First Header Pointer (FHP). The data are stored in pre-allocated slots in the buffer memory
comprising complete Transfer Frames. The module fully supports the FHP generation and does not
require any alignment of the packets with the Transfer Frame Data Field boundary. The buffer memory space allocated to each Virtual Channel is treated as a circular buffer. The function communicates
with the Virtual Channel Frame Service by means of the on-chip buffer memory.
The data input format can be CCSDS Space Packet [CCSDS-133.0] or any user-defined data-block
(see section 5).
The Virtual Channel Generation function for Virtual Channels 3, 4, 5 and 6 is enabled through the
GRTM DMA External VC Control register. The transfer is done automatically via the Virtual Channel
Frame Service (i.e. DMA function).
4.3.4
Virtual Channel Generation - Idle Frames - Virtual Channel 7
The Virtual Channel Generation function is used to generate the Virtual Channel Counter for Idle
Frames as described here below.
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4.3.5
Virtual Channel Multiplexing
The Virtual Channel Multiplexing Function is used to multiplex Transfer Frames of different Virtual
Channels of a Master Channel. Virtual Channel Multiplexing in the core is performed between three
sources: Transfer Frames provided through the Virtual Channel Frame Service (Virtual Channel 0, 1
and 2) (50% bandwidth), Virtual Channel Generation function (Virtual Channels 3, 4, 5 and 6) (50%
bandwidth) and Idle Frames (Virtual Channel 7). Note that multiplexing between different Virtual
Channels is assumed to be done as part of the Virtual Channel Frame Service outside the core, i.e. in
software for Virtual Channels 0, 1 and 2, and in hardware for Virtual Channels 3, 4, 5 and 6.
The Virtual Channel Frame Service (Virtual Channels 0, 1 and 2) user interface is described above.
The Idle Frame generation is described hereafter.
Bandwidth allocation between VC3, VC4, VC5 and VC6 is done in hardware and is equal between
these channels, see section 7.2.1. Bandwidth allocation between the two groups VC0-VC2 and VC3VC6 is equal, i.e. 50% each. Bandwidth allocation to VC7 is only done when no other VC has anything to send. If one VC has not data to send, then the next one can send.
Idle Frame generation can be enabled and disabled by means of a register. The Spacecraft ID to be
used for Idle Frames is programmable by means of a register. The Virtual Channel ID to be used for
Idle Frames is programmable by means of a register, e.g. Virtual Channel 7.
Master Channel Counter generation for Idle Frames can be enabled and disabled by means of a register. Note that it is also possible to generate the Master Channel Counter field as part of the Master
Channel Generation function described in the next section. When Master Channel Counter generation
is enabled for Idle Frames, then the generation in the Master Channel Generation function is
bypassed.
4.3.6
The Master Channel Counter is generated for all frames on the master channel.
The Operational Control Field (OCF) is generated from a 32-bit input, via the Command Link Control
Word (CLCW) input of the Telecommand Decoder - Software Commands (see section 8.9) or the
internal Telecommand Decoder - Hardware Commands. This is done for all frames on the master
channel (MC_OCF).
The transmit order repeats every fourth Transfer Frames and is as follows:
•
CLCW from the internal software commands register (Telecommand Decoder CLCW Register 1
(CLCWR1), see section 8.9 for details) is transmitted in Transfer Frames with Transfer Frame
Master Channel Counter value ending with bits 0b00.
•
CLCW from the internal hardware commands is transmitted in Transfer Frames with Transfer
Frame Master Channel Counter value ending with bits 0b01.
•
CLCW from the external asynchronous bit serial interface input clcwin[0] is transmitted in
Transfer Frames with Transfer Frame Master Channel Counter value ending with bits 0b10.
•
CLCW from the external asynchronous bit serial interface input clcwin[1] is transmitted in
Transfer Frames with Transfer Frame Master Channel Counter value ending with bits 0b11.
Note that bit 16 (No RF Available) and 17 (No Bit Lock) of the CLCW and project specific OCF are
taken from information carried on discrete inputs tcrfa[ ] and tcactive[ ].
4.3.7
Master Channel Frame Service
The Master Channel Frame Service is not implemented.
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4.3.8
Master Channel Multiplexing
The Master Channel Multiplexing Function is not implemented.
4.3.9
All Frame Generation
The All Frame Generation functionality operates on all transfer frames of a Physical Channel.
Frame Error Control Field (FECF) generation can be enabled and disabled by means of registers.
4.4
Synchronization and Channel Coding Sub-Layer
4.4.1
The 32-bit Attached Synchronization Marker is placed in front of each Transfer Frame as per
[CCSDS-131.0] and [ECSS-50-03A].
4.4.2
Reed-Solomon Encoder
The CCSDS recommendation [CCSDS-131.0] and ECSS standard [ECSS-50-03A] specify ReedSolomon codes, one (255, 223) code. The ESA PSS standard [PSS-04-103] only specifies the former
code. Although the definition style differs between the documents, the (255, 223) code is the same in
all three documents. The definition used in this document is based on the PSS standard [PSS-04-103].
The Reed-Solomon encoder is compliant with the coding algorithms in [CCSDS-131.0] and [ECSS50-03A]:
•
there are 8 bits per symbol;
•
there are 255 symbols per codeword;
•
the encoding is systematic:
•
for E=16 or (255, 223), the first 223 symbols transmitted are information symbols, and the last 32
symbols transmitted are check symbols;
•
the E=16 code can correct up to 16 symbol errors per codeword;
•
the field polynomial is
8
6
4
3
2
f esa ( x ) = x + x + x + x + x + x + 1
•
the code generator polynomial for E=8 is
135
g esa ( x ) =
∏
16
i
(x + α ) =
i = 120
∑ gj ⋅ x
j
j=0
for which the highest power of x is transmitted first;
•
the code generator polynomial for E=16 is
143
g esa ( x ) =
∏
32
i
(x + α ) =
i = 112
∑ gj ⋅ x
j
j=0
for which the highest power of x is transmitted first;
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•
interleaving is supported for depth I = {1 to 8}, where information symbols are encoded as I
codewords with symbol numbers i + j*I belonging to codeword i {where 0 ≤ i < I and 0 ≤ j <
255};
•
shortened codeword lengths are supported;
•
the input and output data from the encoder are in the representation specified by the following
transformation matrix Tesa, where i0 is transferred first
ι0 ι 1 ι2 ι 3 ι4 ι5 ι 6 ι7 = α7 α6 α5 α4 α3 α2 α 1 α0
•
0
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
0
1
1
0
1
1
1
0
0
0
1
0
the following matrix T-1esa specifying the reverse transformation
α7 α 6 α5 α4 α3 α2 α1 α0 = ι0 ι 1 ι2 ι3 ι 4 ι5 ι 6 ι7
•
0
0
1
× 0
0
0
0
0
1
0
0
× 0
1
0
0
1
1
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
the Reed-Solomon output is non-return-to-zero level encoded.
The Reed-Solomon Encoder encodes a bit stream from preceding encoders and the resulting symbol
stream is output to subsequent encoder and modulators. The encoder generates codeblocks by receiving information symbols from the preceding encoders which are transmitted unmodified while calculating the corresponding check symbols which in turn are transmitted after the information symbols.
The check symbol calculation is disabled during reception and transmission of unmodified data not
related to the encoding. The calculation is independent of any previous codeblock and is perform correctly on the reception of the first information symbol after a reset.
Each information symbol corresponds to an 8 bit symbol. The symbol is fed to a binary network in
which parallel multiplication with the coefficients of a generator polynomial is performed. The products are added to the values contained in the check symbol memory and the sum is then fed back to
the check symbol memory while shifted one step. This addition is performed octet wise per symbol.
This cycle is repeated until all information symbols have been received. The contents of the check
symbol memory are then output from the encoder. The encoder is based on a parallel architecture,
including parallel multiplier and adder.
The interleave depth is chosen during operation by means of a configuration register.
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Pseudo-Randomiser
The Pseudo-Randomiser (PSR) generates a bit sequence according to [CCSDS-131.0] and [ECSS-5003A] which is xor-ed with the data output of preceding encoders. This function allows the required bit
transition density to be obtained on a channel in order to permit the receiver on ground to maintain bit
synchronization. The polynomial for the Pseudo-Randomiser is h (x) = x8+x7+x5+x3+1 and is implemented as a Fibonacci version (many-to-one implementation) of a Linear Feedback Shift Register
(LFSR). The registers of the LFSR are initialized to all ones between Transfer Frames. The Attached
Synchronization Marker (ASM) is not effected by the encoding.
data in
x8
x7
x6
x5
x4
x3
x2
data out
x1
initialise to all zero
Figure 7. Pseudo-randomiser
4.4.4
Convolutional Encoder
The Convolutional Encoder (CE) implements the basic convolutional encoding scheme. The ESA
PSS standard [PSS-04-103] specifies a basic convolutional code without puncturing. This basic convolutional code is also specified in the CCSDS recommendation [CCSDS-131.0] and ECSS standard
[ECSS-50-03A], which in addition specifies a punctured convolutional code.
The basic convolutional code has a code rate of 1/2, a constraint length of 7, and the connection vectors G1 = 1111001b (171 octal) and G2 = 1011011b (133 octal) with symbol inversion on output path,
where G1 is associated with the first symbol output.
G1
data out G1
1
data in
x6
x5
x4
x3
x2
x1
data out
2
data out G2
G2
Figure 8. Unpuctured convolutional encoder
4.5
Physical Layer
4.5.1
Non-Return-to-Zero Level encoder
The Non-Return-to-Zero Mark encoder (NRZ) encodes differentially a bit stream from preceding
encoders according to [ECSS-50-05A]. The waveform is shown in figure 9. Both data and the
Attached Synchronization Marker (ASM) are affected by the coding. When the encoder is not
enabled, the bit stream is by default non-return-to-zero level encoded.
Symbol:
1
0
0
1
0
1
1
0
NRZ-L
NRZ-M
Figure 9. NRZ-L and NRZ-M waveform
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4.5.2
Clock Divider
The Clock Divider (CD) provides clock enable signals for the telemetry and channel encoding chain.
The clock enable signals are used for controlling the bit rates of the different encoder and modulators.
The source for the bit rate frequency is the dedicated bit rate clock input. The bit rate clock input can
be divided to a degree 215. The divider can be configured during operation to divide the bit rate clock
frequency from 1/1 to 1/215.
The bit rate frequency is based on the output frequency of the last encoder in a coding chain, except
for the sub-carrier modulator. No actual clock division is performed, since clock enable signals are
used. No clock multiplexing is performed in the core.
The Clock Divider (CD) supports clock rate increases for the following encoders and rates:
•
Convolutional Encoder (CE), 1/2, 2/3, 3/4, 5/6 and 7/8
The resulting symbol rate and telemetry rate are depended on what encoders and modulators are
enabled. The following variables are used in the tables hereafter: f = input bit frequency, n = SYMBOLRATE+1 (GRTM physical layer register field +1), c = convolutional coding rate {1/2, 2/3, 3/4, 5/
6, 7/8) (see CERATE field in GRTM coding sub-layer register).
Table 28. Data rates without sub-carrier modulation
Coding &
Modulation
CE
Telemetry
rate
f/n
(f / n) * c
Convolutional
rate
f/n/m
Split-Phase
rate
-
Sub-carrier
frequency
-
Output symbol
rate
f/n
f/n
Output clock
frequency
f/n
f/n
For n = 1, no output symbol clock is generated, i.e. SYMBOLRATE register field equals 0.
n should be an even number, i.e. SYMBOLRATE register field should be uneven and > 0 to generate an output symbol clock with 50% duty cycle. This also
applies to the Manchester encoded output waveform duty cycle.
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38
Connectivity
The output from the Packet Telemetry encoder can be connected to:
•
Reed-Solomon encoder
•
Pseudo-Randomiser
•
Non-Return-to-Zero encoder
•
Convolutional encoder
The input to the Reed-Solomon encoder can be connected to:
•
Packet Telemetry encoder
The output from the Reed-Solomon encoder can be connected to:
•
Pseudo-Randomiser
•
•
The input to the Pseudo-Randomiser (PSR) can be connected to:
•
•
The output from the Pseudo-Randomiser (PSR) can be connected to:
•
•
The input to the Non-Return-to-Zero encoder (NRZ) can be connected to:
•
•
•
Pseudo-Randomiser
The output from the Non-Return-to-Zero encoder (NRZ) can be connected to:
•
The input to the Convolutional Encoder (CE) can be connected to:
•
•
•
Pseudo-Randomiser
•
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4.7
39
Operation
4.7.1
Introduction
The DMA interface provides a means for the user to insert Transfer Frames in the Packet Telemetry
and AOS Encoder. Depending on which functions are enabled in the encoder, the various fields of the
Transfer Frame are overwritten by the encoder. It is also possible to bypass some of these functions
for each Transfer Frame by means of the control bits in the descriptor associated to each Transfer
Frame. The DMA interface allows the implementation of Virtual Channel Frame Service and Master
Channel Frame Service, or a mixture of both, depending on what functions are enabled or bypassed.
4.7.2
Descriptor setup
The transmitter DMA interface is used for transmitting transfer frames on the downlink. The transmission is done using descriptors located in memory.
A single descriptor is shown in table 29 and 30. The number of bytes to be sent is set globally for all
transfer frames in the length field in register DMA length register. The the address field of the descriptor should point to the start of the transfer frame. The address must be word-aligned. If the interrupt
enable (IE) bit is set, an interrupt will be generated when the transfer frame has been sent (this
requires that the transmitter interrupt enable bit in the control register is also set). The interrupt will be
generated regardless of whether the transfer frame was transmitted successfully or not. The wrap
(WR) bit is also a control bit that should be set before transmission and it will be explained later in
this section.
Table 29. GRTM transmit descriptor word 0 (address offset 0x0)
31
16
RESERVED
15
14
13 10
9
8
7
UE
TS
0000
VCE
MCB
FSHB
6
5
OCFB FHECB
4
3
2
1
0
IZB
FECFB
IE
WR
EN
31: 16
RESERVED
15
Underrun Error (UE) - underrun occurred while transmitting frame (status bit only)
14
Time Strobe (TS) - generate a time strobe for this frame
13: 10
RESERVED
9
Virtual Channel Counter Enable (VCE) - enable virtual channel counter generation (using the Idle
Frame virtual channel counter)
8
Master Channel Counter Bypass (MCB) - bypass master channel counter generation (TM only)
7
Frame Secondary Header Bypass (FSHB) - bypass frame secondary header generation (TM only)
6
Operational Control Field Bypass (OCFB) - bypass operational control field generation
5
Frame Error Header Control Bypass (FECHB) - bypass frame error header control generation (AOS)
4
Insert Zone Bypass (IZB) - bypass insert zone generation (AOS)
3
Frame Error Control Field Bypass (FECFB) - bypass frame error control field generation
2
Interrupt Enable (IE) - an interrupt will be generated when the frame from this descriptor has been
sent provided that the transmitter interrupt enable bit in the control register is set. The interrupt is
generated regardless if the frame was transmitted successfully or if it terminated with an error.
1
Wrap (WR) - Set to one to make the descriptor pointer wrap to zero after this descriptor has been
used. If this bit is not set the pointer will increment by 8. The pointer automatically wraps to zero
when the 1 kB boundary of the descriptor table is reached.
0
Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor
fields.
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Table 30. GRTM transmit descriptor word 1 (address offset 0x4)
31
2
ADDRESS
1
0
RES
31: 2
Address (ADDRESS) - Pointer to the buffer area from where the packet data will be loaded.
1: 0
RESERVED
To enable a descriptor the enable (EN) bit should be set and after this is done, the descriptor should
not be touched until the enable bit has been cleared by the core.
4.7.3
Starting transmissions
Enabling a descriptor is not enough to start a transmission. A pointer to the memory area holding the
descriptors must first be set in the core. This is done in the transmitter descriptor pointer register. The
address must be aligned to a 1 kByte boundary. Bits 31 to 10 hold the base address of descriptor area
while bits 9 to 3 form a pointer to an individual descriptor.The first descriptor should be located at the
base address and when it has been used by the core, the pointer field is incremented by 8 to point at
the next descriptor. The pointer will automatically wrap back to zero when the next 1 kByte boundary
has been reached (the descriptor at address offset 0x3F8 has been used). The WR bit in the descriptors
can be set to make the pointer wrap back to zero before the 1 kByte boundary.
The pointer field has also been made writable for maximum flexibility but care should be taken when
writing to the descriptor pointer register. It should never be touched when a transmission is active.
The final step to activate the transmission is to set the transmit enable bit in the DMA control register.
This tells the core that there are more active descriptors in the descriptor table. This bit should always
be set when new descriptors are enabled, even if transmissions are already active. The descriptors
must always be enabled before the transmit enable bit is set.
4.7.4
Descriptor handling after transmission
When a transmission of a frame has finished, status is written to the first word in the corresponding
descriptor. The Underrun Error bit is set if the FIFO became empty before the frame was completely
transmitted. The other bits in the first descriptor word are set to zero after transmission while the second word is left untouched. The enable bit should be used as the indicator when a descriptor can be
used again, which is when it has been cleared by the core.
There are multiple bits in the DMA status register that hold transmission status.
The Transmitter Interrupt (TI) bit is set each time a DMA transmission of a transfer frame ended successfully. The Transmitter Error (TE) bit is set each time a DMA transmission of a transfer frame
ended with an underrun error. For either event, an interrupt is generated for transfer frames for which
the Interrupt Enable (IE) was set in the descriptor (Virtual Channels 0 through 2 only). The interrupt is
maskable with the Interrupt Enable (IE) bit in the control register.
The Transmitter AMBA error (TA) bit is set when an AMBA AHB error was encountered either when
reading a descriptor or when reading transfer frame data. Any active transmissions were aborted and
the DMA channel was disabled (affects Virtual Channels 0 through 6). This can be a result of a DMA
access caused by any of Virtual Channels 0 through 6. It is recommended that the Telemetry Encoder
is reset after an AMBA AHB error. The interrupt is maskable with the Interrupt Enable (IE) bit in the
control register.
The Transfer Frame Sent (TFS) bit is set whenever a transfer frame has been sent, independently if it
was sent via the DMA interface or generated by the core. The interrupt is maskable with the Transfer
Frame Interrupt Enable (TFIE) bit in the control register. Any Virtual Channel causes this interrupt.
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41
The Transfer Frame Failure (TFF) bit is set whenever a transfer frame has failed for other reasons,
such as when Idle Frame generation is not enabled and no user Transfer Frame is ready for transmission, independently if it was sent via the DMA interface or generated by the core. The interrupt is
maskable with the Transfer Frame Interrupt Enable (TFIE) bit in the control register.
The Transfer Frame Ongoing (TFO) bit is set when DMA transfers are enabled (Virtual Channels 0
through 2 only), and is not cleared until all DMA induced transfer frames have been transmitted after
DMA transfers are disabled.
The External Transmitter Interrupt (XTI) bit is set each time a DMA transmission of a transfer frame
ended successfully (unused here). The External Transmitter Error (XTE) bit is set each time a DMA
transmission of a transfer frame ended with an underrun error (for Virtual Channels 3 through 6 only).
4.7.5
Auto start
The telemetry encoder will automatically start transmitting Idle Telemetry Transfer Frames after an
external reset. The internal DMA service and the external Virtual Channels will be disabled.
The following register bit field will have pre-defined reset values:
GRTM DMA control register:
RST = 0
TXRST = 0
GRTM DMA Length register:
LIMIT-1 = 1114 (Transfer Frame length of 1115 octets)
LENGTH-1 = 1114 (Transfer Frame length of 1115 octets)
GRTM control register:
TE = 1
GRTM physical layer register:
SF = 0
SYMBOLRATE = 0x4 (division by 5)
GRTM coding sub-layer register:
RS = 1, RSDEPTH = 4 (interleave depth 5), and RS8 = 0
PSR = 1
NRZ = 0 (NRZ-L)
CE = 0
GRTM all frames generation register:
FECF = 0
GRTM master frame generation register:
MC = 1
OCF = 1 (MC_OCF service, on all frames)
OW = 1
GRTM idle frame generation register:
IDLE = 1
OCF = 1
VCID = 0x7
SCID = from tcscid[0:9] input
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42
Registers
The core is programmed through registers mapped into APB address space.
Table 31. GRTM registers
APB address offset
Register
0x00
GRTM DMA Control register
0x04
GRTM DMA Status register
0x08
GRTM DMA Length register
0x0C
GRTM DMA Descriptor Pointer register
0x10
GRTM DMA Configuration register
0x14
GRTM DMA Revision register
0x20
GRTM DMA External VC Control & Status register
0x2C
GRTM DMA External VC Descriptor Pointer register
0x80
GRTM Control register
0x84
GRTM Status register (unused)
0x88
GRTM Configuration register
0x90
GRTM Physical Layer register
0x94
GRTM Coding Sub-Layer register
0x98
GRTM Attached Synchronization Marker (unused)
0xA0
GRTM All Frames Generation register
0xA4
GRTM Master Frame Generation register
0xA8
GRTM Idle Frame Generation register
0xC0
GRTM FSH/Insert Zone register 0 (unused)
0xC4
0xC8
0xCC
0xD0
GRTM Operational Control Field register (unused)
Table 32. GRTM DMA control register
31
5
RESERVED
4
3
2
1
0
TFIE
RST
TXRST
IE
EN
31: 5
RESERVED
4
Transfer Frame Interrupt Enable (TFIE) - enable telemetry frame sent (TFS) and failure (TFF) interrupt, and time strobe interrupt
3
Reset (RST) - reset DMA and telemetry transmitter
Note: After setting the RST bit to 1 the complete encoder will be reset, and the TXRST will be automatically set to 1 which disables the telemetry encoder completely. Also the TE bit in the GRTM
control register will be cleared to 0.
2
Reset Transmitter (TXRST) - reset telemetry transmitter
1
Interrupt Enable (IE) - enable DMA interrupts (TI), (TE) and (TA)
0
Enable (EN) - enable DMA transfers (Virtual Channels 0 through 2)
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Table 33. GRTM DMA status register
31
8
RESERVED
7
6
TXSTA TXRDY
T
5
4
3
2
1
0
TFO
TFS
TFF
TA
TI
TE
31: 8
RESERVED
7
Transmitter Reset Status (TXSTAT) - telemetry transmitter is in reset mode when set (read-only)
6
Transmitter Ready (TXRDY) - telemetry transmitter ready for operation after setting the TE bit in
GRTM control register (read-only)
5
Transfer Frame Ongoing (TFO) - telemetry frames via DMA transfer (Virtual Channels 0 through 2)
are on-going (read-only)
4
Transfer Frame Sent (TFS) - telemetry frame interrupt, cleared by writing a logical 1 (any Virtual
Channel)
3
Transfer Frame Failure (TFF) - telemetry transmitter failure, cleared by writing a logical 1 (any Virtual Channel)
2
Transmitter AMBA Error (TA) - DMA AMBA AHB error, cleared by writing a logical 1 (Virtual
Channels 0 through 6)
1
Transmitter Interrupt (TI) - DMA interrupt, cleared by writing a logical 1 (Virtual Channels 0
through 2)
0
Transmitter Error (TE) - DMA transmitter underrun, cleared by writing a logical 1 (Virtual Channels
0 through 2)
Table 34. GRTM DMA length register
31
27 26
16 15
RESERVED
31: 27
26: 16
LIMIT-1
11 10
0
RESERVED
LENGTH-1
RESERVED
Transfer Limit (LIMIT)- length-1 of data to be fetched by DMA before transfer starts.
Note: LIMIT must be equal to or less than LENGTH.
LIMIT must be equal to or less than FIFOSZ.
LIMIT must be equal to or larger than BLOCKSZ*2 for LENGTH > BLOCKSZ*2.
15: 11
RESERVED
10: 0
Transfer Length (LENGTH) - length-1 of data to be transferred by DMA
Table 35. GRTM DMA descriptor pointer register
31
10
9
3
BASE
31: 10
INDEX
2
0
“000”
Descriptor base (BASE) - base address of descriptor table (Virtual Channels 0 through 2)
9: 3
Descriptor index (INDEX) - index of active descriptor in descriptor table
2: 0
Reserved - fixed to “00”
Table 36. GRTM DMA configuration register (read-only)
31
16 15
FIFOSZ
0
BLOCKSZ
31: 16
FIFO size (FIFOSZ) - size of FIFO memory in number of bytes (read-only)
15: 0
Block size (BLOCKSZ) - size of block in number of bytes (read-only)
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Table 37. GRTM DMA revision register (read-only)
31
20 19 18 17
RESERVED
FIX EX IN
16
15
TIRQ
8
7
0
REVISION
SUB REVISION
31: 20
RESERVED
19
Fixed Frame Length (FIX) - Frame length fixed
18
External Virtual Channels (EX) - External Virtual Channels supported
17
Internal Virtual Channels (IN) - Internal Virtual Channels supported
16
Time Strobe Interrupt (TIRQ) - Separate time strobe interrupt supported
15: 8
REVISION - Main revision number
0x00: Initial release
7: 0
SUB REVISION - Sub revision number
0x00: Initial release
0x01: Added time interrupt, moved TXRDY bit, added TXSTAT bit, added this revision register
0x02: Added support for internal and external virtual channels
Table 38. GRTM DMA external VC control & status register
31
6
RESERVED
5
4
XTFO
3
RESERVED
2
1
0
XTI
XTE
XEN
31: 6
RESERVED
5
External Transfer Frame Ongoing (XTFO) - telemetry frames via DMA transfer for external VC
(Virtual Channels 3 through 6) are on-going (read-only)
4: 3
RESERVED
2
External Transmitter Interrupt (XTI) - DMA interrupt for external VC, cleared by writing a logical 1
(unused)
1
External Transmitter Error (XTE) - DMA transmitter underrun for external VC (Virtual Channels 3
through 6), cleared by writing a logical 1
0
External Enable (XEN) - enable DMA transfers for external VC (Virtual Channels 3 through 6)(note
that descriptor table is checked continuously till this bit is cleared).
Table 39. GRTM DMA external VC descriptor pointer register
31
10
BASE
9
3
2
INDEX
31: 10
Descriptor base (BASE) - base address of descriptor table (Virtual Channels 3 through 6)
9: 3
Descriptor index (INDEX) - index of active descriptor in descriptor table
2: 0
Reserved - fixed to “00”
0
“000”
Table 40. GRTM control register
31
1
RESERVED
0
TE
31: 1
RESERVED
0:
Transmitter Enable (TE) - enables telemetry transmitter (should be done after the complete configuration of the telemetry transmitter, including the LENGTH field in the GRTM DMA length register)
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Table 41. GRTM configuration register (read-only)
31
23 22 21 20 19 18 17 16 15 14 13 12 11 10
O
C
F
B
RESERVED
C
I
F
A
O
S
F
H
E
C
I
Z
M
C
G
F
S
H
I
D
L
E
E
V
C
O
C
F
F
E
C
F
A
A
S
M
9
8
RS
6
RS
DEPTH
5
4
3
TE
P
S
R
N CE SP SC
R
Z
2
1
0
31: 23
RESERVED
22
Operational Control Field Bypass (OCFB) - CLCW implemented externally, no OCF register
21
Encryption/Cipher Interface (CIF) - interface between protocol and channel coding sub-layers
20
Advanced Orbiting Systems (AOS) - AOS transfer frame generation implemented
19
Frame Header Error Control (FHEC) - frame header error control implemented, only if AOS also set
18
Insert Zone (IZ) - insert zone implemented, only if AOS also set
17
Master Channel Generation (MCG) - master channel counter generation implemented
16
Frame Secondary Header (FSH) - frame secondary header implemented
15
Idle Frame Generation (IDLE) - idle frame generation implemented
14
Extended VC Cntr (EVC) - extended virtual channel counter implemented (ECSS)
13
Operational Control Field (OCF) - CLCW implemented internally, OCF register
12
Frame Error Control Field (FECF) - transfer frame CRC implemented
11
Alternative ASM (AASM) - alternative attached synchronization marker implemented
10: 9
Reed-Solomon (RS) - reed-solomon encoder implemented, “01” E=16, “10” E=8, “11” E=16 & 8
8: 6
Reed-Solomon Depth (RSDEPTH) - reed-solomon interleave depth -1 implemented
5
Turbo Encoder (TE) - turbo encoder implemented (reserved)
4
Pseudo-Randomiser (PSR) - pseudo-Randomiser implemented
3
Non-Return-to-Zero (NRZ) - non-return-to-zero - mark encoding implemented
2
Convolutional Encoding (CE) - convolutional encoding implemented
1
Split-Phase Level (SP) - split-phase level modulation implemented
0
Sub Carrier (SC) - sub carrier modulation implemented
Table 42. GRTM physical layer register
31
30
16
SF
SYMBOLRATE
31
15
14
SCF
0
SUBRATE
Symbol Fall (SF) - symbol clock has a falling edge at start of symbol bit
30: 16
Symbol Rate (SYMBOLRATE) - symbol rate division factor - 1
15
Sub Carrier Fall (SCF) -sub carrier output start with a falling edge for logical 1
14: 0
Sub Carrier Rate (SUBRATE) - sub carrier division factor - 1
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Table 43. GRTM coding sub-layer register
31
20 19 18 17 16 15 14
RESERVED
31: 20
C
I
F
CSEL
12 11 10
A RS RSDEPTH
A
S
M
8
7
R RESERVED P
S
S
8
R
6
5
4
N CE
R
Z
2
CE
RATE
1
0
SP SC
RESERVED
19
Encryption/Cipher Interface (CIF) - enable external encryption/cipher interface between sub-layers
18: 17
Clock Selection (CSEL) - selection of external telemetry clock source (application specific)
16
Alternative ASM (AASM) - alternative attached synchronization marker enable. When enabled the
value from the GRTM Attached Synchronization Marker register is used, else the standardized ASM
value 0x1ACFFC1D is used
15
Reed-Solomon (RS) - reed-solomon encoder enable
14: 12
Reed-Solomon Depth (RSDEPTH) - reed-solomon interleave depth -1
11
Reed-Solomon Rate (RS8) - ‘0’ E=16, ‘1’ E=8
10: 8
RESERVED
7
Pseudo-Randomiser (PSR) - pseudo-Randomiser enable
6
Non-Return-to-Zero (NRZ) - non-return-to-zero - mark encoding enable
5
Convolutional Encoding (CE) - convolutional encoding enable
4: 2
Convolutional Encoding Rate (CERATE):
“00-”
rate 1/2, no puncturing
“01-”
rate 1/2, punctured
“100”
rate 2/3, punctured
“101”
rate 3/4, punctured
“110”
rate 5/6, punctured
“111”
rate 7/8, punctured
1
Split-Phase Level (SP) - split-phase level modulation enable
0
Sub Carrier (SC) - sub carrier modulation enable
Table 44. GRTM attached synchronization marker register
31
0
ASM
31: 0
Attached Synchronization Marker (ASM) - pattern for alternative ASM, (bit 31 MSB sent first, bit 0
LSB sent last) (The reset value is the standardized alternative ASM value 0x352EF853.)
Table 45. GRTM all frames generation register
31
22 21
RESERVED
31: 22
17 16 15 14 13 12 11
FSH / IZ LENGTH
IZ
F
E
C
F
F
H
E
C
VER
0
RESERVED
RESERVED
21: 17
Frame Secondary Header (TM) / Insert Zone (AOS) (FSH / IZ LENGTH) - length in bytes
16
Insert Zone (IZ) - insert zone enabled, only with AOS
15
Frame Error Control Field (FECF) - transfer frame CRC enabled
14
Frame Header Error Control (FHEC) - frame header error control enabled, only with AOS
13: 12
Version (VER) - Transfer Frame Version - “00” Packet Telemetry, “01” AOS
11: 0
RESERVED
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Table 46. GRTM master frame generation register
31
4
RESERVED
3
2
1
0
MC
FSH
OCF
OW
31: 4
RESERVED
3
Master Channel (MC) - enable master channel counter generation (TM only)
2
Frame Secondary Header (FSH) - enable MC_FSH for master channel (TM only)
1
Operation Control Field (OCF) - enable MC_OCF for master channel
0
Over Write OCF (OW) - overwrite OCF bits 16 and 17 when set
Table 47. GRTM idle frame generation register
31
22 21 20 19 18 17 16 15
RESERVED
ID
LE
O
C
F
E
V
C
F
S
H
V MC
C
C
10
9
0
VCID
31: 22
RESERVED
21
Idle Frames (IDLE) - enable idle frame generation
SCID
20
Operation Control Field (OCF) - enable OCF for idle frames
19
Extended Virtual Channel Counter (EVC) - enable extended virtual channel counter generation for
idle frames (TM only, ECSS)
18
Frame Secondary Header (FSH) - enable FSH for idle frames (TM only)
17
Virtual Channel Counter Cycle (VCC) - enable virtual channel counter cycle generation for idle
frames (AOS only)
16
Master Channel (MC) - enable separate master channel counter generation for idle frames (TM only)
15: 10
Virtual Channel Identifier (VCID) - virtual channel identifier for idle frames
9: 0
Spacecraft Identifier (SCID) - spacecraft identifier for idle frames
Table 48. GRTM FSH / IZ register 0, MSB
31
0
DATA
31: 0
FSH / Insert Zone Data (DATA) - data (bit 31 MSB sent first)
Note: Writing to this register prevents the new FSH/Insert Zone data value to be transferred.
Table 49. GRTM FSH / IZ register 1
31
0
DATA
31: 0
FSH / Insert Zone Data (DATA) - data
Table 50. GRTM FSH / IZ register 2
31
0
DATA
31: 0
FSH / Insert Zone Data (DATA) - data
GR-TMTC-0002
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Table 51. GRTM FSH / IZ register 3, LSB
31
0
DATA
31: 0
FSH / Insert Zone Data (DATA) - data (bit 0 LSB sent last)
Note: Writing to this registers enables the new FSH/Insert Zone data value to be transferred.
Table 52. GRTM OCF register
31
0
CLCW
31: 0
4.9
Operational Control Field (OCF) - CLCW data (bit 31 MSB, bit 0 LSB)
Signal definitions and reset values
The signals and their reset values are described in table 53.
Table 53. Signal definitions and reset values
4.10
Signal name
Type
Function
Active
Reset value
transclk
Input
Rising
-
tcrfa[ ]
Input, async
RF Available
-
-
tcactive[ ]
Input, async
Bit Lock
-
-
caduout[ ]
Output
Serial bit data, output at caduclk edge (selectable)
-
-
caduclk[ ]
Output
Serial bit data clock
Rising
Logical 0
clcwin[ ]
Input
CLCW data input
-
-
Timing
The timing waveforms and timing parameters are shown in figure 10 and are defined in table 54.
transclk
caduout[ ], caduclk[ ]
tGRTM0
tcrfa[ ], tcactive[ ]
tGRTM1
tGRTM0
tGRTM2
Figure 10. Timing waveforms
Table 54. Timing parameters
Name
Parameter
Reference edge
Min
Max
Unit
tGRTM0
clock to output delay
rising transclk edge
0
40
ns
tGRTM1
input to clock hold
-
-
ns
tGRTM2
input to clock setup
-
-
ns
tGRTM3
transclk clock period
-
125
125
ns
Note: The inputs are re-synchronized inside the core. The signals do not have to meet any setup or hold requirements. Static
signals should not change between resets.
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5
Telemetry Encoder - Virtual Channel Generation function input interface
5.1
Overview
The Telemetry Encoder Virtual Channel Generation function input interface implements an interfaces
towards the automatic Virtual Channel Generation function of the Telemetry Encoder (also called
external Virtual Channels). Space Packets or any other user-defined data block can be input.
Data is transferred to the Virtual Channel Generation function by writing to the AMBA AHB slave
interface, located in the AHB I/O area. Writing is only possible when the packet valid delimiter is
asserted, else the access results in an AMBA access error. It is possible to transfer one, two or four
bytes at a time, following the AMBA big-endian convention regarding send order. The last written
data can be read back via the AMBA AHB slave interface. Data are output as octets to the Virtual
Channel Generation function.
In the case the data from a previous write access has not been fully transferred over the interface, a
new write access will result in an AMBA retry response. The progress of the interface can be monitored via the AMBA APB slave interface. An interrupt is generated when the data from the last write
access has been transferred. An interrupt is also generated when the ready for input packet indicator is
asserted.
The core incorporates status and monitoring functions accessible via the AMBA APB slave interface.
This includes:
5.2
•
Busy and ready signalling from Virtual Channel Generation function
•
Interrupts on ready for new word, or ready for new packet (size 518 octets)
Interrupts
Two interrupts are implemented by the interface:
5.3
Index:
Name:
Description:
0
NOT BUSY
Ready for a new data (word, half-word or byte)
1
READY
Ready for new packet
Registers
Table 55. GRTM_PAHB registers
APB address offset
Register
16#004#
Status Register
16#008#
Control Register
GR-TMTC-0002
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50
Status Register (R)
Table 56. Status Register
31
1:
0:
2
BUSY
READY
1
0
BUSY
READY
Not ready for new input, busy with octet
Ready for new packet of maximum size
All bits are cleared to 0 at reset.
5.3.2
Control Register (R/W)
Table 57. Control Register
31
10
-
8:
9:
2:
1:
0:
9
8
BUSYEN
READYEN
7
3
-
2
1
0
VALID
RST
EN
BUSYEN Enable not-busy interrupt when 1
READYENEnable ready for packet interrupt when 1
VALID
Packet valid delimiter, packet valid when 1, in-between packets when 0 (read-only)
RST
Reset complete core when 1
EN
Enable interface when 1
All bits are cleared to 0 at reset. Note that RST is read back as 0.
5.4
AHB I/O area
Data to be transferred to the Virtual Channel Generation function is written to the AMBA AHB slave
interface which implements a AHB I/O area. See [GRLIB] for details.
Note that the address is not decoded by the core. Address decoding is only done by the AMBA AHB
controller, for which the I/O area location and size is configured by means of the ioaddr and iomask
VHDL generics. It is possible to transfer one, two or four bytes at a time, following the AMBA bigendian convention regarding send order. The last written data can be read back via the AMBA AHB
slave interface. Data are output as octets on the Virtual Channel Generation interface.
Table 58. AHB I/O area - data word definition
31
24
DATA [31:24]
23
DATA [23:16]
16
15
DATA [15:8]
GR-TMTC-0002
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7
0
DATA [7:0]
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Table 59. AHB I/O area - send order
Transfer size
Address offset
DATA [31:24]
DATA [23:16]
DATA [15:8]
DATA [7:0] Comment
Word
0
first
second
third
last
Halfword
Byte
Four bytes sent
0
first
last
-
-
Two bytes sent
2
-
-
first
last
Two bytes sent
0
first
-
-
-
One byte sent
1
-
first
-
-
One byte sent
2
-
-
first
-
One byte sent
3
-
-
-
first
One byte sent
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6
Telemetry Encoder - Virtual Channel Generation
6.1
Overview
The CCSDS/ECSS/PSS Telemetry Encoder Virtual Channel Generation function implements:
•
•
Transfer Frame Data Field insertion (with support for different lengths due to OCF and FECF)
•
The function keeps track of the number of octets received and the packet boundaries in order to calculated the First Header Pointer (FHP). The data are stored in pre-allocated slots in the buffer memory
comprising complete Transfer Frames. The module fully supports the FHP generation and does not
require any alignment of the packets with the Transfer Frame Data Field boundary.
The data input format can be CCSDS Space Packet [CCSDS-133.0] or any user-defined data-block.
Data is input via a separate Virtual Channel Generation function input interface.
The function communicates with the Telemetry Encoder Virtual Channel Frame Service by means of
a buffer memory space. The buffer memory space allocated to the Virtual Channel is treated as a circular buffer. The buffer memory space is accessed by means of a AMBA AHB master interface.
6.2
Registers
None.
6.3
None.
6.4
Timing
None.
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7
Telemetry Encoder - Descriptor
7.1
Overview
The CCSDS/ECSS/PSS Telemetry Encoder Descriptor implements an automatic descriptor handler
for external Telemetry Virtual Channels implemented in hardware (Telemetry Encoder Virtual Channel Generation function), not requiring software support.
7.2
Operation
7.2.1
Introduction
Warning: software should not read or write the descriptor table. All interaction is performed automatically by hardware.
The bandwidth is allocated equally between the external Telemetry Virtual Channels. Note that the
descriptor table will be continuously checked by the Telemetry Encoder, even when all descriptors
have their Enable (EN) bit cleared. This will go on until the External Enable (XEN) bit in the Telemetry Encoder is cleared by software.
7.2.2
Descriptor definition
A single descriptor is shown in table 60 and 61.
Table 60. Transmit descriptor word 0 (address offset 0x0)
31
16
RESERVED
15
14
13 10
9
8
7
UE
TS
0000
VCE
MCB
FSHB
6
5
OCFB FHECB
4
3
2
1
0
IZB
FECFB
IE
WR
EN
31: 16
RESERVED
15
Underrun Error (UE) - underrun occurred while transmitting frame (status bit only)
14
Time Strobe (TS) - generate a time strobe for this frame (static 0)
13: 10
RESERVED
9
Virtual Channel Counter Enable (VCE) - enable virtual channel counter generation (using the Idle
Frame virtual channel counter) (static 0)
8
Master Channel Counter Bypass (MCB) - bypass master channel counter generation (TM only)
(static 0)
7
Frame Secondary Header Bypass (FSHB) - bypass frame secondary header generation (TM only)
(static 0)
6
Operational Control Field Bypass (OCFB) - bypass operational control field generation (static 0)
5
Frame Error Header Control Bypass (FECHB) - bypass frame error header control generation (AOS)
(static 0)
4
Insert Zone Bypass (IZB) - bypass insert zone generation (AOS) (static 0)
3
Frame Error Control Field Bypass (FECFB) - bypass frame error control field generation (static 0)
2
Interrupt Enable (IE) - an interrupt will be generated when the frame from this descriptor has been
sent provided that the transmitter interrupt enable bit in the control register is set. (static 0)
1
Wrap (WR) - Set to one to make the descriptor pointer wrap to zero after this descriptor has been
used. If this bit is not set the pointer will increment by 8. The pointer automatically wraps to zero
when the 1 kB boundary of the descriptor table is reached. (Set to 1 for last descriptor entry, otherwise static 0).
0
Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor
fields. (Automatically set an cleared by hardware)
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Table 61. Transmit descriptor word 1 (address offset 0x4)
31
2
ADDRESS
7.3
1
0
RES
31: 2
Address (ADDRESS) - Pointer to the buffer area from where the packet data will be loaded.
1: 0
RESERVED
Registers
None.
7.4
None.
7.5
Timing
None.
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8
Telecommand Decoder - Software Commands
8.1
Overview
The Telecommand Decoder (GRTC) is compliant with the Packet Telecommand protocol and specification defined by [PSS-04-107] and [PSS-04-151]. The decoder is also compatible with the CCSDS
recommendations stated in [CCSDS-201.0], [CCSDS-202.0], [CCSDS-202.1] and [CCSDS-203.0].
The Telecommand Decoder (GRTC) only implements the Coding Layer (CL).
In the Coding Layer (CL), the telecommand decoder receives bit streams on multiple channel inputs.
The streams are assumed to have been generated in accordance with the Physical Layer specifications.
In the Coding Layer, the decoder searches all input streams simultaneously until a start sequence is
detected. Only one of the channel inputs is selected for further reception. The selected stream is biterror corrected and the resulting corrected information is passed to the user. The corrected information
received in the CL is transfer by means of Direct Memory Access (DMA) to the on-board processor.
The Command Link Control Word (CLCW) and the Frame Analysis Report (FAR) can be read and
written as registers via the AMBA AHB bus. Parts of the two registers are generated by the Coding
Layer (CL). The CLCW is automatically transmitted to the Telemetry Encoder (TM) for transmission
to the ground. Note that most parts of the CLCW and FAR are not produced by the Telecommand
Decoder (GRTC) hardware portion. This is instead done by th software portion of the decoder.
Telecommand input
NRZ-M
FIFO
Physical Layer
CLCW output
AMBA
AHB
Slave
DMA
BCH Decoder
AMBA AHB
AMBA
AHB
Master
Coding Sub-Layer
Pseudo-Derandomizer
CLCW1
CLCW2
GRTC
8.1.1
Concept
A telecommand decoder in this concept is mainly implemented by software in the on-board processor.
The supporting hardware in the GRTC core implements the Coding Layer, which includes synchronisation pattern detection, channel selection, codeblock decoding, Direct Memory Access (DMA) capability and buffering of corrected codeblocks. The hardware also provides a register via which the
Command Link Control Word (CLCW) is made available to a Telemetry Encoder. The CLCW is to be
generated by the software.
The GRTC has been split into several clock domains to facilitate higher bit rates and partitioning. The
two resulting sub-cores have been named Telecommand Channel Layer (TCC) and the Telecommand
Interface (TCI). Note that TCI is called AHB2TCI. A complete CCSDS packet telecommand decoder
can be realized at software level according to the latest available standards, staring from the Transfer
Layer.
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HCLK
TCI2DMA
HRESETn
HRESET
CRESETn
CRESET
AHBOverrunIrq
Rs232Tx
AHBFullIrq
Rs232Tx
AHBCLTUIrq
TCC_Conf[]
Configuration
interface
CLCW1Data
CLCW
interface
CLCW2Data
TCC_RFAvailPos
AHBFARIrq
External
configuration
interface
TCC_SCId[]
AHBBitLockIrq
TCC_BitLockPos
AHBFRAvailIrq
TCC_Pseudo
TCC_Mark
AHBSIn[]
AHB Slave
interface
TCC_PSS
AHBSOut[]
CLCWRFAvailable[]
Physical Layer
interface
CLCWBitLock[]
RxPtr
AHB2TCI
AHBMOut[]
AHB Master
interface
CLReq[]
DMA2AHB
AHBMIn[]
RxFIFO
RxCL
FARReq[]
Coding Layer (CL)
Receiver Frame
Analysis Report (FAR)
interface
8.1.2
Functions and options
The Telecommand Decoder (GRTC) only implements the Coding Layer of the Packet Telecommand
Decoder standard [PSS-04-107]. All other layers are to be implemented in software, e.g. Authentication Unit (AU). The Command Pulse Distribution Unit (CPDU) is not implemented.
The following functions of the GRTC are programmable by means of registers:
•
Pseudo-De-Randomisation
•
Non-Return-to-Zero – Mark decoding
The following functions of the GRTC are pin configurable:
8.2
•
Polarity of RF Available and Bit Lock inputs
•
Edge selection for input channel clock
Data formats
8.2.1
Reference documents
[PSS-04-107]
Packet Telecommand Standard, PSS-04-107, Issue 2, January 1992
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[PSS-04-151]
Telecommand Decoder Standard, PSS-04-151, Issue 1, September 1993
[CCSDS-201.0] Telecommand – Part 1 – Channel Service, CCSDS 201.0-B-3, June 2000
[CCSDS-202.0] Telecommand – Part 2 – Data Routing Service, CCSDS 202.0-B-3, June 2001
[CCSDS-202.1] Telecommand – Part 2.1 – Command Operation Procedures, CCSDS 202.1-B-2,
June 2001
[CCSDS-203.0] Telecommand – Part 3 – Data Management Service, CCSDS 203.0-B-2, June 2001
8.2.2
Waveforms
Delimiter
Clock
Data
0
1
2
3
4
5
6
7
n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1
MSB
LSB
Figure 13. Telecommand input protocol
8.3
Coding Layer (CL)
The Coding Layer synchronises the incoming bit stream and provides an error correction capability
for the Command Link Transmission Unit (CLTU). The Coding Layer receives a dirty bit stream
together with control information on whether the physical channel is active or inactive for the multiple input channels.
The bit stream is assumed to be NRZ-L encoded, as the standards specify for the Physical Layer. As
an option, it can also be NRZ-M encoded. There are no assumptions made regarding the periodicity or
continuity of the input clock signal while an input channel is inactive. The most significant bit (Bit 0
according to [PSS-04-107]) is received first.
Searching for the Start Sequence, the Coding Layer finds the beginning of a CLTU and decodes the
subsequent codeblocks. As long as no errors are detected, or errors are detected and corrected, the
Coding Layer passes clean blocks of data to the Transfer Layer which is implemented in software.
When a codeblock with an uncorrectable error is encountered, it is considered as the Tail Sequence, its
contents are discarded and the Coding Layer returns to the Start Sequence search mode.
The Coding Layer also provides status information for the FAR, and it is possible to enable an
optional de-randomiser according to [CCSDS-201.0].
8.3.1
Synchronisation and selection of input channel
Synchronisation is performed by means of bit-by-bit search for a Start Sequence on the channel
inputs. The detection of the Start Sequence is tolerant to a single bit error anywhere in the Start
Sequence pattern. The Coding Layer searches both for the specified pattern as well as the inverted
pattern. When an inverted Start Sequence pattern is detected, the subsequent bit-stream is inverted till
the detection of the Tail Sequence.
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The detection is accomplished by a simultaneous search on all active channels. The first input channel
where the Start Sequence is found is selected for the CLTU decoding. The selection mechanism is
restarted on any of the following events:
•
The input channel active signal is de-asserted, or
•
a Tail Sequence is detected, or
•
a Codeblock rejection is detected, or
•
an abandoned CLTU is detected, or the clock time-out expires.
As a protection mechanism in case of input failure, a clock time-out is provided for all selection
modes. The clock time-out expires when no edge on the bit clock input of the selected input channel
in decode mode has been detected for a specified period.
When the clock time-out has expired, the input channel in question is ignored (i.e. considered inactive) until its active signal is de-asserted (configurable with gTimeoutMask=1). [Not implemented]
8.3.2
Codeblock decoding
The received Codeblocks are decoded using the standard (63,56) modified BCH code. Any single bit
error in a received Codeblock is corrected. A Codeblock is rejected as a Tail Sequence if more than
one bit error is detected. Information regarding Count of Single Error Corrections and Count of
Accept Codeblocks is provided to the FAR. Information regarding Selected Channel Input is provided
via a register.
8.3.3
De-Randomiser
In order to maintain bit synchronisation with the received telecommand signal, the incoming signal
must have a minimum bit transition density. If a sufficient bit transition density is not ensured for the
channel by other methods, the randomiser is required. Its use is optional otherwise. The presence or
absence of randomisation is fixed for a physical channel and is managed (i.e., its presence or absence
is not signalled but must be known a priori by the spacecraft and ground system). A random sequence
is exclusively OR-ed with the input data to increase the frequency of bit transitions. On the receiving
end, the same random sequence is exclusively OR-ed with the decoded data, restoring the original
data form. At the receiving end, the de-randomisation is applied to the successfully decoded data. The
de-randomiser remains in the “all-ones” state until the Start Sequence has been detected. The pattern
is exclusively OR-ed, bit by bit, to the successfully decoded data (after the Error Control Bits have
been removed). The de-randomiser is reset to the “all-ones” state following a failure of the decoder to
successfully decode a codeblock or other loss of input channel.
8.3.4
Non-Return-to-Zero – Mark
An optional Non-Return-to-Zero – Mark decoder can be enabled by means of a register.
8.3.5
Design specifics
The coding layer is supporting 1 to 8 channel inputs, although PSS requires at least 4.
A codeblock is fixed to 56 information bits (as per CCSDS/ECSS).
The CCSDS/ECSS (1024 octets) or PSS (256 octets) standard maximum frame lengths are supported,
being programmable via bit PSS in the GCR register. The former allows more than 37 codeblocks to
be received.
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The Frame Analysis Report (FAR) interface supports 8 bit CAC field, as well as the 6 bit CAC field
specified in ESA PSS-04-151- When the PSS bit is cleared to '0', the two most significant bits of the
CAC will spill over into the "LEGAL/ILLEGAL" FRAME QUALIFIER field in the FAR. These bits
will however be all-zero when PSS compatible frame lengths are received or the PSS bit is set to '1'.
The saturation is done at 6 bits when PSS bit is set to '1' and at 8 bits when PSS bit is cleared to '0'.
The Pseudo-Randomiser decoder is included (as per CCSDS/ECSS), its usage being input signal programmable.
The Physical Layer input can be NRZ-L or NRZ-M modulated, allowing for polarity ambiguity. NRZL/M selection is programmable. This is an extension to ECSS: Non-Return to Zero - Mark decoder
added, with its internal state reset to zero when channel is deactivated.
Note: If input clock disappears, it will also affect the codeblock acquired immediately before the
codeblock just being decoded (accepted by ESA PSS-04-151).
In state S1, all active inputs are searched for start sequence, there is no priority search, only round
robin search. The search for the start sequence is sequential over all inputs: maximum input frequency
= system frequency /(gIn+2)
The ESA PSS-04-151 specified CASE-1 and CASE-2 actions are implemented according to aforementioned specification, not leading to aborted frames.
Extended E2 handling is implemented:
•
E2b Channel Deactivation - selected input becomes inactive in S3
•
E2c
•
E2d Channel Deactivation - selected input is timed-out in S3
(design choice being: S3 => S1, abandoned frame)
8.3.6
Channel Deactivation - too many codeblocks received in S3
Direct Memory Access (DMA)
This interface provides Direct Memory Access (DMA) capability between the AMBA bus and the
Coding Layer. The DMA operation is programmed via an AHB slave interface.
The DMA interface is an element in a communication concept that contains several levels of buffering. The first level is performed in the Coding Layer where a complete codeblock is received and kept
until it can be corrected and sent to the next level of the decoding chain. This is done by inserting each
correct information octet of the codeblock in an on-chip local First-In-First-Out (FIFO) memory
which is used for providing improved burst capabilities. The data is then transfered from the FIFO to
a system level ring buffer in the user memory (e.g. SRAM located in on-board processor board) which
is accessed by means of DMA.
The following storage elements can thus be found in this design:
The shift and hold registers in the Coding Layer
The local FIFO (parallel; 32-bit; 4 words deep)
The system ring buffer (SRAM; 32-bit; 1 to 256 kByte deep).
8.4
Transmission
The transmission of data from the Coding Layer to the system buffer is described hereafter.
The serial data is received and shifted in a shift register in the Coding Layer when the reception is
enabled. After correction, the information content of the shift register is put into a hold register.
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When space is available in the peripheral FIFO, the content of the hold register is transferred to the
FIFO. The FIFO is of 32-bit width and the byte must thus be placed on the next free byte location in
the word.
When the FIFO is filled for 50%, a request is done to transfer the available data towards the system
level buffer.
If the system level ring buffer isn’t full, the data is transported from the FIFO, via the AHB master
interface towards the main processor and stored in e.g. SRAM. If no place is available in the system
level ring buffer, the data is held in the FIFO.
When the GRTC keeps receiving data, the FIFO will fill up and when it reaches 100% of data, and the
hold and shift registers are full, a receiver overrun interrupt will be generated
(IRQ_RX_OVERRUN). All new incoming data is rejected until space is available in the peripheral
FIFO.
When the receiving data stream is stopped (e.g. when a complete data block is received), and some
bytes are still in the peripheral FIFO, then these bytes will be transmitted to the system level ring
buffer automatically. Received bytes in the shift and hold register are always directly transferred to
the peripheral FIFO.
The FIFO is automatically emptied when a CLTU is either ready or has been abandoned. The reason
for the latter can be codeblock error, time out etc. as described in CLTU decoding state diagram.
The operational state machine is shown in figure 14.
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HARDWARE WRITE
SOFTWARE READ
START
START
INIT
INIT
init rx_w_ptr (lower bits)
init rx_r_ptr and rx_w_ptr (ASR register)
CHECK
fifo 50% full ?
N
Y
WAIT
CHECK
temp1 = rx_w_ptr
temp2 = rx_w_ptr +
#bytes received
temp3 = rx_r_ptr
OVERFLOW
set 'overflow'-flag
temp1 = rx_w_ptr
temp2 = rx_r_ptr
TBD ms
temp1 = temp2 ?
Y
RESET
CHANNEL
N
Y
temp2 >=
temp3 - offset(*)
Y
fifo full (100%) ?
N
N
WRITE
READ
burst of
writes @ temp1
Y
temp1 >=
endaddr
read @ temp2
N
temp2
=
endaddr
INCREMENT
RESET
Y
temp1=temp1+x
temp1= startaddr+ x
N
RESET
INCREMENT
temp2=startaddr+y
temp2=temp2+y
UPDATE
rx_w_ptr = temp1
All data read?
N
Y
x: amount of bytes written.
y: amount of bytes read
(*) offset is hardcoded and set to fifo depth/2. It's not possible to full a
complete 1kbyte block without a software readout (max. rx write bytes
= (1024*(rx_length+1)) - offset) [without SW readout]
Figure 14. Direct Memory Access
Legend:
rx_w_ptr
Write pointer
rx_r_ptr
Read pointer
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8.4.1
Data formatting
When in the decode state, each candidate codeblock is decoded in single error correction mode as
described hereafter.
8.4.2
CLTU Decoder State Diagram
+----------+
+----------+
+----------+
|
|
|
|
|
|
|
S1
| INACTIVE |-----E1---->|
|
|
S2
|<----E4-----|
S3
|
ACTIVE
|-----E3---->|
DECODE
|
|
|<----E2a----|
|<----E2c----|
|
|
|
|
|
|<----------------E2b----------------|
|
|
|<----------------E2d----------------|
|
+----------+
+----------+
|
+----------+
Note that the diagram has been improved with explicit handling of different E2 possibilities listed
below.
State Definition:
S1
Inactive
S2
Search
S3
Decode
Event Definition:
E1
Channel Activation
E2a
Channel Deactivation - all inputs are inactive
E2b Channel Deactivation - selected becomes inactive (CB=0 -> frame abandoned)
E2c
Channel Deactivation - too many codeblocks received (all -> frame abandoned)
E2d Channel Deactivation - selected is timed-out (all -> frame abandoned)
E3
Start Sequence Found
E4
Codeblock Rejection (CB=0 -> frame abandoned)
8.4.3
Nominal
A: When the first “Candidate Codeblock” (i.e. “Candidate Codeblock” 0, which follows Event 3
(E3):START SEQUENCE FOUND) is found to be error free, or if it contained an error which has
been corrected, its information octets are transferred to the remote ring buffer as shown in Table 3.1.
At the same time, a “Start of Candidate Frame” flag is written to bit 0 or 16, indicating the beginning
of a transfer of a block of octets that make up a “Candidate Frame”. There are two cases that are handled differently as described in the next sections.
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Table 62. Data
format
Bit[31…………24]
Bit[23…………16]
Bit[15….….……8]
Bit[7……....……0]
0x40000000
information octet0
0x01
information octet1
0x00
0x40000004
information octet2
0x00
information octet3
0x00
0x40000008
information octet4
0x00
end of frame
0x02
…
…
0x400000xx
information octet6
0x01
information octet7
0x00
0x400000xx
information octet8
0x00
abandoned frame
0x03
…
Legend: Bit [17:16] or [1:0]:
“00” = continuing octet
“01” = Start of Candidate Frame
“10” = End of Candidate Frame
“11” = Candidate Frame Abandoned
8.4.4
CASE 1
When an Event 4 – (E4): CODEBLOCK REJECTION – occurs for any of the 37 possible “Candidate
Codeblocks” that can follow Codeblock 0 (possibly the tail sequence), the decoder returns to the
SEARCH state (S2), with the following actions:
•
The codeblock is abandoned (erased)
•
No information octets are transferred to the remote ring buffer
•
An “End of Candidate Frame” flag is written, indicating the end of the transfer of a block of
octets that make up a “Candidate Frame”.
8.4.5
CASE 2
When an Event 2 – (E2): CHANNEL DEACTIVATION – occurs which affects any of the 37 possible
“Candidate Codeblocks” that can follow Codeblock 0, the decoder returns to the INACTIVE state
(S1), with the following actions:
•
The codeblock is abandoned (erased)
•
No information octets are transferred to the remote ring buffer
•
An “End of Candidate Frame” flag is written, indicating the end of the transfer of a block of
octets that make up a “Candidate Frame”
8.4.6
Abandoned
•
B: When an Event 4 (E4), or an Event 2 (E2), occurs which affects the first candidate codeblock
0, the CLTU shall be abandoned. No candidate frame octets have been transferred.
•
C: If and when more than 37 Codeblocks have been accepted in one CLTU, the decoder returns
to the SEARCH state (S2). The CLTU is effectively aborted and this is will be reported to the
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software by writing the “Candidate Frame Abandoned flag” to bit 1 or 17, indicating to the software to erase the “Candidate frame”.
8.5
Relationship between buffers and FIFOs
The conversion from the peripheral data width (8 bit for the coding layer receiver), to 32 bit system
word width, is done in the peripheral FIFO.
All access towards the system ring buffer are 32-bit aligned. When the amount of received bytes is
odd or not 32-bit aligned, the FIFO will keep track of this and automatically solve this problem. For
the reception data path, the 32 bit aligned accesses could result in incomplete words being written to
the ring buffer. This means that some bytes aren’t correct (because not yet received), but this is no
problem due to the fact that the hardware write pointer (rx_w_ptr) always points to the last, correct,
data byte.
The local FIFO ensures that DMA transfer on the AMBA AHB bus can be made by means of 2-word
bursts. If the FIFO is not yet filled and no new data is being received this shall generate a combination
of single accesses to the AMBA AHB bus if the last access was indicating an end of frame or an abandoned frame.
If the last single access is not 32-bit aligned, this shall generate a 32-bit access anyhow, but the
receive-write-pointer shall only be incremented with the correct number of bytes. Also in case the previous access was not 32-bit aligned, then the start address to write to will also not be 32-bit aligned.
Here the previous 32-bit access will be repeated including the bytes that were previously missing, in
order to fill-up the 32-bit remote memory-controller without gaps between the bytes.
The receive-write-pointer shall be incremented according to the number of bytes being written to the
remote memory controller.
8.5.1
Buffer full
The receiving buffer is full when the hardware has filled the complete buffer space while the software
didn’t read it out. Due to hardware implementation and safety, the buffer can’t be filled completely
without interaction of the software side. A space (offset) between the software read pointer (rx_r_ptr)
and the hardware write pointer (rx_w_ptr) is used as safety buffer. When the write pointer (rx_w_ptr)
would enter this region (due to a write request from the receiver), a buffer full signal is generated and
all hardware writes to the buffer are suppressed. The offset is currently hard coded to 8 bytes.
Warning: If the software wants to receive a complete 1kbyte block (when RXLEN = 0), then it must
read out at least 8 bytes of data from the buffer. In this case, the hardware can write the 1024 bytes
without being stopped by the rx buffer full signal.
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rx_w_ptr (HW)
OFFSET =
8 bytes
rx_r_ptr (SW)
0x0018
0x001C
rx buffer full condition
Figure 15. Buffer full situation
8.5.2
Buffer full interrupt
The buffer full interrupt is given when the difference between the hardware write pointer (rx_w_ptr)
and the software read pointer (rx_r_ptr) is less than 1/8 of the buffer size. The way it works is the
same as with the buffer full situation, only is the interrupt active when the security zone is entered.
The buffer full interrupt is active for 1 system clock cycle. When the software reads out data from the
buffer, the security zone shifts together with the read pointer (rx_r_ptr) pointer. Each time the hardware write pointer (rx_w_ptr) enters the security zone, a single interrupt is given.
rx buffer full IRQ is given
when the hardware
pointer enters the
security zone
rx_w_ptr (HW)
OFFSET =
256 bytes
rx_r_ptr (SW)
0x0018
0x001C
rx buffer full IRQ condition
Figure 16. Buffer full interrupt (buffers size is 2kbyte in this example)
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66
Command Link Control Word interface (CLCW)
The Command Link Control Word (CLCW) is inserted in the Telemetry Transfer Frame by the Telemetry Encoder (TM) when the Operation Control Field (OPCF) is present. The CLCW is created by the
software part of the telecommand decoder. The telecommand decoder hardware provides two registers for this purpose which can be accessed via the AMBA AHB bus.
Note that bit 16 (No RF Available) and 17 (No Bit Lock) of the CLCW are not possible to write by
software. The information carried in these bits is based on discrete inputs.
The CLCW Register 1 (CLCWR1) is internally connected to the Telemetry Encoder.
The CLCW Register 2 (CLCWR2) is connected to the external clcwout[0] signal. One PacketAsynchronous interfaces (PA) are used for the transmission of the CLCW from the telecommand decoder.
The protocol is fixed to 115200 baud, 1 start bit, 8 data bits, 1 stop, with a BREAK command for message delimiting (sending 13 bits of logical zero). The CLCWs are automatically transferred over the
PA interface after reset, on each write access to the CLCW register and on each change of the bit 16
(No RF Available) and 17 (No Bit Lock).
Table 63. CLCW
8.7
transmission protocol
Byte
Number
CLCWR
register bits
CLCW contents
First
[31:24]
Control Word Type
CLCW
Version
Number
Second
[23:16]
Virtual Channel
Identifier
Reserved Field
Third
[15:8]
No RF
Available
No Bit
Lock
Fourth
[7:0]
Report Value
Fifth
N/A
[RS232 Break Command]
Status
Field
Lock
Out
COP In Effect
Wait
Retransmit
Farm B
Counter
Report
Type
Configuration Interface (AMBA AHB slave)
The AMBA AHB slave interface supports 32 bit wide data input and output. Since each access is a
word access, the two least significant address bits are assumed always to be zero, address bits 23:0 are
decoded. Note that address bits 31:24 are not decoded and should thus be handled by the AHB arbiter/
decoder. The address input of the AHB slave interfaces is thus incompletely decoded. Misaligned
addressing is not supported. For read accesses, unmapped bits are always driven to zero.
The AMBA AHB slave interface has been reduced in function to support only what is required for the
TC. The following AMBA AHB features are constrained:
•
Only supports HSIZE=WORD, HRESP_ERROR generated otherwise
•
Only supports HMASTLOCK='0', HRESP_ERROR generated otherwise
•
Only support HBURST=SINGLE or INCR, HRESP_ERROR generated otherwise
•
No HPROT decoding
•
No HSPLIT generated
•
HRETRY is generated if a register is inaccessible due to an ongoing reset.
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•
HRESP_ERROR is generated for unmapped addresses, and for write accesses to register without
any writeable bits
•
Only big-endianness is supported.
During a channel reset the RRP and RWP registers are temporary unavailable. The duration of this
reset-inactivity is 8 HCLK clock periods and the AHB-slave generates a HRETRY response during
this period if an access is made to these registers.
If the channel reset is initiated by or during a burst-access the reset will execute correctly but a part of
the burst could be answered with a HRETRY response. It is therefore not recommended to initiate
write bursts to the register.
GRTC has interrupt outputs, that are asserted for at least two clock periods on the occurrence of one of
the following events:
8.8
•
‘CLTU stored’ (generated when CLTU has been stored towards the AMBA bus, also issued for
abandoned CLTUs)
•
‘Receive buffer full’ (generated when the buffer has less than 1/8 free) (note that this interrupt is
issued on a static state of the buffer, and can thus be re-issued immediately after the corresponding register has been read out by software, it should be masked in the interrupt controller to avoid
an immediate second interrupt).
•
‘Receiver overrun’ (generated when received data is dropped due to a reception overrun)
•
‘CLTU ready’ (note that this interrupt is also issued for abandoned CLTUs)
•
FAR interrupt ‘Status Survey Data’
•
CLCW interrupt ‘Bit Lock’
•
CLCW interrupt ‘RF Available’
Interrupts
The core generates the interrupts defined in table 64.
Table 64. Interrupts
Interrupt offset
Interrupt name
Description
1:st
RFA
RF Available changed
2:nd
BLO
Bit Lock changed
3:rd
FAR
FAR available
4:th
CR
CLTU ready/aborted
5:th
RBF
Output buffer full
6:th
OV
Input data overrun
7:th
CS
CLTU stored
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68
Registers
The core is programmed through registers mapped into AHB I/O address space.
Table 65. GRTC registers
AHB address offset
Register
0x00
Global Reset Register (GRR)
0x04
Global Control Register (GCR)
0x08
Physical Interface Mask Register (PMR)
0x0C
Spacecraft Identifier Register (SIR)
0x10
Frame Acceptance Report Register (FAR)
0x14
CLCW Register 1 (CLCWR1) (internal)
0x18
CLCW Register 2 (CLCWR2) (external)
0x1C
Physical Interface Register (PHIR)
0x20
Control Register (COR)
0x24
Status Register (STR)
0x28
Address Space Register (ASR)
0x2C
Receive Read Pointer Register (RRP)
0x30
Receive Write Pointer Register (RWP)
0x60
Pending Interrupt Masked Status Register (PIMSR)
0x64
Pending Interrupt Masked Register (PIMR)
0x68
Pending Interrupt Status Register (PISR)
0x6C
Pending Interrupt Register (PIR)
0x70
Interrupt Mask Register (IMR)
0x74
Pending Interrupt Clear Register (PICR)
Table 66. Global Reset Register (GRR)
31
24 23
1
SEB
31: 24
23: 1
0
RESERVED
0
SRST
SEB (Security Byte):
Write:
‘0x55’= the write will have effect (the register will be updated).
Any other value= the write will have no effect on the register.
Read:
All zero.
RESERVED
Write:
Don’t care.
Read:
All zero.
System reset (SRST): [1]
Write:
‘1’= initiate reset,‘0’= do nothing
Read:
‘1’= unsuccessful reset, ‘0’= successful reset
Note: The Coding Layer is not reset.
Power-up default: 0x00000000
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Table 67. Global Control Register (GCR)
31
24 23
13
SEB
31: 24
23: 13
RESERVED
12
11
10
PSS
NRZM
PSR
9
0
RESERVED
Write:
Read:
All zero.
RESERVED
Write:
Don’t care.
Read:
All zero.
12
PSS (ESA/PSS enable) [11]
11
NRZM (Non-Return-to-Zero Mark Decoder enable)
10
PSR (Pseudo-De-Randomiser enable)
9: 0
RESERVED
Write/Read:
Write/Read:
Write/Read:
‘0’= disable, ‘1’= enable [read-only]
Write:
Don’t care.
Read:
All zero.
Power-up default: 0x00001000, The default value depends on the tcmark and tcpseudo inputs.
Table 68. Physical Interface Mask Register (PMR)
31
8
RESERVED
31: 8
7: 0
7
0
MASK
RESERVED
Write:
Don’t care.
Read:
All zero.
MASK
Write:
Mask TC input when set, bit 0 correponds to TC input 0 [Not implemented]
Read:
Current mask
Table 69. Spacecraft Identifier Register (SIR) [7]
31
10
RESERVED
31: 10
9: 0
9
0
SCID
RESERVED
Write:
Don’t care.
Read:
All zero.
SCID (Spacecraft Identifier)
Write:
Don’t care.
Read:
Bit[9]=MSB, Bit[0]=LSB
Power-up default: Depends on SCID input configuration.
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Table 70. Frame Acceptance Report Register (FAR) [7]
31
30
SSD
25 24
19 18
RESERVED
31
CAC
16 15
CSEC
14 13
RESERVED
11 10
0
SCI
RESERVED
SSD (Status of Survey Data) (see [PSS-04-151])
30: 25
Write:
Don’t care.
Read:
Automatically cleared to 0 when any other field is updated by the coding layer.
Automatically set to 1 upon a read.
RESERVED
24: 19
Write:
Don’t care.
Read:
All zero.
CAC (Count of Accept Codeblocks) (see [PSS-04-151])
18: 16
Write:
Don’t care.
Read:
Information obtained from coding layer. [2]
CSEC (Count of Single Error Corrections) (see [PSS-04-151])
15: 14
Write:
Don’t care.
Read:
Information obtained from coding layer.
RESERVED
13: 11
Write:
Don’t care.
Read:
All zero.
SCI (Selected Channel Input) (see [PSS-04-151])
10: 0
Write:
Don’t care.
Read:
Information obtained from coding layer.
RESERVED
Write:
Don’t care.
Read:
All zero.
Table 71. CLCW Register (CLCWRx) (see [PSS-04-107])
31
CWTY
30 29 28 26 25 24 23
VNUM
STAF
CIE
18 17
VCI
16
15
RESERVED NRFA
31
CWTY (Control Word Type)
30: 29
VNUM (CLCW Version Number)
28: 26
STAF (Status Fields)
25: 24
CIE (COP In Effect)
23: 18
VCI (Virtual Channel Identifier)
17: 16
Reserved (PSS/ECSS requires “00”)
15
NRFA (No RF Available)
14
14
13
12
NBLO
LOUT
WAIT
Write:
Don’t care.
Read:
Based on discrete inputs.
11
RTMI
10
9
8
FBCO RTYPE
7
0
RVAL
NBLO (No Bit Lock)
Write:
Don’t care.
Read:
Based on discrete inputs.
13
LOUT (Lock Out)
12
WAIT (Wait)
11
RTMI (Retransmit)
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10: 9
Table 71. CLCW Register (CLCWRx) (see [PSS-04-107])
FBCO (FARM-B Counter)
8
RTYPE (Report Type)
7: 0
RVAL (Report Value)
Table 72. Physical Interface Register (PHIR) [7]
31
16 15
RESERVED
31: 16
15: 8
8
7
0
RFA
BLO
RESERVED
Write:
Don’t care.
Read:
All zero.
RFA (RF Available) [3]
Only implemented inputs are taken into account. All other bits are zero.
Write:
Don’t care.
Read:
7: 0
BLO (Bit Lock)
Bit[8] = input 0, Bit[15] = input 7
[3]
Only implemented inputs are taken into account. All other bits are zero.
Write:
Don’t care.
Read:
Bit[0] = input 0, Bit[7] = input 7
Power-up default: Depends on inputs.
Table 73. Control Register (COR)
31
24 23
10
SEB
31: 24
23: 10
9
RESERVED
9
CRST
8
1
RESERVED
0
RE
Write:
Read:
All zero.
RESERVED
Write:
Don’t care.
Read:
All zero.
CRST (Channel reset) [4]
Write:
‘1’= initiate channel reset,‘0’= do nothing
Read:
‘1’= unsuccessful reset, ‘0’= successful reset
Note: The Coding Layer is not reset.
8: 1
0
RESERVED
Write:
Don’t care.
Read:
All zero.
RE (Receiver Enable)
The input from the Coding Layer receiver is masked when the RE bit is disabled.
Read/Write:
‘0’= disabled, ‘1’= enabled
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Table 74. Status Register (STR) [7]
31
11
RESERVED
31: 11
10
10
RBF
9
8
7
RESERVED
RFF
6
5
RESERVED
4
OV
3
1
RESERVED
0
CR
RESERVED
Write:
Don’t care.
Read:
All zero.
RBF (RX BUFFER Full)
Write:
Don’t care.
Read:
‘0’ = Buffer not full,
‘1’= Buffer full (this bit is set if the buffer has less then 1/8 of free space)
9: 8
7
6: 5
4
3: 1
0
RESERVED
Write:
Don’t care.
Read:
All zero.
RFF (RX FIFO Full)
Write:
Don’t care.
Read:
‘0’ = FIFO not full, ‘1’ = FIFO full
RESERVED
Write:
Don’t care.
Read:
All zero.
OV (Overrun) [5]
Write:
Don’t care.
Read:
‘0’= nominal, ‘1’= data lost
RESERVED
Write:
Don’t care.
Read:
All zero.
CR (CLTU Ready) [5]
There is a worst case delay from the CR bit being asserted, until the data has actually been transferred from the receiver FIFO to the ring buffer. This depends on the PCI load etc.
Write:
Don’t care.
Read:
‘1’= new CLTU in ring buffer. ‘0’= no new CLTU in ring buffer.
Table 75. Address Space Register (ASR) [8]
31
10
BUFST
9
8
RESERVED
7
0
RXLEN
31: 10
BUFST (Buffer Start Address)
22-bit address pointer
This pointer contains the start address of the allocated buffer space for this channel.
Register has to be initialized by software before DMA capability can be enabled.
9: 8
RESERVED
7: 0
Write:
Don’t care.
Read:
All zero.
RXLEN (RX buffer length)
Number of 1kB-blocks reserved for the RX buffer.
(Min. 1kByte = 0x00, Max. 256kByte = 0xFF)
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Table 76. Receive Read Pointer Register (RRP) [6] [9][10]
31
24 23
0
RxRd Ptr Upper
31: 24
23: 0
RxRd Ptr Lower
10-bit upper address pointer
Write:
Don’t care.
Read:
This pointer = ASR[31..24].
24-bit lower address pointer.
This pointer contains the current RX read address. This register is to be incremented with the actual
amount of bytes read.
Table 77. Receive Write Pointer Register (RWP) [6] [9]
31
24 23
0
RxWr Ptr Upper
31: 24
23: 0
RxWr Ptr Lower
10-bit upper address pointer
Write:
Don’t care.
Read:
This pointer = ASR[31..24].
24-bit lower address pointer.
This pointer contains the current RX write address. This register is incremented with the actual
amount of bytes written.
Legend:
[1]
The global system reset caused by the SRST-bit in the GRR-register results in the following actions:
- Initiated by writing a ‘1”, gives ‘0’ on read-back when the reset was successful.
- No need to write a ‘0’ to remove the reset.
- Unconditionally, means no need to check/disable something in order for this reset-function to correctly execute.
- Could of course lead to data-corruption coming/going from/to the reset core.
- Resets the complete core (all logic, buffers & register values)
- Behaviour is similar to a power-up. {Note that the above actions require that the HRESET signal is fed back
inverted to HRESETn, and the CRESET signal is fed back inverted to CRESETn}
- The Coding Layer is not reset.
[2]
The FAR register supports the CCSDS/ECSS standard frame lengths (1024 octets), requiring an 8 bit CAC field
instead of the 6 bits specified for PSS. The two most significant bits of the CAC will thus spill over into
the "LEGAL/ILLEGAL" FRAME QUALIFIER field, Bit [26:25]. This is only the case when the PSS bit is set to '0'.
[3]
Only inputs 0 through 3 are implemented.
[4]
The channel reset caused by the CRST-bit in the COR-register results in the following actions:
- Initiated by writing a ‘1”, gives ‘0’ on read-back when the reset was successful.
- No need to write a ‘0’ to remove the reset.
- All other bit’s in the COR are neglected (not looked at) when the CRST-bit is set during a write, meaning that
the value of these bits has no impact on the register-value after the reset.
- Could of course lead to data-corruption coming/going from/to the reset channel.
- Resets the complete channel (all logic, buffers & register values)
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- Except the ASR-register of that channel which remains it’s value.
- All read- and write-pointers are automatically re-initialized and point to the start of the ASR-address.
- All registers of the channel (except the ones described above) get their power-up value.
- This reset shall not cause any spurious interrupts.
{Note that the above actions require that the CRESET signal is fed back inverted to CRESETn}
[5]
These bits are sticky bits which means that they remain present until the register is read and
that they are cleared automatically by reading the register.
[6]
The value of the pointers depends on the content of the corresponding Address Space Register (ASR).
During a system reset, a channel reset or a change of the ASR register, the pointers are recalculated
based on the values in the ASR register.
The software has to take care (when programming the ASR register) that the pointers never have to cross a
16MByte boundary (because this would cause an overflow of the 24-bit pointers).
It is not possible to write an out of range value to the RRP register. Such access will be ignored with an HERROR.
[7]
An AMBA AHB ERROR response is generated if a write access is attempted to a register without any writeable bits.
[8]
The channel reset caused by a write to the ASR-register results in the following actions:
- Initiated by writing an updated value into the ASR-register.
- Could of course lead to data-corruption coming/going from/to the reset channel.
- Resets the complete channel (all logic & buffers) but not all register values, only the following:
- COR-register, TE & RE bits get their power-up value, other bits remain their value.
- STR-register, all bits get their power-up value
- Other registers remain their value
- Updates the ASR-register of that channel with the written value
- All read- and write-pointers are automatically re-initialized and point to the start of the ASR-address.
- This reset shall not cause any spurious interrupts
[9]
During a channel reset the register is temporarily unavailable and HRETRY response is generated if accessed.
[10] It is not possible to write an out of range value to the RRP register. Such access will be ignored without an error.
[11] The PSS bit usage is only supported if the gPSS generic is set on the TCC module. Fixed to 0.
8.9.1
Interrupt registers
The interrupt registers give complete freedom to the software, by providing means to mask interrupts,
clear interrupts, force interrupts and read interrupt status.
When an interrupt occurs the corresponding bit in the Pending Interrupt Register is set. The normal
sequence to initialize and handle a module interrupt is:
•
Set up the software interrupt-handler to accept an interrupt from the module.
•
Read the Pending Interrupt Register to clear any spurious interrupts.
•
Initialize the Interrupt Mask Register, unmasking each bit that should generate the module interrupt.
•
When an interrupt occurs, read the Pending Interrupt Status Register in the software interrupthandler to determine the causes of the interrupt.
•
Handle the interrupt, taking into account all causes of the interrupt.
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Clear the handled interrupt using Pending Interrupt Clear Register.
Masking interrupts: After reset, all interrupt bits are masked, since the Interrupt Mask Register is zero.
To enable generation of a module interrupt for an interrupt bit, set the corresponding bit in the Interrupt Mask Register.
Clearing interrupts: All bits of the Pending Interrupt Register are cleared when it is read or when the
Pending Interrupt Masked Register is read. Reading the Pending Interrupt Masked Register yields the
contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register.
Selected bits can be cleared by writing ones to the bits that shall be cleared to the Pending Interrupt
Clear Register.
Forcing interrupts: When the Pending Interrupt Register is written, the resulting value is the original
contents of the register logically OR-ed with the write data. This means that writing the register can
force (set) an interrupt bit, but never clear it.
Reading interrupt status: Reading the Pending Interrupt Status Register yields the same data as a read
of the Pending Interrupt Register, but without clearing the contents.
Reading interrupt status of unmasked bits: Reading the Pending Interrupt Masked Status Register
yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask
Register, but without clearing the contents.
The interrupt registers comprise the following:
•
Pending Interrupt Masked Status Register
[PIMSR]
R
•
Pending Interrupt Masked Register
[PIMR]
R
•
Pending Interrupt Status Register
[PISR]
R
•
Pending Interrupt Register
[PIR]
R/W
•
Interrupt Mask Register
[IMR]
R/W
•
Pending Interrupt Clear Register
[PICR]
W
Table 78. Interrupt registers
31
7
-
6:
5:
4:
3:
2:
1:
0:
6
5
4
3
2
1
0
CS
OV
RBF
CR
FAR
BLO
RFA
CS
OV
RBF
CR
FAR
BLO
RFA
CLTU stored
Input data overrun
Output buffer full
CLTU ready/aborted
FAR available
Bit Lock changed
RF Available Changed
All bits in all interrupt registers are reset to 0b after reset.
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8.11
Signal name
Type
Function
Active
Reset value
tcscid
Input, static
Spacecraft Identity
-
-
tcrfpos
Input, static
RF Available polarity
-
-
tchigh
Input, static
Bit Lock polarity
-
-
tcrise
Input, static
Rising clock edge
-
-
tcpseudo
Input, static
Pseudo-Derandomiser
-
-
tcmark
Input, static
NRZ-M decoder
-
-
tcrfa[0:7]
Input, async
RF Available for CLCW
-
-
tcactive[0:7]
Input, async
Active
-
-
tcclk[0:7]
Input, async
Bit clock
-
-
tcdata[0:7]
Input, async
Data
-
-
clcwout[0 ]
Output
CLCW output data 2
-
Logical 1
Timing
clk
clcwout[ 0]
tGRTC0
tGRTC0
Name
Parameter
Reference edge
Min
Max
Unit
tGRTC0
rising clk edge
0
40
ns
Note: The inputs are re-synchronized internally. The signals do not have to meet any setup or hold
requirements. Static signals should not change between resets.
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9
Telecommand Decoder - Hardware Commands
9.1
Overview
9.1.1
Concept
The Telecommand Decoder - Hardware Commands provides access to an output port via telecommands.
The decoder implements the following layers:
•
Application Layer:
•
•
•
Hardware command decoding and execution
Space Packet Protocol:
•
Packet Extraction
•
Path Recovery
Data Link - Protocol Sub-Layer:
•
•
Virtual Channel Reception:
•
•
•
Support for Command Link Control Word (CLCW)
•
•
•
All Frames Reception
Data Link - Synchronization and Channel Coding Sub-Layer:
•
Pseudo-Derandomization
•
BCH codeblock decoding
•
Start Sequence Search
Physical Layer:
•
Non-Return-to-Zero Level/Mark de-modulation (NRZ-L/M)
The Channel Coding Sub-Layer and the Physical Layer are shared with the Telecommand Decoder Software Commands, and are therefore not repeated here.
9.2
Operation
In the Application Layer and the Data Link - Protocol Sub-Layer, the information octets from the
Channel Coding Sub-Layer are decoded as follows.
9.2.1
All Frames Reception
The All Frames Reception function performs two procedures:
•
Frame Delimiting and Fill Removal Procedure; and
•
Frame Validation Check Procedure, in this order.
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The Frame Delimiting and Fill Removal Procedure is used to reconstitute Transfer Frames from the
data stream provided by the Channel Coding Sub-Layer and to remove any Fill Data transferred from
the Channel Coding Sub-Layer. The Frame Length field is checked to correspond to a fixed value as
listed below. The number of information octets is checked to be a fixed number 21.
The Fill Data is checked to match the 0x55 pattern, or the corresponding pseudo-randomized pattern
when pseudo-derandomization is enabled (pin configurable). Note that it is assumed that the Fill Data
is not pseudo-randomized at the transmitting end.
The Frame Validation Checks procedure performs the following checks:
•
Version Number is checked to be 0
•
Bypass Flag is checked to be 1
•
Control Command Flag is checked to be 0
•
Reserved Spare bits are checked to be 0
•
Spacecraft Identifier is compared with a pin configurable input value
•
Virtual Channel identifier is compared with a pin configurable input value
•
Frame Length field is checked to be a fixed value of 0000010011b (i.e. 20-1)
•
Frame Sequence Number is checked to be a fixed value of 0
•
The Frame Error Control Field is checked to match the recomputed CRC value
9.2.2
The Master Channel Demultiplexing is performed implicitly during the All Frames Reception procedure described above.
9.2.3
The Virtual Channel Demultiplexing is performed implicitly during the All Frames Reception procedure described above.
9.2.4
Virtual Channel Reception
The Virtual Channel Reception supports Command Link Control Word (CLCW) generation and transfer to the Telemetry Encoder, according to the following field description.
•
Control Word Type field is 0
•
CLCW Version Number field is 0
•
Status Field is 0
•
COP in Effect field is 1
•
Virtual Channel Identification is taken from pin configurable input value
•
Reserved Spare field is 0
•
No RF Available Flag is 0, but is overwritten by the Telemetry Encoder
•
No Bit Lock Flag is 0, but is overwritten by the Telemetry Encoder
•
Lockout Flag is 1
•
Wait Flag is 0
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•
Retransmit Flag is 0
•
FARM-B Counter is taken from the to least significant bits of a reception counter
•
Reserved Spare field is 0
•
Report Value field is 0
9.2.5
The Virtual Channel Packet Extraction function extracts the Space Packet from the Frame Data Unit
on the Virtual Channel, received from the Virtual Channel Reception function.
No blocking of Space Packets is permitted.
The Packet Version Number is checked to be 000, before delivered to the next function, else the Space
Packet is discarded.
9.2.6
Path Recovery
The Path Recovery function receives and demultiplexes Space Packets received from the underlying
subnetwork. The Path Recovery function receives Space Packets from the underlying subnetwork and
demultiplex, if necessary, the received Space Packets on the basis of the Path Identifier of each Space
Packet.
The Path Identifier is derived directly from the Application Identifier (APID) of the Space Packet,
which is checked to be 00000000000, else the Space Packet is discarded.
Since the application layer uses the Octet String Service, the received Space Packets are delivered to
the user through the Packet Extraction function described hereafter.
9.2.7
Packet Extraction
The Packet Extraction function extracts service data units from Space Packets. The Packet Extraction
function extracts Octet Strings by stripping the Packet Primary Header, and the Packet Error Control
field.
The following checks are performed before the Octet Strings (i.e. User Data Field) is forwarded to the
Application Layer, else it is discarded:
•
Packet Version field is 000b
•
Packet Type is 1b
•
Secondary Header Flagis 0b
•
Application Process Id is 00000000000b
•
Sequence Flagsare 11b
•
Packet Data Length is 0000000000000110b
The Packet Extraction Function does not check the continuity of the Packet Sequence Count, since
Packet Name is used.
The Packet Extraction function verifies the correctness of the Packet Error Control field to match the
recomputed CRC value (calculated over the complete Space Packet), if incorrect the Space Packet is
not forwarded to the Application Layer, being discarded.
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9.2.8
Application Layer
The Application Layer interprets only Transfer Frames that have successfully passed the Data Link
Layer and Space Packet Protocol checks as described above.
The Application Layer interprets the Octet Strings (i.e. User Data Field) of the Packet Data Field.
The User Data Field consists of 5 octets comprising the hardware command, as defined in the bit
order hereafter (MSB of first octet corresponds to OUTPUT(0), LSB of last octet corresponds to
PULSE(7):
•
OUTPUT(0 to 31) (32 bits in total)
•
PULSE(0 to 7) (8 bits in total)
Before a hardware command is executed, the following is checked that:
•
no hardware command is ongoing
The OUTPUT bits 0 to 31 correspond to the tcgpio[] bits 0 to 31.
The PULSE field has three interpretations: 0 to clear bits, 255 to set bits, 1 to 254 to generate pulses
on bits:
•
When PULSE field is 0, the corresponding bits that are not set in the OUTPUT field are cleared
on the tcgpio outputs (AND function).
•
When PULSE field is 255, the corresponding bits that are set in the OUTPUT field are set on the
tcgpio outputs (OR function).
•
When PULSE field is in the range 1 to 254, the corresponding bits that are set in the OUTPUT
field are set on the tcgpio outputs for a duration of PULSE * 8192 system clock cycles, after
which they are cleared again.
The tcgpio[0:31] outputs are cleared to logical 0 at reset.
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Telecommand Transfer Frame format - Hardware Commands
The telecommand Transfer Frame for Hardware Commands has the following structures.
Transfer Frame
Transfer Frame
Primary Header
Frame Error
Control Field
Space Packet
Packet Primary Header
(FECF)
Packet Data Field
User Data Field
Packet Error Control
Hardware Command
0:39
40:87
88:127
128:143
144:159
5 octets
6 octets
5 octets
2 octets
2 octets
20 octets
Table 81. Telecommand Transfer Frame format
Version
Bypass
Control
Reserved
S/C
Virtual
Frame
Frame
Flag
Command
Spare
Id
Channel
Length
Sequence
Flag
Id
Number
00b
1b
0b
00b
PIN
PIN
0000010011b
00000000b
0:1
2
3
4:5
6:15
16:21
22:31
32:39
2 bits
1 bit
1 bit
2 bits
10 bits
6 bits
10 bits
8 bits
2 octets
2 octets
1 octet
Table 82. Telecommand Transfer Frame Primary Header format
Space Packet
Packet Primary Header
Packet
Packet Identification
Version Type Secondary
Application
Number
Header Flag
Process Id
Packet Data Field
Packet Sequence Control
Sequence
Flags
Packet
Name
Packet
User
Packet
Data
Data
Error
Length
Field
Control
Hardware Command
CRC
88:127
128:143
000b
1b
0b
00000000000b
11b
Don’t care 000616
40:42
43
44
45:55
56:57
58:71
72:87
3 bits
1 bit
1 bit
11 bits
2 bits
14 bits
16 bits
6 octets
40 bits
16 bits
5 octets
2 octets
Table 83. CCSDS Space Packet format
Hardware Command
OUTPUT (0:31)
PULSE (0:7)
88:119
120:127
32 bits
8 bits
4 octets
1 octet
Table 84. Hardware Command format
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9.4
82
9.5
Signal name
Type
Function
Active
Reset value
tcgpio[0:31]
Output
Hardware command output
Logical 1
Logical 0
tcscid[0:9]
Input, static
Telecommand Spacecraft Identifier
-
-
tcvcid[0:5]
Input, static
Telecommand Virtual Channel Identifier
.
.
clcwout[1 ]
Output
CLCW output data
-
Logical 1
Timing
clk
tcgpio[ ] , clcwout[1]
tGRTCHW0
tGRTCHW0
Name
Parameter
Reference edge
Min
Max
Unit
tGRTCHW0
rising clk edge
0
40
ns
Note: The inputs are re-synchronized internally. The signals do not have to meet any setup or hold
requirements. Static signals should not change between resets.
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10
SpaceWire Interface with RMAP target
10.1
Overview
The SpaceWire core provides an interface between the AHB bus and a SpaceWire network. It implements the SpaceWire standard (ECSS-E-50-12A) with the protocol identification extension (ECSS-E50-11).The Remote Memory Access Protocol (RMAP) target implements the ECSS standard (ECSSE-50-11).
TXCLK
D(1:0)
TRANSMITTER
S(1:0)
LINKINTERFACE
FSM
SEND
FSM
TRANSMITTER
FSM
RMAP
TRANSMITTER
TRANSMITTER
DMA ENGINE
AHB
MASTER INTERFACE
RECEIVER
DMA ENGINE
D0
S0
RXCLK RECEIVER0
RXCLK
RECOVERY
RMAP
RECEIVER
RECEIVER
AHB FIFO
RXCLK RECEIVER1
RXCLK
RECOVERY
N-CHAR
FIFO
RECEIVER DATA
PARALLELIZATION
D1
S1
10.2
Operation
10.2.1 Overview
The main sub-blocks of the core are the link-interface, the RMAP target and the AMBA interface. A
block diagram of the internal structure can be found in figure 19.
The link interface consists of the receiver, transmitter and the link interface FSM. They handle communication on the SpaceWire network. The AMBA interface consists of the DMA engines, the AHB
master interface and the APB interface. The link interface provides FIFO interfaces to the DMA
engines. These FIFOs are used to transfer N-Chars between the AMBA and SpaceWire domains during reception and transmission.
The RMAP target handles incoming packets which are determined to be RMAP commands instead of
the receiver DMA engine. The RMAP command is decoded and if it is valid, the operation is performed on the AHB bus. If a reply was requested it is automatically transmitted back to the source by
the RMAP transmitter.
10.2.2 Protocol support
The core only accepts packets with a destination address corresponding to the one set in the node
address register. Packets with address mismatch will be silently discarded. The node address register
is initialized to the default address 254 during reset.
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RMAP (Protocol ID = 0x01) commands are handled. All RMAP commands are processed, executed
and replied in hardware. All RMAP replies received are still stored to the DMA channel. Figure 20
shows a packet with a normal protocol identifier.
Addr ProtID D0
D1
D2
D3
..
Dn-2 Dn-1 EOP
Figure 20. The SpaceWire packet with protocol ID that is expected by the GRSPW.
10.3
Link interface
The link interface handles the communication on the SpaceWire network and consists of a transmitter,
receiver, a FSM and FIFO interfaces. An overview of the architecture is found in figure 19.
10.3.1 Link interface FSM
The FSM controls the link interface (a more detailed description is found in the SpaceWire standard).
The low-level protocol handling (the signal and character level of the SpaceWire standard) is handled
by the transmitter and receiver while the FSM in the host domain handles the exchange level.
When the link interface is in the connecting- or run-state it is allowed to send FCTs. FCTs are sent
automatically by the link interface when possible. This is done based on the maximum value of 56 for
the outstanding credit counter and the currently free space in the receiver N-Char FIFO. FCTs are sent
as long as the outstanding counter is less than or equal to 48 and there are at least 8 more empty FIFO
entries than the counter value.
N-Chars are sent in the run-state when they are available from the transmitter FIFO and there are
credits available. NULLs are sent when no other character transmission is requested or the FSM is in
a state where no other transmissions are allowed.
The credit counter (incoming credits) is automatically increased when FCTs are received and
decreased when N-Chars are transmitted. Received N-Chars are stored to the receiver N-Char FIFO
for further handling by the DMA interface.
10.3.2 Transmitter
The state of the FSM, credit counters, requests from the time-interface and requests from the DMAinterface are used to decide the next character to be transmitted. The type of character and the character itself (for N-Chars) to be transmitted are presented to the low-level transmitter which is located in
a separate clock-domain. This is done because one usually wants to run the SpaceWire link on a different frequency than the host system clock.
The transmitter logic in the host clock domain decides what character to send next and sets the proper
control signal and presents any needed character to the low-level transmitter as shown in figure 21.
The transmitter sends the requested characters and generates parity and control bits as needed. If no
requests are made from the host domain, NULLs are sent as long as the transmitter is enabled. Most of
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the signal and character levels of the SpaceWire standard is handled in the transmitter. External LVDS
drivers are needed for the data and strobe signals.
D
S
Transmitter
Transmitter Clock Domain
Send Time-code
Send FCT
Send NChar
Time-code[7:0]
NChar[8:0]
Host Clock Domain
Figure 21. Schematic of the link interface transmitter.
A transmission FSM reads N-Chars for transmission from the transmitter FIFO. It is given packet
lengths from the DMA interface and appends EOPs/EEPs and RMAP CRC values if requested. When
it is finished with a packet the DMA interface is notified and a new packet length value is given.
10.3.3 Receiver
The receiver detects connections from other nodes and receives characters as a bit stream on the data
and strobe signals. It is also located in a separate clock domain which runs on a clock generated from
the received data and strobe signals.
The receiver is activated as soon as the link interface leaves the error reset state. Then after a NULL is
received it can start receiving any characters. It detects parity, escape and credit errors which causes
the link interface to enter the error reset state. Disconnections are handled in the link interface part in
the system clock domain because no receiver clock is available when disconnected.
Received Characters are flagged to the host domain and the data is presented in parallel form. The
interface to the host domain is shown in figure 22. L-Chars are the handled automatically by the host
domain link interface part while all N-Chars are stored in the receiver FIFO for further handling. If
two or more consecutive EOPs/EEPs are received all but the first are discarded.
There are no signals going directly from the transmitter clock domain to the receiver clock domain
and vice versa. All the synchronization is done to the system clock.
D
Receiver
S
Receiver Clock Domain
Got Time-code
Got FCT
Got EOP
Got EEP
Got NChar
Time-code[7:0]
NChar[7:0]
Host Clock Domain
Figure 22. Schematic of the link interface receiver.
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86
RMAP
The Remote Memory Access Protocol (RMAP) is used to implement access to resources in the node
via the SpaceWire Link. Some common operations are reading and writing to memory, registers and
FIFOs. The core has an optional hardware RMAP target which is enabled with a VHDL generic. This
section describes the basics of the RMAP protocol and the target implementation.
10.4.1 Fundamentals of the protocol
RMAP is a protocol which is designed to provide remote access via a SpaceWire network to memory
mapped resources on a SpaceWire node. It has been assigned protocol ID 0x01. It provides three operations write, read and read-modify-write. These operations are posted operations which means that a
source does not wait for an acknowledge or reply. It also implies that any number of operations can be
outstanding at any time and that no timeout mechanism is implemented in the protocol. Time-outs
must be implemented in the user application which sends the commands. Data payloads of up to 16
Mb - 1 is supported in the protocol. A destination can be requested to send replies and to verify data
before executing an operation. A complete description of the protocol is found in the RMAP standard.
10.4.2 Implementation
The core includes a taget for RMAP commands which processes all incoming packets with protocol
ID = 0x01 and type field (bit 7 and 6 of the 3rd byte in the packet) equal to 01b. When such a packet
is detected it is not stored to the DMA channel, instead it is passed to the RMAP receiver.
The core implements all three commands defined in the standard with some restrictions. The implementation is based on draft F of the RMAP standard (the only exception being that error code 12 is
not implemented). Support is only provided for 32-bit big-endian systems. This means that the first
byte received is the msb in a word. The command handler will not receive RMAP packets using the
extended protocol ID which are always dumped to the DMA channel.
The RMAP receiver processes commands. If they are correct and accepted the operation is performed
on the AHB bus and a reply is formatted. If an acknowledge is requested the RMAP transmitter automatically send the reply. RMAP transmissions have priority over DMA channel transmissions.
Packets with a mismatching destination logical address are never passed to the RMAP target. There is
a user accessible destination key register which is compared to destination key field in incoming
packets. If there is a mismatch and a reply has been requested the error code in the reply is set to 3.
Replies are sent if and only if the ack field is set to ‘1’.
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Detection of all error codes except code 12 is supported. When a failure occurs during a bus access the
error code is set to 1 (General Error). There is predetermined order in which error-codes are set in the
case of multiple errors in the core. It is shown in table 87.
Table 87. The order of error detection in case of multiple errors in the GRSPW. The error detected first has number 1.
Detection Order
Error Code
Error
1
2
Unused RMAP packet type or command code
2
3
Invalid destination key
3
9
Verify buffer overrun
4
11
RMW data length error
5
10
Authorization failure
6*
1
General Error (AHB errors during non-verified writes)
7
5/7
Early EOP / EEP (if early)
8
4
Invalid Data CRC
9
1
General Error (AHB errors during verified writes or RMW)
10
7
EEP
11
6
Cargo Too Large
*The AHB error is not guaranteed to be detected before Early EOP/EEP or Invalid Data CRC. For very long accesses
the AHB error detection might be delayed causing the other two errors to appear first.
Read accesses are performed on the fly, that is they are not stored in a temporary buffer before transmission. This means that the error code 1 will never be seen in a read reply since the header has
already been sent when the data is read. If the AHB error occurs the packet will be truncated and
ended with an EEP.
Errors up to and including Invalid Data CRC (number 8) are checked before verified commands. The
other errors do not prevent verified operations from being performed.
The details of the support for the different commands are now presented. All defined commands
which are received but have an option set which is not supported in this specific implementation will
not be executed and a possible reply is sent with error code 10.
10.4.3 Write commands
The write commands are divided into two subcategories when examining their capabilities: verified
writes and non-verified writes. Verified writes have a length restriction of 4 B and the address must be
aligned to the size. That is 1 B writes can be done to any address, 2 B must be halfword aligned, 3 B
are not allowed and 4 B writes must be word aligned. Since there will always be only one AHB operation performed for each RMAP verified write command the incrementing address bit can be set to
any value.
Non-verified writes have no restrictions when the incrementing bit is set to 1. If it is set to 0 the number of bytes must be a multiple of 4 and the address word aligned. There is no guarantee how many
words will be written when early EOP/EEP is detected for non-verified writes.
10.4.4 Read commands
Read commands are performed on the fly when the reply is sent. Thus if an AHB error occurs the
packet will be truncated and ended with an EEP. There are no restrictions for incrementing reads but
non-incrementing reads have the same alignment restrictions as non-verified writes. Note that the
“Authorization failure” error code will be sent in the reply if a violation was detected even if the
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length field was zero. Also note that no data is sent in the reply if an error was detected i.e. if the status
field is non-zero.
10.4.5 RMW commands
All read-modify-write sizes are supported except 6 which would have caused 3 B being read and written on the bus. The RMW bus accesses have the same restrictions as the verified writes. As in the verified write case, the incrementing bit can be set to any value since only one AHB bus operation will be
performed for each RMW command. Cargo too large is detected after the bus accesses so this error
will not prevent the operation from being performed. No data is sent in a reply if an error is detected
i.e. the status field is non-zero.
10.4.6 Control
The RMAP command handler mostly runs in the background without any external intervention, but
there are a few control possibilities.
There is an enable bit in the control register of the core which can be used to completely disable the
RMAP command handler. When it is set to ‘0’ no RMAP packets will be handled in hardware, instead
they are all stored to the DMA channel.
There is a possibility that RMAP commands will not be performed in the order they arrive. This can
happen if a read arrives before one or more writes. Since the command handler stores replies in a
buffer with more than one entry several commands can be processed even if no replies are sent. Data
for read replies is read when the reply is sent and thus writes coming after the read might have been
performed already if there was congestion in the transmitter. To avoid this the RMAP buffer disable
bit can be set to force the command handler to only use one buffer which prevents this situation.
The last control option for the command handler is the possibility to set the destination key which is
found in a separate register.
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Table 88. GRSPW hardware RMAP handling of different packet type and command fields.
Bit 7
Bit 6
Command
Action
Reserved
Verify
data
Command Write / before
/ Response Read
write
Acknow- Increment
ledge
Address
0
0
-
-
-
-
Response
Stored to DMA-channel.
0
1
0
0
0
1
0
0
0
0
Not used
Does nothing. No reply is sent.
0
1
Not used
0
1
0
0
1
0
Read single
address
Executed normally. Address has
to be word aligned and data size
a multiple of four. Reply is sent.
If alignment restrictions are violated error code is set to 10.
0
1
0
0
1
1
Read incrementing
address.
Executed normally. No restrictions. Reply is sent.
0
1
0
1
0
0
Not used
0
1
0
1
0
1
Not used
0
1
0
1
1
0
Not used
Does nothing. Reply is sent with
error code 2.
0
1
0
1
1
1
Read-Modify-Write
incrementing address
Executed normally. If length is
not one of the allowed rmw values nothing is done and error
code is set to 11. If the length
was correct, alignment restrictions are checked next. 1 byte
can be rmw to any address. 2
bytes must be halfword aligned.
3 bytes are not allowed. 4 bytes
must be word aligned. If these
restrictions are violated nothing
is done and error code is set to
10. If an AHB error occurs error
code is set to 1. Reply is sent.
0
1
1
0
0
0
Write, single-address,
do not verify
before writing, no
acknowledge
a multiple of four. If alignment is
violated nothing is done. No
reply is sent.
0
1
1
0
0
1
Write, incrementing
address, do
not verify
before writing, no
acknowledge
Executed normally. No restrictions. No reply is sent.
Bit 5
Bit 4
Bit 3
Bit 2
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Table 88. GRSPW hardware RMAP handling of different packet type and command fields.
Bit 7
Bit 6
Command
Action
Reserved
Verify
data
Command Write / before
/ Response Read
write
Acknow- Increment
ledge
Address
0
1
1
0
1
0
Write, single-address,
do not verify
before writing, send
acknowledge
a multiple of four. If alignment is
violated nothing is done and
error code is set to 10. If an AHB
error occurs error code is set to 1.
Reply is sent.
0
1
1
0
1
1
Write, incrementing
address, do
not verify
before writing, send
acknowledge
Executed normally. No restrictions. If AHB error occurs error
code is set to 1. Reply is sent.
0
1
1
1
0
0
Write, single
address, verify before
writing, no
acknowledge
Executed normally. Length must
be 4 or less. Otherwise nothing is
done. Same alignment restrictions apply as for rmw. No reply
is sent.
0
1
1
1
0
1
Write, incrementing
writing, no
acknowledge
done. Same alignment restrictions apply as for rmw. If they
are violated nothing is done. No
reply is sent.
0
1
1
1
1
0
Write, single
writing, send
acknowledge
done and error code is set to 9.
Same alignment restrictions
apply as for rmw. If they are violated nothing is done and error
code is set to 10. If an AHB error
occurs error code is set to 1.
Reply is sent.
0
1
1
1
1
1
Write, incrementing
writing, send
acknowledge
done and error code is set to 9.
Same alignment restrictions
apply as for rmw. If they are violated nothing is done and error
code is set to 10. If an AHB error
occurs error code is set to 1.
Reply is sent.
1
0
-
-
-
-
Unused
1
1
-
-
-
-
Unused
Bit 5
Bit 4
Bit 3
Bit 2
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91
Signal name
Type
Function
Active
Reset value
spw_clk
Input
Transmitter default run-state clock
Rising edge
-
spw_rxd
Input, LVTTL
Data input, positive
High
-
spw_rxdn
Input, LVDS
Data input, negative {spare}
Low
-
spw_rxs
Input, LVTTL
Strobe input, positive
High
-
spw_rxsn
Input, LVDS
Strobe input, negative {spare}
Low
-
spw_txd
Output, LVTTL
Data output, positive
High
Logical 0
spw_txdn
Output, LVDS
Data output, negative {spare}
Low
Logical 1
spw_txs
Output, LVTTL
Strobe output, positive
High
Logical 0
spw_txsn
Output, LVDS
Strobe output, negative {spare}
Low
Logical 1
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Timing
tSPW0
spw_clk
spw_txd, spw_txdn
spw_txs, spw_txsn
tSPW1
spw_rxd, spw_rxdn
spw_rxs, spw_rxsn
tSPW2
tSPW4
tSPW1
tSPW3
tSPW4
spw_txd, spw_txdn
spw_txs, spw_txsn
tSPW4
tSPW5
tSPW5
tSPW6
spw_rxd, spw_rxdn
tSPW5
spw_rxs, spw_rxsn
tSPW6
tSPW7
spw_txd, spw_txdn
spw_txs, spw_txsn
Name
Parameter
Reference edge
Min
Max
Unit
tSPW0
transmit clock period
-
100
100
ns
tSPW1
rising spw_clk edge
0
25
ns
tSPW2
input to clock hold
-
-
-
not applicable
tSPW3
-
-
-
not applicable
tSPW4
output data bit period
-
-
-
tSPW0 -5
tSPW0 +5 ns
clk periods
tSPW5
input data bit period
-
100
100
ns
tSPW6
data & strobe edge separation
-
10
-
ns
tSPW7
data & strobe output skew
-
-
5
ns
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11
Fault Tolerant PROM/SRAM Memory Interface
11.1
Overview
The fault tolerant 32-bit PROM/SRAM memory interface uses a common 32-bit memory bus to interface PROM, SRAM and I/O devices. In addition it also provides an Error Detection And Correction
Unit (EDAC), correcting one and detecting two errors. Configuration of the memory controller functions is performed through the APB bus interface. Note that control signals for I/O devices, and bus
error and ready are not supported.
A
AHB
SRO.ROMSN
SRO.OEN
SRO.WRITEN
D
CB
A
CS
OE
WE
PROM
CS
OE
WE
SRAM
D
CB
MEMORY
CONTROLLER
SRO.RAMSN
SRO.RAMOEN
SRO.RWEN[3:0]
A
D
CB
SRI.A[27:0]
SRI.D[31:0]
SRO.D[31:0]
CB[7:0]
AHB/APB
APB
Bridge
Figure 24. 32-bit FT PROM/SRAM/IO controller
11.2
Operation
The controller is configured through to decode three address ranges: PROM, SRAM and I/O area. By
default the PROM area is mapped into address range 0x0 - 0x00FFFFFF, the SRAM area is mapped
into address range 0x40000000 - 0x40FFFFFF, and the I/O area is mapped to 0x20000000 0x20FFFFFF.
One chip select is decoded for the I/O area, while SRAM and PROM can have up to 8 chip select signals. The controller generates both a common write-enable signal (WRITEN) as well as four bytewrite enable signals (WREN). If the SRAM uses a common write enable signal the controller can be
configured to perform read-modify-write cycles for byte and half-word write accesses. Number of
waitstates is separately configurable for the three address ranges.
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The configuration of the EDAC is done through a configuration register accessed from the APB bus.
During nominal operation, the EDAC checksum is generated and checked automatically. Single errors
are corrected without generating any indication of this condition in the bus response. If a multiple
error is detected, a two cycle error response is given on the AHB bus.
When EDAC is enabled, one extra latency cycle is generated during reads and subword writes.
The EDAC function can be enabled for SRAM and PROM area accesses, but not for I/O area
accesses. For the SRAM area, the EDAC functionality is only supported for accessing 32-bit wide
SRAM banks. For the PROM area, the EDAC functionality is supported for accessing 32-bit wide
PROM banks. EDAC enabled 32-bit wide accesses to SRAM and PROM areas generate a read-modify-write access.
The equations below show how the EDAC checkbits are generated:
CB0
CB1
CB2
CB3
CB4
CB5
CB6
=
=
=
=
=
=
=
D0
D0
D0
D0
D2
D8
D0
^
^
^
^
^
^
^
D4
D1
D3
D1
D3
D9
D1
^
^
^
^
^
^
^
D6 ^ D7 ^
D2 ^ D4 ^
D4 ^ D7 ^
D5 ^ D6 ^
D4 ^ D5 ^
D10 ^ D11
D2 ^ D3 ^
D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31
D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28
D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31
D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29
D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31
^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
11.2.1 Access errors
The active low Bus Exception signal (BEXCN) can be used to signal access errors. It is enabled by
setting the BEXCEN bit in MCFG1 and is active for all types of accesses to all areas (PROM, SRAM
and I/O). The BEXCN signal is sampled on the same cycle as read data is sampled. For writes it is
sampled on the last rising edge before writen/rwen is de-asserted (writen and rwen are clocked on the
falling edge). When a bus exception is detected an error response will be generated for the access.
data
lead-out
clk
address
A1
romsn/iosn/ramsn
oen
data
D1
bexcn
Figure 25. Read cycle with BEXCN.
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lead-in
data1
data2
data3 lead-out
clk
address
A1
romsn/iosn/ramsn
rwen
data
D1
bexcn
Figure 26. Write cycle with BEXCN.
11.2.2 Using bus ready signalling
The Bus Ready (BRDYN) signal can be used to add waitstates to I/O-area accesses, covering the
complete memory area and both read and write accesses. It is enabled by setting the Bus Ready
Enable (BRDYEN) bit in the MCFG1 register. An access will have at least the amount of waitstates
set, but will be further stretched until BRDYN is asserted. Additional waitstates can thus be inserted
after the pre-set number of waitstates by de-asserting the BRDYN signal. BRDYN should be asserted
in the cycle preceding the last one. It is recommended that BRDYN remains asserted until the IOSN
signal is de-asserted, to ensure that the access has been properly completed and avoiding the system to
stall. Read accesses will have the same timing as when EDAC is enabled while write accesses will
have the timing as for single accesses even if bursts are performed.
lead-in
wait
data
data
clk
address
A1
iosn
oen
data
D1
brdyn
first
sample
Figure 27. I/O READ cycle, programmed with 1 wait state, and with an extra data cycle added with BRDYN.
11.3
PROM/SRAM/IO waveforms
The internal and external waveforms of the interface are presented in the figures hereafter.
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data1
lead-out
data1 lead-out
clk
address
A1
A2
romsn
ramsn
oen
data
cb
haddr
htrans
D1
D2
CB1
CB2
A1
A2
A3
10
10
00
hready
hrdata
D1
D2
Figure 28. PROM/SRAM non-consecutive read cyclecs.
data1
data1
data1
data1
lead-out
clk
address
A1
A3
A2
A4
romsn
ramsn
oen
data
cb
haddr
htrans
A1
D1
D2
D3
D4
CB1
CB2
CB3
CB4
A3
A4
A2
A5
00
11
10
hready
hrdata
D1
D2
D3
D4
Figure 29. 32-bit PROM/SRAM sequential read access with 0 wait-states and EDAC disabled.
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data1
unused lead-out data1
unused lead-out
clk
address
A1
A2
romsn
ramsn
oen
data
cb
haddr
htrans
D1
D2
CB1
CB2
A1
A2
A3
10
10
00
hready
hrdata
D1
D2
Figure 30. 32-bit PROM/SRAM non-sequential read access with 0 wait-states and EDAC enabled.
data1
data1
data1
data1
unused
lead-out
clk
address
A1
A3
A2
A4
romsn
ramsn
oen
data
cb
haddr
htrans
A1
10
D1
D2
D3
D4
CB1
CB2
CB3
CB4
A3
A2
A5
A4
00
11
hready
hrdata
D1
D2
D3
D4
Figure 31. 32-bit PROM/SRAM sequential read access with 0 wait-states and EDAC enabled..
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lead-in
data1
data2
lead-out lead-in
data1
data2
lead-out
clk
address
A1
A2
romsn
ramsn
writen
data
cb
haddr
htrans
D1
D2
CB1
CB2
A1
A2
A3
10
10
00
hready
hwdata
D1
D2
Figure 32. 32-bit PROM/SRAM non-sequential write access with 0 wait-states and EDAC disabled.
lead-in
data1
data2
data1
data2
data1
data2 lead-out
clk
address
A2
A1
A3
romsn
ramsn
writen
data
cb
haddr
htrans
A1
D1
D2
D3
CB1
CB2
CB3
A2
10
A3
A4
11
00
hready
hwdata
D1
D2
D3
Figure 33. 32-bit PROM/SRAM sequential write access with 0 wait-states and EDAC disabled.
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If waitstates are configured, one extra data cycle will be inserted for each waitstate in both read and
write cycles. The timing for write accesses is not affected when EDAC is enabled while one extra
latency cycle is introduced for single access reads and at the beginning of read bursts.
clk
address
A1
romsn
ramsn
writen
oen
data
D1
cb
D1/M1
CM1
CB1
haddr
htrans
A1
A2
10
00
hready
hwdata
M1
Figure 34. 32-bit PROM/SRAM rmw access with 0 wait-states and EDAC disabled.
Read-Modify-Write (RMW) accesses will have an additional waitstate inserted to accommodate
decoding when EDAC is enabled.
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I/O accesses are similar to PROM and SRAM accesses but a lead-in and lead-out cycle is always
present.
lead-in
data1
data2
data3 lead-out
clk
address
A1
iosn
writen
data
haddr
htrans
D1
A1
A2
10
00
hready
hwdata
D1
Figure 35. I/O write access with 0 wait-states.
lead-in
data
lead-out
clk
address
A1
iosn
oen
data
haddr
htrans
D1
A1
A2
10
00
hready
hrdata
D1
Figure 36. I/O read access with 0 wait-states
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11.4
101
Registers
Table 91. FT
PROM/SRAM/IO controller registers
APB Address offset
Register
0x0
Memory configuration register 1
0x4
0x8
Table 92. Memory configuration register 1.
31
27 26 25 24 23
RESERVED
BR BE
20 19 18 17
IOWS
14 13 12 11 10
ROMBSZ
EBSZ RW
9
8
7
RBW
4
3
RESERVED
0
ROMWS
31: 27
RESERVED
26
Bus ready enable (BR) - Enables the bus ready signal (BRDYN) for I/O-area.
25
Bus exception enable (BE) - Enables the bus exception signal (BEXCEN) for PROM, SRAM and I/
O areas
24
RESERVED
23: 20
I/O wait states (IOWS) - Sets the number of waitstates for accesses to the I/O-area.
19: 18
RESERVED
17: 14
ROM bank size (ROMBSZ) - Sets the PROM bank size.
13: 12
EDAC bank size (EBSZ) - [Not implemented]
11
ROM write enable (RW) - Enables writes to the PROM memory area. When disabled, writes to the
PROM area will generate an ERROR response on the AHB bus.
10
RESERVED
9: 8
ROM data bus width (RBW) - Sets the PROM data bus width. “00” = 8-bit, “10” = 32-bit, others
reserved. [Only 32-bit supported]
7: 4
RESERVED
3: 0
ROM waitstates (ROMWS) - Sets the number of waitstates for accesses to the PROM area. Reset to
all-ones.
31
13 12
RESERVED
9
8
7
RAMBSZ
6
RW
5
4
3
2
RESERVED
31: 13
RESERVED
12: 9
RAM bank size (RAMBSZ) - Sets the number of waitstates for accesses to the RAM area.
8: 7
RESERVED
6
Read-modify-write enable (RW) - Enables read-modify-write cycles for write accesses.
5: 2
RESERVED
1: 0
RAM waitstates (RAMW) - Sets the number of waitstates for accesses to the RAM area.
1
0
RAMW
31
20 19
RESERVED
31: 20
12 11 10
SEC
9
8
7
WB RB SE PE
6
5
4
3
2
1
0
TCB
RESERVED
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19: 12
11.5
Single error counter.(SEC) - This field increments each time a single error is detected until the maximum value that can be stored in the field is reached. Each bit can be reset by writing a one to it.
11
Write bypass (WB) - Enables EDAC write bypass. When enabled the TCB field will be used as
checkbits in all write operations.
10
Read bypass (RB) - Enables EDAC read bypass. When enabled checkbits read from memory in all
read operations will be stored in the TCB field.
9
SRAM EDAC enable (SE) - Enables EDAC for the SRAM area.
8
PROM EDAC enable (PE) - Enables EDAC for the PROM area. Reset value is taken from the input
signal sri.edac.
7: 0
Test checkbits (TCB) - Used as checkbits in write operations when WB is activated and checkbits
from read operations are stored here when RB is activated.
Signal name
Type
Function
Active
Reset value
address[27:0]
Output
Memory address
High
Undefined
data[31:0]
Input/Output
Memory data
High
Tri-state
cb[7:0]
Input/Output
Check bits
High
Tri-state
ramsn[7:0]
Output
SRAM chip select
Low
Logical 1
ramoen[7:0]
Output
SRAM output enable
Low
Logical 1
rwen[3:0]
Output,
SRAM write byte enable:
Low
Logical 1
Low
Logical 1
Low
Logical 1
rwen[0] corresponds to data[31:24],
rwen[3] corresponds to data[7:0].
Any rwen[ ] signal can be used for cb[ ].
ramben[3:0]
Output
SRAM read/write byte enable:
ramben[0] corresponds to data[31:24],
ramben[3] corresponds to data[7:0].
Any ramben[ ] signal can be used for cb[ ].
oen
Output
Output enable
writen
Output
Write strobe
Low
Logical 1
romsn[7:0]
Output
PROM chip select
Low
Logical 1
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103
Timing
clk
tFTSRCTRL0
address[]
tFTSRCTRL1
ramsn[], romsn[]
iosn
tFTSRCTRL1
tFTSRCTRL2
tFTSRCTRL2
rwen[], writen
tFTSRCTRL3, tFTSRCTRL4
data[], cb[]
(output)
tFTSRCTRL5
tFTSRCTRL3
clk
address[]
ramsn[], romsn[]
iosn
tFTSRCTRL6
ramoen[]
ramben[], oen, read
tFTSRCTRL6
tFTSRCTRL7
tFTSRCTRL8
data[], cb[]
(input)
tFTSRCTRL10
tFTSRCTRL9
brdyn, bexcn
Name
Parameter
Reference edge
Min
Max
Unit
tFTSRCTRL0
address clock to output delay
rising clk edge
0
25
ns
tFTSRCTRL1
rising clk edge
0
25
ns
tFTSRCTRL2
rising clk edge
0
25
ns
tFTSRCTRL3
clock to data output delay
falling clk edge
2
25
ns
tFTSRCTRL4
clock to data non-tri-state delay
rising clk edge
0
25
ns
tFTSRCTRL5
clock to data tri-state delay
rising clk edge
2
25
ns
tFTSRCTRL6
rising clk edge
0
25
ns
tFTSRCTRL7
data input to clock setup
rising clk edge
7
-
ns
tFTSRCTRL8
data input from clock hold
rising clk edge
1
-
ns
tFTSRCTRL9
rising clk edge
7
-
ns
tFTSRCTRL10
input from clock hold
rising clk edge
1
-
ns
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12
On-chip Memory with EDAC Protection
12.1
Overview
The on-chip memory is accessed via an AMBA AHB slave interface. The two separate memories
implements 16 kBytes and 4 kBytes of data. Registers are accessed via an AMB APB interface.
The on-chip memory implements volatile memory that is protected by means of Error Detection And
Correction (EDAC). One error can be corrected and two errors can be detected, which is performed
by using a (32, 7) BCH code. Some of the optional features available are single error counter
(unused), diagnostic reads and writes and autoscrubbing (unused)(automatic correction of single
errors during reads). Configuration is performed via a configuration register.
Figure 38 shows a block diagram of the internals of the memory.
AHB Bus
AHB Slave
Interface
FTAHBRAM
data
Mux
AHB/APB
Bridge
error Configuration Register
Mux
Encoding
Config bits
TCB
cb
APB Bus
Decoding
Mux
data
cb
Syncram
12.2
Operation
The on-chip fault tolerant memory is accessed through an AMBA AHB slave interface.
Run-time configuration is done by writing to a configuration register accessed through an AMBA
APB interface.
The following can be configured during run-time: EDAC can be enabled and disabled. When it is disabled, reads and writes will behave as the standard memory. Read and write diagnostics can be controlled through separate bits. The single error counter can be reset.
If EDAC is disabled (EN bit in configuration register set to 0) write data is passed directly to the
memory area and read data will appear on the AHB bus immediately after it arrives from memory. If
EDAC is enabled write data is passed to an encoder which outputs a 7-bit checksum. The checksum is
stored together with the data in memory and the whole operation is performed without any added
waitstates. This applies to word stores (32-bit). If a byte or halfword store is performed, the whole
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word to which the byte or halfword belongs must first be read from memory (read - modify - write). A
new checksum is calculated when the new data is placed in the word and both data and checksum are
stored in memory. This is done with 1 - 2 additional waitstates compared to the non EDAC case.
Reads with EDAC disabled are performed with 0 or 1 waitstates while there could also be 2 waitstates
when EDAC is enabled. There is no difference between word and subword reads. Table 97 shows a
summary of the number of waitstates for the different operations with and without EDAC.
Table 97. Summary of the number of waitstates for the different operations for the memory.
Operation
Waitstates with EDAC Disabled
Waitstates with EDAC Enabled
Read
0-1
0-2
Word write
0
0
Subword write
0
1-2
If the pipeline registers are enabled, one extra waitstate should be added to the read and subword write
cases in Table 97.
When EDAC is used, the data is decoded the first cycle after it arrives from the memory and appears
on the bus the next cycle if no uncorrectable error is detected. The decoding is done by comparing the
stored checksum with a new one which is calculated from the stored data. This decoding is also done
during the read phase for a subword write. A so-called syndrome is generated from the comparison
between the checksum and it determines the number of errors that occured. One error is automatically
corrected and this situation is not visible on the bus. Two or more detected errors cannot be corrected
so the operation is aborted and the required two cycle error response is given on the AHB bus (see the
AMBA manual for more details). If no errors are detected data is passed through the decoder unaltered.
As mentioned earlier the memory provides read and write diagnostics when EDAC is enabled. When
write diagnostics are enabled, the calculated checksum is not stored in memory during the write
phase. Instead, the TCB field from the configuration register is used. In the same manner, if read diagnostics are enabled, the stored checksum from memory is stored in the TCB field during a read (and
also during a subword write). This way, the EDAC functionality can be tested during run-time. Note
that checkbits are stored in TCB during reads and subword writes even if a multiple error is detected.
A single error counter (SEC) field is present in the configuration register, and is incremented each
time a single databit error is encountered (reads or subword writes). The number of bits of this counter
is 8. It is accessed through the configuration register. Each counter bit can be reset to zero by writing a
one to it. The counter saturates at the value 28 - 1.
Autoscrubbing is an error handling feature which is enabled and cannot be controlled through the configuration register. If enabled, every single error encountered during a read results in the word being
written back with the error corrected and new checkbits generated. It is not visible externally except
for that it can generate an extra waitstate. This happens if the read is followed by an odd numbered
read in a burst sequence of reads or if a subword write follows. These situations are very rare during
normal operation so the total timing impact is negligible.
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106
Registers
Table 98. FTAHBRAM registers
APB Address offset
Register
0x0
Configuration Register
Table 99. Configuration Register
31
21
20
RESERVED
13 12
SEC
10
9
8
7
MEMSIZE WB RB EN
6
0
TCB
31
21
RESERVED. Always read as ‘000...0’.
20:
13
Single error counter (SEC): Incremented each time a single error is corrected (includes errors on
checkbits). Each bit can be set to zero by writing a one to it. (unused)
12:
10
Log2 of the current memory size
9
Write Bypass (WB): When set, the TCB field is stored as check bits when a write is performed to the
memory.
8
Read Bypass (RB) : When set during a read or subword write, the check bits loaded from memory
are stored in the TCB field.
7
EDAC Enable (EN): When set, the EDAC is used otherwise it is bypassed during read and write
operations.
6: 0
Test Check Bits (TCB) : Used as checkbits when the WB bit is set during writes and loaded with the
check bits during a read operation when the RB bit is set.
Any unused most significant bits are reserved. Always read as ‘000...0’.
All fields except TCB are initialised at reset. The EDAC is initally disabled (EN = 0), which also applies to diagnostics fiels (RB and WB are zero).
When available, the single error counter (SEC) field is cleared to zero.
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Status Registers
13.1
Overview
107
The status registers store information about AMBA AHB accesses triggering an error response. There
is a status register and a failing address register capturing the control and address signal values of a
failing AMBA bus transaction, or the occurence of a correctable error being signaled from a fault tolerant core.
13.2
Operation
13.2.1 Errors
The registers monitor AMBA AHB bus transactions and store the current HADDR, HWRITE,
HMASTER and HSIZE internally. The monitoring are always active after startup and reset until an
error response (HRESP = “01”) is detected. When the error is detected, the status and address register
contents are frozen and the New Error (NE) bit is set to one. At the same time an interrupt is generated, as described hereunder.
Note that many of the fault tolerant units containing EDAC signal an un-correctable error as an
AMBA error response, so that it can be detected by the processor as described above.
13.2.2 Correctable errors
Not only error responses on the AHB bus can be detected. Many of the fault tolerant units containing
EDAC have a correctable error signal which is asserted each time a single error is detected. When
such an error is detected, the effect will be the same as for an AHB error response. The only difference
is that the Correctable Error (CE) bit in the status register is set to one when a single error is detected.
When the CE bit is set the interrupt routine can acquire the address containing the single error from
the failing address register and correct it. When it is finished it resets the CE bit and the monitoring
becomes active again. Interrupt handling is described in detail hereunder.
13.2.3 Interrupts
The interrupt is connected to the interrupt controller to inform the processor of the error condition.
The normal procedure is that an interrupt routine handles the error with the aid of the information in
the status registers. When it is finished it resets the NE bit and the monitoring becomes active again.
Interrupts are generated for both AMBA error responses and correctable errors as described above.
13.3
Registers
Table 100.AHB Status registers
APB address offset
Registers
0x0
AHB Status register
0x4
AHB Failing address register
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Table 101. AHB Status register
31
10
RESERVED
9
8
CE NE
7
HWRITE
6
3
HMASTER
2
0
HSIZE
31: 10
RESERVED
9
CE: Correctable Error. Set if the detected error was caused by a single error and zero otherwise.
8
NE: New Error. Deasserted at start-up and after reset. Asserted when an error is detected. Reset by
writing a zero to it.
7
The HWRITE signal of the AHB transaction that caused the error.
6: 3
The HMASTER signal of the AHB transaction that caused the error.
2: 0
The HSIZE signal of the AHB transaction that caused the error
Table 102. AHB Failing address register
31
0
AHB FAILING ADDRESS
31: 0
The HADDR signal of the AHB transaction that caused the error.
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14
Serial Debug Interface
14.1
Overview
The interface consists of a UART connected to the AMBA AHB bus as a master. A simple communication protocol is supported to transmit access parameters and data. Through the communication link,
a read or write transfer can be generated to any address on the AMBA AHB bus.
Baud-rate
generator
RX
Serial port
Controller
8*bitclk
AMBA APB
Receiver shift register
Transmitter shift register
AHB master interface
AHB data/response
TX
AMBA AHB
14.2
Operation
14.2.1 Transmission protocol
The interface supports a simple protocol where commands consist of a control byte, followed by a 32bit address, followed by optional write data. Write access does not return any response, while a read
access only returns the read data. Data is sent on 8-bit basis as shown below.
Start D0
D1
D2
D3
D4
D5
D6
D7 Stop
Figure 40. Data frame
Write Command
Send
11 Length -1
Addr[31:24]
Addr[23:16]
Addr[15:8]
Addr[7:0]
Addr[7:0]
Data[31:24]
Data[23:16]
Data[15:8]
Data[7:0]
Read command
Send
10 Length -1
Addr[31:24]
Addr[23:16]
Addr[15:8]
Receive
Data[31:24]
Data[23:16]
Data[15:8]
Data[7:0]
Figure 41. Commands
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Block transfers can be performed be setting the length field to n-1, where n denotes the number of
transferred words. For write accesses, the control byte and address is sent once, followed by the number of data words to be written. The address is automatically incremented after each data word. For
read accesses, the control byte and address is sent once and the corresponding number of data words is
returned.
14.2.2 Baud rate generation
The UART contains a 18-bit down-counting scaler to generate the desired baud-rate. The scaler is
clocked by the system clock and generates a UART tick each time it underflows. The scaler is
reloaded with the value of the UART scaler reload register after each underflow. The resulting UART
tick frequency should be 8 times the desired baud-rate.
If not programmed by software, the baud rate will be automatically discovered. This is done by
searching for the shortest period between two falling edges of the received data (corresponding to two
bit periods). When three identical two-bit periods has been found, the corresponding scaler reload
value is latched into the reload register, and the BL bit is set in the UART control register. If the BL bit
is reset by software, the baud rate discovery process is restarted. The baud-rate discovery is also
restarted when a ‘break’ or framing error is detected by the receiver, allowing to change to baudrate
from the external transmitter. For proper baudrate detection, the value 0x55 should be transmitted to
the receiver after reset or after sending break.
The best scaler value for manually programming the baudrate can be calculated as follows:
scaler = (((system_clk*10)/(baudrate*8))-5)/10
14.3
Registers
Table 103.AHB UART registers
APB address offset
Register
0x4
AHB UART status register
0x8
AHB UART control register
0xC
AHB UART scaler register
31
2
RESERVED
1
0
BL EN
Figure 42. AHB UART control register
0:
1:
Receiver enable (EN) - if set, enables both the transmitter and receiver. Reset value: ‘0’.
Baud rate locked (BL) - is automatically set when the baud rate is locked. Reset value: ‘0’.
31
7
RESERVED
6
FE
5
4
3
2
1
0
OV BR TH TS DR
Figure 43. AHB UART status register
0:
Data ready (DR) - indicates that new data has been received by the AMBA AHB master interface. Read only. Reset
value: ‘0’.
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1:
Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Read only. Reset value:
‘1’
Transmitter hold register empty (TH) - indicates that the transmitter hold register is empty. Read only. Reset value:
‘1’
Break (BR) - indicates that a BREAKE has been received. Reset value: ‘0’
Overflow (OV) - indicates that one or more character have been lost due to receiver overflow. Reset value: ‘0’
Frame error (FE) - indicates that a framing error was detected. Reset value: ‘0’
2:
3:
4:
6:
18 17
31
0
SCALER RELOAD VALUE
RESERVED
Figure 44. AHB UART scaler reload register
17:0
14.4
Baudrate scaler reload value = (((system_clk*10)/(baudrate*8))-5)/10. Reset value: “3FFFF“.
Table 104.Signal definitions and reset values
14.5
Signal name
Type
Function
Active
Reset value
dsutx
Output
UART transmit data line
-
Logical 1
dsurx
Input
UART receive data line
-
-
Timing
clk
dsutx
tAHBUART0
dsurx
tAHBUART1
tAHBUART0
tAHBUART2
Table 105.Timing parameters
Name
Parameter
Reference edge
Min
Max
Unit
tAHBUART0
rising clk edge
0
40
ns
tAHBUART1
input to clock hold
rising clk edge
-
-
ns
tAHBUART2
rising clk edge
-
-
ns
Note: The dsurx input is re-synchronized internally. The signal does not have to meet any setup or
hold requirements.
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15
Interrupt Controller
15.1
Overview
The interrupts generated on the interrupt bus are all forwarded to the interrupt controller. The interrupt
controller prioritizes, masks and propagates the interrupt with the highest priority to the processor.
15.2
Operation
15.2.1 Interrupt prioritization
The interrupt controller monitors interrupt 1 - 15 of the interrupt bus (APBI.PIRQ[15:1]). When any
of these lines are asserted high, the corresponding bit in the interrupt pending register is set. The pending bits will stay set even if the PIRQ line is de-asserted, until cleared by software or by an interrupt
acknowledge from the processor.
Each interrupt can be assigned to one of two levels (0 or 1) as programmed in the interrupt level register. Level 1 has higher priority than level 0. The interrupts are prioritised within each level, with interrupt 15 having the highest priority and interrupt 1 the lowest. The highest interrupt from level 1 will
be forwarded to the processor. If no unmasked pending interrupt exists on level 1, then the highest
unmasked interrupt from level 0 will be forwarded. PIRQ[31:16] are not used by the IRQMP core.
Interrupts are prioritised at system level, while masking and forwarding of interrupts in done for each
processor separately. Each processor in an multiprocessor system has separate interrupt mask and
force registers. When an interrupt is signalled on the interrupt bus, the interrupt controller will prioritize interrupts, perform interrupt masking for each processor according to the mask in the corresponding mask register and forward the interrupts to the processors.
Priority
select
IRQ
Pending
Priority
encoder
APBI.PIRQ[15:1]
4
15
IRQO[0].IRL[3:0]
IRQ
IRQ
Force[0] mask[0]
Priority
encoder
4
IRQO[n].IRL[3:0]
IRQ
IRQ
Force[n] mask[n]
Figure 46. Interrupt controller block diagram
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When a processor acknowledges the interrupt, the corresponding pending bit will automatically be
cleared. Interrupt can also be forced by setting a bit in the interrupt force register. In this case, the processor acknowledgement will clear the force bit rather than the pending bit. After reset, the interrupt
mask register is set to all zeros while the remaining control registers are undefined. Note that interrupt
15 cannot be maskable by the LEON3 processor and should be used with care - most operating systems do not safely handle this interrupt.
15.2.2 Extended interrupts
The AHB/APB interrupt consist of 32 signals ([31:0]), while the IRQMP only uses lines 1 - 15 in the
nominal mode. To use the additional 16 interrupt lines (16-31), extended interrupt handling can be
enabled by setting the VHDL generic eirq to a value between 1 - 15. The interrupt lines 16 - 31 will
then also be handled by the interrupt controller, and the interrupt pending and mask registers will be
extended to 32 bits. Since the LEON3 processor only has 15 interrupt levels (1 - 15), the extended
interrupts will generate one of the regular interrupts, indicated by the value of the eirq generic. When
the interrupt is taken and acknowledged by the processor, the regular interrupt (eirq) and the extended
interrupt pending bits are automatically cleared. The extended interrupt acknowledge register will
identify which extended interrupt that was most recently acknowledged. This register can be used by
software to invoke the appropriate interrupt handler for the extended interrupts.
15.2.3 Processor status monitoring
The processor status can be monitored through the Multiprocessor Status Register. The STATUS field
in this register indicates if a processor is halted (‘1’) or running (‘0’). A halted processor can be reset
and restarted by writing a ‘1’ to its status field. After reset, all processors except processor 0 are
halted. When the system is properly initialized, processor 0 can start the remaining processors by
writing to their STATUS bits.
15.2.4 Irq broadcasting
The Broadcast Register is activated when the generic ncpu is > 1. A incoming irq that has its bit set in
the Broadcast Register is propagated to the force register of all CPUs rather than only to the Pending
Register. This can be used to implement a timer that fires to all cpus with that same irq.
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114
Registers
The core is controlled through registers mapped into APB address space. The number of implemented
registers depend on number of processor in the multiprocessor system.
Table 106.Interrupt Controller registers
APB address offset
Register
0x00
Interrupt level register
0x04
Interrupt pending register
0x08
Interrupt force register (NCPU = 0)
0x0C
Interrupt clear register
0x10
Multiprocessor status register
0x14
Broadcast register
0x40
Processor interrupt mask register
0x80
Processor interrupt force register
0xC4
Processor 1 extended interrupt acknowledge register
0xC0 + 4 * n
Processor n extended interrupt acknowledge register
15.3.1 Interrupt level register
31
17
16
1
IL[15:1]
“000..0”
0
0
Figure 47. Interrupt level register
[31:16] Reserved.
[15:1] Interrupt Level n (IL[n]): Interrupt level for interrupt n.
[0]
Reserved.
15.3.2 Interrupt pending register
1
16 15
31
EIP[31:16]
IP[15:1]
0
0
Figure 48. Interrupt pending register
[31:17] Extended Interrupt Pending n (EIP[n]).
[15:1] Interrupt Pending n (IP[n]): Interrupt pending for interrupt n.
[0]
Reserved
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15.3.3 Interrupt force register (NCPU = 0)
16 15
31
“000...0”
1
0
0
IF[15:1]
Figure 49. Interrupt force register
[31:16] Reserved.
[15:1] Interrupt Force n (IF[n]): Force interrupt nr n.
[0]
Reserved.
15.3.4 Interrupt clear register
16 15
31
“000...0”
1
0
0
IC[15:1]
Figure 50. Interrupt clear register
[31:16] Reserved.
[15:1] Interrupt Clear n (IC[n]): Writing ‘1’ to ICn will clear interrupt n.
[0]
Reserved.
15.3.5 Multiprocessor status register
28
31
NCPU
16 15
20 19
“000...0”
0
STATUS[15:0]
EIRQ
Figure 51. rocessor status register
[31:28] NCPU. Number of CPU’s in the system -1 .
[19:16] EIRQ. Interrupt number (1 - 15) used for extended interrupts. Fixed to 0 if extended interrupts are disabled.
[15:1] Power-down status of CPU [n]: ‘1’ = power-down, ‘0’ = running. Write with ‘1’ to start processor n.
15.3.6 Processor interrupt mask register
16 15
31
1
IM[15:1]
EIM[31:16]
0
0
Figure 52. Processor interrupt mask register
[31:16] Interrupt mask for extended interrupts
[15:1] Interrupt Mask n (IM[n]): If IMn = 0 the interrupt n is masked, otherwise it is enabled.
[0]
Reserved.
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15.3.7 Broadcast register (NCPU > 0)
16 15
31
0
1
IM[15:1]
“000...0”
0
Figure 53. Processor interrupt mask register
[31:16] Reserved.
[15:1] Broadcast Mask n (BM[n]): If BMn = 1 the interrupt n is broadcasted (written to the Force Register of all CPUs),
otherwise standard semantic applies (Pending Register).
[0]
Reserved.
15.3.8 Processor interrupt force register (NCPU > 0)
17 16 15
31
IFC[15:1]
0
1
0
IF[15:1]
0
Figure 54. Processor interrupt force register
[31:17] Interrupt force clear n (IFC[n]).
[15:1] Interrupt Force n (IF[n]): Force interrupt nr n.
[0]
Reserved.
15.3.9 Extended interrupt acknowledge register
5
31
4
0
EID[4:0]
Figure 55. Extended interrupt acknowledge register
[4:0]
15.4
ID (16 - 31) of the most recent acknowledged extended interrupt
15.5
Signal name
Type
Function
Active
Reset value
irq
Output
Interrupt
Logical 1
Logical 0
Timing
clk
irq
tGRIRQ0
tGRIRQ0
Name
Parameter
Reference edge
Min
Max
Unit
tGRIRQ0
rising clk edge
0
40
ns
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16
Clock generation
16.1
Overview
The clock generator implements internal clock generation and buffering.
16.2
16.3
Signal name
Type
Function
Active
Reset value
clk
Input
System clock
Rising edge
-
Timing
tCLKGEN0
clk
Name
Parameter
Reference edge
Min
Max
Unit
tCLKGEN0
clock period
-
50
50
ns 1)
Note 1:
The minimum clock period, and the resulting maximum clock frequency, is dependent on
the manufacturing lot for the Actel parts and expected radiation levels. The functional
behavior of the part is not guaranteed under radiation.
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17
Reset generation
17.1
Overview
The reset generator implements input reset signal synchronization with glitch filtering and generates
the internal reset signal. The input reset signal can be asynchronous.
17.2
17.3
Signal name
Type
Function
Active
resetn
Input
Reset
Low
Reset value
Timing
clk
resetn
tRSTGEN0
Name
Parameter
Reference edge
Min
Max
Unit
tRSTGEN0
asserted period
-
1000
-
ns
Note: The reset_n input is re-synchronized internally. The signals does not have to meet any setup or
hold requirements.
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18
AMBA AHB controller with plug&play support
18.1
Overview
The AMBA AHB controller is a combined AHB arbiter, bus multiplexer and slave decoder according
to the AMBA 2.0 standard.
MASTER
MASTER
AHBCTRL
ARBITER/
DECODER
SLAVE
SLAVE
Figure 59. AHB controller block diagram
18.2
Operation
18.2.1 Arbitration
In fixed-priority mode, the bus request priority is equal to the master’s bus index, with index 0 being
the lowest priority. If no master requests the bus, the master with bus index 0 will be granted.
In round-robin mode, priority is rotated one step after each AHB transfer. If no master requests the
bus, the last owner will be granted (bus parking).
During incremental bursts, the AHB master should keep the bus request asserted until the last access
as recommended in the AMBA 2.0 specification, or it might loose bus ownership. For fixed-length
burst, the AHB master will be granted the bus during the full burst, and can release the bus request
immediately after the first access has started.
18.2.2 Decoding
Decoding of AHB slaves is done using the plug&play method explained in the GRLIB User’s Manual. A slave can occupy any binary aligned address space with a size of 1 - 4096 Mbyte. A specific I/
O area is also decoded, where slaves can occupy 256 byte - 1 Mbyte. The default address of the I/O
area is 0xFFF00000. Access to unused addresses will cause an AHB error response.
18.2.3 Plug&play information
The plug&play information is mapped on a read-only address area. By default, the area is mapped on
address 0xFFFFF000 - 0xFFFFFFFF. The master information is placed on the first 2 kbyte of the
block (0xFFFFF000 - 0xFFFFF800), while the slave information is placed on the second 2 kbyte
block. Each unit occupies 32 bytes, which means that the area has place for 64 masters and 64 slaves.
The address for masters is thus 0xFFFFF000 + n*32, and 0xFFFFF800 + n*32 for slaves.
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31
00
Identification Register
24 23
12 11 10 9
VENDOR ID
DEVICE ID
04
USER-DEFINED
08
USER-DEFINED
0C
USER-DEFINED
00
5 4
VERSION
0
IRQ
BAR0 10
HADDR
ADDR
00
P C
MASK
MASK
TYPE
BAR1 14
ADDR
00
P C
MASK
TYPE
BAR2 18
ADDR
00
P C
MASK
TYPE
BAR3 1C
ADDR
00
P C
MASK
TYPE
Bank Address Registers
31
20 19 18 17 16 15
P = Prefetchable
C = Cacheable
4 3
0
TYPE
0001 = APB I/O space
0010 = AHB Memory space
0011 = AHB I/O space
Figure 60. AHB plug&play information record
18.3
Registers
The core does not implement any registers.
testen
testrst
scanen
testoen
18.4
:
:
:
:
in
in
in
in
std_ulogic
std_ulogic
std_ulogic
std_ulogic
:=
:=
:=
:=
’0’;
’1’;
’0’;
’1’
Debug print-out
If the debug generic is set to 2, the plug&play information of all attached AHB units are printed to the
console during the start of simulation. Reporting starts by scanning the master interface array from 0
to NAHBMST - 1 (defined in the grlib.amba package). It checks each entry in the array for a valid
vendor-id (all nonzero ids are considered valid) and if one is found, it also retrieves the device-id. The
descriptions for these ids are obtained from the GRLIB.DEVICES package, and are then printed on
standard out together with the master number. If the index check is enabled (done with a VHDL
generic), the report module also checks if the hindex number returned in the record matches the array
number of the record currently checked (the array index). If they do not match, the simulation is
aborted and an error message is printed.
This procedure is repeated for slave interfaces found in the slave interface array. It is scanned from 0
to NAHBSLV - 1 and the same information is printed and the same checks are done as for the master
interfaces. In addition, the address range and memory type is checked and printed. The address information includes type, address, mask, cacheable and pre-fetchable fields. From this information, the
report module calculates the start address of the device and the size of the range. The information
finally printed is type, start address, size, cacheability and pre-fetchability. The address ranges currently defined are AHB memory, AHB I/O and APB I/O. APB I/O ranges are ignored by this module.
# vsim -c -quiet leon3mp
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VSIM 1> run
# LEON3 MP Demonstration design
# GRLIB Version 1.0.7
# Target technology: inferred, memory library: inferred
# ahbctrl: AHB arbiter/multiplexer rev 1
# ahbctrl: Common I/O area disabled
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte
# ahbctrl: mst0: Gaisler Research
Leon3 SPARC V8 Processor
# ahbctrl: mst1: Gaisler Research
AHB Debug UART
# ahbctrl: slv0: European Space Agency
Leon2 Memory Controller
# ahbctrl:
memory at 0x00000000, size 512 Mbyte, cacheable, prefetch
# ahbctrl:
memory at 0x20000000, size 512 Mbyte
# ahbctrl:
memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch
# ahbctrl: slv1: Gaisler Research
AHB/APB Bridge
# ahbctrl:
memory at 0x80000000, size 1 Mbyte
# apbctrl: APB Bridge at 0x80000000 rev 1
# apbctrl: slv0: European Space Agency
Leon2 Memory Controller
# apbctrl:
I/O ports at 0x80000000, size 256 byte
# apbctrl: slv1: Gaisler Research
Generic UART
# apbctrl:
Multi-processor Interrupt Ctrl.
# apbctrl:
Modular Timer Unit
# apbctrl:
AHB Debug UART
# apbctrl:
General Purpose I/O port
# apbctrl:
I/O ports at 0x80000b00, size 256 byte
# grgpio11: 8-bit GPIO Unit rev 0
# gptimer3: GR Timer Unit rev 0, 8-bit scaler, 2 32-bit timers, irq 8
# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1
# apbuart1: Generic UART rev 1, fifo 4, irq 2
# ahbuart7: AHB Debug UART rev 0
# leon3_0: LEON3 SPARC V8 processor rev 0
# leon3_0: icache 1*8 kbyte, dcache 1*8 kbyte
VSIM 2>
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19
AMBA AHB/APB bridge with plug&play support
19.1
Overview
The AMBA AHB/APB bridge is a APB bus master according the AMBA 2.0 standard.
AHB/APB Bridge
AHB BUS
APBO[0]
APB SLAVE
AHBSI
APBO[n]
AHB Slave
Interface
AHBSO[n]
APB SLAVE
•••
APBI
Figure 61. AHB/APB bridge block diagram
19.2
Operation
19.2.1 Decoding
Decoding of APB slaves is done using the plug&play method explained in the GRLIB IP Library
User’s Manual. A slave can occupy any binary aligned address space with a size of 256 bytes - 1
Mbyte. Write to unassingned areas will be ignored, while reads from unassigned areas will return an
arbitrary value. AHB error response will never be generated.
19.2.2 Plug&play information
The plug&play information is mapped on a read-only address area at the top 4 kbytes of the bridge
address space. Each plug&play block occupies 8 bytes. If the bridge is mapped on AHB address
0x80000000, the address for the plug&play records is thus 0x800FF000 + n*8.
31
APB Plug&play record
24 23
VENDOR ID
0x00
12 11 10 9
DEVICE ID
ADDR
0x04
31
C/P
20 19
00
5
0
4
VERSION
MASK
16 15
Configuration word
IRQ
TYPE
4 3
BAR
0
Figure 62. APB plug&play information
19.3
Debug print-out
The APB bridge can print-out the plug-play information from the attached during simulation. This is
enabled by setting the debug VHDL generic to 2. Reporting starts by scanning the array from 0 to
NAPBSLV - 1 (defined in the grlib.amba package). It checks each entry in the array for a valid vendor-id (all nonzero ids are considered valid) and if one is found, it also retrieves the device-id. The
GR-TMTC-0002
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123
description for these ids are obtained from the GRLIB.DEVICES package, and is printed on standard
out together with the slave number. If the index check is enabled (done with a VHDL generic), the
report module also checks if the pindex number returned in the record matches the array number of
the record currently checked (the array index). If they do not match, the simulation is aborted and an
error message is printed.
The address range and memory type is also checked and printed. The address information includes
type, address and mask. The address ranges currently defined are AHB memory, AHB I/O and APB I/
O. All APB devices are in the APB I/O range so the type does not have to be checked. From this information, the report module calculates the start address of the device and the size of the range. The
information finally printed is start address and size.
GR-TMTC-0002
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20
Electrical description
20.1
Absolute maximum ratings
124
According to Actel data sheet [RTAX].
20.2
Operating conditions
20.3
Input voltages, leakage currents and capacitances
20.4
Output voltages, leakage currents and capacitances
20.5
Clock Input voltages, leakage currents and capacitances
20.6
Power supplies
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21
Mechanical description
21.1
Package
Implemented in an ACTEL RTAX2000S FPGA in a CQ352 package, as per [RTAX] and [PACK].
21.2
Pin assignment
The pin assignment in table 113 shows the implementation characteristics of each signal according to
the Actel data sheet [RTAX], indicating how each pin has been configured in terms of electrical levels, voltage, slew rate, drive capability and internal pull-up or pull-down in the FPGA device.
Table 113. Pin assignment
Name
I/O
Pin
CQ352
Pin
CG624
Level
Volt.
Slew
Load
Drive [pF]
Pull
Polarity
Note
clk
in
314
C12
LVTTL
3.3
-
-
None Rise
System clock
resetn
in
92
D24
LVTTL
3.3
-
-
None Low
System reset
irq
out
137
J22
LVTTL
3.3
Low
12
dsurx
in
338
E23
LVTTL
3.3
-
-
dsutx
out
337
F23
LVTTL
3.3
Low
12
transclk
in
306
N18
LVTTL
3.3
-
-
35
35
None Low
System interrupt
None Low
DSU data receive
None Low
DSU data transmit
None Rise
caduclk[0]
out
78
M18
LVTTL
3.3
Low
12
35
None Low
Telemetry serial bit clock
caduclk[1]
out
83
L24
LVTTL
3.3
Low
12
35
None Low
caduclk[2]
out
335
W22
LVTTL
3.3
Low
12
35
None Low
caduclk[3]
out
343
P21
LVTTL
3.3
Low
12
35
None Low
caduout[0]
out
79
M19
LVTTL
3.3
Low
12
35
None Low
Telemetry serial bit data
caduout[1]
out
84
K24
LVTTL
3.3
Low
12
35
None Low
caduout[2]
out
336
W23
LVTTL
3.3
Low
12
35
None Low
caduout[3]
out
342
R19
LVTTL
3.3
Low
12
35
None Low
Telemetry serial bit data, Manchester coded
tcscid[0]
in
4
N/A
LVTTL
3.3
-
-
-
None -
TC Spacecraft Identifier, MSB
tcscid[1]
in
5
N/A
LVTTL
3.3
-
-
-
None -
tcscid[2]
in
6
N/A
LVTTL
3.3
-
-
-
None -
tcscid[3]
in
7
N/A
LVTTL
3.3
-
-
-
None -
tcscid[4]
in
10
N/A
LVTTL
3.3
-
-
-
None -
tcscid[5]
in
12
N/A
LVTTL
3.3
-
-
-
None -
tcscid[6]
in
16
N/A
LVTTL
3.3
-
-
-
None -
tcscid[7]
in
18
N/A
LVTTL
3.3
-
-
-
None -
tcscid[8]
in
22
N/A
LVTTL
3.3
-
-
-
None -
tcscid[9]
in
24
N/A
LVTTL
3.3
-
-
-
None -
TC Spacecraft Identifier, LSB
tcvcid[0]
in
28
N/A
LVTTL
3.3
-
-
-
None -
TC Virtual Channel Identifier, MSB
tcvcid[1]
in
30
N/A
LVTTL
3.3
-
-
-
None -
tcvcid[2]
in
34
N/A
LVTTL
3.3
-
-
-
None -
tcvcid[3]
in
36
N/A
LVTTL
3.3
-
-
-
None -
tcvcid[4]
in
40
N/A
LVTTL
3.3
-
-
-
None -
tcvcid[5]
in
42
N/A
LVTTL
3.3
-
-
-
None -
TC Virtual Channel Identifier, LSB
tcrfpos
in
46
F24
LVTTL
3.3
-
-
-
None High
TC RF available positive
tchigh
in
47
G24
LVTTL
3.3
-
-
-
None High
TC input active positive
GR-TMTC-0002
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126
Name
I/O
Pin
CQ352
Pin
CG624
Level
Volt.
Slew
Load
Drive [pF]
Pull
Polarity
Note
tcrise
in
48
K18
LVTTL
3.3
-
-
-
None High
TC serial bit clock rising
tcpseudo
in
49
L18
LVTTL
3.3
-
-
-
None High
TC Pseudo-derandomiser
tcmark
in
52
H22
LVTTL
3.3
-
-
-
None High
TC NRZ-M de-modulation
tcrfa[0]
in
54
J24
LVTTL
3.3
-
-
-
None -
TC CLTU RF Available
tcrfa[1]
in
60
L20
LVTTL
3.3
-
-
-
None -
tcrfa[2]
in
65
AA23
LVTTL
3.3
-
-
-
None -
tcrfa[3]
in
71
P24
LVTTL
3.3
-
-
-
None -
tcactive[0]
in
53
H24
LVTTL
3.3
-
-
-
None -
tcactive[1]
in
59
L21
LVTTL
3.3
-
-
-
None -
tcactive[2]
in
66
Y23
LVTTL
3.3
-
-
-
None -
tcactive[3]
in
72
N20
LVTTL
3.3
-
-
-
None -
tcclk[0]
in
55
N16
LVTTL
3.3
-
-
-
None -
tcclk[1]
in
61
G25
LVTTL
3.3
-
-
-
None -
tcclk[2]
in
70
V21
LVTTL
3.3
-
-
-
None -
tcclk[4]
in
73
Y22
LVTTL
3.3
-
-
-
None -
tcdata[0]
in
58
L23
LVTTL
3.3
-
-
-
None -
tcdata[1]
in
64
F25
LVTTL
3.3
-
-
-
None -
tcdata[2]
in
67
U21
LVTTL
3.3
-
-
-
None -
tcdata[3]
in
76
Y21
LVTTL
3.3
-
-
-
None -
GR-TMTC-0002
TC CLTU Input Active
TC CLTU Serial Bit Clock
TC CLTU Serial Bit Data
GAISLER
127
Name
I/O
Pin
CQ352
Pin
CG624
Level
Volt.
Slew
Load
Drive [pF]
Pull
Polarity
tcgpio[0]
out
94
V3
LVTTL
3.3
Low
12
35
None High
tcgpio[1]
out
95
AA3
LVTTL
3.3
Low
12
35
None High
tcgpio[2]
out
98
AA2
LVTTL
3.3
Low
12
35
None High
tcgpio[3]
out
99
W3
LVTTL
3.3
Low
12
35
None High
tcgpio[4]
out
100
V6
LVTTL
3.3
Low
12
35
None High
tcgpio[5]
out
101
AB2
LVTTL
3.3
Low
12
35
None High
tcgpio[6]
out
104
U4
LVTTL
3.3
Low
12
35
None High
tcgpio[7]
out
105
W4
LVTTL
3.3
Low
12
35
None High
tcgpio[8]
out
106
K25
LVTTL
3.3
Low
12
35
None High
tcgpio[9]
out
107
L25
LVTTL
3.3
Low
12
35
None High
tcgpio[10]
out
110
N24
LVTTL
3.3
Low
12
35
None High
tcgpio[11]
out
111
M24
LVTTL
3.3
Low
12
35
None High
tcgpio[12]
out
112
G22
LVTTL
3.3
Low
12
35
None High
tcgpio[13]
out
113
M17
LVTTL
3.3
Low
12
35
None High
tcgpio[14]
out
118
K19
LVTTL
3.3
Low
12
35
None High
tcgpio[15]
out
119
E25
LVTTL
3.3
Low
12
35
None High
tcgpio[16]
out
86
D25
LVTTL
3.3
Low
12
35
None High
tcgpio[17]
out
93
K20
LVTTL
3.3
Low
12
35
None High
tcgpio[18]
out
122
J21
LVTTL
3.3
Low
12
35
None High
tcgpio[19]
out
123
J20
LVTTL
3.3
Low
12
35
None High
tcgpio[20]
out
128
J23
LVTTL
3.3
Low
12
35
None High
tcgpio[21]
out
129
L19
LVTTL
3.3
Low
12
35
None High
tcgpio[22]
out
136
V22
LVTTL
3.3
Low
12
35
None High
tcgpio[23]
out
289
V23
LVTTL
3.3
Low
12
35
None High
tcgpio[24]
out
290
U22
LVTTL
3.3
Low
12
35
None High
tcgpio[25]
out
295
V24
LVTTL
3.3
Low
12
35
None High
tcgpio[26]
out
296
R21
LVTTL
3.3
Low
12
35
None High
tcgpio[27]
out
299
T22
LVTTL
3.3
Low
12
35
None High
tcgpio[28]
out
300
W24
LVTTL
3.3
Low
12
35
None High
tcgpio[29]
out
305
AB24
LVTTL
3.3
Low
12
35
None High
Note
TC Hardware Command, MSB
tcgpio[30]
out
313
M20
LVTTL
3.3
Low
12
35
None High
tcgpio[31]
out
319
N17
LVTTL
3.3
Low
12
35
None High
TC Hardware Command, LSB
CLCW Input to Telemetry
clcwin[0]
in
277
M23
LVTTL
3.3
-
-
-
None Low
clcwin[1]
in
278
N23
LVTTL
3.3
-
-
-
None Low
clcwout[0]
out
281
M25
LVTTL
3.3
Low
12
35
None Low
clcwout[1]
out
282
N25
LVTTL
3.3
Low
12
35
None Low
GR-TMTC-0002
CLCW Output from Telecommand
GAISLER
128
Name
I/O
Pin
CQ352
Pin
CG624
Level
Volt.
Slew
Load
Drive [pF]
Pull
Polarity
Note
spw_clk
in
320
G14
LVTTL
3.3
-
-
-
None -
SpaceWire clock
spw_rxd[0]
in
N/A
P19
LVDS
2.5
-
-
-
-
High
SpaceWire data - Link 0
spw_rxdn[0]
in
N/A
P20
LVDS
2.5
-
-
-
-
Low
- “-
spw_rxs[0]
in
N/A
P23
LVDS
2.5
-
-
-
-
High
SpaceWire strobe
spw_rxsn[0]
in
N/A
R23
LVDS
2.5
-
-
-
-
Low
- “-
spw_txd[0]
out
N/A
P25
LVDS
2.5
-
-
-
-
High
SpaceWire data
spw_txdn[0]
out
N/A
R25
LVDS
2.5
-
-
-
-
Low
- “-
spw_txs[0]
out
N/A
P22
LVDS
2.5
-
-
-
-
High
SpaceWire strobe
spw_txsn[0]
out
N/A
R22
LVDS
2.5
-
-
-
-
Low
- “-
spw_rxd[1]
in
N/A
R18
LVDS
2.5
-
-
-
-
High
spw_rxdn[1]
in
N/A
T18
LVDS
2.5
-
-
-
-
Low
- “-
spw_rxs[1]
in
N/A
R24
LVDS
2.5
-
-
-
-
High
SpaceWire strobe
spw_rxsn[1]
in
N/A
T24
LVDS
2.5
-
-
-
-
Low
- “-
spw_txd[1]
out
N/A
T25
LVDS
2.5
-
-
-
-
High
SpaceWire data
spw_txdn[1]
out
N/A
U25
LVDS
2.5
-
-
-
-
Low
- “-
spw_txs[1]
out
N/A
R20
LVDS
2.5
-
-
-
-
High
SpaceWire strobe
spw_txsn[1]
out
N/A
T20
LVDS
2.5
-
-
-
-
Low
spw_rxd[2]
in
N/A
V20
LVCMOS
2.5
-
-
-
None High
- “SpaceWire data - Link 2
spw_rxs[2]
in
N/A
AB25
LVCMOS
2.5
-
-
-
None High
SpaceWire strobe
spw_txd[2]
out
N/A
U20
LVCMOS
2.5
High
24
35
None High
SpaceWire data
spw_txs[2]
out
N/A
AA25
LVCMOS
2.5
High
24
35
None High
SpaceWire strobe
spw_rxd[3]
in
N/A
T19
LVCMOS
2.5
-
-
-
None High
SpaceWire data - Link 3 {spare}
spw_rxs[3]
in
N/A
W25
LVCMOS
2.5
-
-
-
None High
SpaceWire strobe {spare}
spw_txd[3]
out
N/A
U19
LVCMOS
2.5
High
24
35
None High
SpaceWire data {spare}
spw_txs[3]
out
N/A
Y25
LVCMOS
2.5
High
24
35
None High
spw_rxd[0]
in
43
N/A
LVTTL
3.3
-
-
-
None High
spw_rxs[0]
in
41
N/A
LVTTL
3.3
-
-
-
None High
SpaceWire strobe
spw_txd[0]
out
37
N/A
LVTTL
3.3
High
24
35
None High
SpaceWire data
spw_txs[0]
out
35
N/A
LVTTL
3.3
High
24
35
None High
SpaceWire strobe
spw_rxd[1]
in
31
N/A
LVTTL
3.3
-
-
-
None High
spw_rxs[1]
in
29
N/A
LVTTL
3.3
-
-
-
None High
SpaceWire strobe
spw_txd[1]
out
25
N/A
LVTTL
3.3
High
24
35
None High
SpaceWire data
spw_txs[1]
out
23
N/A
LVTTL
3.3
High
24
35
None High
SpaceWire strobe
spw_rxd[2]
in
19
N/A
LVTTL
3.3
-
-
-
None High
spw_rxs[2]
in
17
N/A
LVTTL
3.3
-
-
-
None High
SpaceWire strobe
spw_txd[2]
out
13
N/A
LVTTL
3.3
High
24
35
None High
SpaceWire data
spw_txs[2]
out
11
N/A
LVTTL
3.3
High
24
35
None High
SpaceWire strobe
spw_rxd[3]
in
N/A
N/A
LVTTL
3.3
-
-
-
None High
SpaceWire data - Link 3 {spare}
spw_rxs[3]
in
N/A
N/A
LVTTL
3.3
-
-
-
None High
spw_txd[3]
out
N/A
N/A
LVTTL
3.3
High
24
35
None High
SpaceWire data {spare}
spw_txs[3]
out
N/A
N/A
LVTTL
3.3
High
24
35
None High
GR-TMTC-0002
GAISLER
129
Name
I/O
Pin
CQ352
Pin
CG624
Level
Volt.
Slew
Load
Drive [pF]
Pull
Polarity
address[0]
out
223
P9
LVTTL
3.3
Low
12
35
None High
address[1]
out
224
N6
LVTTL
3.3
Low
12
35
None High
address[2]
out
225
M6
LVTTL
3.3
Low
12
35
None High
address[3]
out
226
N8
LVTTL
3.3
Low
12
35
None High
address[4]
out
229
N7
LVTTL
3.3
Low
12
35
None High
address[5]
out
230
M4
LVTTL
3.3
Low
12
35
None High
address[6]
out
231
L3
LVTTL
3.3
Low
12
35
None High
address[7]
out
232
M3
LVTTL
3.3
Low
12
35
None High
Note
Address, LSB
address[8]
out
235
N10
LVTTL
3.3
Low
12
35
None High
address[9]
out
236
N9
LVTTL
3.3
Low
12
35
None High
address[10]
out
237
K1
LVTTL
3.3
Low
12
35
None High
address[11]
out
238
L1
LVTTL
3.3
Low
12
35
None High
address[12]
out
241
M5
LVTTL
3.3
Low
12
35
None High
address[13]
out
242
L6
LVTTL
3.3
Low
12
35
None High
address[14]
out
243
L5
LVTTL
3.3
Low
12
35
None High
address[15]
out
244
K2
LVTTL
3.3
Low
12
35
None High
address[16]
out
247
L2
LVTTL
3.3
Low
12
35
None High
address[17]
out
248
K4
LVTTL
3.3
Low
12
35
None High
address[18]
out
249
L4
LVTTL
3.3
Low
12
35
None High
address[19]
out
250
J3
LVTTL
3.3
Low
12
35
None High
address[20]
out
253
J2
LVTTL
3.3
Low
12
35
None High
address[21]
out
254
J1
LVTTL
3.3
Low
12
35
None High
address[22]
out
255
L7
LVTTL
3.3
Low
12
35
None High
address[23]
out
256
M7
LVTTL
3.3
Low
12
35
None High
address[24]
out
259
M9
LVTTL
3.3
Low
12
35
None High
address[25]
out
260
M8
LVTTL
3.3
Low
12
35
None High
address[26]
out
261
F1
LVTTL
3.3
Low
12
35
None High
address[27]
out
262
G1
LVTTL
3.3
Low
12
35
None High
Address, MSB
data[0]
inout
172
H2
LVTTL
3.3
Low
12
35
None High
Data, LSB
data[1]
inout
173
E2
LVTTL
3.3
Low
12
35
None High
data[2]
inout
179
F2
LVTTL
3.3
Low
12
35
None High
data[3]
inout
180
H4
LVTTL
3.3
Low
12
35
None High
data[4]
inout
181
J4
LVTTL
3.3
Low
12
35
None High
data[5]
inout
182
H5
LVTTL
3.3
Low
12
35
None High
data[6]
inout
183
H6
LVTTL
3.3
Low
12
35
None High
data[7]
inout
184
D2
LVTTL
3.3
Low
12
35
None High
data[8]
inout
187
J6
LVTTL
3.3
Low
12
35
None High
data[9]
inout
188
J5
LVTTL
3.3
Low
12
35
None High
data[10]
inout
189
F3
LVTTL
3.3
Low
12
35
None High
data[11]
inout
190
E3
LVTTL
3.3
Low
12
35
None High
data[12]
inout
193
G4
LVTTL
3.3
Low
12
35
None High
data[13]
inout
194
G3
LVTTL
3.3
Low
12
35
None High
data[14]
inout
195
K8
LVTTL
3.3
Low
12
35
None High
GR-TMTC-0002
GAISLER
130
Name
I/O
Pin
CQ352
Pin
CG624
Level
Volt.
Slew
Load
Drive [pF]
Pull
Polarity
data[15]
inout
196
L8
LVTTL
3.3
Low
12
35
None High
data[16]
inout
199
W2
LVTTL
3.3
Low
12
35
None High
data[17]
inout
200
Y2
LVTTL
3.3
Low
12
35
None High
data[18]
inout
201
R6
LVTTL
3.3
Low
12
35
None High
data[19]
inout
202
T6
LVTTL
3.3
Low
12
35
None High
data[20]
inout
205
T7
LVTTL
3.3
Low
12
35
None High
data[21]
inout
206
U7
LVTTL
3.3
Low
12
35
None High
data[22]
inout
207
V2
LVTTL
3.3
Low
12
35
None High
Note
data[23]
inout
208
R4
LVTTL
3.3
Low
12
35
None High
data[24]
inout
211
T4
LVTTL
3.3
Low
12
35
None High
data[25]
inout
212
R3
LVTTL
3.3
Low
12
35
None High
data[26]
inout
213
R5
LVTTL
3.3
Low
12
35
None High
data[27]
inout
214
AA1
LVTTL
3.3
Low
12
35
None High
data[28]
inout
217
AB1
LVTTL
3.3
Low
12
35
None High
data[29]
inout
218
R8
LVTTL
3.3
Low
12
35
None High
data[30]
inout
219
T8
LVTTL
3.3
Low
12
35
None High
data[31]
inout
220
W1
LVTTL
3.3
Low
12
35
None High
Data, MSB
cb[0]
inout
160
V4
LVTTL
3.3
Low
12
35
None High
Checkbits, LSB
cb[1]
inout
161
Y5
LVTTL
3.3
Low
12
35
None High
cb[2]
inout
164
W5
LVTTL
3.3
Low
12
35
None High
cb[3]
inout
165
U6
LVTTL
3.3
Low
12
35
None High
cb[4]
inout
166
U5
LVTTL
3.3
Low
12
35
None High
cb[5]
inout
167
U3
LVTTL
3.3
Low
12
35
None High
cb[6]
inout
170
T2
LVTTL
3.3
Low
12
35
None High
cb[7]
inout
171
U2
LVTTL
3.3
Low
12
35
None High
Checkbits, MSB
ramsn[0]
out
146
M2
LVTTL
3.3
Low
12
35
None Low
SRAM chip select
ramsn[1]
out
147
P4
LVTTL
3.3
Low
12
35
None Low
ramsn[2]
out
152
P1
LVTTL
3.3
Low
12
35
None Low
ramsn[3]
out
153
P6
LVTTL
3.3
Low
12
35
None Low
ramsn[4]
out
142
P5
LVTTL
3.3
Low
12
35
None Low
ramsn[5]
out
323
G20
LVTTL
3.3
Low
12
35
None Low
ramsn[6]
out
324
F20
LVTTL
3.3
Low
12
35
None Low
ramsn[7]
out
331
F19
LVTTL
3.3
Low
12
35
None Low
ramoen[0]
out
154
P3
LVTTL
3.3
Low
12
35
None Low
ramoen[1]
out
155
N4
LVTTL
3.3
Low
12
35
None Low
ramoen[2]
out
158
U1
LVTTL
3.3
Low
12
35
None Low
ramoen[3]
out
159
T1
LVTTL
3.3
Low
12
35
None Low
ramoen[4]
out
143
R2
LVTTL
3.3
Low
12
35
None Low
ramoen[5]
out
325
E18
LVTTL
3.3
Low
12
35
None Low
ramoen[6]
out
326
F18
LVTTL
3.3
Low
12
35
None Low
ramoen[7]
out
332
G21
LVTTL
3.3
Low
12
35
None Low
GR-TMTC-0002
SRAM output enable
GAISLER
131
Name
I/O
Pin
CQ352
Pin
CG624
Level
Volt.
Slew
Load
Drive [pF]
Pull
Polarity
rwen[0]
out
272
H3
LVTTL
3.3
Low
12
35
None Low
rwen[1]
out
271
G2
LVTTL
3.3
Low
12
35
None Low
rwen[2]
out
270
E1
LVTTL
3.3
Low
12
35
None Low
rwen[3]
out
269
D1
LVTTL
3.3
Low
12
35
None Low
ramben[0]
out
N/A
Y1
LVTTL
3.3
Low
12
35
None Low
ramben[1]
out
N/A
P2
LVTTL
3.3
Low
12
35
None Low
ramben[2]
out
N/A
K7
LVTTL
3.3
Low
12
35
None Low
ramben[3]
out
N/A
K6
LVTTL
3.3
Low
12
35
None Low
Note
SRAM write strobe 1)
SRAM read/write byte enable1)
romsn[0]
out
288
N2
LVTTL
3.3
Low
12
35
None Low
romsn[1]
out
287
R1
LVTTL
3.3
Low
12
35
None Low
romsn[2]
out
276
U23
LVTTL
3.3
Low
12
35
None Low
{non standard pinout for GR-TMTC-MEZZ}
romsn[3]
out
275
Y24
LVTTL
3.3
Low
12
35
None Low
{non standard pinout for GR-TMTC-MEZZ}
romsn[4]
out
77
U24
LVTTL
3.3
Low
12
35
None Low
romsn[5]
out
82
AA24
LVTTL
3.3
Low
12
35
None Low
romsn[6]
out
85
H20
LVTTL
3.3
Low
12
35
None Low
romsn[7]
out
341
H19
LVTTL
3.3
Low
12
35
None Low
oen
out
283
N1
LVTTL
3.3
Low
12
35
None Low
PROM output enable
writen
out
284
P7
LVTTL
3.3
Low
12
35
None Low
PROM write strobe
Note 1:
PROM chip select
Refer to signal definitions of each memory controller for detailed usage of these signals.
GR-TMTC-0002
GAISLER
21.3
132
RTAX2000S specific pins - CQ352 package
The Actel RTAX2000S FPGA device has special pins that need to be correctly connected on the
printed circuit board, as shown in table 114. Please refer to the Actel data sheet [RTAX] for details.
Table 114.RTAX2000S special pins - CQ352 package
Name
Pin CQ352
GND
1, 9, 15, 21, 27, 33, 39, 45, 51, 57, 63, 69, 75, 81, 88, 89, 97, 103, Low supply voltage, ground
109, 115, 121, 133, 145, 151, 157, 163, 169, 176, 177, 186, 192,
198, 204, 210, 216, 222, 228, 234, 240, 246, 252, 258, 264, 265,
274, 280, 286, 292, 298, 310, 322, 330, 334, 340, 345, 352
Note
VCCA
3, 14, 32, 56, 74, 87, 102, 114, 150, 162, 175, 191, 209, 233, 251, 1.5 V supply voltage for array
263, 279, 291, 329, 339
VCCDA
2, 44, 90, 91, 116, 117, 130, 131, 132, 148, 149, 174, 178, 221,
266, 268, 293, 294, 307, 308, 309, 327, 328, 346
3.3 V supply voltage for I/O differential amplifier and JTAG
and probe interfaces.
VCCIB0
321, 333, 344
3.3 V supply voltage for I/O
VCCIB1
273, 285, 297
VCCIB2
227, 239, 245, 257
VCCIB3
185, 197, 203, 215
VCCIB4
144, 156, 168
VCCIB5
96, 108, 120
VCCIB6
50, 62, 68, 80
VCCIB7
8, 20, 26, 38
VCCIB7
8, 20, 26, 38
VPUMP
267
Voltage External Pump. In normal operation, using the internal charge pump, should be tied to ground.
TRST
351
JTAG Test Clock. Actel recommends this pin be hardwired
to ground for flight.
TCK
349
to ground. Must not be left unconnected.
TDI
348
JTAG Test Data Input. Actel recommends this pin be hardwired to VCCDA, or left unconnected.
TDO
347
JTAG Test Data Output. Must be left unconnected.
TMS
350
JTAG Test Mode Select. Actel recommends that this pin be
hardwired to VCCDA, or left unconnected.
PRA
312
Test Probe. The pins’ probe capabilities are disabled to protect programmed design confidentiality. These pins must be
left unconnected.
PRB
311
PRC
135
PRD
134
NC
124, 125, 126, 127, 138, 139, 140, 141, 301, 302, 303, 304, 315, No Connection. Pins are not connected to circuitry within
316, 317, 318
the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
CLK*
122, 123, 128, 129, 136, 137, 142, 143
Global clocks. When pins are unused, Actel recommends
they are tied to known state, preferably ground.
HCLK*
299, 300, 305, 306, 313, 314, 319, 320
Hardwired clocks. When pins are unused, it is recommended
that they are tied to ground.
GR-TMTC-0002
GAISLER
21.4
133
RTAX2000S specific pins - CG624 package
The Actel RTAX2000S FPGA device has special pins that need to be correctly connected on the
printed circuit board, as shown in table 114. Please refer to the Actel data sheet [RTAX] for details.
Table 115.RTAX2000S special pins - CG624 package
Name
Pin CG624
GND
A18, A24, A25, A2, A8, AA10, AA16, AA18, AA21, AA5,
Low supply voltage, ground
AB22, AB4, AC10, AC16, AC23, AC3, AD1, AD2, AD24,
AD25, AE1, AE18, AE24, AE2, AE25, AE8, B1, B2, B25, B24,
C10, C16, C23, C3, D22, D4, E10, E16, E21, E5, E8, H1, H21,
H25, K21, K23, K3, K5, L11, L12, L13, L14, L15, M11, M12,
M13, M14, M15, N11, N12, N13, N14, N15, P11, P12, P13, P14,
P15, R11, R12, R13, R14, R15, T21, T23, T3, T5, V1, V25, V5
Note
VCCA
AB20, F22, F4, J17, J9, K10, K11, K15, K16, L10, L16, R10,
R16, T10, T11, T15, T16, U17, U9, Y4
VCCDA
A12, A14, AA13, AA15, AA20, AA7, AB13, AC11, AD11,
3.3 V supply voltage for I/O differential amplifier and JTAG
AD4, AE12, AE17, B15, C15, C6, D13, E13, E19, F21, G10, G5, and probe interfaces.
N21, N5, W21
VCCIB0
A3, B3, C4, D5, J10, J11, K12
VCCIB1
A23, B23, C22, D21, J15, J16, K14
VCCIB2
C24, C25, D23, E22, K17, L17, M16
VCCIB3
AA22, AB23, AC24, AC25, P16, R17, T17
VCCIB3
AA22, AB23, AC24, AC25, P16, R17, T17
VCCIB4
AB21, AC22, AD23, AE23, T14, U15, U16
VCCIB5
AB5, AC4, AD3, AE3, T12, U10, U11
VCCIB6
AA4, AB3, AC1, AC2, P10, R9,T9
VCCIB7
C1, C2, D3, E4, K9, L9, M10
VPUMP
E20
Voltage External Pump. In normal operation, using the internal charge pump, should be tied to ground.
TRST
E6
to ground for flight.
TCK
F5
to ground. Must not be left unconnected.
TDI
C5
JTAG Test Data Input. Actel recommends that this pin be
hardwired to VCCDA, or left unconnected.
1.5 V supply voltage for array
TDO
F6
JTAG Test Data Output. Must be left unconnected.
TMS
D6
JTAG Test Mode Select. Actel recommends this pin be hardwired to VCCDA, or left unconnected.
PRA
F13
Test Probe. The pins’ probe capabilities are disabled to protect programmed design confidentiality. These pins must be
left unconnected.
PRB
A13
PRC
AB12
PRD
AE13
NC
AA12, AA14, E12, E14, F12, F14, H12, H14, J12, J14, U12,
U14, V12, V14, Y12, Y14
No Connection. Pins are not connected to circuitry within
the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
CLK*
AC12, AC13, AD12, AD13, W14, W15, W13, Y13
Global clocks. When pins are unused, Actel recommends
they are tied to known state, preferably ground.
CLKH*
B13, B14, C12, C13, G12, G13, G14, G15
Hardwired clocks. When pins are unused, it is recommended
that they are tied to ground.
GR-TMTC-0002
GAISLER
21.5
134
Package figure
21.6
Mechanical drawing
21.7
Weight
21.8
Package materials
21.9
Thermal characteristics
GR-TMTC-0002
GAISLER
22
135
Reference documents
[GRLIB]
GRLIB IP Library User's Manual, Aeroflex Gaisler
[GRIP]
GRLIB IP Core User's Manual, Aeroflex Gaisler
[TMTC]
Spacecraft Data Handling IP Core User’s Manual, Aeroflex Gaisler
[AMBA]
AMBA Specification, Rev 2.0, ARM IHI 0011A, Issue A, ARM Limited
[CCSDS-131.0]
CCSDS 131.0-B-1 TM Synchronization and Channel Coding
[CCSDS-132.0]
CCSDS 132.0-B-1 TM Space Data Link Protocol
[CCSDS-133.0]
CCSDS 133.0-B-1 Space Packet Protocol
[CCSDS-732.0]
CCSDS 732.0-B-2 AOS Space Data Link Protocol
[ECSS-50-01A]
ECSS-E-50-01A Space engineering - Space data links - Telemetry synchronization and channel coding
[ECSS-50-03A]
ECSS-E-50-03A Space engineering - Space data links - Telemetry
transfer frame protocol
[ECSS-50-05A]
ECSS-E-50-05A Space engineering - Radio frequency and modulation
[PSS-04-103]
ESA PSS-04-103 Telemetry channel coding standard
[PSS-04-105]
ESA PSS-04-105 Radio frequency and modulation standard
[PSS-04-106]
ESA PSS-04-106 Packet telemetry standard
[CCSDS-231.0]
CCSDS 231.0-B-1 TC Synchronization and Channel Coding
[CCSDS-232.0]
CCSDS 232.0-B-1 TC Space Data Link Protocol
[CCSDS-232.1]
CCSDS 232.1-B-1 Communications Operation Procedure-1
[ECSS-50-04A]
ECSS-E-50-04A Space data links – Telecommand protocols, synchronization and channel coding
[PSS-04-151]
ESA PSS-04-151 Telecommand Decoder Standard
[SPW]/[ECSS-50-12C]
ECSS - Space Engineering, SpaceWire - Links, Nodes, Routers and
Networks, ECSS-E-ST-50-12C, 31 July 2008
[RMAPID]/[ECSS-50-11C]
ECSS - Space Engineering, SpaceWire Protocols, ECSS-E-ST-50-11C,
Draft 1.3, July 2008
[RMAP]/[ECSS-50-11C]
ECSS - Space Engineering, SpaceWire Protocols, ECSS-E-ST-50-11C,
Draft 1.3, July 2008
[RTAX]
RTAX-S/SL RadTolerant FPGAs, 5172169-12/5.09, v5.4, May 2009,
Actel Corporation
[PACK]
Package Mechanical Drawings, 5193068-34/2.09, v11.0, February
2009, Actel Corporation
GR-TMTC-0002
GAISLER
23
136
Ordering information
Ordering information is provided in table 116 and a legend is provided in table 117.
Table 116.Ordering information
Product
Note
GR-TMTC-RTAX
ReedDevice
Solomon
Speed Grade Package Lead
Type
Count
STD -1
EV
E
B
No
STD -1
EV
E
B
RTAX2000S
CQ
352
Application
Table 117.Ordering legend
Designator
Option
Description
Product
GR-TMTC-RTAX
Telemetry Encoder and Telecommand Decoder
Reed-Solomon
Yes / No
Optional Reed-Solomon protected SDRAM memory
Device
RTAX2000S
2,000,000 Equivalent System Gates
Speed Grade
Package Type
Application
RTAX2000SL
2,000,000 Equivalent System Gates - Low-Power Option
STD
Standard Speed
-1
Approximately 15% Faster than Standard
CQ
Ceramic Quad Flat Pack
CG
Ceramic Column Grid Array
LG
Land Grid Array
B
MIL-STD-883 Class B
E
Actel Extended Flow (Actel Space-Level Flow)
EV
Class V Equivalent Flow Processing Consistent with MIL-PRF 38535
Commercial quality AX2000 components can be supplied for prototyping. The footprint corresponds
to either a CQ352 or a CG624 package. The prototyping component is supplied in a FG896 package
and should be used with an FG896-to-CQ352 or an FG896-to-CG624 adapter, respectively. This
allows the use of the same footprint on prototyping and flight boards. The pinout of the prototyping
component (i.e. the FG896 package) can be provided upon request.
Prototyping components can also be supplied in CQ352 and CG624 packages.
GR-TMTC-0002
GAISLER
24
137
Change record
Change record information is provided in table 118.
Table 118.Change record
Issue
Date
1.5
2009 December 4.7.7, 4.8
1.4
1.3
1.2
1.1
1.0
Sections
Note
Added ongoing and status bits for Virtual Channels 3-6
4.75, 4.8
Difference made between external (power-on) reset and internal
software controlled reset via control registers.
8.9
Telecommand channel reset and enable re-introduced for DMA
only (software commands), but not for Coding Layer. It is thus not
possible to reset or to disable the Coding Layer by software access
to registers (and subsequently the hardware commands cannot be
affected by software).
2009 December 12.1
Amount of on-chip memory corrected
2.4, 4.10, 10.6, 16.3
Fixed clock frequencies clarified
1.7, 12.1, 12.3
On-chip memory error counter and automatic scrubber unused.
2.2, 3.12
Manchester encoding clarified and IEEE 802.3 waveform added
4.7.4, 4.8
Clarified interrupt usage etc. for different Virtual Channels
2009 November 1.4.3, 2.1, 9.1.1, 9.2.1, 9.2.59.2.8, 9.3
Hardware commands carried in CCSDS Space Packets
8.9
Register definition for telecommand decoder clarified
15
Interrupt controller updated
4.10, 9.5, 10.6, 11.6, 14.5,
15.5
Clock to output timing increased to meet high utilization
4.9, 4.10, 8.10, 8.11, 9.4, 9.5
CLCW signal and timing added
1.4.2, 2.1, 8.6
Both CLCW registers are used for software telecommands
10.6
SpaceWire transmit clock period corrected
4.9, 4.10
Telemetry transmit clock period defined
11.1, 11.2, 11.4
8-bit PROM support removed, read-modify-write introduced
21.2
Modified CG624 pinout for prototype board
21.2
Increased drive on SpaceWire transmit signals
2009 November 4.7.4
Introduction of automatic telemetry after reset
1.3, 14.2, 14.3, 2.1, 2.2, 2.8,
3.11, 8.6, 21.2
Introduction of CLCW cross-strapping capability
4.3.5
Bandwidth allocation clarified
4.5.2
Clock division constraints clarified regarding 50% duty cycle of
output clock and Manchester encoded output.
2009 November 2.2, 2.7 2.8, 21.2
Added third SpaceWire interface, introduced three AMBA buses
5.1, 5.3
Virtual Channel input interface: available size set to 518 octets
2.6, 5.3
Added interrupts for Virtual Channel 3-6, and enable bit to register
2.8, 9, 21.2
Added additional hardware telecommands
1.7
Clarified size of on-chip memory and dedicated descriptor memory
4.3.3, 4.3.5, 4.8, 6, 7
Virtual Channel 3-6 interaction with telemetry encoder described
2.5
Added telemetry IP cores to listing
2009 September All
New document
GR-TMTC-0002
GAISLER
138
Information furnished by Aeroflex Gaisler is believed to be accurate and reliable.
However, no responsibility is assumed by Aeroflex Gaisler for its use, nor for any infringements of patents or
other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler.
Aeroflex Gaisler AB
tel +46 31 7758650
Kungsgatan 12
fax +46 31 421407
411 19 Göteborg
sales@gaisler.com
Sweden
www.gaisler.com
GAISLER
Copyright © 2009 Aeroflex Gaisler AB.
All information is provided as is. There is no warranty that it is correct or suitable for any purpose, neither
implicit nor explicit.
GR-TMTC-0002

GR-TMTC-0002 Data Sheet and User`s Manual

Transcription

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