UC Berkeley Technical Report

Transcription

BSIM-CMG 106.0.0
Multi-Gate MOSFET Compact Model
Technical Manual
Authors:
Sriramkumar V., Navid Paydavosi,
Darsen Lu, Chung-Hsun Lin,
Mohan Dunga, Shijing Yao, Tanvir Morshed,
Ali Niknejad, and Chenming Hu
Project Director:
Prof. Ali Niknejad and Prof. Chenming Hu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720
Copyright 2012
The Regents of University of California
All Right Reserved
Nondisclosure Statement
The content of BSIM-CMG model (including source code, manual, technical note,
and equation list) is currently distributed by BSIM Group, a research group at EECS
Department, University of California at Berkeley, to designated Receiving Parties only.
The content of BSIM-CMG model can not be distributed by Receiving Party to any
third party without written agreement by BSIM Group.
Contents
1 Introduction
5
2 Model Description
5
3 BSIM-CMG 106.0.0 Model Equations
7
3.1
Bias Independent Calculations . . . . . . . . . . . . . . . . . . . . . . . .
7
3.2
Terminal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
3.3
Short Channel Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
3.4
Surface Potential Calculation . . . . . . . . . . . . . . . . . . . . . . . .
17
3.5
Drain Saturation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
3.6
Average Potential, Charge and Related Variables . . . . . . . . . . . . .
27
3.7
Quantum Mechanical Effects . . . . . . . . . . . . . . . . . . . . . . . . .
27
3.8
Mobility degradation and series resistance . . . . . . . . . . . . . . . . .
29
3.9
Output Conductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
3.10 Velocity Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
3.11 Drain Current Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.12 Intrinsic Capacitance Model . . . . . . . . . . . . . . . . . . . . . . . . .
33
3.13 Parasitic resistances and capacitance models . . . . . . . . . . . . . . . .
36
3.14 Impact Ionization and GIDL/GISL Model . . . . . . . . . . . . . . . . .
51
3.15 Gate Tunneling Current . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
3.16 Non Quasi-static Models . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
3.17 Generation-recombination Component . . . . . . . . . . . . . . . . . . .
60
3.18 Junction Current and capacitances . . . . . . . . . . . . . . . . . . . . .
60
3.19 Self-heating model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
3.20 Noise Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
4 Simulation Outputs
72
3
5 Parameter Extraction Procedure
5.1
73
Global Parameter Extraction . . . . . . . . . . . . . . . . . . . . . . . . .
73
5.1.1
Basic Device Parameter List . . . . . . . . . . . . . . . . . . . . .
73
5.1.2
Parameter Initialization . . . . . . . . . . . . . . . . . . . . . . .
75
5.1.3
Linear region . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
5.1.4
Saturation region . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
5.1.5
Other Parameters representing important physical effects . . . . .
83
5.1.6
Smoothing between Linear and Saturation regions . . . . . . . . .
83
5.1.7
Other Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
6 Complete Parameter List
86
6.1
Instance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
6.2
Model Controllers and Process Parameters . . . . . . . . . . . . . . . . .
87
6.3
Basic Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
6.4
Parameters for geometry-dependent parasitics . . . . . . . . . . . . . . . 100
6.5
Parameters for Temperature Dependence and Self-heating
6.6
Parameters for Variability Modeling . . . . . . . . . . . . . . . . . . . . . 104
7 History of BSIM-MG Models
. . . . . . . . 102
105
4
1
Introduction
The continuous evolution and enhancement of planar bulk CMOS technology has
fueled the growth of the microelectronics industry for the past several decades. When
we reach the end of the technology roadmap for the classical CMOS, multiple gate
MOSFETs (MuGFETs) will likely take up the baton. We have developed a multiple
gate MOSFET compact model for technology/circuits development in the short term
and for product design in the longer term [1].
Several different MuGFET structures and two different modes of operation are being
pursued in the industry today. In the case of horizontal double gate (DG), the two gates
will likely be asymmetric– having different work functions and underlying dielectric
thicknesses, complicating the compact model. Also, the two gates are likely to be biased
at two different voltages, known as independent gates. In the other double, triple, or
all-around gate cases, the gates are biased at the same voltage, known as the common
gate. Some designs will use lightly doped body to maximize mobility, others will use
very high doping concentrations in thin body to obtain sufficient Vt adjustment.
BSIM-CMG has been developed to model the electrical characteristics of MG structures. The details of the model will be described in this document. It will serve the needs
of all circuit designer/ technology developers by providing versatility without compromising ease of use and computational efficiency. The model currently addresses common
gate devices. A separate model BSIM-IMG addresses independent gate devices [2].
2
Model Description
BSIM-CMG is implemented in Verilog-A. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping.
The surface potentials at the source and drain ends are solved analytically with polydepletion and quantum mechanical effects. The effect of finite body doping is captured
through a perturbation approach. The analytic surface potential solution agrees with
2-D device simulation results well. If the channel doping concentration is low enough to
be neglected, computational efficiency can be further improved by setting COREMOD
= 1.
All the important MG transistor behaviors are captured by this model. Volume inversion is included in the solution of the Poisson’s equation, hence the subsequent I-V
5
formulation automatically captures the volume inversion effect. Analysis of the electrostatic potential in the body of MG MOSFETs provided the model equation for the short
channel effects (SCE). The extra electrostatic control from the end-gates (top/bottom
gates) (triple or quadruple-gate) is also captured in the short channel model.
Users can specify the MG structure of interest via a geometry mode selector (GEOMOD, DG = 0, TG = 1, QG = 2, CG = 3). Hybrid-surface-orientation mobility,
corner-induced effective width reduction, and end-channel-enhanced electrostatic control are considered to address the physics of tri-gate (TG) and quadruple-gate (QG)
devices.
BSIM-CMG provides the flexibility to model devices with novel materials. This
includes parameters for non-silicon channel devices and High-K/ Metal-gate stack.
Other important effects, such as, mobility degradation, velocity saturation, velocity
overshoot, series resistance, channel length modulation, quantum mechanical effects,
gate tunneling current, gate-induced-drain-leakage, temperature effects, channel thermal
noise, flicker noise, noise associated with device parasitics, and parasitic capacitance, are
also incorporated in the model.
BSIM-CMG has been verified with industrial experimental data. The model is continuous and symmetric at Vds = 0. This physics-based model is scalable and predictive
over a wide range of device parameters.
6
3
BSIM-CMG 106.0.0 Model Equations
3.1
Bias Independent Calculations
Physical Constants
Physical quantities in BSIM-CMG are in M.K.S units unless specified otherwise.
q = 1.6 × 10−19
(3.1)
0 = 8.8542 × 10−12
(3.2)
h̄ = 1.05457 × 10−34
(3.3)
me = 9.11 × 10−31
(3.4)
k = 1.3787 × 10−23
(3.5)
sub = EP SRSU B · 0
(3.6)
ox = EP SROX · 0
3.9 · 0
Cox =
EOT
sub
Csi =
T F IN
EP SRSU B
ratio =
3.9
(3.7)
(3.8)
(3.9)
(3.10)
Effective Channel Width, Channel Length and Fin Number
LL
(L + XL)LLN
LLC
= DLC +
(L + XL)LLN
∆L = LIN T +
(3.11)
∆LCV
(3.12)
Lef f = L + XL − 2∆L
(3.13)
Lef f,CV = L + XL − 2∆LCV
(3.14)
If GEOM OD = 0 then
Wef f 0 = 2 · HF IN − DELT AW
(3.15)
Wef f,CV 0 = 2 · HF IN − DELT AW CV
(3.16)
7
If GEOM OD = 1 then
Wef f 0 = 2 · HF IN + F ECH · T F IN − DELT AW
(3.17)
Wef f,CV 0 = 2 · HF IN + F ECH · T F IN − DELT AW CV
(3.18)
If GEOM OD = 2 then
Wef f 0 = 2 · HF IN + 2 · F ECH · T F IN − DELT AW
(3.19)
Wef f,CV 0 = 2 · HF IN + 2 · F ECH · T F IN − DELT AW CV
(3.20)
If GEOM OD = 3 then
D
2
Wef f 0 = π · D − DELT AW
(3.21)
R=
(3.22)
Wef f,CV 0 = π · D − DELT AW CV
(3.23)
N F INtotal = N F IN × N F
(3.24)
Geometry-dependent source/drain resistance
Please refer to section 3.13.
Quantum Mechanical Effects
The following bias-independent calculations are for the threshold voltage shift and bias dependence of inversion charge centroid due to quantum mechanical confinement. See section on
’Surface Potential Calculation’ and ’Quantum Mechanical Effects’ for more details.
mx = 0.916 · me
(3.25)
m0x = 0.190 · me
(3.26)
md = 0.190 · me
(3.27)
m0d = 0.417 · me
(3.28)
g 0 = 4.0
(3.29)
g = 2.0
(3.30)
8
If GEOM OD = 0 then
M T cen = 1 + AQM T CEN · exp(−
T F IN
)
BQM T CEN
(3.31)
min(HF IN, T F IN )
)
BQM T CEN
(3.32)
min(HF IN, T F IN )
)
BQM T CEN
(3.33)
R
)
BQM T CEN
(3.34)
If GEOM OD = 1 then
If GEOM OD = 2 then
If GEOM OD = 3 then
Binning Calculations
The optional binning methodology [3] is adopted in BSIM-MG.
For a given L, NFIN, each model parameter P ARAMi is calculate as a function of PARAM,
a length dependent term, LPARAM, a number of fin per finger(NFIN) dependent term,
NPARAM and a product L × N F IN term, PPARAM:
P ARAMi = P ARAM +
Lef f
10−6
1.0
· LP ARAM +
· N P ARAM +
+ DLBIN
N F IN
10−6
N F IN · (Lef f + DLBIN )
· P P ARAM
(3.35)
For the list of binable parameters, please refer to the complete parameter list in the end
of this technical note.
9
Length scaling equations

U 0i · 1 − U Pi · Lef f −LP A LP A > 0
U 0[L] =
U 0 · [1 − U P ]
Otherwise
i
i
(3.36)
M EXP [L] = M EXPi + AM EXP · Lef f −BM EXP
Lef f
P CLM [L] = P CLMi + AP CLM · exp −
BP CLM
(3.37)
(3.38)
Lef f
U A[L] = U Ai + AU A · exp −
BU A
Lef f
U D[L] = U Di + AU D · exp −
BU D
(3.39)
(3.40)
(3.41)
If RDSM OD = 0 then
Lef f
RDSW [L] = RDSWi + ARDSW · exp −
BRDSW
(3.42)
If RDSM OD = 1 then
Lef f
RSW [L] = RSWi + ARSW · exp −
BRSW
Lef f
RDW [L] = RDWi + ARDW · exp −
BRDW
Lef f
P T W G[L] = P T W Gi + AP T W G · exp −
BP T W G
Lef f
V SAT [L] = V SATi + AV SAT · exp −
BV SAT
Lef f
V SAT 1[L] = V SAT 1i + AV SAT 1 · exp −
BV SAT 1
10
(3.43)
(3.44)
(3.45)
(3.46)
(3.47)
Temperature Effects
T = $temperature + DT EM P
(3.48)
T BGASU B · T N OM 2
(3.49)
T N OM + T BGBSU B
T BGASU B · T 2
(3.50)
Eg = BG0SU B −
T + T BGBSU B
3
2
Eg · q
T
BG0SU B · q
ni = N I0SU B ·
· exp
(3.51)
−
300.15
2k · 300.15
2k · T
3
2
T
Nc = N C0SU B ·
(3.52)
300.15
N SD · N BODY
kT
)
(3.53)
· ln (
Vbi =
q
n2i
N BODY
ΦB = Vt · ln (
)
(3.54)
ni
KT 1L
T
∆Vth,temp = KT 1 +
·
− 1 + KT 2 · (Vbgx − ∆Φ2 ) + KT 3 · Vdsx
Lef f
T N OM
Eg,T N OM = BG0SU B −
(3.55)
µ0 (T ) = U 0[L] ·
T
T N OM
U T Ei
· [1 + U T Li · (T − T N OM )]
U A(T ) = U A[L] · [1 + U A1i · (T − T N OM )]
U D1i
T
U D(T ) = U D[L] ·
T N OM
U CST Ei
T
U CS(T ) = U CSi ·
T N OM
(3.56)
(3.57)
(3.58)
(3.59)
(3.60)
11
V SAT (T ) = V SAT [L] · (1 − AT · (T − T N OM ))
(3.61)
V SAT 1(T ) = V SAT 1[L] · (1 − AT · (T − T N OM ))
(3.62)
P T W G(T ) = P T W G[L] · (1 − P T W GT · (T − T N OM ))
(3.63)
M EXP (T ) = M EXP [L] · (1 + T M EXP · (T − T N OM ))
IIT
T
BET A0(T ) = BET A0i ·
T N OM
T
−1
SII0(T ) = SII0i 1 + T II
T N OM
(3.64)
(3.65)
BGIDL(T ) = BGIDLi · (1 + T GIDL · (T − T N OM ))
(3.67)
BGISL(T ) = BGISLi · (1 + T GIDL · (T − T N OM ))
(3.68)
RDSW M IN (T ) = RDSW M IN · (1 + P RT · (T − T N OM ))
(3.69)
RDSW (T ) = RDSW [L] · (1 + P RT · (T − T N OM ))
(3.70)
RSW M IN (T ) = RSW M IN · (1 + P RT · (T − T N OM ))
(3.71)
RDW M IN (T ) = RDW M IN · (1 + P RT · (T − T N OM ))
(3.72)
RSW (T ) = RSW [L] · (1 + P RT · (T − T N OM ))
(3.73)
RDW (T ) = RDW [L] · (1 + P RT · (T − T N OM ))
(3.74)
Rs,geo (T ) = Rs,geo · (1 + P RT · (T − T N OM ))
(3.75)
Rd,geo (T ) = Rd,geo · (1 + P RT · (T − T N OM ))
IGTi
T
Igtemp =
T N OM
(3.76)
12
(3.66)
(3.77)
T3s = exp
qEg,T N OM
k·T N OM
−
qEg
kT
+ XT IS · ln
N JS
T
T N OM
!
(3.78)
Jss (T ) = JSS · T3s
(3.79)
Jssws (T ) = JSW S · T3s
(3.80)
Jsswgs (T ) = JSW GS · T3s
T3d = exp
qEg,T N OM
k·T N OM
−
qEg
kT
(3.81)
+ XT ID · ln
N JD
T
T N OM
!
(3.82)
Jsd (T ) = JSD · T3d
(3.83)
Jsswd (T ) = JSW D · T3d
(3.84)
Jsswgd (T ) = JSW GD · T3d
(3.85)
CJS(T ) = CJS · [1 + T CJ · (T − T N OM )]
(3.86)
CJD(T ) = CJD · [1 + T CJ · (T − T N OM )]
(3.87)
CJSW S(T ) = CJSW S · [1 + T CJSW · (T − T N OM )]
(3.88)
CJSW D(T ) = CJSW D · [1 + T CJSW · (T − T N OM )]
(3.89)
CJSW GS(T ) = CJSW GS · [1 + T CJSW G · (T − T N OM )]
(3.90)
CJSW GD(T ) = CJSW GD · [1 + T CJSW G · (T − T N OM )]
(3.91)
P BS(T ) = P BS(T N OM ) − T P B · (T − T N OM )
(3.92)
P BD(T ) = P BD(T N OM ) − T P B · (T − T N OM )
(3.93)
P BSW S(T ) = P BSW S(T N OM ) − T P BSW · (T − T N OM )
(3.94)
P BSW D(T ) = P BSW D(T N OM ) − T P BSW · (T − T N OM )
(3.95)
P BSW GS(T ) = P BSW GS(T N OM ) − T P BSW G · (T − T N OM )
(3.96)
P BSW GD(T ) = P BSW GD(T N OM ) − T P BSW G · (T − T N OM )
(3.97)
13
Body Doping and Gate Workfunction
If COREM OD = 1 and N BODYi > 1023 m−3 then
nbody = 1023 m−3
(3.98)
nbody = N BODYi
(3.99)
else
If N GAT Ei > 0 then
∆Φ = max(0,
Eg
kT
N GAT Ei
−
· ln (
))
2
q
ni
(3.100)
else

P HIGi − EASU B
∆Φ =
(EASU B + E ) − P HIG
g
i
for NMOS,
(3.101)
for PMOS.
nbody
kT
· ln (
)
q
ni
Eg kT
N SDi
,
· ln (
)
φSD = min
2 q
ni

P HIGi − (EASU B + Eg − φSD )
for NMOS,
2
h
i
Vf bsd =
− P HIG − (EASU B + Eg + φ ) for PMOS.
i
SD
2
φB =
If GEOM OD 6= 3 then
p
2q sub nbody
γ0 =
Cox
1 qnbody T F IN 2
φbulk =
2 sub
2
(3.102)
(3.103)
(3.104)
(3.105)
(3.106)
φpert = min(φbulk , 0.4)
p
Qbulk = 2qnbody sub φpert
(3.107)
(3.108)
14
tox =
qbs =

 EOT ·ox
if GEOM OD 6= 3
3.9
R · exp EOT ·ox − 1 if GEOM OD = 3
R·3.9

 q·nbody ·T F IN if GEOM OD 6= 3
2·Cox
 q·nbody ·R
(3.110)
if GEOM OD = 3
2·Cox
Polysilicon Depletion

 1 q·N GAT2Ei ·sub
Cox
Vpoly0 = 2
 1 q·N GAT Ei ·sub ·
2
C2
ox
χpoly
(3.109)
if GEOM OD 6= 3
R+tox 2
R
(3.111)
if GEOM OD = 3
1
=
4 · Vpoly0
(3.112)
κpoly = 1 + 2 · χpoly · qbs
(3.113)
Short Channel Effects
N SDi · nbody
kT
· ln (
)
q
n2i
r
HF IN
· (HF IN + 2 · ratio · EOT )
Hef f =
8
r

ratio
T F IN

1
+

2
4ratio EOT T F IN · EOT





1

s


1

+ 12

4H
 ratio
T F IN
1+
T F IN ·EOT
ef f
2
4ratio EOT
λ=

0.5

s
1

+ 12

ratio

4H
T F IN

1+
T
F
IN
·EOT
ef f
2

4ratio EOT

r




R
 ratio
1 + 2ratio
2
EOT R · EOT
Vbi =
15
(3.114)
(3.115)
if GEOM OD = 0
if GEOM OD = 1
(3.116)
if GEOM OD = 2
if GEOM OD = 3
3.2
Terminal Voltages
Terminal Voltages and Vdsx Calculation
3.3
Vgs = Vg − Vs
(3.117)
Vgd = Vg − Vd
(3.118)
Vge = Vg − Ve
(3.119)
Vds = Vd − Vs
q
2 + 0.01 − 0.1
Vdsx = Vds
(3.120)
(3.121)
Short Channel Effects
Weighting Function for forward and reverse modes
T 0 = tanh
0.6 ∗ q · Vds
kT
Use un-swapped Vds here
(3.122)
T 1 = 0.5 + 0.5 · T 0
(3.123)
T 2 = 0.5 − 0.5 · T 0
(3.124)
Asymmetric parameters
CDSCDa = CDSCDi · T 1 + CDSCDRi · T 2
(3.125)
ET A0a = ET A0i · T 1 + ET A0Ri · T 2
(3.126)
(3.127)
16
Vt Roll-off, DIBL, and Subthreshold Slope Degradation
ψst = 0.4 + P HINi + ΦB
0.5
Cdsc =
· (CDSCi + CDSCDa · Vdsx )
L f
cosh DV T 1i · ef
−
1
λ

1 +
n=
1 +
CITi +Cdsc
(2Csi )kCox
if GEOM OD 6= 3
CITi +Cdsc
Cox
if GEOM OD = 3
∆Vth,SCE = −
0.5 · DV T 0i
Lef f
λ
cosh DV T 1i ·
∆Vth,DIBL = −
−1
cosh DSU Bi ·
Lef f
λ
(3.129)
(3.130)
· (Vbi − ψst )
0.5 · ET A0a
(3.128)
−1
· Vdsx
(3.132)
"s
∆Vth,RSCE = K1RSCEi ·
3.4
#
p
LP E0i
− 1 · ψst
1+
Lef f
(3.131)
(3.133)
∆Vth,all = ∆Vth,SCE + ∆Vth,DIBL + ∆Vth,RSCE + ∆Vth,temp
(3.134)
Vgsf b = Vgs − ∆Φ − ∆Vth,all − DV T SHIF T
(3.135)
Surface Potential Calculation
Surface potentials at the source and drain ends are derived from the Poisson’s equation with a perturbation method [4] and computed using the Householder’s cubic iteration method [5, 6]. Perturbation allows accurate modeling of finite body doping.
When the body is lightly-doped, a simplified surface potential algorithm can be
activated by setting COREM OD = 1 to enhance computational efficiency.
17
Constants for Surface Potential Calculation
2sub
r1 =
Cox · T F IN

0
if N GAT Ei = 0
r2 =

4·nkT sub
if N GAT Ei > 0
q·T F IN 2 ·N GAT Ei
5 kT
q CSi + 2Qbulk
q0 =
Cox
If GEOM OD = 3 then
2 sub
r1 =
R · Cox

0
r2 =
 2·nkT ·χpoly ·r12
q
q0 =
(3.136)
(3.137)
(3.138)
(3.139)
if N GAT Ei = 0
(3.140)
if N GAT Ei > 0
2 · nkT · r1
q
(3.141)
Body-Doping adjustment for GEOM OD = 0, 1, 2 case
If COREM OD = 1 then
Vgsf b = Vgsf b −
qnbody · T F IN
2Cox
(3.142)
Body-Doping based calculations for GEOM OD = 3 case
qnbody R
Cox
nkT
nkT
nkT
q.T 0
ln
−
ln 1 − exp
Vt,dop = −
q
q · T0
q
2.r1.nkT
q · Vt,dop
cdop = 2 · r1 · exp −
nkT
T0
nkT
0.5 · q · T 0
Vt0 =
+ 2.n.φb −
ln
+ Vt,dop
2
q
nkT
T0 =
18
(3.143)
(3.144)
(3.145)
(3.146)
Quantum Mechanical Vt correction
Note: QM F ACT ORi also serves as a switch here.
h̄2 π 2
2mx · T F IN 2
h̄2 π 2
E00 =
2m0x · T F IN 2
(3.147)
E0 =
(3.148)
E1 = 4E0
(3.149)
E10 = 4E00
(3.150)
g 0 m0d
E0 − E00
E0 − E10
E0 − E1
+
· exp
+ exp
γ = 1 + exp
kT
gmd
kT
kT
g · md
kT
E0 kT
−
ln
·
·γ
∆Vt,QM = QM F ACT ORi ·
2
q
q
πh̄ Nc T F IN
(3.151)
(3.152)
If GEOM OD = 3 then
E0,QM =
h̄2 (2.4048)2
2mx · R2
∆Vt,QM = QM F ACT ORi ·
(3.153)
E0,QM
q
(3.154)
Voltage Limiting for Accumulation
2 · Lef f · 10−15
nkT
T 0 = −(∆Vt,QM +
ln
)
q
µ0 (T ) · Wef f · nkT · Nc · T F IN
T 1 = Vgsf b + T 0 + DELV T RAN D
i
p
1h
Vgsf bef f =
T 1 + (T 1)2 + 4 × 10−8 − T 0
2
If GEOM OD = 3 then
2 · Lef f · 10−15
nkT
T 0 = −(∆Vt,QM +
ln
)
q
µ0 (T ) · Wef f · nkT · ni · R
Eg
T 1 = Vgsf b + T 0 + n · ΦB +
+ DELV T RAN D
2
i
p
1h
Vgsf bef f =
T 1 + (T 1)2 + 4 × 10−8 − T 0 − Vt0
2
19
(3.155)
(3.156)
(3.157)
(3.158)
(3.159)
(3.160)
Case: GEOM OD = 0, 1, 2
Calculations Common to the Source and Drain Surface Potentials
a=e
b=
qφpert
nkT
(3.161)
φbulk
(nkT /q)2
c = 2nkT /q
s
F1 = ln
(3.162)
(3.163)
2
2sub nkT
q 2 Nc T F IN
!
(3.164)
Surface Potential 2-stage Analytical Approximation (COREM OD = 0)

∆Vt,QM
at source
Vch =
∆V
at drain
t,QM + Vdsef f
F =
q(Vgsf bef f − φpert − Vch )
− F1
2nkT
s
Z1 = T an−1
Z2 = T an−1
exp F − r1 ·
(3.165)
(3.166)
φbulk · φpert
φbulk · φpert
− r2 ·
2
n(kT /q)
n(kT /q)2
!!
2ln(1 + eF )
r1 · π · eqφpert /2nkT
(3.167)
(3.168)
β = M IN (Z1, Z2)
(3.169)
T 0 = (1 + β T anβ)
s a
T 2 = β2
−
1
+ b · (φpert − c · ln(Cosβ))
Cos2 β
(3.170)
T 3 = −2 · β + b · c · T an(β) + 2a · β · Sec2 (β) · T 0
(3.172)
(3.171)
T 4 = −2 + 2a · β 2 Sec4 (β)
+ Sec2 (β) 2a + b · c + 8a · βT an(β) + 4a · β 2 T an2 (β)
(3.173)
T 5 = 2T 4 · T an(β)
+ 4 3T 0 · a · βSec4 (β) + T an(β) + 2T 0 · a · Sec2 (β)T an(β)
20
(3.174)
f 0 = ln(β) − ln(Cos(β)) + r1 · T 2 − F + r2 · T 22
r1 · T 3
1
+ T an(β) +
+ r2 · T 3
β
2T 2
1
r1 · T 32 r1 · T 4
f 2 = − 2 + Sec2 (β) −
+
+ r2 · T 4
β
4T 23
2T 2
2
3r1 · T 33 3r1 · T 3 · T 4
f 3 = 3 + 2Sec2 (β)T an(β) +
−
β
8T 25
4T 23
r1 · T 5
+
+ r2 · T 5
2T 2
f1 =
f 0 · f 2 f 02 · (3f 22 − f 1 · f 3)
f0
· 1+
+
β=β−
f1
2f 12
6f 14
(3.175)
(3.176)
(3.177)
(3.178)
(3.179)
Repeat (3.170) to (3.179).
s
!
2sub nkT · nbody
2β
2nkT
ψ0 =
· ln
·
q
TSi
q 2 n2i

ψs = ψ0 − 2nkT ln(Cos(β)) + φpert
q
ψ = ψ − 2nkT ln(Cos(β)) + φ
0
pert + Vdsef f
d
q
(3.180)
at source
(3.181)
at drain
Simplified Surface Potential Approximation (COREM OD = 1)

∆Vt,QM
at source
Vch =
∆V
at drain
t,QM + Vdsef f
(3.182)
q(Vgsf bef f − Vch )
− F1
2nkT
Z1 = T an−1 (exp(F ))
F
−1 2ln(1 + e )
Z2 = T an
r1 · π
(3.184)
β = M IN (Z1, Z2)
(3.186)
F =
(3.183)
(3.185)
21
f 0 = ln(β) − ln(Cos(β)) + r1 · β · T an(β) + r2 · β 2 · T an2 (β) − F
1
f 1 = + β · Sec2 (β) [r1 + 2 · r2 · β · T an(β)] +
β
(3.187)
T an(β) [1 + r1 + 2 · r2 · β · T an(β)]
"
2
f 2 = Sec (β) 1 + 2 r1 + r2 · β 2 · Sec2 (β) + r1 · β · T an(β)
(3.188)
#
1 + 2 2 · r2 · β 2 · T an2 (β) − 1
+ 2 · r2 · β 2 T an2 (β) + 2β · T an(β)
β
2
4
f 3 = 3 + 2 · β · Sec (β) r1 + 2 · r2 · 3 + 4βT an(β)
β
2
+ 2Sec (β)T an(β) · 1 + 3 · r1
2
2
+ 2 · r1 · β · T an(β) + 2 · r2 3 1 + 2 · β · T an(β) + 2 · β · T an (β)
f 0 · f 2 f 02 · (3f 22 − f 1 · f 3)
f0
· 1+
+
β=β−
f1
2f 12
6f 14
(3.189)
(3.190)
(3.191)
Repeat (3.187) to (3.191).

ψs =
ψ =
d
2nkT
q
[ln(β) − ln (cos(β)) + F1 ]
at source
2nkT
q
[ln(β) − ln (cos(β)) + F1 ] + Vdsef f
at drain
(3.192)
Case: GEOM OD = 3, same for both COREM OD = 0, 1
Vch

∆Vt,QM
=
∆V
t,QM + Vdsef f
at source
(3.193)
at drain
22
q(Vgsf bef f − Vch )
2nkT
If F < -10 g = exp(2 · F )
F =
(3.194)
(3.195)
F
Else if F > 10 g =
r1
p
0.25 + r12 · (ln(1 + exp(F )))2
Else g =
r12
(3.196)
(3.197)
T 0 = 1 + cdop · g
cdop
T1 =
T0
T 2 = T 12
(3.198)
f 0 = 0.5 · ln(g) + 0.5 · ln(T 0) + r1 · g + r2 · g 2 − F
1
f 1 = 0.5 · + 0.5 · T 1 + r1 + 2 · r2 · g
g
1
f 2 = −0.5 · 2 − 0.5 · T 2 + 2 · r2
g
1
f3 = 3 + T1 · T2
g
(3.201)
g=g−
(3.199)
(3.200)
f0
f 0 · f 2 f 02 · (3f 22 − f 1 · f 3)
· 1+
+
f1
2f 12
6f 14
(3.202)
(3.203)
(3.204)
(3.205)
Repeat (3.198) to (3.205).
Source side calculations
nkT
· r2 · g 2
q
nkT
ψs = Vgsf bef f − 2 ·
· r1 · g − Vpolys
q
Vpolys = 2 ·
qis = q0 · g
(3.206)
(3.207)
(3.208)
23
Drain side calculations
nkT
· r2 · g 2
q
nkT
ψd = Vgsf bef f − 2 ·
· r1 · g − Vpolyd
q
Vpolyd = 2 ·
qid = q0 · g
3.5
(3.209)
(3.210)
(3.211)
Drain Saturation Voltage
The drain saturation voltage model is calculated after the source-side surface potential (ψs ) has been calculated. Vdsef f is subsequently used to compute the drain-side
surface potential (ψd ).
Electric Field Calculations
Electric Field is in M V /cm
s
Vgsf bef f − ψs
Tpolys = 1 +
−1
Vpoly0
(3.212)
2
Vpolys = Vpoly0 · Tpolys
(3.213)
else
Vpolys = 0

Vgsf bef f − ψs − qbs − Vpolys
qis =
V
gsf bef f − ψs − Vpolys
−8
Eef f s = 10
·
qbs + η · qis
ratio · EOT
(3.214)
if COREM OD = 0
(3.215)
if COREM OD = 1
(3.216)
24
Drain Saturation Voltage (Vdsat ) Calculations
Dmobs = 1 + U A(T ) · (Eef f s )EU + Dmobs =
1
2
U D(T )
U CS(T )
is
· 1 + qqbs
Dmobs
U 0M U LT
(3.218)
If RDSM OD = 0 then
(3.219)
Rds,s = Rs,geo (T ) + Rd,geo (T )+
1
RDSW (T )
· RDSW M IN (T ) +
(Wef f 0 (µm))W Ri
1 + P RW Gi · qis
If RDSM OD = 1 then
(3.220)
(3.221)
Rds,s = 0
Esat =
(3.217)
(3.222)
2 · V SAT (T )
µ0 (T )/Dmobs
(3.223)
EsatL = Esat · Lef f
(3.224)
25
If Rds,s = 0 then
Vdsat =
EsatL · KSAT IVi · (Vgsf bef f − ψs + 2 kT
q )
EsatL + KSAT IVi · (Vgsf bef f − ψs + 2 kT
q )
(3.225)
else
W V Cox = Wef f 0 · V SAT (T ) · Cox
(3.226)
Ta = 2 · W V Cox · Rds,s
kT
) · (1 + 3 · W V Cox · Rds,s ) + EsatL
q
kT
Tc = KSAT IVi · (Vgsf bef f − ψs + 2 )
q
kT
× EsatL + Ta · KSAT IVi · (Vgsf bef f − ψs + 2 )
q
q
Tb − Tb2 − 2Ta Tc
Vdsat =
Ta
Vds
Vdsef f = M EXP (T ) 1/M EXP (T )
ds
1 + VVdsat
Tb = KSAT IVi · (Vgsf bef f − ψs + 2
26
(3.227)
(3.228)
(3.229)
3.6
Average Potential, Charge and Related Variables
∆ψ = ψd − ψs
(3.230)
qba = qbs
(3.231)
s
Vgsf bef f − ψd
Tpolyd = 1 +
−1
Vpoly0
(3.232)
2
Vpolyd = Vpoly0 · Tpolyd
(3.233)
else
Vpolyd = 0

Vgsf bef f − ψd − qba − Vpolyd
qid =
V
gsf bef f − ψd − Vpolyd
3.7
(3.234)
if COREM OD = 0
(3.235)
if COREM OD = 1
qia = 0.5 · (qis + qid )
(3.236)
∆qi = qis − qid
(3.237)
Quantum Mechanical Effects
Effects that arise due to structural and electrical confinement in the multi-gate structures are dealt in this section. The threshold voltage shift arising due to bias-dependent
ground state sub-band energy is already accounted for in the surface potential calculations. (See the section on ’Surface Potential Calculation’). The reduction in width
and bias-dependence in effective oxide thickness due to the inversion charge centroid
being away from the interface is taken care of here. The section is evaluated only if
QM T CEN IVi or QM T CEN CVi is non-zero. While a single equation with parameters
ET AQM , QM 0 and ALP HAQM govern the motion of charge centroid w.r.t. bias, two
different quasi-switches are introduced here for the purpose of effective width calculation
and effective oxide thickness calculation. QM T CEN IVi uses the above expression to
27
account for the effective width in I − V calculations and QM T CEN CVi uses the same
expression for the effective width and effective oxide thickness for C − V calculations.
The pre-calculated factor MTcen is for the geometric dependence (on T F IN/HF IN/R)
of the charge centroid in sub-threshold region.
Charge Centroid Calculation for Inversion
qia + ET AQM · qba
QM 0
P QM
T5 = 1 + T4
(3.238)
T4 =
(3.239)
Charge Centroid Calculation for Accumulation
P QM ACC
qi,acc
T6 = 1 +
QM 0ACC
(3.240)
Effective Width Model
If GEOM OD = 0 then
Tcen = T F IN · M T cen
(3.241)
Wef f = Wef f 0
(3.242)
Wef f,CV = Wef f,CV 0
(3.243)
If GEOM OD = 1 then
Tcen = min(T F IN, HF IN ) · M T cen
(3.244)
Wef f = Wef f 0 − 4 · QM T CEN IVi · Tcen
(3.245)
Wef f,CV = Wef f,CV 0 − 4 · QM T CEN CVi · Tcen
(3.246)
If GEOM OD = 2 then
Tcen = min(T F IN, HF IN ) · M T cen
(3.247)
Wef f = Wef f 0 − 8 · QM T CEN IVi · Tcen
(3.248)
Wef f,CV = Wef f,CV 0 − 8 · QM T CEN CVi · Tcen
(3.249)
28
If GEOM OD = 3 then
(3.250)
Tcen = R · M T cen
(3.251)
Wef f = Wef f 0 − 2π · QM T CEN IVi · Tcen
(3.252)
Wef f,CV = Wef f,CV 0 − 2π · QM T CEN CVi · Tcen
(3.253)
Effective Oxide Thickness / Effective Capacitance
If QM T CEN CVi = 0, then Cox /Cox,acc (with EOT /EOT ACC) will continue to be
used for both I − V and C − V . Else the following calculations yield a Cox,ef f that
shall be used for C − V purposes. However Cox will continue to be used for I − V . For
calculation of Cox,ef f , the physical oxide thickness, T OXP scaled appropriately will be
added to the inversion charge centroid, Tcen calculated above instead of using EOT .
If QM T CEN CVi 6= 0 then

0
GEOM OD 6= 3
 T OXP 3.9 3.9·
QM T CEN CVi
+ TTcen
·
EP SROX
5
ratio
Cox,ef f =
3.9·0
i
 h 1
GEOM OD = 3
T
3.9
R· ln( R−T R /T 5 )+ EP SROX
ln 1+ oxp
R
cen
ratio

0
GEOM OD 6= 3
 T OXP 3.9 3.9·
QM T CEN CVi
+ TTcen
·
EP SROX
6
ratio
Cox,acc =
3.9·0
i
 h 1
GEOM OD = 3
T
3.9
R· ln( R−T R /T 6 )+ EP SROX
ln 1+ oxp
R
cen
ratio
(3.254)
If QM T CEN CVi = 0 then
(3.257)
Cox,ef f = Cox
3.9 · 0
Cox,acc =
EOT ACC
(3.258)
(3.255)
(3.256)
(3.259)
(3.260)
3.8
Mobility degradation and series resistance
Mobility degradation
29

 1 · ET AM OB
η= 2
 1 · ET AM OB
3
−8
Eef f a = 10
·
for NMOS
qba + η · qia
ratio · EOT
Dmob = 1 + U A(T ) · (Eef f a )EU + Dmob =
(3.261)
for PMOS
(3.262)
1
2
U D(T )
U CS(T )
ia
· 1 + qqba
Dmob
U 0M U LT
(3.263)
(3.264)
Series resistance
The source/drain series resistance is the sum of a bias-independent component and a biasdependent component. They are described in detail in section 3.13. If RDSMOD=0 the
resistance will affect the Ids expressions through a degradation factor Dr .
3.9
Output Conductance
Channel Length Modulation


P CLMi + P CLM Gi · qia for P CLM Gi > 0
Cclm =

for P CLM Gi < 0
 1 −P1CLM G ·q
i ia
P CLMi
Vds − Vdsef f
1
Mclm = 1 +
ln 1 +
· Cclm
Cclm
V ASATi
Output Conductance due to DIBL


1 + P V AGi · E qia
sat Lef f
P V AGf actor =
1

 1−P V AGi · qia
Esat Lef f
30
(3.265)
(3.266)
for P V AGi > 0
for P V AGi < 0
(3.267)
0.5 · P DIBL1i
+ P DIBL2i
L f
cosh DROU Ti · ef
−1
λ
Vdsat
qia + 2kT /q
· 1−
· P V AGf actor
VADIBL =
θrout
Vdsat + qia + 2kT /q
Vds − Vdsef f
Moc = 1 +
· Mclm
VADIBL
θrout =
(3.268)
(3.269)
(3.270)
Moc is multiplied to Ids in the final drain current expression.
3.10
Velocity Saturation
Current Degradation Due to Velocity Saturation The following formulation
models the current degradation factor due to velocity saturation in the linear region. It
is adopted from the BSIM5 model [7, 8].
Esat1 =
2 · V SAT 1(T )
µef f
(3.271)
δvsat = DELT AV SAT
r
2
∆qi
1 + δvsat + Esat1
Lef f
1
√
Dvsat =
+ · P T W G(T ) · qia · ∆qi2
2
1 + δvsat
31
(3.272)
(3.273)
3.11
Drain Current Model
Case: GEOM OD = 0, 1, 2 and COREM OD = 1
Assume solution to SPE for source and drain side to be βs and βd respectively
2Csi
Cox
(3.274)
T1 = βs · tan βs
(3.275)
T2 = βd · tan βd

T0 · (T1 + T2 ) + 4 · r2 ·
T3 =
T · (T + T )
(3.276)
T0 =
0
1
T1 2 +T1 T2 +T2 2
3
N GAT Ei > 0
(3.277)
otherwise
2
T6 = βs 2 + βd 2
4Csi nkT 2
· [(T3 + 2) · (T1 − T2 ) − T6 ]
ids0 =
Cox
q
ids0
nkT
· (T3 + 1)
=
∆qi
2q
Wef f
Moc
· ids0 ·
× N F INtotal
Ids = IDS0M U LT · µ0 (T ) · Cox ·
Lef f
Dvsat · Dr · Dmob
32
(3.278)
(3.279)
(3.280)
(3.281)
Case: All other cases
cdop = 1
(3.282)
Tpoly = 2 · χpoly ·
Tcom
3
(3.283)
T 1 = κpoly · qia
(3.284)
Else
Tpoly = 0
(3.285)
T 1 = qia
q0
ηiv =
q0 + cdop qia
nkT
· ∆qi
T 2 = (2 − ηiv ) ·
q
ids0
= Tpoly + T 1 + T 2
∆qi
ids0
ids0 =
· ∆qi
∆qi
Ids = IDS0M U LT · µ0 (T ) · Cox ·
3.12
(3.286)
(3.287)
(3.288)
(3.289)
(3.290)
Wef f
Moc
· ids0 ·
× N F INtotal
Lef f
Dmob · Dr · Dvsat
(3.291)
Intrinsic Capacitance Model
In BSIM-MG both the intrinsic capacitances and parasitic capacitances are modeled.
In this section we describe the formulation of intrinsic capacitances. The formulation of
parasitic capacitances will be described in section 3.13
To ensure charge conservation, terminal charges instead of terminal voltages are used
as state variables. The terminal charges Qg , Qb , Qs , and Qd are the charges associated
with the gate, bulk, source, and drain terminals, respectively. Please refer to [9] for
details of the terminal charge derivation.
33
Intrinsic (Normalized) Charge
qb = qbs
ids,CV

2 · χpoly · Tcom + κpoly · qia + (2 − ηiv ) nkT
3
q
=
q + (2 − η ) nkT
ia
iv
q
Calculating qg

κpoly + 4 · χpoly · qia
T0 =
1
∆qi2
qg = qia + T 0 ·
12 · ids,CV
N GAT Ei > 0
(3.292)
N GAT Ei = 0
N GAT Ei > 0
(3.293)
N GAT Ei = 0
(3.294)
Calculating qd

15 · κpoly + χpoly · (32 · qid + 28 · qis )
T1 =
15
N GAT Ei > 0
(3.295)
N GAT Ei = 0

63 · κ2 + 126 · χpoly · κpoly · qia + χ2 · (256 · Tcom + 240 · qis · qid ) N GAT Ei > 0
poly
poly
T2 =
63
N GAT Ei = 0
(3.296)
"
qd = 0.5 · qia −
∆qi
·
12
1 − T1
∆qi
∆qi2
− T2
30 · ids,CV
1260 · i2ds,CV
!#
(3.297)
Accumulation Charge
Note: This section is still subject to verification and may be changed or removed in future
versions.
The calculation for accumulation region charge are performed only if both the switches CAPMOD and BULKMOD are set to 1, i.e. for a bulk-substrate device only. This introduces
a computational effort equal to the calculation of surface potential on the source side. For
calculation of accumulation region charge, the device is treated as intrinsically doped i.e.
34
NBODY=ni . However additional flexibility is introduced through a separate effective oxide
thickness (EOTACC) and a separate Flatband voltage value (through DELVFBACC) for the
accumulation side calculations. The following equations (here written together) are present at
appropriate places in the code.
r1acc =


2 sub
T F IN ·Cox,acc
GEOM OD 6= 3

2 sub
R·Cox,acc
GEOM OD = 3
(3.298)
s
!
2
2sub · kT
F1,acc = ln
q 2 Nc T F IN
(3.299)
If GEOM OD = 3 then
2 · kT · r1acc
q
q · ni · R
T 0acc =
Cox,acc
kT
q.T 0acc
kT
kT
ln
ln 1 − exp
Vt,dop,acc = −
−
q
q · T 0acc
q
2.r1acc .kT
q · Vt,dop,acc
cdop,acc = 2 · r1acc · exp −
kT
T 0acc
kT
0.5 · q · T 0acc
Vt0,acc =
−
ln
+ Vt,dop,acc
2
q
kT
q0,acc =
(3.300)
(3.301)
(3.302)
(3.303)
(3.304)
Voltage limiting for Vge > Vf b region
Eg
T 1 = −Vge + ∆φ −
+ DELV F BACC
 h 2
i
√

 1 T 1 + T 12 + 4 × 10−8 − Eg
2
2
h
i
Vgsf bef f,acc =
√

1
2
−8
 T 1 + T 1 + 4 × 10
− Vt0,acc
2
35
(3.305)
GEM OD 6= 3
(3.306)
GEM OD = 3
Surface Potential Evaluation
For GEM OD 6= 3, the simplified surface potential calculation outlined for COREM OD = 1
case is used with Vgsf bef f,acc , F1,acc and r1acc calculated above together with r2 = 0, Vch = 0.
Then the normalized charge is evaluated the following way...
qi,acc = Vgsf bef f,acc −
2kT
[ln(β) − ln (cos(β)) + F1,acc ]
q
(3.307)
Similarly for GEM OD = 3, the surface potential calculations are performed with Vgsf bef f,acc
and r1acc , with r2 and Vch both set to 0. The normalized charge in this case is give by,
qi,acc = q0,acc · g
(3.308)
Terminal Charges
3.13
Qg,intrinsic = N F INtotal · Cox,ef f · Wef f,CV · Lef f,CV · (qg )
(3.309)
Qd,intrinsic = N F INtotal · Cox,ef f · Wef f,CV · Lef f,CV · (−qd )
(3.310)
Qb,intrinsic = N F INtotal · Cox · Wef f,CV · Lef f,CV · (−qb )
(3.311)
Qs,intrinsic = −Qg,intrinsic − Qd,intrinsic − Qb,intrinsic
(3.312)
Qg,acc = N F INtotal · Cox,acc · Wef f,CV 0 · Lef f,CV · (−qi,acc )
(3.313)
Qb,acc = N F INtotal · Cox,acc · Wef f,CV 0 · Lef f,CV · (−qi,acc )
(3.314)
Parasitic resistances and capacitance models
In this section we will describe the models for parasitic resistances and capacitances in
BSIM-MG.
BSIM-MG models the parasitic source/drain resistance in two components: a bias dependent extension resistance and a bias independent diffusion resistance. Parasitic gate resistance
is modeled as well.
The parasitic capacitance model in BSIM-MG includes a bias-indepedent fringe capacitance, a bias-dependent overlap capacitance, and substrate capacitances. In the case of
MuGFETs on SOI, the substrate capacitances are from source/drain/gate to the substrate
36
through the buried oxide. For MuGFETs on bulk substrate, an additional junction capacitor
is modeled, which we will describe along with the junction current model in section 3.18.
Bias-dependent extension resistance
The bias-dependent extension resistance model is adopted from BSIM4 [10]. There are two
options for this bias dependent component. In BSIM3 models Rds (V ) is modeled internally
through the I-V equation and symmetry is assumed for the source and drain sides. BSIM4
and BSIM-MG keep this option for the sake of simulation efficiency. In addition, BSIM4
and BSIM-MG allow the source extension resistance Rs (V ) and the drain extension resistance
Rd (V ) to be external and asymmetric (i.e. Rs (V ) and Rd (V ) can be connected between the
external and internal source and drain nodes, respectively; furthermore, Rs (V ) does not have
to be equal to Rd (V )). This feature makes accurate RF CMOS simulation possible.
The internal Rds (V ) option can be invoked by setting the model selector RDSM OD = 0
(internal) and the external one for Rs (V ) and Rd (V ) by setting RDSM OD = 1 (external).
The expressions for source/drain series resistances are as follows:
RDSM OD = 0 (Internal)
RDSW (T )
1
Rds =
· RDSW M IN (T ) +
1 + P RW Gi · qia
N F INtotal × W ef f 0W Ri
Wef f ids0
1
·
·
Dr = 1.0 + N F INtotal × µ0 (T ) · Cox ·
Lef f ∆qi Dvsat · Dmob
(Rds + Rs,geo + Rd,geo )
(3.315)
(3.316)
37
Dr goes into the denominator of the final Ids expression.
RDSM OD = 1 (External)
q
1
2
−4
Vgs − Vf bsd + (Vgs − Vf bsd ) + 10
Vgs,ef f =
(3.317)
2
q
1
2
−4
Vgd − Vf bsd + (Vgd − Vf bsd ) + 10
(3.318)
Vgd,ef f =
2
1
RSW (T )
Rsource =
· RSW M IN (T ) +
1 + P RW Gi · Vgs,ef f
W ef f 0W Ri · N F INtotal
+ Rs,geo
Rdrain =
W Ri
W ef f 0
1
· N F INtotal
· RDW M IN (T ) +
RDW (T )
1 + P RW Gi · Vgd,ef f
+ Rd,geo
(3.319)
(3.320)
Dr = 1.0
(3.321)
Rs,geo and Rd,geo are the source and drain diffusion resistances, which we will describe as
follows.
Sheet resistance model
BSIM-MG offers two models for the source/drain diffusion resistance, selected by a parameter
RGEOM OD. If RGEOM OD = 0, the resistance will be simply calculated as the sheet
resistance (RSHS,RSHD) times the number of squares (N RS,N RD):
RGEOM OD = 0 (sheet resistance model)
Rs,geo = N RS · RSHS
(3.322)
Rd,geo = N RD · RSHD
(3.323)
Diffusion resistance model for variability modeling
If RGEOM OD = 1, a diffusion resistance model for variability modeling will be invoked. The
physically-derived model captures the complex dependences of resistance on the geometry of
FinFETs.
RGEOM OD = 1 is derived based on the FinFET structure (single-fin or multi-fin with
merged source/drain). Figure 1 shows the cross section of a double-gate FinFET with raised
38
Figure 1: Cross section of a raised source/drain double-gate FinFET and symbol definition
source/drain (RSD) along the source-drain direction. Lg (gate length) and T OXP (physical
oxide thickness, not shown in figure 1) are calculated in section 3.1. A hard mask with
thickness T M ASK often exists on top of the fin. If T M ASK = 0, the model will assume there
is no hard mask and the dielectric thickness on top of the fin is T OXP (triple-gate FinFET).
In the figure, LSP is the spacer thickness, LRSD is the length of the raised source/drain,
HF IN is the fin height, T GAT E is the gate height, and HEP I is the height of the epitaxial
silicon above the fin. These parameters are specified by the user.
The resistivity of the raised source/drain can be specified with the parameter RHORSD.
39
If RHORSD is not given the resistivity is calculated using the following expressions [11]:

1417 for NMOS
µM AX =
(3.324)
470.5 for PMOS
µrsd =



52.2 +
1+


44.9 +
1+
µM AX −52.2
0.680
−
43.4
26 m−3 2.0
1+ 3.41×10
N SD
cm2 /V − s for NMOS
µM AX −44.9
0.719
−
29.0
2.0
6.10×1026 m−3
1+
N SD
cm2 /V − s for PMOS
N SD
9.68×1022 m−3
N SD
2.23×1023 m−3
(3.325)
ρRSD =
1
q N SD µRSD
(3.326)
where N SD is the active doping concentration of the raised source/drain. The resistivity of
the extension region under the spacer, ρext , can be specified with the parameter RHOEXT .
If RHOEXT is not given, the resistivity is set to ρRSD .
The diffusion resistance includes three components: the resistance of the extension region
under the spacer (Rext ), the spreading resistance due to current spreading from the extension
region into the raised source/drain (Rsp ) and the resistance of the raised source/drain region
(Rcon ).
To calculate Rext we assume a doping profile as shown in figure 2. The doping concentration
at the channel edge is NSDE (default: 2 × 1019 cm−3 ) 1 . The doping concentration increases
exponentially with position until it reaches NSD. The doping gradient can be specified with
the parameter LDG in units of meters per decade. The extension resistance is given by:
N SD
LDG
N SD
ρRSD
LSP + ∆L − LDG · log
+
−1
Rext =
Af in0
N SDE
ln(10) N SDE
(3.327)
where
Af in0 = HF IN × T F IN × N F IN
(3.328)
The spreading resistance, Rsp is derived by assuming the current spreads at a constant angle
θRSP in the raised source/drain. Comparison with numerical simulation shows that θRSP is
1
the channel edge may be on either side of the gate edge depending of the sign of ∆L
40
Figure 2: Doping profile considered in RGEOM OD = 1.
around 55 degrees. The spreading resistance is given as a function of the cross sectional area
of the raised source/drain (Arsd ) and the effective fin area (Af in ):
s
"
#
Af in
ρRSD · cot(θrsp )
2
1
−√
+
Rsp = √
· p
π · N F IN
A2rsd
Arsd
Af in
(3.329)
Af in is given by
Af in

HF IN × T F IN
=
(HF IN + HEP I) × T F IN
for HEP I ≥ 0
(3.330)
for HEP I < 0
Here HEP I < 0 is the case where silicidation removes part of the silicon, forming a recessed
source/drain (Fig. 3).
41
Figure 3: Lithography-defined FinFET with a smaller source/drain height compared to
the fin height (silicide not shown).
The raised source drain cross sectional area (Arsd ) is given by



F P IT CH · HF IN + T F IN +




Arsd =
(F P IT CH − T F IN ) · CRAT IO · HEP I for HEP I ≥ 0





F P IT CH · (HF IN + HEP I)
for HEP I < 0
(3.331)
In the above formula, we have assumed a rectangular geometry for negative HEP I (Figure.
3) and the cross sectional area is simply the fin pitch times the final height of the source/drain.
For positive HEP I, we have considered a RSD formed by selective epitaxial growth, in which
case the RSD may not be rectangular (e.g. fig. 4). In calculating the cross sectional area, we
take into account the non-rectangular corner through the parameter CRAT IO. CRAT IO is
defined as the ratio of corner area filled with silicon to the total corner area. In the example
given in figure 5, CRAT IO is 0.5.
The calculation of the contact resistance (Rcon ) is based on the transmission line model
[12]. Rcon is expressed as a function of the total area (Arsd,total ) and the total perimeter
(Prsd,total ):
Rrsd,T M L =
ρRSD · lt cosh(α) + η · sinh(α)
·
Arsd,total sinh(α) + · cosh(α)
LRSD
l
s t
RHOC · Arsd,total
lt =
ρRSD · Prsd,total
α=
(3.332)
(3.333)
(3.334)
where RHOC is the contact resistivity at the silicide/silicon interface.
42
Figure 4: FinFET with non-rectangular epi and top silicide
Figure 5: 2-D cross section of a FinFET with non-rectangular epi and top silicide
43
Figure 6: FinFET with a non-rectangular epi and silicide on top and two ends.
The total area and perimeter are given by
Arsd,total = Arsd × N F IN + ARSDEN D
(3.335)
Prsd,total = (F P IT CH + DELT AP RSD) × N F IN + P RSDEN D
(3.336)
DELT AP RSD is the per-fin increase in perimeter due to non-rectangular raised source/drains.
ARSDEN D and P RSDEN D are introduced to model the additional cross-sectional area and
the additional perimeter, respectively, at the two ends of a multi-fin FinFET.
SDT ERM = 1 indicates the source/drain are terminated with silicide (Fig. 6), while
SDT ERM = 0 indicates they are not. η is given by

 ρRSD ·lt SDT ERM = 1
η = RHOC
0.0
SDT ERM = 0
(3.337)
In the case of the recessed source/drain, a side component of the contact resistance must
be modeled as well. It is given by
Rrsd,side =
RHOC
N F IN · (−HEP I) · T F IN
44
(3.338)
Finally, the total diffusion resistance is given by
Rrsd + Rext
Rs,geo = Rd,geo =
· RGEOA + RGEOB × T F IN +
NF
(3.339)
RGEOC × F P IT CH + RGEOD × LRSD + RGEOE × HEP I
where
Rrsd

Rrsd,T M L + Rsp
=
 (Rrsd,T M L +Rsp )×Rrsd,side
(Rrsd,T M L +Rsp )+Rrsd,side
for HEP I ≥ 0
(3.340)
for HEP I < 0
Fitting parameters RGEOA, RGEOB, RGEOC, RGEOD and RGEOE are introduced for
fitting flexibility.
Gate electrode resistance model
The gate electrode resistance model can be switched on by setting RGAT EM OD = 1. This
introduces an internal node ”ge”. The gate electrode resistor (Rgeltd ) is placed between the
external ”g” node and the internal ”ge” node.
The gate electrode resistance model takes into account the number of gate contacts,
N GCON . N GCON = 1 indicates single-sided contact; N GCON = 2 indicates double-sided
contact. Rgeltd is given by
Rgeltd =

 RGEXT +RGF IN ·N F IN
for N GCON = 1
 RGEXT +RGF IN ·N F IN
for N GCON = 2
3·N F
12·N F
(3.341)
Bias-dependent overlap capacitance model
An accurate overlap capacitance model is essential. This is especially true for the drain side
where the effect of the capacitance is amplified by the transistor gain. The overlap capacitance
changes with gate to source and gate to drain biases. In LDD MOSFETs a substantial portion
of the LDD region can be depleted, both in the vertical and lateral directions. This can lead
to a large reduction of the overlap capacitance. This LDD region can be in accumulation or
depletion. We use a single equation for both regions by using such smoothing parameters as
Vgs,overlap and Vgd,overlap for the source and drain side, respectively. Unlike the case with the
45
intrinsic capacitance, the overlap capacitances are reciprocal. In other words, Cgs,overlap =
Csg,overlap and Cgd,overlap = Cdg,overlap .
The bias-dependent overlap capacitance model in BSIM-MG is adopted from BSIM4 [10]
for CGEOM OD = 0 and CGEOM OD = 2. The overlap charge is given by:
Qgs,ov
= CGSO · Vgs +
N F INtotal · W ef f CV
"
CKAP P AS
CGSL · Vgs − Vf bsd − Vgs,overlap −
2
r
4Vgs,overlap
1−
−1
CKAP P AS
!#
(3.342)
Qgd,ov
= CGDO · Vgd +
N F INtotal · W ef f CV
"
CKAP P AD
CGDL · Vgd − Vf bsd − Vgd,overlap −
2
!#
4Vgd,overlap
1−
−1
CKAP P AD
r
(3.343)
q
1
2
Vgs − Vf bsd + δ1 − (Vgs − Vf bsd + δ1 ) + 4δ1
Vgs,overlap =
2
q
1
2
Vgd,overlap =
Vgd − Vf bsd + δ1 − (Vgd − Vf bsd + δ1 ) + 4δ1
2
δ1 = 0.02V
(3.344)
(3.345)
(3.346)
For CGEOM OD = 1, the overlap capacitors are bias-independent, as we will discuss in
the end of this section.
Substrate parasitics
In multi-gate devices such as the FinFET, there is capacitive coupling from the source/drain
to the substrate through the buried oxide. This component is modeled in BSIM-MG and is
given by:
Csbox = Cbox · ASEO + Cbox,sw · (P SEO − F P IT CH ∗ N F INtotal )
(3.347)
Cdbox = Cbox · ADEO + Cbox,sw · (P DEO − F P IT CH ∗ N F INtotal )
(3.348)
where the side component per width is [13]
HF IN
Cbox,sw = CSDESW · ln 1 +
EOT BOX
46
(3.349)
Figure 7: Illustration of the direct gate-to-substrate overlap region in the FinFET.
There is also direct capacitive coupling from the gate to the substrate in FinFETs (Fig.
7). Following BSIM4[10] this component is given by
Cge,overlap = CGBO · Lef f,CV
(3.350)
Csbox , Cdbox and Cge,overlap are all linear capacitors.
Fringe capacitances and capacitance model selectors
The fringing capacitance consists of a bias-independent outer fringing capacitance and a biasdependent inner fringing capacitance. Only the bias-independent outer fringing capacitance is
modeled.
BSIM-MG offers 3 models for the outer fringe capacitance, selected by CGEOM OD.
For CGEOM OD = 0, the fringe and overlap capacitances are proportional to the number
of fins and the effective width. The fringe capacitances is given by:
CGEOM OD = 0
Cgs,f r = N F INtotal · Wef f,CV · CF Si
(3.351)
Cgd,f r = N F INtotal · Wef f,CV · CF Di
(3.352)
47
Figure 8:
R-C network for CGEOMOD=0, NQSMOD=1, RGATEMOD=1 and
RDSMOD=1. If NQSMOD, RGATEMOD or RDSMOD is 0, then the corresponding
resistances become 0 and the nodes collapse.
Fig. 8 illustrates the parasitic resistance and capacitance network used for CGEOM OD = 0.
In some multi-gate applications the parasitic capacitances are not directly proportional to
the width of the device. BSIM-MG offers CGEOM OD = 1 so that the fringe and overlap
capacitance values can be directly specified without assuming any width dependencies. The
simple expressions for fringe and overlap capacitances in CGEOM OD = 1 are:
CGEOM OD = 1
Cgs,ov = COV Si
(3.353)
Cgd,ov = COV Di
(3.354)
Cgs,f r = CGSP
(3.355)
Cgd,f r = CGDP
(3.356)
Cds,f r = CDSP
(3.357)
The parasitic resistance and capacitance network for CGEOM OD = 1 is illustrated in Fig. 9.
If CGEOM OD = 2, an outer fringe capacitance model for variability modeling which
address the complex dependencies on the FinFET geometry will be invoked. RGEOM OD = 1
and CGEOM OD = 2 share the same set of input parameters and can be used at the same
48
Figure 9:
R-C network for CGEOMOD=1, NQSMOD=1, RGATEMOD=1 and
RDSMOD=1. If NQSMOD, RGATEMOD or RDSMOD is 0, then the corresponding
resistances become 0 and the nodes collapse.
time. Both models are derived based on the FinFET structure (single-fin or multi-fin with
merged source/drain).
In CGEOM OD = 2 the fringe capacitance is partitioned into a top component, a corner
component and a side component (Fig. 10). The top and side components are calculated
based on a 2-D fringe capacitance model, which has been derived and calibrated to numerical
simulation in [14]. The corner component is calculated based on the formula of parallel plate
capacitors.
Cf r,top = Cf ringe,2D (Hg , Hrsd , LRSD) × T F IN × N F IN
(3.358)
Cf r,side = 2 × Cf ringe,2D (Wg , Trsd , LRSD) × HF IN × N F IN
sp
· [Acorner × N F IN + ARSDEN D + ASILIEN D]
Ccorner =
LSP
(3.359)
49
(3.360)
Figure 10: Illustration of top, corner and side components of the outer fringe capacitance
where
Hg = T GAT E + T M ASK
1
Trsd = (F P IT CH − T F IN )
2
Wg = Trsd − T OXP
(3.361)
(3.363)
Hrsd = HEP I + T SILI
(3.364)
(3.362)
ARSDEND and ASILIEND are the additional area of silicon and silicide, respectively, at the
two ends of a multi-fin FinFET.
The three components are summed up to give the total fringe capacitance. Several fitting
50
parameters are added to aid fitting. The final expression is:
CGEOM OD = 2
Cf r,geo = (Ccorner + Cf r,top + CGEOE · Cf r,side ) × N F ×
[CGEOA + CGEOB · T F IN + CGEOC · F P IT CH + CGEOD · LRSD] (3.365)
For the case of T M ASK > 0 the fringe capacitances are calculated a little differently,
since the 2D model is valid only for a thin Tox . Ccorner is set to 0. Cf r,top is proportional to
F P IT CH and is given by
(
Cf r,top =
3.467 × 10−11 · ln
EP SRSP · 10−7
3.9 · LSP
sp
+ 0.942 · Hrsd ·
LSP
· ([T F IN + (F P IT CH − T F IN ) · CRAT IO] · N F IN
3.14
)
(3.366)
Impact Ionization and GIDL/GISL Model
Impact Ionization Current
Iii can be switched off by setting IIM OD = 0
Case: IIM OD = 1
Iii =
(3.367)
BET A0(T )
ALP HA0i + ALP HA1i · Lef f
(Vds − Vdsef f ) · e Vds −Vdsef f · Ids
Lef f
51
(3.368)
Case: IIM OD = 2
Iii = ALP HAIIi · Ids · exp
Vdif f
2
BET AII2i + BET AII1i Vdif f + BET AII0i Vdif
f
!
(3.369)
Vdif f = Vds − Vdsatii
(3.370)
LIIi
Vdsatii = VgsStep · 1 −
(3.371)
Lef f
ESAT IIi Lef f
SII0(T ) · Vgsf bef f
1
VgsStep =
+ SII2i
1 + ESAT IIi Lef f
1 + SII1i Vgsf bef f
1 + SIIDi Vds
(3.372)
Gate-Induced-Drain/Source-Leakage Current
GIDL/GISL are calculated only for GIDLM OD = 1
Vds − Vgs − EGIDLi + Vf bsd P GIDLi
T 0 = AGIDLi · Wef f 0 ·
ratio · EOT
ratio · EOT · BGIDL(T )
× exp −
× N F INtotal
Vds − Vgs − EGIDLi + Vf bsd

3
Vde
T 0 ·
for BU LKM OD = 1
3
CGIDLi +Vde
Igidl =

T 0 · Vds
for BU LKM OD = 0
−Vds − Vgd − EGISLi + Vf bsd P GISLi
T 1 = AGISLi · Wef f 0 ·
ratio · EOT
ratio · EOT · BGISL(T )
× exp −
× N F INtotal
−Vds − Vgd − EGISLi + Vf bsd

3
Vse
T 1 ·
for BU LKM OD = 1
3
CGISLi +Vse
Igisl =
T 1 · V
for BU LKM OD = 0
sd
52
(3.373)
(3.374)
(3.375)
(3.376)
3.15
Gate Tunneling Current
Tox,ratio =
1
T OXP 2
(3.377)
Gate to body current Igbinv and Igbacc calculated only if IGBM OD = 1
A = 3.75956 × 10−7
(3.378)
B = 9.82222 × 1011
(3.379)
Vaux,igbinv
kT
qia − EIGBIN Vi
= N IGBIN Vi ·
· ln 1 + exp
q
N IGBIN Vi · kT /q
(3.380)
Igbinv = Wef f 0 · Lef f · A · Tox,ratio · Vge · Vaux,igbinv · Igtemp · N F INtotal
× exp (−B · T OXP · (AIGBIN Vi − BIGBIN Vi · qia ) · (1 + CIGBIN Vi · qia ))
(3.381)
53
A = 4.97232 × 10−7
(3.382)
B = 7.45669 × 1011
(3.383)
Vf bzb = ∆Φ − Eg /2 − φB
(3.384)
T 0 = Vf bzb − Vge
(3.385)
T 1 = T 0 − 0.02;
(3.386)
Vaux,igbacc = N IGBACCi ·
Voxacc
kT
· ln 1 + exp
q


qi,acc



p
= 0.5 · [T 1 + (T 1)2 − 0.08 · Vf bzb ]


p


0.5 · [T 1 + (T 1)2 + 0.08 · Vf bzb ]
T0
N IGBACCi · kT /q
(3.387)
for BULKMOD=1 and CAPMOD=1
for CAP M OD 6= 1 and Vf bzb ≤ 0
for CAP M OD 6= 1 and Vf bzb > 0
(3.388)
Igbacc = Wef f 0 · Lef f · A · Tox,ratio · Vge · Vaux,igbacc · Igtemp · N F INtotal
× exp (−B · T OXP · (AIGBACCi − BIGBACCi · Voxacc ) · (1 + CIGBACCi · Voxacc ))
(3.389)
For BULKMOD=1, Igb simply flows from the gate into the substrate. For BULKMOD=0,
Igb mostly flows into the source because the potential barrier for holes is lower at the source,
which has a lower potential. To ensure continuity when Vds switches sign, Igb is partitioned
into a source component, Igbs and a drain component, Igbd using a partition function:
Igbs = (Igbinv + Igbacc ) · Wf
(3.390)
Igbd = (Igbinv + Igbacc ) · Wr
(3.391)
54
Gate to channel current Igc is calculated only for IGCM OD = 1

4.97232 × 10−7
A=
3.42536 × 10−7

7.45669 × 1011
B=
1.16645 × 1012
for NMOS
(3.392)
for PMOS
for NMOS
(3.393)
for PMOS
T 0 = qia · (Vge − 0.5 · Vdsx + 0.5 · Ves + 0.5 · Ved )
(3.394)
Igc0 = Wef f 0 · Lef f · A · Tox,ratio · Igtemp · N F INtotal · T 0
× exp (−B · T OXP · (AIGCi − BIGCi · qia ) · (1 + CIGCi · qia ))
q
2
Vdsef f x = Vdsef
f x + 0.01 − 0.1
(3.395)
(3.396)
Igcs = Igc0 ·
P IGCDi · Vdsef f x + exp(P IGCDi · Vdsef f x ) − 1.0 + 1.0E − 4
2
P IGCDi2 · Vdsef
f x + 2.0E − 4
Igcd = Igc0 ·
1.0 − (P IGCDi · Vdsef f x + 1.0) exp(−P IGCDi · Vdsef f x ) + 1.0E − 4
2
P IGCDi2 · Vdsef
f x + 2.0E − 4
(3.397)
(3.398)
55
Gate to source/drain current Igs , Igd are calculated only for IGCM OD = 1

4.97232 × 10−7
A=
3.42536 × 10−7

7.45669 × 1011
B=
1.16645 × 1012
q
0
2 + 10−4
Vgs
= Vgs
q
0
2 + 10−4
= Vgd
Vgd
igsd,mult = Igtemp ·
for NMOS
(3.399)
for PMOS
for NMOS
(3.400)
for PMOS
(3.401)
Wef f 0 · A
2
(T OXP · P OXEDGEi )
·
T OXREF
T OXP · P OXEDGEi
(3.402)
N T OXi
(3.403)
0
Igs = igsd,mult · DLCIGS · Vgs · Vgs
· N F INtotal
0
0
× exp −B · T OXP · P OXEDGEi · AIGSi − BIGSi · Vgs
· 1 + CIGSi · Vgs
(3.404)
0
· N F INtotal
Igd = igsd,mult · DLCIGD · Vgd · Vgd
0
0
· 1 + CIGDi · Vgd
× exp −B · T OXP · P OXEDGEi · AIGDi − BIGDi · Vgd
(3.405)
3.16
Non Quasi-static Models
This version offers three different Non quasi-static (NQS) models. Each of these can
be turned on/off using the NQSMOD switch. Setting N QSM OD = 0 turns off all NQS
models and switches to plain quasi-static calculations.
Gate Resistance Model (N QSM OD = 1)
NQS effects for N QSM OD = 1 is modeled through an effective intrinsic input resistance,
Rii [15]. This would introduce a gate node in between the intrinsic gate and the physical gate
electrode resistance (RGATEMOD). This node collapses to the intrinsic gate if the user turns
56
Figure 11: R-C network for calculating deficient charge Qdef and the instantaneous
charge, Qdef /τ is used in place of the quasi-static charges. [17]
off this model.
Wef f
Moc
qia ·
Lef f
Dvsat
µef f Coxe Wef f kT
1
NF
· XRCRG1i · IdovV ds + XRCRG2 ·
=
Rii
N F IN
qLef f
IdovV ds = µ0 (T )Cox
(3.406)
(3.407)
Charge Deficit Model (N QSM OD = 2)
The charge-deficit model from BSIM4 has been adopted here [16]. Based on a relaxation
time approach, the deficient charge (equilibrium quasi-static charge minus the instantaneous
channel charge) is kept track through a R-C sub-circuit [17]. An extra node whose voltage
is equal to the deficient charge is introduced for this purpose. The instantaneous channel
charge that is obtained from the self-consistent solution of the MOSFET and R-C sub-circuit
is then split between the source and drain using a partition ratio (Xd,part ) calculated from the
quasi-static charges. A capacitance of 1 Farad is used for this purpose, while the resistance is
give by the inverse of the relaxation time constant, 1/τ .
57
Xd,part =
qd
qg
(3.408)
Wef f
Moc
qia
Lef f
Dvsat
µef f Coxe Wef f kT
1
NF
=
· XRCRG1i · IdovV ds + XRCRG2 ·
Rii
N F IN
qLef f
1
1
=
τ
Rii · Cox · Wef f · Lef f
IdovV ds = µ0 (T )Cox
(3.409)
(3.410)
(3.411)
Charge Segmentation Model (N QSM OD = 3)
Note: This model is not supported for COREM OD = 1 && GEOM OD 6= 3, i.e. for double
gate and likes together with the simplified surface potential solution.
The charge segmentation approach is a simplified form of a full-fledged segmentation where
a long channel transistor is divided into N number of segments each of length
L
N.
The approach
used here takes advantage of the fact that the core I-V and the C-V model can be broken down
and expressed into separate functions of the source end and the drain end channel charge (qis
and qid respectively), i.e. a certain F(qis )-F(qid ) for some functional form F(). Based on the
value for the parameter NSEG (minimum 4 and a maximum of 10), selecting N QSM OD = 3
would introduce NSEG-1 number of internal nodes (q1 , q2 , ...qN SEG−1 ) in the channel. From
the bias-independent calculation up until the surface potential solutions including calculations
pertaining to mobility degradation, velocity saturation , channel length modulation are all
performed only once for a given transistor. However the core I-V and C-V calculations are
repeated NSEG number of times with varying boundary conditions. The calculations for the
n-th segement would be look something like F(qn−1 ) - F(qn ). The continuity of current together
with the boundary conditions imposed by the quasi-static solutions to the surface potential
at source and drain ends (qis and qid ) would yield a self-consistent result where the voltage
at each of nodes, V (qn ) would end up being the channel charge at that position. The leakage
currents and other effects are also evaluated only once. The computational effort is far less
compared to a full-fledged segmentation as the core I-V and C-V calculations take up only a
fraction of the time compared to a full transistor model. There is no non quasi-static effect for
the body charge, as the channel is assumed to be fully-depleted. This model does not extend
58
Figure 12: A N-segment charge-segmented MOSFET with N-1 internal nodes
59
to accumulation region where we assume the holes are supplied quickly form the body contact
for the BULKMOD=1 case.
This model introduces no new parameters, and hence does not require any additional fitting
/ measurements to be performed. The DC and AC results for NQSMOD=3 and NSEG number
of segments are also self-consistent with the quasi-static results. We are still investigating a
metric to identify the best number of segments, NSEG that would suit your accuracy while
balancing the additional computational effort introduced with each additional segment.
3.17
Generation-recombination Component
3
)
Ids,gen = HF IN · T F IN · (Lef f − LIN T IGEN ) · (AIGENi · Vds + BIGENi · Vds
qEg
T
− 1 × N F INtotal
(3.412)
· exp
N T GENi · kT T N OM
3.18
Junction Current and capacitances
The junction current and capacitances are only calculated for bulk multi-gate devices
(BU LKM OD = 1).
60
Source side junction current
Isbs = ASEJ · Jss (T ) + P SEJ · Jssws (T ) + Wef f 0 · N F INtotal · Jsswgs (T )
kT
· N JS
q
BV S
· XJBV S
XExpBV S = exp −
N Vtms
IJT HSF W D
Tb = 1 +
− XExpBV S
Isbs
q


Tb + Tb2 + 4 · XExpBV S

VjsmF wd = N Vtms · ln 
2
VjsmF wd
T0 = exp
N Vtms
XExpBV S
+ XExpBV S − 1
IVjsmF wd = Isbs T0 −
To
Isbs
XExpBV S
SslpF wd =
· T0 +
N Vtms
T0
!
IJT HSREV
−
1
Isbs
VjsmRev = −BV S − N Vtms · ln
XJBV S
BV S + VjsmRev
T1 = XJBV S · exp −
N Vtms
N Vtms =
IVjsmRev = Isbs · (1 + T1 )
SslpRev = −Isbs ·
(3.413)
(3.414)
(3.415)
(3.416)
(3.417)
(3.418)
(3.419)
(3.420)
(3.421)
(3.422)
(3.423)
T1
N Vtms
(3.424)
61
Bias Dependent Calculations
If Ves < VjsmRev
Ves
− 1 · (IVjsmRev + SslpRev (Ves − VjsmRev ))
Ies = exp
N Vtms
(3.425)
Else If VjsmRev ≤ Ves ≤ VjsmF wd
Ves
BV S + Ves
Ies = Isbs · exp
+ XExpBV S − 1 − XJBV S · exp −
N Vtms
N Vtms
(3.426)
Else Ves > VjsmF wd
Ies = IVjsmF wd + SslpF wd (Ves − VjsmF wd )
62
(3.427)
Drain side junction current
Isbd = ADEJ · Jsd (T ) + P DEJ · Jsswd (T ) + Wef f 0 · N F INtotal · Jsswgd (T )
kT
· N JD
q
BV D
· XJBV D
XExpBV D = exp −
N Vtmd
IJT HDF W D
Tb = 1 +
− XExpBV D
Isbd
q


Tb + Tb2 + 4 · XExpBV D

VjdmF wd = N Vtmd · ln 
2
VjdmF wd
T0 = exp
N Vtmd
XExpBV D
+ XExpBV D − 1
IVjdmF wd = Isbd T0 −
To
XExpBV D
Isbd
· T0 +
DslpF wd =
N Vtmd
T0
!
IJT HDREV
−
1
Isbd
VjdmRev = −BV D − N Vtmd · ln
XJBV D
BV D + VjdmRev
T1 = XJBV D · exp −
N Vtmd
N Vtmd =
IVjdmRev = Isbd · (1 + T1 )
DslpRev = −Isbd ·
(3.428)
(3.429)
(3.430)
(3.431)
(3.432)
(3.433)
(3.434)
(3.435)
(3.436)
(3.437)
(3.438)
T1
N Vtmd
(3.439)
63
If Ved < VjdmRev
Ved
− 1 · (IVjdmRev + DslpRev (Ved − VjdmRev ))
Ied = exp
N Vtmd
(3.440)
Else If VjdmRev ≤ Ved ≤ VjdmF wd
Ved
BV D + Ved
Ied = Isbd · exp
+ XExpBV D − 1 − XJBV D · exp −
N Vtmd
N Vtmd
(3.441)
Else Ved > VjdmF wd
Ied = IVjdmF wd + DslpF wd (Ved − VjdmF wd )
(3.442)
Source side junction capacitance
Czbs = CJS(T ) · ASEJ
(3.443)
Czbssw = CJSW S(T ) · P SEJ
(3.444)
Czbsswg = CJSW GS(T ) · Wef f 0 · N F INtotal
(3.445)

1−M JS
Ves

1− 1− P BS(T

)
Ves < 0
Czbs · P BS(T ) ·
1−M JS
Qes1 =

V · C + V 2 · M JS·Czbs
Ves > 0
es
zbs
es 2·P BS(T )

1−M JSW S
Ves

1− 1− P BSW

S(T )
Czbssw · P BSW S(T ) ·
Ves
1−M JSW S
Qes2 =

V · C
2 M JSW S·Czbssw
Ves
es
zbssw + Ves · 2·P BSW S(T )

1−M JSW GS
Ves

1− 1− P BSW

GS(T )
Czbsswg · P BSW GS(T ) ·
1−M JSW GS
Qes3 =

V · C
2 M JSW GS·Czbsswg
es
zbsswg + Ves · 2·P BSW GS(T )
Qes = Qes1 + Qes2 + Qes3
(3.446)
<0
(3.447)
>0
Ves < 0
(3.448)
Ves > 0
(3.449)
Two-Step Source side junction capacitance
In some cases, the depletion edge in the channel/ substrate edge might transition into a region
64
with a different doping (for ex. in a NMOS device: [n+ (source) , p1 (channel/substrate) ,
p2 (substrate)], where p1 and p2 are regions with different doping levels). The following could
be used to capture such a situation. In what follows, Vescn (< 0) can be interpreted as the
transition voltage at which the depletion region switches from p1 to p2 region. It is calculated
assuming parameters SJxxx (proportionality constant for second region) and MJxxx2 (gradient
of second region’s doping) are given, to give a continuous charge and capacitance.
For Ves < Vesc1

Vesc1
P BS(T )
1−M JS
1− 1−

Qes1 = Czbs · P BS(T ) ·
1 − M JS

+ SJS · P bs2 ·
Ves −Vesc1 1−M JS2

P bs2
1− 1−
1 − M JS2
(3.450)
Else use the Qes1 of single junction above for Ves > Vesc1 where,
1 !
M JS
1
Vesc1 = P BS(T ) · 1 −
SJS
P bs2 =
P BS(T ) · SJS · M JS2
−1−M JS
esc1
M JS · 1 − P VBS(T
)
(3.451)
(3.452)
For Ves < Vesc2
1− 1−
Qes2 = Czbssw · P BSW S(T ) ·
Vesc2
P BSW S(T )
1−M JSW S
1 − M JSW S
−Vesc2 1−M JSW S2
1 − 1 − Ves
P bsws2
+ Czbssw · SJSW S · P bsws2 ·
1 − M JSW S2
1 !
M JSW S
1
Vesc2 = P BSW S(T ) · 1 −
SJSW S
P bsws2 =
P BSW S(T ) · SJSW S · M JSW S2
−1−M JSW S
Vesc2
M JSW S · 1 − P BSW
S(T )
65
(3.453)
(3.454)
(3.455)
(3.456)

For Ves < Vesc3
1− 1−
Qes3 = Czbsswg · P BSW GS(T ) ·
+ Czbsswg · SJSW GS · P bswgs2 ·
Vesc3
P BSW GS(T )
1−M JSW GS
1 − M JSW GS
1−M JSW GS2
−Vesc3
1 − 1 − VPesbswgs2
1 − M JSW GS2
!
1
M JSW GS
1
Vesc3 = P BSW GS(T ) · 1 −
SJSW GS
P bswgs2 =
(3.457)
(3.458)
(3.459)
P BSW GS(T ) · SJSW GS · M JSW GS2
−1−M JSW GS
Vesc3
M JSW GS · 1 − P BSW
GS(T )
(3.460)
Drain side junction capacitance
Czbd = CJD(T ) · ADEJ
(3.461)
Czbdsw = CJSW D(T ) · P DEJ
(3.462)
Czbdswg = CJSW GD(T ) · Wef f 0 · N F INtotal
(3.463)

1−M JD
Ved

1− 1− P BD(T

)
Ved < 0
Czbd · P BD(T ) ·
1−M JD
Qed1 =

V · C + V 2 · M JD·Czbd
Ved > 0
ed
zbd
ed 2·P BD(T )

1−M JSW D
V

1− 1− P BSWed

D1(T )
Czbdsw · P BSW D(T ) ·
Ved
1−M JSW D
Qed2 =

V · C
2 M JSW D·Czbdsw
Ved
ed
zbdsw + Ved · 2·P BSW D(T )

1−M JSW GD
V

1− 1− P BSWed

GD(T )
Czbdswg · P BSW GD(T ) ·
1−M JSW GD
Qed3 =

V · C
2 M JSW GD·Czbdswg
ed
zbdswg + Ved · 2·P BSW GD(T )
Qed = Qed1 + Qed2 + Qed3
(3.464)
<0
(3.465)
>0
Ved < 0
(3.466)
Ved > 0
(3.467)
Two-Step Drain side junction capacitance
Refer to the description made for the source side.
66
For Ved < Vedc1

1− 1−

Qed1 = Czbd · P BD(T ) ·
Vedc1
P BD(T )
1−M JD
1− 1−
+ SJD · P bd2 ·
1 − M JD
Ved −Vedc1
P bd2
1−M JD2 
1 − M JD2
(3.468)
Else use the Qed1 of single junction above for Ved > Vedc1 where,
1 !
M JD
1
Vedc1 = P BD(T ) · 1 −
SJD
P bd2 =
P BD(T ) · SJD · M JD2
−1−M JD
Vedc1
M JD · 1 − P BD(T
)
(3.469)
(3.470)
For Ved < Vedc2
1− 1−
Qed2 = Czbdsw · P BSW D(T ) ·
+ Czbdsw · SJSW D · P bswd2 ·
Vedc2
P BSW D(T )
1−M JSW D
1 − M JSW D
1−M JSW D2
−Vedc2
1 − 1 − Ved
P bswd2
1 − M JSW D2
1 !
M JSW D
1
Vedc2 = P BSW D(T ) · 1 −
SJSW D
P bswd2 =
P BSW D(T ) · SJSW D · M JSW D2
−1−M JSW D
Vedc2
M JSW D · 1 − P BSW D(T )
(3.471)
(3.472)
(3.473)
(3.474)
For Ved < Vedc3
1− 1−
Qed3 = Czbdswg · P BSW GD(T ) ·
+ Czbdswg · SJSW GD · P bswgd2 ·
Vedc3
P BSW GD(T )
1−M JSW GD
1 − M JSW GD
1−M JSW GD2
−Vedc3
1 − 1 − VPedbswgd2
1 − M JSW GD2
67
(3.475)
(3.476)


Figure 13: R-C network for self-heating calculation [13]
!
1
M JSW GD
1
Vedc3 = P BSW GD(T ) · 1 −
SJSW GD
P bswgd2 =
3.19
P BSW GD(T ) · SJSW GD · M JSW GD2
−1−M JSW GD
Vedc3
M JSW GD · 1 − P BSW
GD(T )
(3.477)
(3.478)
Self-heating model
The self-heating effect is modeled using an R-C network approach (based on BSIMSOI
[13]), as illustrated in figure 13. The voltage at the temperature node (T) is used for all
temperature-dependence calculations in the model.
Thermal resistance and capacitance calculations
The thermal resistance (Rth ) and capacitance (Cth ) are modified from BSIMSOI to capture
the fin pitch (F P IT CH) dependence.
W T H0 + F P IT CH · N F INtotal
1
= Gth =
Rth
RT H0
(3.479)
Cth = CT H0 + F P IT CH · N F INtotal
(3.480)
68
Table 1: Origin of noise models in BSIM-CMG
Model in BSIM-CMG 106.0.0
Origin
Flicker noise model
BSIM4 Unified Model (FNOIMOD=1)
Thermal noise
BSIM4 TNOIMOD=0
Gate current shot noise
BSIM4 gate current noise
Noise associated with parasitic resistances
BSIM4 parasitic resistance noise
3.20
Noise Models
Noise models in BSIM-CMG are based on BSIM4 [10]. Table 1 lists the origin of
each noise model:
69
Flicker noise model
Esat,noi =
2V SATi
µef f
(3.481)
Lef f,noi = Lef f − 2 · LIN T N OI
(3.482)
Vds − Vdsef f
1
·
∆Lclm = l · ln
+ EM
(3.483)
Esat,noi
l
Coxe · qis
N0 =
(3.484)
q
Coxe · qid
Nl =
(3.485)
q
kT
N ∗ = 2 (Coxe + CIT )
(3.486)
q
N0 + N ∗
N OIC 2
(3.487)
F N 1 = N OIA · ln
(N0 − Nl2 )
+ N OIB · (N0 − Nl ) +
∗
Nl + N
2
N OIA + N OIB · Nl + N OIC · Nl2
FN2 =
(3.488)
(Nl + N ∗ )2
2 ∆L
kT q 2 µef f Ids
kT Ids
clm
·
F
N
1
+
· FN2
Ssi =
Coxe L2ef f,noi f EF · 1010
Wef f · N F INtotal · L2ef f,noi f EF · 1010
(3.489)
2
N OIA · kT · Ids
Wef f · N F INtotal · Lef f,noi f EF · 1010 · N ∗ 2
Swi Ssi
Sid,f licker =
Swi + Ssi
Swi =
(3.490)
(3.491)
Thermal noise model (T N OIM OD = 0)
Qinv = |Qs,intrinsic + Qd,intrinsic | × N F INtotal

4kT ∆f


if RDSMOD = 0
N T N OI ·
L2
Rds + µ efQf
2
id =
ef f inv


4kT
∆f
N T N OI · 2
· µef f Qinv if RDSMOD = 1
L
ef f
70
(3.492)
(3.493)
Gate current shot noise
i2gs = 2q(Igcs + Igs )
(3.494)
i2gd = 2q(Igcd + Igd )
(3.495)
i2gb = 2qIgbinv
(3.496)
Resistor noise The noise associated with each parasitic resistors in BSIM-MG are calculated
If RDSM OD = 1 then
i2RS
1
= 4kT ·
∆f
Rsource
(3.497)
i2RD
1
= 4kT ·
∆f
Rdrain
(3.498)
If RGAT EM OD = 1 then
i2RG
1
= 4kT ·
∆f
Rgeltd
(3.499)
71
Table 2: Sample input decks for BSIM-CMG
4
Netlist
Description
idvgnmos.sp
Id - Vgs characteristics for n-FETs (25 ◦ C)
idvgpmos.sp
Id - Vgs characteristics for p-FETs (25 ◦ C)
idvdnmos.sp
Id - Vds characteristics for n-FETs (25 ◦ C)
idvdpmos.sp
Id - Vds characteristics for p-FETs (25 ◦ C)
ac.sp
AC simulation example
noise.sp
Noise simulation example
gummel n.sp
Gummel symmetry test for nFET
gummel p.sp
Gummel symmetry test for pFET
inv dc.sp
Inverter DC simulation
rdsgeo.sp
Test for RGEOMOD=1
cfrgeo.sp
Test for CGEOMOD=2
inverter transient.sp
Inverter transient response simulation example
ringosc 17stg.sp
17-stage ring oscillator simulation example
Simulation Outputs
Sample input decks for BSIM-CMG are listed in Table 2
72
Table 4: Examples of parameters that are measured or specified by the user
Parameter Name
Description
EOT
Gate oxide thickness
HFIN
Fin Height
TFIN
Fin Thickness
L
Fin Length Drawn
NFIN
Number of Fins
NF
Number of Fingers in parallel
NBODY
Channel Doping Concentration
BULKMOD
0: SOI 1: bulk
GIDLMOD
0: off 1:on
GEOMOD
0: double gate 1: triple gate 2: quadruple gate
RDSMOD
0: internal 1: external
DEVTYPE
0: PMOS 1:NMOS
NGATE
0: metal gate > 0: Poly Gate doping
5
5.1
5.1.1
Parameter Extraction Procedure
Global Parameter Extraction
Basic Device Parameter List
The objective of this procedure is to find one global set of parameters for BSIMCMG to fit experimental data for devices with channel length ranging from short to
long dimensions. The original work is published in [18].
Some parameters are measured or specified by user, and need not be extracted, such
as those given in Table 4.
Parameters that are going to be extracted are divided into two categories. Category
One parameters are presented as the coefficients in a set of length dependent intermedi73
ate quantities. These intermediate quantities are introduced to facilitate the extraction
procedure. To keep the procedure simple, these quantities are not visible to the end
user. Category Two parameters don’t appear in these intermediate quantities.
The length dependent intermediate quantities, 9 in total, are summarized below.
Group 1: U0[L], ∆L[L], UA[L], UD[L], RDSW[L] [Relates to Mobility and Rseries ]
Group 2: VSAT[L], VSAT1[L], PTWG[L] [Relates to Velocity Saturation]
Group 3: MEXP[L] [Relates to Smoothing Functions]
U0[L] and ∆L[L] and the associated Category One parameters are
A
U 0[L] = U 00 × (1 − U P × L−LP
) .....Eq (1); (Here, Lef f = L − 2 × ∆L[L])
ef f
∆L[L] = LIN T + LL × e
−(L+XL)
LLN
.....Eq (2);
The other length dependent quantities UA[L], UD[L], RDSW[L], MEXP[L], VSAT[L],
VSAT1[L], PTWG[L]. These 8 length dependent variables have identical functional form,
and are represented as Param[L]:
Lef f
P aram[L] = P aram0 + AP aram × e− Bparam .....Eq(4);
Lef f
Example: U A[L] = U A0 + AU A × e− BU A
Here, P aram[L] = P aram0 when Lef f is large, while AParam, BParam are geometry
scaling parameters which add necessary correction to P aram0 when the Lef f shrinks.
P aram0 , AParam, BParam belong to Category One.
Category Two parameters which don’t appear in the length dependent functions are:
PHIG, CIT, EU, ETAMOB, DVT0, DVT1, CDSC, DVT2, ETA0, DSUB, CDSCD,
AGIDL, BGIDL, EGIDL, VTL, XN, LC,MM, PCLM, PDIBL1, PDIBL2, DROUT,
PVAG, etc
Since Category One parameters can only manifest themselves by first yielding the 9
length dependent intermediate quantities, determining the value of these intermediate
quantities is inevitable if we want to extract them. Category Two parameters, however,
can be extracted from experimental data directly.
Now we start extracting all the global parameters in both categories.
The extraction procedure can be divided into 8 stages:
• Parameter initialization
• Linear region: Step 1-6
74
Figure 14: Extraction Flow Chart
• Saturation region: Step 7-11
• GIDL and Output Conductance: Step 12-13
• Smoothing between linear and saturation regions: Step 14
• Parameters for temperature effect and self-heating effect: Step 15
• Gate / Junction leakage current : Step 16
• Other important physical effects : Step 17
See the extraction overview flow chart for details.
5.1.2
Parameter Initialization
• Determine Vth (L) by strong inversion region data using maximum slope extrapolation algorithm.
• Plot
Vd (∼0.05V )
v.s.L
Id (Vg ,L)
for different
• Make linear fitting to the curve set above, extrapolate each straight line and find
the intersection (∆L ,Rseries ), Initialize LINT = ∆L
, RDSW = Rseries as shown in the
2
Fig. 15.
75
Figure 15: Initialize ∆L and Rseries
76
Figure 16: Initialize SCE and RSCE Parameters
• Use Constant-Current method to extract Vth (L) by using sub-threshold region
data.
• Plot ∆Vth (L)v.s.@Vd ∼ 0.05V and Vdd respectively. Extract short channel effect(SCE) and Reverse SCE parameters DVT0, DVT1, ETA0, DSUB, K1RSCE, LPE0
as shown in Figure 16 left.
v.s.L@Vd ∼ 0.05V and Vdd . Extract CDSC, CDSCD, DVT2 as
• Plot 2.3n(L) × kT
q
shown in Figure 16 right.
• Set all other parameters in Category One and Two as default value as the manual
shows.
77
5.1.3
Linear region
Step 1: Extract work function, interface charge and mobility model parameters
for long gate length. [Note: Larger length is better, as it will minimize the short
channel effect and emphasize carrier mobility, work function and interface charge related
parameters.]
Extracted Parameters
Device & Experimental Data
Extraction Methodology
PHIG, CIT
A long device Id v.s. Vg @ Vd ∼
Observe sub-threshold region off-
0.05V
set and slope.
A long device Id v.s. Vg @ Vd ∼
Observe strong inversion region
0.05V
Idlin and Gm lin.
U 00 , U A0 , U D0 , EU, ETAMOB
Step 2: Refine Vth roll-off, DIBL and SS degradation parameters.
DVT0, DVT1, CDSC, DVT2
Both short and medium devices
Observe sub-threshold region of
Id v.s. Vg @ Vd ∼ 0.05V
all devices in the same plot.
Optimize DVT0, DVT1, CDSC,
DVT2.
Note: need not very accurate fitting because mobility, series resistance parameters
are not determined yet.
Step 3: Extract low field mobility U0[L] for long and medium gate lengths.
So far, we have good fit with data in sub-threshold regions from long to short channel
devices, and strong inversion for long channel devices. We need good fit for strong
inversion in medium and short channel devices.
In linear region, current is to the first order, governed by low field mobility. So we
start by tuning low field mobility values.
In short channel devices series resistance, coulombic scattering and enhanced mobility degradation effects are pronounced. To avoid the influence of these effects, long
and medium channel length devices are selected to especially extract low field mobility
parameters.
78
UP,LPA
Long and medium devices Id v.s.
Vg @ Vd ∼ 0.05V U0 [L] = U 00 ×
Idlin and Gm lin, extract U0[L]
A
(1 − U P × L−LP
)
ef f
to get UP,LP. i.e.
for each
Li , find Yi corresponding to Li ,
fit (Li ,Yi ) by Eq(1) to extract
UP,LP). Refer to Figure 17 for
instance.
Step 4: Extract mobility model and series resistance parameters for short gate
lengths.
P aram0 ,AParam,
Short and medium devices Id v.s.
a. Observe strong inversion re-
BParam,LINT, LL,LLN
Vg @ Vd ∼ 0.05V
gion Id lin and Gm lin. Similar
to Step 3, find values of UA[L],
UD[L], RDSW[L] and DeltaL[L]
that gives good fit to experimental data, varying them simultaneously. U A0 ,U D0 are provided
from Step 1 and RDSW0, LINT
are provided from parameter Initialization.
b. Variation of each parameter
with respect to L should be kept
minimal with smooth continuous
trend.
c. From the length dependence
of
UA[L],
UD[L],
RDSW[L]
and L[L], find AUA, BUA;
AUD,BUD; ARDSW, BRDSW;
LL, LLN .
Note: Step 3 parameters are extracted from long and medium channel lengths,
79
Figure 17: Fit low field electron mobility with Lg
80
Figure 18: Id v.s.Vg and Gm v.s.Vg @ Vd ∼ 0.05V
whereas, Step 4 involves short and medium channel lengths. As in Step 4 ’exponential’ corrections are particularly pronounced for small L (short channel). Its Taylor
expansion when Lef f is medium can give appropriate modifications when power functions alone don’t fit very well for medium lengths. Thus, the extracted parameters
remain valid for all channel lengths to bring forth the intended length dependence in
effect.
Step 5: Refine geometry scaling parameters for mobility degradation parameters.
Refined Parameters
AUA,AUD,ARDSW,LL
Short and medium devices Id v.s.
Vg @ Vd ∼ 0.05V
of all devices in the same plot;
optimize AUA, AUD, ARDSW,
LL.
Step 6: Refine all Group 1 scaling parameters.
Further optimize the parameters by repeating step 5 and 2. If not getting good
fitting, tune LLN, BUA, BUD, BRDSW. If still not good, tune other parameters in
Group 1 as appropriate. Iteration ends in step 5 and then proceeds to step 7. A sample
fitting result up till this step is shown in Figure 18.
81
5.1.4
Saturation region
Step 7: Refine DIBL parameters.
ETA0, DSUB, CDSCD
Short and long devices Id v.s. Vg
Observe sub-threshold region of
@ Vd ∼ Vdd
all devices in the same plot. Optimze ETA0, DSUB, CDSCD.
Note: need not very accurate fitting because velocity saturation, smoothing function
and output conductance parameters are not determined yet.
Step 8: Extract velocity saturation parameters for long and medium gate lengths
V SAT0 ,
long device and medium devices
Id v.s. Vg @ Vd ∼ Vdd
Id sat, Gm sat, Id Vd .
V SAT 10 ,
P T W G0 ,
KSAT IV0 , M EXP0
Note: long channel alone is not enough to accurately extract velocity saturation
parameters.
Step 9: Extract velocity saturation parameters for short and medium gate lengths
AVSAT,
AVSAT1,
APTWG,
BVSAT, BVSAT1, BPTWG
short and medium devices Id v.s.
a. Observe strong inversion re-
Vg @ Vd ∼ Vdd
gion of Id sat and Gm sat. Find
VSAT1[Li ]=Xi ,
VSAT[Li ]=Yi ,
PTWG[Li ]=Zi to fit data.
b. Extract AVSAT1, BVSAT1
from (Li , Xi ); AVSAT,BVSAT
from
(Li , Yi );
APTWG,
BPTWG from (Li , Zi ).
Step 10: Refine geometry scaling parameters for velocity saturation, over the range
from short to long channel devices.
Refined Parameters
82
Figure 19: Id v.s.Vg and Gm v.s.Vg @ Vd ∼ Vdd
AVSAT, AVSAT1, APTWG
medium and short devices Id v.s.
Observe strong inversion re-
Vg @ Vd ∼ Vdd
gion
of
all
same plot.
devices
in
the
Optimize AVSAT,
AVSAT1, APTWG.
Step 11: Refine Group 2 scaling parameters.
Further refine the geometry scaling parameters by repeating step 10 and 7. If not
getting good fitting, tune BVSAT, BVSAT1, BPTWG. If still not good, tune other
parameters in Group 2 as appropriate. Iteration ends in step 10 and then proceeds to
step 13. A sample fitting result up till this step is shown in Figure 19.
5.1.5
Other Parameters representing important physical effects
Step 12: Extract GIDL current model parameters.
AGIDL, BGIDL, EGIDL
long and short devices Id v.s. Vd
Observe sub-threshold region Id
@ different Vg
v.s. Vg @ Vd ∼ Vdd & Rout v.s.
Vd @ Vg ∼ 0V .
83
Step 13: Extract output conductance parameters.
MEXP[L],
Long and short devices Id v.s. Vd
@ differentVg
Id v.s.Vd & Gd v.s.Vd @ different
PCLM,
PDIBL1,
PDIBL2, DROUT, PVAG
Vg .
M EXP0 , AMEXP, BMEXP
MEXP[L] v.s. L from Step 14,
Observe data trend; extract AM-
i.e. (Li ,Xi )
EXP and BMEXP. An example
is shown in Figure 20.
A sample global fitting result for Lg =90nm N-Channel MOS is shown in Figure 21
as below.
5.1.7
Other Effects
Step 15: Temperature and Self-Heating Effects.
Thermal resistance (RTH0) and
Ids v.s. Vgs @ Vd Vdd under dif-
Observe data trend and tune
capacitances (CTH0) for the self-
ferent temperatures.
RTH0, CTH0, TNOM, TBGA-
heating model and etc.
SUB, TBGBSUB, etc.
Step 16: Gate / Junction leakage current
Gate tunneling current and junc-
Igb v.s. Vgs @ Vd 0V .
Observe data trend and tune
tion current parameters.
NIGBINV,
AIGBINV,
BIG-
BINV, CIGBINV, EIGBINV,
AS, PS1, PS2, NJS, IJTHSFWD, BVS, XJBVS, AD, PD1,
PD2, NJD, IJTHDFWD, BVD,
XJBVD, etc.
Step 17: Advanced Feature
Non quasi static effect, noise
S-parameters, noise figure, CV
Extract XRCRG1,
model, poly depletion, genera-
measurement, etc.
NOIA, NOIB, NOIC, FN1, FN2,
tion recombination etc.
AIGEN, BIGEN, etc.
84
XRCRG2,
Figure 20: MEXP v.s. Lg
85
Figure 21: Id v.sVd and Rout v.s.Vd
6
Complete Parameter List
6.1
Instance Parameters
Note: Instance parameters with superscript
Name
L
(m)
D
(m)
TFIN
(m)
FPITCH
(m)
NF
NFIN
(m)
NGCON
(m)
(m)
ASEO
(m)
are also model parameters
Unit
Default
Min
Max
Description
m
30n
1n
-
Designed Gate Length
m
40n
1n
-
Diameter of cylinder (for GEOM OD = 3)
m
15n
1n
-
Body (fin) thickness
m
80n
TFIN
-
Fin Pitch
-
1
1
-
Number of fingers
-
1
1
-
Number of fins per finger
1
1
2
Number of gate contacts
0
0
-
Source to substrate overlap area through oxide
2
m
(all fingers)
86
ADEO(m)
m2
0
0
-
Drain to substrate overlap area through oxide
(all fingers)
(m)
PSEO
m
0
0
-
Perimeter of source to substrate overlap region
through oxide (all fingers)
(m)
PDEO
m
0
0
-
Perimeter of drain to substrate overlap region
through oxide (all fingers)
(m)
ASEJ
2
m
0
0
-
Source junction area (all fingers; for bulk
MuGFETs, BU LKM OD = 1)
ADEJ
(m)
2
m
0
0
-
Drain junction area (all fingers; for bulk
(m)
PSEJ
m
0
0
-
Source junction perimeter (all fingers; for bulk
(m)
PDEJ
m
0
0
-
Drain junction perimeter (all fingers; for bulk
CGSP
(m)
F
0
0
-
Constant gate to source fringe capacitance (for
CGEOM OD = 1)
CGDP
(m)
F
0
0
-
F
0
0
-
Constant gate to drain fringe capacitance (for
CGEOM OD = 1)
CDSP(m)
Constant drain to source fringe capacitance
(for CGEOM OD = 1)
NRS
(m)
-
0
0
-
Number of source diffusion squares (for
RGEOM OD = 0)
NRD
(m)
-
0
0
-
Number of drain diffusion squares (for
RGEOM OD = 0)
LRSD
(m)
6.2
m
L
0
-
Length of the source/drain
Model Controllers and Process Parameters
Note: binnable parameters are marked as:
(b)
Name
Unit
Default
Min
Max
Description
DEVTYPE
-
NMOS
PMOS
NMOS
NMOS=1, PMOS=0
87
BULKMOD
-
0
0
1
Substrate model selector. 0 = multi-gate on
SOI substrate, 1 = multi-gate on bulk substrate.
COREMOD
-
0
0
1
simplified surface potential selector ; 0=turn
off, 1=turn on (lightly-doped or undoped)
GEOMOD
-
1
0
3
structure selector; 0 = double gate, 1 = triple
gate, 2 = quadruple gate, 3 = cylindrical gate
RDSMOD
-
0
0
1
bias-dependent source/drain resistance model
selector (controls si and di nodes); 0 = internal, 1 = external
IGCMOD
-
0
0
1
model selector for Igc, Igs and Igd; 1=turn on,
0=turn off
IGBMOD
-
0
0
1
model selector for Igb; 1=turn on, 0=turn off
GIDLMOD
-
0
0
1
GIDL/GISL current switcher; 1=turn on,
0=turn off
IIMOD
-
0
0
2
impact ionization model switch; 0 = OFF, 1
= BSIM4 based, 2 = BSIMSOI based
NQSMOD
-
0
0
1
NQS gate resistor and gi node switcher;
1=turn on, 0=turn off
SHMOD
-
0
0
1
Self-heating and T node switcher; 1=turn on,
0=turn off
RGATEMOD
-
0
0
1
Gate electrode resistor and ge node switcher ;
1=turn on, 0=turn off
RGEOMOD
-
0
0
1
bias independent parasitic resistance model
selector (see sec. 3.13)
CGEOMOD
-
0
0
2
parasitic capacitance model selector (see sec.
3.13)
CAPMOD
-
0
0
1
accumulation region capacitance model selector; 0=no accumulation capacitance, 1=accumulation capacitance included
XL
m
0
-
-
L offset for channel length due to mask/etch
effect
88
LINT
m
0.0
-
-
Length reduction parameter (dopant diffusion
effect)
(LLN +1)
LL
m
0.0
-
-
effect)
LLN
-
1.0
-
-
effect)
DLC
m
0.0
-
-
Length reduction parameter for CV (dopant
diffusion effect)
(LLN +1)
LLC
m
0.0
-
-
Length reduction parameter for CV (dopant
diffusion effect)
DLBIN
m
0.0
-
-
Length reduction parameter for binning
EOT
m
1.0n
0.1n
-
SiO2 equivalent gate dielectric thickness (including inversion layer thickness)
TOXP
m
1.2n
0.1n
-
Physical oxide thickness
EOTBOX
m
140n
1n
-
SiO2 equivalent buried oxide thickness (including substrate depletion)
HFIN
m
30n
1n
-
fin height
FECH
-
1.0
0
-
end-channel
factor,
for
different
orien-
taion/shape (Mobility difference between the
side channel and the top channel is handled
by this parameter)
DELTAW
m
0.0
-
-
reduction of effective width due to shape of fin
FECHCV
-
1.0
0
-
CV end-channel factor, for different orientaion/shape
DELTAWCV
m
0.0
-
-
CV reduction of effective width due to shape
of fin
NBODY
(b)
NSD
PHIG
(b)
EPSROX
−3
m
1e22
1e18
5e24
channel (body) doping concentration
m−3
2e26
2e25
1e27
S/D doping concentration
eV
4.61
0
-
workfunction of gate
-
3.9
1
-
relative dielectric constant of the gate insulator
2
Model currently supports N BODY < 5 × 1024 m−3 . For larger values, we recommend the use of
BSIM4 or BSIM4SOI.
89
2
EPSRSUB
-
11.9
1
-
relative dielectric constant of the channel material
EASUB
eV
NI0SUB
−3
m
4.05
0
-
electron affinity of the substrate material
1.1e16
-
-
intrinsic carrier concentration of channel at
300.15K
BG0SUB
NC0SUB
(b)
NGATE
eV
1.12
-
-
band gap of the channel material at 300.15K
−3
2.86e25
-
-
conduction band density of states at 300.15K
−3
0
-
-
parameter for Poly Gate doping.
m
m
N GAT E = 0 for metal gates
90
Set
6.3
Basic Model Parameters
Name
CIT
Unit
(b)
CDSC
(b)
(b)
Default
Min
Max
Description
F/m
2
0.0
-
-
parameter for interface trap
F/m
2
7e-3
0.0
-
coupling capacitance between S/D and
F/m
2
channel
(b)
CDSCD
DVT0
(b)
DVT1
(b)
(b)
PHIN
7e-3
0.0
-
drain-bias sensitivity of CDSC
-
0.0
0.0
-
SCE coefficient
-
0.60
>0
-
SCE exponent coefficient
V
0.05
-
-
nonuniform vertical doping effect on
surface potential
(b)
ETA0
-
(b)
DSUB
(b)
K1RSCE
V
1/2
0.60
0.0
-
DIBL coefficient
1.06
>0
-
DIBL exponent coefficient
0.0
-
-
prefactor for reverse short channel effect
(b)
LPE0
m
−Lef f
5e-9
-
equivalent length of pocket region at
zero bias
DVTSHIFT
QMFACTOR
(b)
QMTCENIV
V
-
0.0
-
Additional Vth shift handle
-
0.0
-
-
prefactor for QM Vth shift correction
-
0.0
-
-
prefactor/switch for QM effective width
correction for IV
QMTCENCV
-
0.0
-
-
prefactor/switch for QM effective width
and oxide thickness correction for CV
ETAQM
-
0.54
-
-
body-charge coefficient for QM charge
centroid
QM0
V
1e-3
>0
-
normalization parameter for QM charge
centroid (inversion)
PQM
-
0.66
-
-
Fitting parameter for QM charge centroid (inversion)
QM0ACC
V
1e-3
>0
-
normalization parameter for QM charge
centroid (accumulation)
PQMACC
-
0.66
-
-
Fitting parameter for QM charge centroid (accumulation)
91
VSAT(b)
m/s
85000
-
-
saturation velocity for the saturation
region
(b)
VSAT1
(b)
DELTAVSAT
m/s
VSAT
-
-
saturation velocity for the linear region
-
1.0
0.01
-
velocity saturation parameter in the linear region
(b)
KSATIV
-
(b)
-
MEXP
PTWG
U0
(b)
(b)
ETAMOB
UP
(b)
UA
parameter for long channel Vdsat
2
-
smoothing function factor for Vdsat
0.0
-
-
Correction factor for velocity saturation
2
m /V − s
3e-2
-
-
low field mobility
-
2.0
-
-
effective field parameter
0.0
-
-
mobility L coefficient
1.0
-
-
mobility L power coefficient
0.3
> 0.0
-
phonon / surface roughness scattering
LP A
-
(b)
-
4
µm
LPA
-
−2
V
(b)
1.0
(cm/M V )
EU
parameter
EU
(b)
cm/M V
2.5
> 0.0
-
phonon / surface roughness scattering
parameter
UD
(b)
(b)
UCS
PCLM
(b)
cm/M V
0.0
> 0.0
-
columbic scattering parameter
-
1.0
> 0.0
-
columbic scattering parameter
-
0.013
> 0.0
-
Channel Length Modulation (CLM) parameter
PCLMG
(b)
-
0
-
-
Gate bias dependent parameter for
channel Length Modulation (CLM)
(b)
VASAT
V
0.2
-
-
Channel Length Modulation (CLM) parameter
RDSWMIN
Ω−
R
µW
m
0.0
0.0
-
RDSM OD = 0 S/D extension resistance per unit width at high Vgs
RDSW(b)
R
Ω − µW
m
100
0.0
-
RDSM OD = 0 zero bias S/D extension resistance per unit width
RSWMIN
Ω−
R
µW
m
Ω−
R
µW
m
0.0
0.0
-
RDSM OD = 1 source extension resistance per unit width at high Vgs
(b)
RSW
50
0.0
-
RDSM OD = 1 zero bias source extension resistance per unit width
92
R
Ω − µW
m
RDWMIN
0.0
0.0
-
RDSM OD = 1 drain extension resistance per unit width at high Vgs
RDW
(b)
Ω−
R
µW
m
50
0.0
-
RDSM OD = 1 zero bias drain extension resistance per unit width
PRWG
(b)
V
−1
0.0
0.0
-
gate bias dependence of S/D extension
resistance
(b)
WR
-
1.0
-
-
W dependence parameter of S/D extension resistance
RGEXT
Ω
0.0
0.0
-
Effective gate electrode external resistance (Experimental)
RGFIN
Ω
1.0e-3
1.0e-3
-
Effective gate electrode resistance per
fin per finger
RSHS
RSHD
Ω
0.0
0.0
-
Source-side sheet resistance
Ω
RSHS
0.0
-
Drain-side sheet resistance
PDIBL1
(b)
-
1.30
0.0
-
parameter for DIBL effect on Rout
PDIBL2
(b)
-
2e-4
0.0
-
parameter for DIBL effect on Rout
(b)
-
1.06
> 0.0
-
L dependence of DIBL effect on Rout
1.0
-
-
Vgs dependence on early voltage
1.11e-2
-
-
parameter for Igb in inversion
9.49e-4
-
-
6.00e-3
-
-
1.1
-
-
3.0
> 0.0
-
1.36e-2
-
-
parameter for Igb in accumulation
1.71e-3
-
-
7.5e-2
-
-
1.0
> 0.0
-
1.36e-2
-
-
parameter for Igc in inversion
1.71e-3
-
-
0.075
-
-
DROUT
PVAG
(b)
(b)
2
(F s /g)
0.5
(b)
2
0.5
AIGBINV
BIGBINV
V
(b)
V
(b)
-
CIGBINV
EIGBINV
NIGBINV
BIGBACC
2
(F s /g)
0.5
(b)
2
0.5
CIGBACC
(F s /g)
(b)
V
(b)
-
NIGBACC
2
(F s /g)
0.5
(b)
2
0.5
CIGC
V
−1
m
−1
m
−1
V
−1
−1
(b)
AIGC
m
−1
−1
(b)
AIGBACC
BIGC
(F s /g)
(b)
m
−1
(F s /g)
−1
m
−1
m
−1
V
−1
(b)
V
(b)
-
1.0
> 0.0
-
-
1.0
> 0.0
-
Vds dependence of Igcs and Igcd
m
0.0
-
-
Delta L for Igs model.
NIGC
PIGCD
(b)
DLCIGS
93
(F s2 /g)0.5 m−1
AIGS(b)
BIGS
(b)
CIGS
2
(F s /g)
(b)
BIGD
2
(F s /g)
0.5
(b)
2
0.5
CIGD
V
−1
m
(b)
AIGD
m
−1
−1
V
DLCIGD
0.5
(F s /g)
(b)
−1
V
POXEDGE
(b)
−1
m
−1
m
−1
V
−1
1.36e-2
-
-
parameter for Igs in inversion
1.71e-3
-
-
0.075
-
-
DLCIGS
-
-
Delta L for Igd model.
AIGS
-
-
parameter for Igd in inversion
BIGS
-
-
CIGS
-
-
1
> 0.0
-
Factor for the gate edge Tox
6.055e-12
-
-
pre-exponetial coeff. for GIDL
0.3e9
-
-
exponential coeff. for GIDL
(b)
Ω
(b)
V /m
(b)
V
3
0.2
-
-
parameter for body bias effect of GIDL
EGIDL(b)
V
0.2
-
-
band bending parameter for GIDL
PGIDL(b)
−
1.0
-
-
Exponent of electric field for GIDL
AGISL(b)
Ω−1
AIGDL
-
-
pre-exponetial coeff for GISL.
BGISL(b)
V /m
BGIDL
-
-
exponential coeff. for GISL
CGISL(b)
V3
0.2
-
-
parameter for body bias effect of GISL
EGISL(b)
V
EGIDL
-
-
band bending parameter for GISL
1.0
-
-
Exponent of electric field for GISL
AGIDL
BGIDL
CGIDL
PGISL(b)
−
ALPHA0
(b)
(b)
ALPHA1
(b)
BETA0
m·V
−1
0.0
-
-
first parameter of Iii (IIMOD=1)
V
−1
0.0
-
-
L scaling parameter of Iii (IIMOD=1)
V
−1
0.0
-
-
Vds
dependent
paramter
of
Iii
for
Iii
paramter
of
Iii
paramter
of
Iii
paramter
of
Iii
(IIMOD=1)
(b)
ALPHAII
−
0.0
-
-
Pre-exponential
constant
(IIMOD=2)
(b)
BETAII0
V
−1
0.0
-
-
Vds
dependent
(IIMOD=2)
(b)
BETAII1
−
0.0
-
-
Vds
dependent
(IIMOD=2)
(b)
BETAII2
V
0.1
-
-
Vds
dependent
(IIMOD=2)
ESATII
(b)
V /m
1.0e7
-
-
Saturation channel E-Field for Iii
(IIMOD=2)
94
LII(b)
V −m
0.5e-9
-
-
Channel length dependent parameter of
Iii (IIMOD=2)
(b)
SII0
V
−1
0.5
-
-
Vgs
dependent
paramter
of
Iii
paramter
of
Iii
paramter
of
Iii
paramter
of
Iii
(IIMOD=2)
SII1(b)
−
0.1
-
-
Vgs
dependent
(IIMOD=2)
(b)
SII2
V
0.0
-
-
Vgs
dependent
(IIMOD=2)
(b)
SIID
V
0.0
-
-
Vds
dependent
(IIMOD=2)
EOTACC
m
EOT
0.1n
-
SiO2 equivalent gate dielectric thickness for accumulation region
DELVFBACC
V
0.0
-
-
Additional Vf b shift required for accumulation region
CFS
(b)
F/m
2.5e-11
0.0
-
source-side
outer
fringe
cap
(for
fringe
cap
(for
CGEOM OD = 0)
(b)
CFD
F/m
CFS
0.0
-
CGSO
F/m
calculated
0.0
-
drain-side
outer
CGEOM OD = 0)
Non LDD region source-gate overlap capacitance per unit channel width (for
CGEOM OD = 0, 2)
CGDO
F/m
calculated
0.0
-
Non LDD region drain-gate overlap capacitance per unit channel width (for
CGEOM OD = 0, 2)
CGSL
(b)
F/m
0
0.0
-
Overlap
capacitance
between
gate
and lightly-doped source region (for
CGEOM OD = 0, 2)
CGDL
(b)
F/m
CGSL
0.0
-
Overlap
capacitance
between
gate
and lightly-doped drain region (for
CGEOM OD = 0, 2)
(b)
CKAPPAS
V
0.6
0.02
-
Coefficient of bias-dependent overlap
capacitance for the source side (for
CGEOM OD = 0, 2)
95
CKAPPAD(b)
V
CKAPPAS 0.02
-
Coefficient of bias-dependent overlap
capacitance for the drain side (for
CGEOM OD = 0, 2)
CGBO
F/m
0
0.0
-
Gate-substrate overlap capacitance per
unit channel length
CSDESW
F/m
0
0.0
-
Source/drain sidewall fringing capacitance per unit length
COVS
(b)
F/m
2.5e-11
0.0
-
Constant gate-to-source overlap cap
(for CGEOM OD = 1)
COVD
(b)
F/m
COVS
0.0
-
Constant gate-to-drain overlap cap (for
CGEOM OD = 1)
CJS
F/m
2
F/m
2
0.0005
0.0
-
Unit area source-side junction capacitance at zero bias
CJD
CJS
0.0
-
Unit area drain-side junction capacitance at zero bias
CJSWS
F/m
5.0e-10
0.0
-
Unit length sidewall junction capacitance at zero bias (source-side)
CJSWD
F/m
CJSWS
0.0
-
Unit length sidewall junction capacitance at zero bias (drain-side)
CJSWGS
F/m
0.0
0.0
-
Unit length gate sidewall junction capacitance at zero bias (source-side)
CJSWGD
F/m
CJSWGS
0.0
-
Unit length gate sidewall junction capacitance at zero bias (drain-side)
PBS
V
1.0
0.01
-
Bottom
junction
built-in
potential
built-in
potential
(source-side)
PBD
V
PBS
0.01
-
Bottom
junction
(drain-side)
PBSWS
V
1.0
0.01
-
Isolation-edge sidewall junction built-in
potential (source-side)
PBSWD
V
PBSWS
0.01
-
Isolation-edge sidewall junction built-in
potential (drain-side)
PBSWGS
V
PBSWS
0.01
-
Gate-edge sidewall junction built-in potential (source-side)
96
PBSWGD
V
PBSWGS
0.01
-
Gate-edge sidewall junction built-in potential (drain-side)
MJS
−
0.5
-
-
Source bottom junction capacitance
grading coefficient
MJD
−
MJS
-
-
Drain bottom junction capacitance
grading coefficient
MJSWS
−
0.33
-
-
Isolation-edge sidewall junction capacitance grading coefficient (source-side)
MJSWD
−
MJSWS
-
-
Isolation-edge sidewall junction capacitance grading coefficient (drain-side)
MJSWGS
−
MJSWS
-
-
Gate-edge sidewall junction capacitance grading coefficient (source-side)
MJSWGD
−
MJSWGS
-
-
Gate-edge sidewall junction capacitance grading coefficient (drain-side)
SJS
−
0.0
0.0
-
Constant for source-side two-step second junction capacitance
SJD
−
SJS
0.0
-
SJSWS
−
0.0
0.0
-
Constant for drain-side two-step second
junction capacitance
Constant for sidewall two-step second
junction capacitance (source-side)
SJSWD
−
SJSWS
0.0
-
Constant for sidewall two-step second
junction capacitance (drain-side)
SJSWGS
−
0.0
0.0
-
Constant for gate sidewall two-step second junction capacitance (source-side)
SJSWGD
−
SJSWGS
0.0
-
Constant for gate sidewall two-step second junction capacitance (drain-side)
MJS2
−
0.125
-
-
Source bottom two-step second junction capacitance grading coefficient
MJD2
−
MJS2
-
-
Drain bottom two-step second junction
capacitance grading coefficient
MJSWS2
−
0.083
-
-
Isolation-edge sidewall two-step second
junction capacitance grading coefficient
(source-side)
97
MJSWD2
−
MJSWS2
-
-
Isolation-edge sidewall two-step second
(drain-side)
MJSWGS2
−
MJSWS2
-
-
Gate-edge sidewall two-step second
(source-side)
MJSWGD2
−
MJSWGS2 -
-
Gate-edge sidewall two-step second
(drain-side)
JSS
2
A/m
1.0e-4
0.0
-
Bottom source junction reverse saturation current density
JSD
2
A/m
JSS
0.0
-
Bottom drain junction reverse saturation current density
JSWS
A/m
0
0.0
-
Unit length reverse saturation current
for isolation-edge source sidewall junction
JSWD
A/m
JSWS
0.0
-
for isolation-edge drain sidewall junction
JSWGS
A/m
0
0.0
-
for gate-edge source sidewall junction
JSWGD
A/m
JSWGS
0.0
-
for gate-edge drain sidewall junction
NJS
-
1.0
0.0
-
Source junction emission coefficient
NJD
-
NJS
0.0
-
Drain junction emission coefficient
IJTHSFWD
A
0.1
10Isbs
-
Forward source diode breakdown limiting current
IJTHDFWD
A
IJTHSFWD
10Isbd
-
Forward drain diode breakdown limiting current
IJTHSREV
A
0.1
10Isbs
-
Reverse source diode breakdown limiting current
IJTHDREV
A
IJTHSREV
10Isbd
-
Reverse drain diode breakdown limiting
current
98
BVS
V
10.0
-
-
Source diode breakdown voltage
BVD
V
BVS
-
-
Drain diode breakdown voltage
XJBVS
-
1.0
-
-
Fitting parameter for source diode
XJBVD
-
XJBVS
-
-
breakdown current
Fitting parameter for source diode
breakdown current
LINTIGEN
NTGEN
(b)
m
0.0
-
Lef f /2 Lint offset for R/G current
-
1.0
> 0.0
-
parameter for R/G current (Experimental)
AIGEN
(b)
−3
m
V
−1
V
−3
0.0
-
-
BIGEN
(b)
−3
m
0.0
-
-
(b)
XRCRG1
-
12.0
0.0
≥
or
10
(b)
XRCRG2
-
1.0
-
resistance (NQSMOD=1) and NQS-
−3
-
parameter for non quasi-static gate
MOD=2
-
parameter for non quasi-static gate
resistance (NQSMOD=1) and NQSMOD=2
NSEG
-
5
4
10
Number of channel segments for NQSMOD=3
EF
-
1.0
> 0.0
2.0
LINTNOI
m
0.0
-
Lef f /2 Lint offset for flicker noise calculation
EM
V /m
eV
−1 1−EF
m
−3
eV
−1 1−EF
m
−1
NOIC
eV
−1 1−EF
m
NTNOI
-
NOIA
NOIB
s
s
s
Flicker noise frequency exponent
4.1e7
-
-
Flicker noise parameter
6.250e39
-
-
3.125e24
-
-
8.750e7
-
-
1.0
0.0
-
Thermal noise parameter
99
6.4
Parameters for geometry-dependent parasitics
The parameters listed in this section are for RGEOMOD=1 and CGEOMOD=2.
Name
Unit
Default
Min
Max
Description
HEPI
m
10n
-
-
Height of the raised source/drain on top of the
fin
TSILI
m
10n
-
-
Thickness of the silicide on top of the raised
source/drain
RHOC
Ω−m
2
1p
−18
10
10
−9
Contact resistivity at the silicon/silicide interface
RHORSD
Ω−m
calculated
0
-
Average resistivity of silicon in the raised
source/drain region
RHOEXT
Ω−m
RHORSD
0
-
Average resistivity of silicon in the fin extension region
CRATIO
-
0.5
0
1
Ratio of the corner area filled with silicon to
the total corner area
DELTAPRSD
m
0.0
-
-
FPITCH
SDTERM
-
0
0
Change in silicon/silicide interface length due
to non-rectangular epi
1
Indicator of whether the source/drain are terminated with silicide
LSP
m
0.2(L+XL) 0
-
Thickness of the gate sidewall spacer
LDG
m
5n
-
Lateral diffusion gradient in the fin extension
0
region
EPSRSP
-
3.9
1
-
Relative dielectric constant of the gate sidewall spacer material
TGATE
m
30n
0
-
Gate height on top of the hard mask
TMASK
m
30n
0
-
Height of the hard mask on top of the fin
0
0
-
Extra silicide cross sectional area at the two
ASILIEND
2
m
ends of the FinFET
ARSDEND
2
m
0
0
-
Extra raised source/drain cross sectional area
at the two ends of the FinFET
PRSDEND
m
0
0
-
Extra silicon/silicide interface perimeter at
the two ends of the FinFET
100
NSDE
m−3
2 × 1025
1025
1026
Active doping concentration at the channel
edge
RGEOA
-
1.0
-
-
Fitting parameter for RGEOMOD=1
RGEOB
−1
m
0
-
-
RGEOC
m−1
0
-
-
RGEOD
m−1
0
-
-
RGEOE
m−1
0
-
-
CGEOA
-
1.0
-
-
Fitting parameter for CGEOMOD=2
CGEOB
m−1
0
-
-
CGEOC
m−1
0
-
-
CGEOD
m−1
0
-
-
CGEOE
-
1.0
-
-
101
6.5
Parameters for Temperature Dependence and Self-heating
(b)
Name
Unit
Default
Min
Max
Description
TNOM
C
27
0.0
-
Temperature at which the model is extracted (in Celcius)
TBGASUB
eV /K
7.02e-4
-
-
Bandgap Temperature Coefficient
TBGBSUB
K
1108.0
-
-
Bandgap Temperature Coefficient
KT1
V
0.0
-
-
Vth Temperature Coefficient
V ·m
0.0
-
-
Vth Temperature Coefficient
(b)
-
0.0
-
-
Mobility Temperature Coefficient
(b)
-
-1.5e-3
-
-
(b)
-
1.032e-3
-
-
-
0.0
-
-
-
-4.775e-3
-
-
1/K
-0.00156
-
-
Saturation Velocity Temperature Coef-
KT1L
UTE
UTL
UA1
UD1
(b)
UCSTE
(b)
(b)
AT
ficient
(b)
TMEXP
1/K
0
-
-
Temperature Coefficient for Vdsef f
smoothing
PTWGT
(b)
(b)
PRT
1/K
0.004
-
-
PTWG Temperature Coefficient
-
0.001
-
-
Series Resistance Temperature Coefficient
IIT(b)
-
-0.5
-
-
Impact Ionization Temperature Coefficient (IIMOD=1)
(b)
TII
-
0.0
-
-
Impact Ionization Temperature Coefficient (IIMOD=2)
TGIDL
(b)
1/K
-0.003
-
-
GISL/GIDL Temperature Coefficient
-
2.5
-
-
Gate Current Temperature Coefficient
TCJ
1/K
0.0
-
-
Temperature coefficient for CJS/CJD
TCJSW
1/K
0.0
-
-
Temperature
IGT
(b)
coefficient
for
coefficient
for
CJSWS/CJSWD
TCJSWG
1/K
0.0
-
-
Temperature
CJSWGS/CJSWGD
TPB
1/K
0.0
-
102
-
Temperature coefficient for PBS/PBD
TPBSW
1/K
0.0
-
-
Temperature
coefficient
for
PB-
coefficient
for
PB-
SWS/PBSWD
TPBSWG
1/K
0.0
-
-
Temperature
SWGS/PBSWGD
XTIS
-
3.0
-
-
Source junction current temperature
exponent
XTID
-
XTIS
-
-
Drain junction current temperature exponent
RTH0
Ω
0.01
0.0
-
Thermal resistance for self-heating calculation
CTH0
F
1.0e-5
0.0
-
Thermal capacitance for self-heating
calculation
WTH0
m
0.0
0.0
-
Width-dependence coefficient for selfheating calculation
103
6.6
Parameters for Variability Modeling
A set of parameters causing variability in device behavior are identified. Users can
associate appropriate variability function as appropriate. The list is open to modification
with users feedbacks and suggestions. Other than DTEMP, DELVTRAND, UOMULT
and IDS0MULT, the parameters listed here were already introduced previously as either instance parameters or model parameters. All of the following parameters should
be elevated to instance parameter status if required for variability modeling or should
be delegated to a model parameter status (unless introduced before as an instance parameter). Note: parameters already introduced as instance parameters are
marked: (i) and model parameters are marked: (model)
Name
Unit
Default
Min
Max
Description
DELVTRAND
V
0.0
-
-
Threshold voltage shift handle
U0MULT
-
1.0
-
-
Multiplier to mobility (or more precisely divides Dmob ,Dmobs )
IDS0MULT
-
1.0
-
-
Multiplier to source-drain channel current
DTEMP
TFIN
(i)
FPITCH
XL
(i)
(mod)
K
0.0
-
-
Temperature shift handle
m
15n
1n
-
Body (fin) thickness
m
80n
TFIN
-
Fin Pitch
m
0
-
-
L offset for channel length due to
mask/etch effect
NBODY
EOT
(mod)
(mod)
−3
m
1e22
1e18
5e24
channel (body) doping concentration
m
1.0n
0.1n
-
SiO2 equivalent gate dielectric thickness (including inversion layer thickness)
TOXP
RSHS
(mod)
m
1.2n
0.1n
-
Physical oxide thickness
(mod)
Ω
0.0
0.0
-
Source-side sheet resistance
(mod)
Ω
RSHS
0.0
-
RSHD
RHOC
(mod)
Ω−m
2
1p
10
−18
Drain-side sheet resistance
−9
10
Contact
resistivity
at
the
sili-
con/silicide interface
RHORSD
(mod)
Ω−m
calculated
0
-
Average resistivity of silicon in the
raised source/drain region
RHOEXT
(mod)
Ω−m
RHORSD
0
-
Average resistivity of silicon in the fin
extension region
104
7
History of BSIM-MG Models
October, 2006 BSIM-CMG 1.0 alpha version released.
August, 2007 BSIM-CMG 1.0 released.
January 2008 BSIM-CMG 1.0.1 released with several bug fixes compared with
BSIM-CMG1.0.
March, 2008 BSIM-IMG 1.0 alpha version released.
November 2008 BSIM-CMG 1.1.0 alpha version released. Temperature effects,
noise models (flicker noise, thermal noise and shot noise), junction current, intrinsic
input resistance (Rii ) are added. Both RDSM OD = 0 and RDSM OD = 1 in BSIM4
are now supported in BSIM-CMG. M OBM OD = 0 (based on BSIM4[10]) is added and
set as the default mobility model.
May 2009 BSIM-CMG 102.0 released. This release is essentially the official release
of 1.1.0 alpha. Gmin 3 is added for improved convergence.
Oct 2009 BSIM-CMG 103.0 released. This release now supports a Cylindrical gate
geometry through GEOM OD = 3 with an associated short channel scale length and
quantum effects model. The existing I-V have been enhanced to model Poly-depletion
accurately. Self-heating is now supported with addition of a Temperature node. Junction
Capacitance and Junction Current equations were revamped with source-drain asymmetry supported. The asymmetry is now also in GIDL/GISL currents. Length dependent equations have been added for a Global Parameter Extraction without binning.
SHMOD, RGATEMOD, NQSMOD and RDSMOD also control the number of internal
nodes for faster simulations. Many bug-fixes were implemented too.
Feb 2010 BSIM-CMG 104.0 released. A new channel length modulation model
adopted from BSIM4 is added. This release also supports the impact ionization model
similar to one in BSIMSOI. NRS/NRD parameter and its associated equations have
been added. Gmin implementation has been removed with consensus among various
EDA vendors. The suggested value for simulator side Gmin (between source/drain to
body node) is 1E-18 S. Lots of bug-fixes were implemented too.
November, 2010 BSIM-IMG 101.0 alpha version released.
3
A very large resistor between the bulk node and the intrinsic source/drain node.
105
References
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Huang, F.-L. Yang, A. M. Niknejad, and C. Hu, “BSIM-MG: A Versatile Multi-Gate
FET Model for Mixed-Signal Design,” in 2007 Symposium on VLSI Technology,
2007.
[2] D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad, and C. Hu, “A multi-gate MOSFET compact model featuring independent-gate operation,” in IEDM Technical
Digest, 2007, p. 565.
[3] Y. Cheng and C. Hu, MOSFET Modeling and BSIM3 User’s Guide.
Academic Publishers, 1999.
Kluwer
[4] M. V. Dunga, Ph.D. Dissertation: Nanoscale CMOS Modeling. UC Berkeley, 2007.
[5] A. S. Householder, The Numerical Treatment of a Single Nonlinear Equation.
McGraw-Hill, New York, 1970.
[6] X. Gourdon and P. Sebah, Newton’s method and high order iterations. [Online].
Available: http://numbers.computation.free.fr/Constants/constants.html
[7] J. He, J. Xi, M. Chan, H. Wan, M. Dunga, B. Heydari, A. M. Niknejad, and C. Hu,
“Charge-Based Core and the Model Architecture of BSIM5,” in International Symposium on Quality Electronic Design, 2005, pp. 96–101.
[8] BSIM5.0.0 MOSFET Model, BSIM Group, The Regents of the University of California, February 2005.
[9] S. Venugopalan, “A Compact Model of Cylindrical Gate MOSFET for Circuit Simulations,” UC Berkeley Master’s Report, december 2009.
[10] BSIM Models. Department of Electrical Engineering and Computer Science, UC
Berkeley. [Online]. Available: http://www-device.eecs.berkeley.edu/∼bsim3/
[11] G. Masetti, M. Severi, and S. Solmi, “Modeling of Carrier Mobility Against Carrier
Concentration in Arsenic-, Phosphorus-, and Boron-Doped Silicon,” IEEE Transaction on Electron Devices, vol. 30, no. 7, pp. 764–769, july 1983.
[12] H. H. Berger, “Model for contacts to planar devices,” Solid-State Electronics,
vol. 15, pp. 145–158, 1972.
106
[13] BSIM-SOI Model. University of California, Berkeley. [Online]. Available:
http://www-device.eecs.berkeley.edu/∼bsimsoi/
[14] W.-M. Lin, F. Li, D. D. Lu, A. M. Niknejad, and C. Hu, “A Compact Fringe
Capacitance Model for FinFETs,” unpublished.
[15] X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. J. Deen, P. R. Gray, and C. Hu, “An
Effective Gate Resistance Model for CMOS RF and Noise Modeling,” in IEDM
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[16] BSIM Models. Department of Electrical Engineering and Computer Science,
UC Berkeley. [Online]. Available: http://www-device.eecs.berkeley.edu/∼bsim3/
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[17] M. Chan, K. Y. Hui, C. Hu, and P. K. Ko, “A robust and physical BSIM3 non-quasistatic transient and AC small-signal model for circuit simulation,” IEEE Transaction on Electron Devices, vol. 45, no. 4, pp. 834–841, April 1998.
[18] S. Yao, T. H. Morshed, D. D. Lu, S. Venugopalan, W. Xiong, C. R. Cleavelin, A. M.
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107
Acknowledgments
We deeply appreciate the feedback we received from (in alphabetical order by last name):
Brian Chen (Accelicon)
Wei-Hung Chen (UC Berkeley)
Jung-Suk Goo (GlobalFoundries)
Keith Green (TI)
Ben Gu (Freescale)
Wilfried Haensch (IBM)
Min-Chie Jeng (TSMC)
Yeung Gil Kim (Proplus Solutions)
Wai-Kit Lee (TSMC)
Dayong Li (Cadence)
Hancheng Liang (Proplus Solutions)
Sally Liu (TSMC)
Weidong Liu (Synopsys)
James Ma (Proplus Solutions)
Colin C. McAndrew (Freescale)
Slobodan Mijalkovic (Silvaco)
Andrei Pashkovich (Silvaco)
S. C. Song (Qualcomm)
Ke-wei Su (TSMC)
Niraj Subba (GlobalFoundries)
Charly Sun (Synopsys)
Sushant Suryagandh (GlobalFoundries)
Lawrence Wagner (IBM)
Joddy Wang (Synopsys)
Qingxue Wang (Synopsys)
Josef Watts (IBM)
Richard Williams (IBM)
Dehuang Wu (Synopsys)
Jane Xi (Synopsys)
Jushan Xie (Cadence)
Wade Xiong (TI)
Wenwei Yang (Proplus Solutions)
Fulong Zhao (Cadence)
Manual created: March 13, 2012

UC Berkeley Technical Report

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