Pamięć ulotna RAM

Pamięć ROM (Read-Only Memory)
Podstawy techniki
mikroprocesorowej
ETEW006
Pamięci komputera
ROM i RAM
Andrzej Stępień
Katedra Metrologii Elektronicznej i Fotonicznej
Pamięć ulotna RAM
tylko odczyt, brak wpływu napięcia zasilania Vcc na zawartość pamięci
ROM - programowane przez producenta pamięci w czasie produkcji (MROM Mask programmable ROM)
PROM (Programmable ROM) - pamięć 1-krotnego zapisu (programowania);
programowane przez przepalenie połączeń struktury wewnętrznej
EPROM (Electrically Programmable ROM) - pamięć, programowalna
elektrycznie, kasowana innymi metodami np. przez naświetlanie światłem
ultrafioletowym o wysokiej energii
OTP EPROM (One -Time Programmable EPROM) - pamięć EPROM
1-krotnie programowalna (brak okienka)
EEPROM (Erasable Electrically Programmable ROM) - pamięć wielokrotnego
zapisu, kasowalna i programowalna elektrycznie
Flash EEPROM – zapis / kasowanie wielu (bloków) komórek pamięci
podczas jednej operacji programowania
FRAM (Ferroelectric RAM) – ferroelektryczna pamięć RAM
Pamięć nieulotna NVRAM
Pamięć ulotna RAM (Volatile Random Access Memory):
pamięć o dostępie swobodnym, utrata zawartości w momencie
zaniku napięcia zasilania Vcc
SRAM (Static RAM):
• przerzutnik bistabilny jako element pamięciowy
• brak cykli odświeżania
• większa (~4 razy) powierzchnia od pamięci DRAM o tej samej
pojemności
• szybsza w stosunku do pamięci dynamicznej
DRAM (Dynamic RAM)
• kondensator jako element pamięciowy
• odświeżanie (refresh) ładunku (upływność) kondensatora
• małe rozmiary
Pamięć nieulotna NVRAM (Non-Volatile Random Access Memory)
pamięć o dostępie swobodnym, zachowanie zawartości w momencie
zaniku napięcia zasilania Vcc
• pamięci ferrytowe używane w latach 50. i 60. XX wieku
• pamięci z podtrzymaniem bateryjnym
• NRAM - technologia nanorurek węglowych
• MRAM – magnetyczny efekt tunelowy magnetycznego
• OUM - zmiany stanu stopów pierwiastków rudotwórczych
(analogia do płyt CD, DVD – zapis/kasowanie za pomocą lasera,
zmiana stanu z krystalicznego na amorficzny)
• FRAM - właściwości ferromagnetyczne
www.samsung.com/global/business/
semiconductor/support/brochures
Fusion Memory
As consumers continue their insatiable demand for higher-performance,
ever-smaller mobile devices, Samsung’s fusion memory products are
increasingly chosen by handheld designers.
Memory Parameter
(www.st.com → Memories)
Memory Size – [Storage Capacity] The amount of data that can be contained in a
storage device measured in binary characters, bytes, words, or other units of
data. IEEE Std. 610.10-1994.
Supply Voltage(VCC) - the value as specified by level (minTypMax) of the direct
supply voltage, applied to an IC. IEC61360-AAE690 (VCC).
These fusion semiconductors integrate different memory technologies
and can also include logic, software and other elements on a single
chip. Samsung’s fusion products simplify device architecture, reduce power
consumption, increase performance and cut costs while enabling mobile
products to be smaller and deliver greater functionality than ever.
Memory Organization - Shown as a text representation of the Memory
Organization (i.e. 512 x 8).
Samsung as the world memory leader and a strong player in mobile logic
chips, Samsung has exploited its considerable expertise in technologies and
processes to create its fusion memory offerings. These chips are optimal for
today’s fast-selling consumer products, from mobile phones, portable
media players and digital cameras to personal navigation devices and
multi-function handhelds.
Programming Voltage (VPP) / Current (IPP) - Programming voltage or current by
the specified test condition
Access Time (tACC) - time of address to output delay.
Chip Enable To Output Delay (tCE) - time of chip enable to output delay.
Output Enable To Output Delay(tOE) - time of output enable to output delay.
Standby Supply Voltage Current CMOS(ICC2)-Operating supply current by the
specified test condition.
Operating Temperature - The value as specified by level (minTypMax) of the
ambient temperature (in Cel) in which this item was designed to operate.
1
MODE
Memory
Select
Microprocessor & Memory
Ai
I/O
Standby/Write Inhibit H
X
X
X
High Z
Output disable
Read
X
L
H
L
X
H
Ai
High Z
DOUT
Program
L
H
L
Ai
DIN
Single CS#
Address
Decoder
Address
Decoder
Addr
Data
Addr Address Bus
Data
Single CS#
OE
Memory
Microprocessor
Microcontroller
Addr Address Bus
Data Bus
Addr
RD
WR
WE
OE
OE
CS
Data
Data Bus
Data
Addr
Data
ROM
Memory
CS
Microprocessor
Microcontroller
CE OE WE
Addr (A15..0)
RAM
Memory
AT29LV512 . 512K
(64Kx8) 3-volt Only
Flash Memory. Atmel,
0177O–FLASH–9/08
RD
WR
ISB1 VCC Standby Current < 50 µA
ICC VCC Active Current
< 15 mA
CS
Data (IO7..0)
WE
OE
Flash
Memory
CS
Address Valid
Memory Address
Decoder (1/2)
Memory
Read Waveforms
FFFFh
Single CS#
Address
Decoder
Microprocessor
Microcontroller
AT29LV512 . 512K
(64Kx8) 3-volt Only
Flash Memory. Atmel,
0177O–FLASH–9/08
Addr Address Bus
Addr
OE
CS
Data
Data Bus
Memory Address
Decoder (2/2)
FFFFh
RAM (8) F000h
EFFFh
RAM (7) E000h
DFFFh
.........
9FFFh
RAM (2) 9000h
8FFFh
RAM (1) 8000h
7FFFh
ROM (8) 7000h
6FFFh
A15 = 0
tACC
Output
Data
Valid Memory
AC Read Characteristics AT29LV512-12
Symbol Parameter
tACC
Address to OutputRD
Delay
tCE
CE to Output Delay
tOE
OE to Output DelayWR
CE or OE to Output Float
tDF
tOH
Output Hold from OE, CE
or Address, whichever occurred first
A15 = 1
Access Time
ROM (7) 6000h
5FFFh
.........
2FFFh
ROM (3) 2000h
1FFFh
ROM (2) 1000h
0FFFh
ROM (1) 0000h
Units
.. 120 ns
.. 120 ns
0 .. 50 ns
0 .. 30 ns
0 .. ns
Addr (A15..0)
Data (IO7..0)
WE
OE
Flash
Memory
CS
A15 = 1
RAM (8) F000h
EFFFh
RAM (7) E000h
DFFFh
.........
9FFFh
RAM (2) 9000h
16
A15
8FFFh
RAM (1) 8000h
Addr Address Bus
Microprocessor
7FFFh
ROM (8) 7000h
Microcontroller
Data6FFFh Data Bus
ROM (7) 6000h
5FFFh
8
.........
A15 = 0
2FFFh
ROM (3) 2000h
RD
WR1FFFh
ROM (2) 1000h
0FFFh
ROM (1) 0000h
Addr11..0
Data7..0
OE
ROM
Memory
4Kx8
CS
Addr11..0
Data7..0
WE
OE
RAM
Memory
4Kx8
CS
FFFFh= 1111 1111 1111 1111b
F000h = 1111 0000 0000 0000b
EFFFh= 1110
E000h = 1110
A15
9FFFh= 1001
9000h = 1001
1111 1111 1111b
0000 0000 0000b
A11 .. 0
1111 1111 1111b
0000 0000 0000b
8FFFh= 1000 1111 1111 1111b
8000h = 1000 0000 0000 0000b
7FFFh= 0111 1111 1111 1111b
7000h = 0111 0000 0000 0000b
6FFFh= 0110
6000h = 0110
A15
2FFFh= 0010
2000h = 0010
1111 1111 1111b
0000 0000 0000b
A11 .. 0
1111 1111 1111b
0000 0000 0000b
1FFFh= 0001 1111 1111 1111b
1000h = 0001 0000 0000 0000b
0FFFh= 0000 1111 1111 1111b
0000h = 0000 0000 0000 0000b
EPROM / OTP EPROM
EPROM (Electrically Programmable Read Only Memory) is a nonvolatile
memory which offers the ability to both program and erase the contents
of the memory multiple times.
An EPROM must be programmed using a 12.5 volt (or higher) PROM
programmer, and then transferred into the system in which it is intended
to function.
EPROMs can be erased by shining ultraviolet light into the window in
the top of the IC package. The process of writing data into an EPROM
and then erasing it may be repeated almost indefinitely. EPROMs are
usually used for product development, and later replaced with less
expensive one–time programmable EPROMs.
OTP EPROM: One–Time Programmable EPROM. An EPROM which
can only be written with code/data once instead of multiple times.
Generally, OTP EPROMs are less expensive then erasable EPROMs.
2
A0-Q12
EPROM
EPROM
M27C64 (1/4)
M27C64A. 64 Kbit (8Kbitx8) UV EPROM and OTP EPROM. STMicroelectronics, October 2002
Mode
E
G
P
VPP
Q Output
Read
Output Disable
VIL
VIL
VIL
VIH
VIH
VIH
VCC
VCC
Data Out
Hi-Z
Program
Verify
VIL
VIL
X
VIL
VIL Pulse
VIH
VPP
VPP
Data Input
Data Output
Standby
VIH
X
X
VCC
Hi-Z
CIN Input Capacitance
COUT Output Capacitance
VIN = 0V
VOUT = 0V
6 pFMAX
12 pFMAX
ICC Supply Current
ICC1 Supply Current (Standby) TTL
ICC2 Supply Current (Standby) CMOS
E = VIL G = VIL
E = VIH G = X
E > VCC – 0.2V
30 mAMAX
1 mAMAX
100 µAMAX
EPROM
D 7 .. D 0
standard
C51
B7
..
B0
Bufor
danych
DIR
xx245
A7
..
A0
/ D 7 .. D 0
D7
Bufor
..
D0 adresów
LE
Q7
..
Q0
OE
ALE
xx573
port P2
EEPROM
The erasure begins when the cells are exposed to light with wavelengths
4000each
Å. Iterasure
should be
that sunlight
and
shorter
thandelivered
approximately
When
(and after
for noted
UV EPROM),
all bits
of some
the
type M27C64A
of fluorescent
wavelengths in the 3000-4000 Å range.
are inlamps
the "1”have
state.
Data is
introduced
by selectively
programming
"0"sfluorescent
into the desired
bit
Research
shows
that constant
exposure
to room level
lighting
Although
only "0"sinwill
be programmed,
"1"s take
and "0"s can
couldlocations.
erase a typical
M27C64A
about
3 years, whileboth
it would
be present1 in
the data
word.erasure when exposed to direct sunlight.
week
to cause
approximately
D7 .. D 0
A7 .. A 0 /
- M27C64 ERASURE OPERATION (4/4)
G
Vcc
port P0
Multiplexed,
Non-Page
Mode Addressing
D7 .. D 0
G
Q0-Q7
EPROM
(3/4)
konieczny
dodatkowy bufor
jeśli pamięć
programu zbyt
wolno przechodzi
w stan wysokiej
impedancji
E
M27C64 (2/4)
A7 .. A 0
Pamięć
danych
(XDATA)
A15 .. A 8
P3.6/WR
WE
P3.7/RD
OE
PSEN
A7 .. A 0
Pamięć
programu
(CODE)
A15 .. A 8
OE/ CE
- AT25XXX Serial
AT25128/AT25256. SPI Serial Automotive EEPROMs 128K (16,384 x 8) / 256K (32,768 x 8)
doc3262.pdf - Rev. 3262A–SEEPR–02/02, Atmel Corporation 2002.
Serial Peripheral Interface (SPI) Compatible
Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
3 MHz Clock Rate
64-byte Page Mode and Byte Write Operation
The only way to erasure
change procedure
a "0" to a "1"
byM27C64A
die exposition
to ultraviolet
The recommended
for isthe
is exposure
to short
(UV EPROM).
Thehas
M27C64A
is in theofprogramming
mode when
2537 Å.
wavelight
ultraviolet
light which
a wavelength
VPP input is at 12.5V, E is at VIL and P is pulsed to VIL.
The integrated dose (i.e. UV intensity x exposure time) for erasure should be
The data to be programmed is applied to 8 bits in parallel to the data
a minimum of 15 W-sec/cm2. The erasure time with this dosage is
output pins. The levels required for the address and data inputs are TTL.
approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2
V is specified to be 6V ± 0.25V.
power CC
rating. The M27C64A should be placed within 2.5 cm (1 inch) of the
lamp tubes during the erasure.
NOR flash memory:
NOR or NAND
?
(1/2)
– reading from NOR flash is similar to reading from random-access
memory, provided the address and data bus are mapped correctly
– because of this, most microprocessors can use NOR flash memory as
execute in place (XIP) memory, meaning that programs stored in NOR
flash can be executed directly without the need to copy them into RAM
– NOR flash chips typically have slow write speeds compared with NAND
flash
NAND flash memory:
Write Protect (WP) Pin and Write Disable Instructions for both Hardware and
Software Data Protection
– memories are accessed much like block devices such as USB Flash,
hard disks, memory cards, digital cameras, MP3 players for storing larger
quantities of data on - pages are typically 512 or 2,048 or 4,096 bytes in
size
Self-timed Write Cycle (5 ms Typical)
– NAND is best suited to flash devices requiring high capacity data storage
High-reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >200 Years
– NAND flash architecture combines higher storage space with lower
cost, faster erase, write, and read capabilities over the execute in place
advantage of the NOR architecture
Block Write Protection – Protect 1/4, 1/2, or Entire Array
3
K9XXG08UXM 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory.
SAMSUNG Electronics, May 3rd. 2005
NOR or NAND
(2/2)
?
Memory
Array Organization
- Page Size : (2K + 64)Byte
- Random Read : 20µs(Max.)
- Serial Access : 25ns(Min.)
NOR flash memory:
• the Random Access is possible and very fast (@ 70 ns)
• the Write Time is the main disadvantage, as it is slow (@ 6 µs/Byte
and around 3 ms/512 Bytes).
NAND flash memory:
• allows a very fast Sequential Access (@ 50 ns), it is not adapted
for a random access (@ 25 µs)
• are about 40% smaller, and achieves a higher density (Sixteen
neighbouring cells are serially connected without any contact area
in-between)
• becomes more advantageous than the NOR Flash for the Write
Time in bundle (several Bytes together (@ 200 µs/512 Bytes)). It is
around 10 times faster than the NOR Flash.
NOR or NAND
(2/2)
?
NOR flash memory:
• the Random Access is possible and very fast (@ 70 ns)
• the Write Time is the main disadvantage, as it is slow (@ 6 µs/Byte
and around 3 ms/512 Bytes).
NAND flash memory:
• allows a very fast Sequential Access (@ 50 ns), it is not adapted
for a random access (@ 25 µs)
• are about 40% smaller, and achieves a higher density (Sixteen
neighbouring cells are serially connected without any contact area
in-between)
• becomes more advantageous than the NOR Flash for the Write
Time in bundle (several Bytes together (@ 200 µs/512 Bytes)). It is
around 10 times faster than the NOR Flash.
SRAM (Static Random Access Memory)
Figure 2. K9K8G08U0M Array Organization
Solid State Disc (SSD)
electrically, mechanically and software compatible with a conventional
(magnetic) hard disk
this provides faster access time than a hard disk, because the SSD data
can be randomly accessed in the same time whatever the storage
location
SSD access time does not depend on a read/write interface head
synchronising with a data sector on a rotating disk
SSD also provides greater physical resilience to physical vibration, shock
and extreme temperature fluctuations
only downside is a higher cost per megabyte of storage - although in
some applications the higher reliability of SSDs makes them cheaper to
own than replacing multiple failing hard disks
NV SRAM (NonVolatile Static Random Access Memory)
NV SRAM is a single package which contains a low–power SRAM, a
nonvolatile memory controller, and a lithium type battery
SRAM is essentially a stable DC flip–flop requiring no clock timing or
refreshing
contents of an SRAM memory are retained as long as power is supplied
when the power supply to this single modular package falls below the
minimum requirement to maintain the contents of the SRAM, the memory
controller in the module switches the power supply from the external
source to the internal lithium battery and write protects the SRAM
SRAMs support extremely fast access times
these transitions to and from the external power source are transparent to
the SRAM, making it a true nonvolatile memory
SRAMs also have relatively few strict timing requirements and a parallel
address structure, making them particularly suited for cache and other
low–density, frequent–access applications
this unique construction combines the strategic advantages of SRAM–
addressing structure, high–speed access, and timing requirements – with the
nonvolatility advantages of EEPROM technologies
Battery–backed SRAM modules from Dallas Semiconductor are pin–
compatible with non–battery–backed SRAMs, making them ideal for any
application where a traditional SRAM would be suitable
4
SRAM
SRAM
Single Access Read Cycle
K6R1008V1D (1/4)
K6R1008V1D.
1Mbit Asynchronous
Fast SRAM High-Speed
CMOS Static RAM.
Samsung Electronics
June 2003
tRC Read Cycle Time
tAA Address Access Time
tOH Output Hold from Address Change
tRC
CS
H
L
L
L
Address
tAA
tOH
VSS
Data Out Previous Data Valid
SRAM
A0 - OE
A16 Mode
Address InputsI/O Pin
WE
WE
Write Enable
X X* NotChip
Select
CS
Select High-Z
H
H
Output
Disable
OE
Output
EnableHigh-Z
H ~L I/O8
Read
DOUT
I/O1
Data Inputs/Outputs
VCC
Power(+3.3V) DIN
L X Write
Supply Current
ISB, ISB1
ICC
ICC
ICC
Ground
Data Valid
???
SRAM - READ
K6R1008V1D-08 (3/4)
K6R1008V1D-08/ -10 (2/4)
Operating Temperature:
Parameter
Commercial
Industrial
Symbol
Operating Current
ICC
Standby Current
ISB
Input/Output Capacitance
CI/O
Input Capacitance
CIN
SRAM - Write
TA = 0 to 70 °C
TA = – 40 to 85 °C
Test Conditions
Commercial
8ns
10ns
Industrial
8ns
10ns
Min. Cycle, CS=VIH
ISB1 f=0MHz,
CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
VI/O=0V
VIN=0V
Max
80 mA
65 mA
90 mA
75 mA
20 mA (TTL)
5 mA (CMOS)
8 pF
6 pF
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
tRC
tAA
tCO
tOE
8 nsMIN
8 nsMAX
8 nsMAX
4 nsMAX
Output Hold from Address Change
tOH
3 nsMIN
Chip Selection to Power Up Time
Chip Selection to Power DownTime
tPU
tPD
0 nsMIN
8 nsMAX
K6R1008V1D-08 (4/4)
Memory & Memory
(1/2)
K6R1008V1D. 1Mbit Asynchronous Fast SRAM High-Speed CMOS
Static RAM. Samsung Electronics June 2003
K6F1008V2C. 128Kx8 bit Super Low Power and Low Voltage
CMOS Static RAM. Samsung Electronics, March 2005
(OE= Clock)
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
tWC
tCW
tAS
tAW
tWP
8 nsMIN
6 nsMIN
0 nsMIN
6 nsMIN
6 nsMIN
End of Write to Output Low-Z
tOW
3 nsMIN
(OE=Low Fixed)
(CS = Controlled)
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Output Hold from Address Change
tRC
tAA
tCO
tOE
tOH
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
End of Write to Output Low-Z
tWC
tCW
tAS
tAW
tWP
tOW
K6R1008V1D-08 K6F1008V2C-55
8 nsMIN
55 nsMIN
8 nsMAX
55 nsMAX
8 nsMAX
55 nsMAX
4 nsMAX
25 nsMAX
3 nsMIN
10 nsMIN
8 nsMIN
6 nsMIN
0 nsMIN
6 nsMIN
6 nsMIN
3 nsMIN
55 nsMIN
45 nsMIN
0 nsMIN
45 nsMIN
40 nsMIN
5 nsMIN
5
Memory & Memory
Synchronous Pipelined
Boundary SCAN-JTAG
(2/2)
SRAM
K6R1008V1D. 1Mbit Asynchronous Fast SRAM High-Speed CMOS
Static RAM. Samsung Electronics June 2003
SCAN-JTAG to test the
connectivity during
manufacturing
between SRAM,
printed circuit board
and other
components
K6F1008V2C. 128Kx8 bit Super Low Power and Low Voltage
CMOS Static RAM. Samsung Electronics, March 2005
Parameter
Symbol
K6R1008V1D-08
K6F1008V2C-55
Operating
Current
ICC2
ICC1
90 mA
35 mAMAX
3 mAMAX
TTL
CMOS
Standby
Current
ISB
ISB1
20 mA
5 mA
5 µAMAX
TTL
CMOS
Input/Output Capacitance
CI/O
8 pFMAX
Input Capacitance
6 pFMAX
CIN
IEEE 1149.1 Test Access Port &
TCK
10 pFMAX
JTAG Test Clock
TMS
JTAG Test Mode Select
TDI
JTAG Test Data Input
TDO
JTAG Test Data Output
M1, M2 Read Protocol Mode Pins
8 pFMAX
DRAM (Dynamic Random Access Memory)
SRAM / DRAM Cell
in an SRAM, this information is stored in a four to six transistor flip–
flop which is easy to address, but requires a relatively large memory
cell
SRAM Cell
DRAM Cell
Switching
element
Select = 1
DRAM, by comparison, stores its 1 or 0 as a charge on a small
capacitor, requir ing much more current then an SRAM to maintain the
stored data
P1
Word Line
P2
Off On
net memory cell size is smaller for the DRAM than for the SRAM, so
the total cost per bit of memory is less
On
On
Bit
Line
On Off
N1
N2
DRAM’s capacitors must be constantly refreshed so that they retain
their charge
bit = 1
C
Storage
element
(capacitor)
C = 0,020 – 0,040 pF
bit = 0
DRAMs require more sophisticated interface circuitry
1. Activation:
– bias the row’s bit lines
– sense the word lines’
- timing
capacitor cells
– store sensed value
statically
Column Decoder
Data In/Out
Buffers
.. Word Lines ..
Row Decoder
Data
DRAM Cell
Switching
element
Sense Amps
.. Bit Lines ..
~RAS
~CAS
Storage
element
(capacitor)
Memory
Array
OE CS
tRC
Engineer To Engineer. Note EE-126 Contributed by Robert Hoffmann,
tRAS
tRPRev1 (20-March-02)
European DSP Applications.
Analog Devices,
Word Line
Bit
Line
Addr RAS CAS R/W
2. Access Column:
3. Precharge:
– select bit lines
– write stored value back to
the cell
– WR: write to sense amp
– RD: read stored value
– deselect row and columns
DRAM
DRAM Architecture
~WE
tRCD
tCAS
tWCH
tWCS
tCAC
~OE
RAS – Row Access Select
CAS – Column Access Select
R/W – Read / Write
OE – Output Enable
CS – Chip Select
Address
Data
Row
Col
tARS tARH
tACS tACH
D
Row
Idle state
Col
Q
6
What does 4-3-3 SDRAM mean
4–3–3
tRP = 20 ns
tRAS
~RAS
~CAS
tRCD = 20 ns
~WE
tCLK = 7,5 ns (133 MHz Bus)
~RAS
tRP / tCLK = 2,67 → 3
~CAS
tCAS
tRCD / tCLK = 2,67 → 3
tCLK = 7,5 ns (133 MHz Bus)
CL = tCAC / tCLK = 2
CL is CAS Latency
→2
tRP / tCLK = 2,67 → 3
tRCD = 20 ns
~WE
tCAC = 25 ns
tCAS
tRCD / tCLK = 2,67 → 3
tRAS / tCLK = 5,33 → 6
Bank cycle time
tCAC = 15 ns
~OE
Col
Row
Row
Col
Address
tRAC
Col
Row
Row
Col
tRAC
Data
DRAM
tRAS = 40 ns tRP = 20 ns
2–3–3–6
CL = tCAC / tCLK = 3,33 → 4
CL is CAS Latency
~OE
Address
What does 2-3-3-6-1T DRAM mean
Q
Idle state
D
Data
DRAM
Refresh
Engineer To Engineer. Note EE-126 Contributed by Robert Hoffmann.
European DSP Applications. Analog Devices, Rev1 (20-March-02)
TN-04-30. VARIOUS METHODS OF DRAM REFRESH
Rev. 2/99, Micron Technology
Q
Idle state
D
RAS only Refresh (ROR)
The external row address during the falling edge of the ~RAS pin
starts a refresh each time it is required.
Note: The RAS only refresh requires an external address counter.
each cell unit consisting of a transistor and a very small capacitor of
about 20-40 fF (Femtofarad, 0.020-0.040 pF) - a charged capacitor has a
logical 1, a discharged capacitor a logical 0
Refresh
the DRAM must refresh the row each time the spec tREF is elapsed. The
row refresh pattern is free until the time tREF is satisfied for each row.
Note: The Refresh uses internal read during tRAS and write during tRP.
Note: The Refresh row cycle tRC=tRAS+tRP.
3 different refresh modes are available: RAS only Refresh, Hidden
Refresh, CAS before RAS Refresh
FRAM Operation
FRAM
ferroelectric crystal has a mobile atom in the center of the crystal,
applying an electric field across a face of the crystal causes this atom to move
in the direction of the field
reversing the field causes the atom to move in the opposite direction
atom positions at the top and bottom of the crystal are stable
removing the electric field
leaves the atom in a
stable position, even in the
absence of power
as a memory element, the
ferroelectric crystal creates
an ideal digital memory - it
contains two stable data
states, it requires very little
time and energy to change
states, and is very stable
over a variety of
environmental conditions
Shan Sun, Bob Sommervold, Terri Culbreth, Tom Davenport: Data Retention
Performance of 0.5 µm FRAM Products. Technical paper, Ramtron, Apr. 2006
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