Cosmos OpenSSD: a PCIe-based Open Source SSD Platform
Transcription
Cosmos OpenSSD: a PCIe-based Open Source SSD Platform
Cosmos OpenSSD: A PCIe-based Open Source SSD Platform Yong Ho Song1, Sanghyuk Jung1, Sang-Won Lee2, Jin-Soo Kim2 Hanyang University1, Sungkyunkwan University2, Korea Flash Memory Summit 2014 Santa Clara, CA 1 OpenSSD Introduction Flash Memory Summit 2014 Santa Clara, CA 2 What’s the OpenSSD Project Open-source SSD platform for research and education on the SSD technology since 2011 New “OpenSSD platform” for developing SSD firmware, controller hardware, and host software Contribution • Indilinx (Merged to OCZ in 2012) • HYU (Hanyang University), Korea • SKKU (Sungkyunkwan University), Korea Flash Memory Summit 2014 Santa Clara, CA 3 Why OpenSSD? Solve your problem in a real system Share your solution with people in society Design your own SSD controller, if possible Contribute to “open” community Use it as a PC disk Play for fun Flash Memory Summit 2014 Santa Clara, CA 4 OpenSSD Project History Jasmine OpenSSD (2011) • SSD controller: Indilinx Barefoot (SoC w/SATA-2) • Firmware: SKKU VLDB Lab • Users from 10+ countries • 10+ papers published Barefoot Controller SoC NAND Flash Memory (32GB/module) SATA-2 Interface Flash Memory Summit 2014 Santa Clara, CA 5 OpenSSD Project History Cosmos OpenSSD (2014) • SSD controller: HYU Tiger3 (FPGA w/PCIe Gen2) • Firmware: HYU ENC Lab, SKKU VLDB Lab • Users from ?? countries (at least one) • ?? papers to be published (at least three) SSD Controller In FPGA NAND Flash Memory (256GBs/module) External PCIe Interface Flash Memory Summit 2014 Santa Clara, CA 6 Comparison among the Platforms Jasmine OpenSSD Cosmos Cosmos Prototype (Tiger2) OpenSSD (Tiger3) SSD Controller Indilinx Barefoot (SoC) HYU Tiger2 (FPGA) HYU Tiger3 (FPGA) Year 2011 2012 2014 Host Interface SATA-2 PCIe Gen1.1 (AHCI Subset) PCIe Gen2 (AHCI Subset) Storage Capacity 128 GB 512 GB 512 GB NAND Data Interface Asynchronous Asynchronous Synchronous DRAM Capacity 64 MB 512 MB 1 GB Flash Memory Summit 2014 Santa Clara, CA 7 OpenSSD Project Homepage http://www.openssd-project.org Flash Memory Summit 2014 Santa Clara, CA 8 Cosmos OpenSSD Platform Features Flash Memory Summit 2014 Santa Clara, CA 9 Design Objective A simple NAND storage platform to be used for • Firmware development and evaluation • Controller architecture exploration • New controller design (e.g. Intelligent SSD) An open-source SSD platform with AP-class CPUs and other hardware resources Flash Memory Summit 2014 Santa Clara, CA 10 Cosmos SSD Hardware Features FPGA MCU Storage DRAM Bus Xilinx Zynq-7000 series Type CortexTM- A9 Clock Frequency 667 MHz Total Capacity 512 GB NAND Organization 4-Channel / 8-Way Device Interface DDR3 (533 MHz) Total Capacity 1 GB System AXI-Lite (Bus width: 32 bits) Storage Data AXI (Bus width: 64 bits, Burst Length: 256) SRAM 256 KB (FPGA Internal) Error Correction Code BCH 32 bits/2 KB Host Interface PCI-Express Gen2 4-Lane (2 GB/s) Power Measurement NAND Flash and Board Power Measurement (External ADC Module or NI DAC) Flash Memory Summit 2014 Santa Clara, CA 11 NAND Flash NAND Flash Memory Specification Vendor / Model SK Hynix / H27QDG8VEBIR-BCB Device Interface Synchronous (ONFI 2.2) Cell Technology MLC (2 Bits/cell) Capacity 16 GBs/package Page Size Data Area 8192 Bytes/page Spare Area 640 Bytes/page Dies per Package 4 dies (QDP) Data Cycle 20 ns (DDR: 10 ns) Page Read 70 us (typical) Page Program 1400 us (typical) Block Erase 3.5 ms (typical) Speed NV-DDR100 Flash Memory Summit 2014 Santa Clara, CA 12 DRAM DRAM Memory Specification Vendor Samsung (K4B4G1646B-HCK0) Device Interface DDR3-1066F DRAM Device Bus Width 16 Bits Capacity 1 GB (512 MBs x2) CAS Latency 7 Cycles CAS Write Latency 6 Cycles RAS to CAS Delay 7 Cycles Precharge Time 7 Cycles Throughput 8.5 GB/s Flash Memory Summit 2014 Santa Clara, CA 13 Cosmos SSD Platform Board 8 4 No. Information 1 Xilinx Zynq-7000 (HYU Tiger3 Controller) 2 DDR3 (512 MB x2) 3 NAND SODIMM x2 4 External PCIe x2 5 USB JTAG 6 UART 7 USB 2.0 OTG 8 SD Card 9 Power Measurement Connector 3 2 1 5 9 6 7 4 Flash Memory Summit 2014 Santa Clara, CA 14 HYU Tiger3 Controller HYU Tiger3 Controller DDR3-1066 1 GB DRAM RS232 256 Mb QSPI DMA RX Engine Host I/F Controller DDR3 Memory Controller External Interface ARM A9 Dual-Core ARM A9 Processor System DMA TX Engine QSPI Flash Controller Flash Memory Summit 2014 Santa Clara, CA 7 Series PCI-Express Core SG DMA Controller Host PCI-Express Gen2 4-Lane TX FIFO PCI-Express Engine with SG-DMA Central Interconnect NAND Flash Buffer Controller FPGA to Memory Interconnect NAND Flash Channel Controller Performance Monitor ZYNQ-7000 FPGA (XC7Z045-3FFG900) RX FIFO Page Buffer ECC Engine NANDFlash Flash NAND NAND Flash Way Controller WayController Controller Way NAND Flash NAND Flash NAND Flash Arrays NAND Flash Arrays Arrays Arrays NAND Storage Controller AXI Bus 15 Storage Performance Monitor Statistics on the performance and utilization of hardware resources NAND Flash Buffer Controller Page Buffer ECC Engine Statistics Registers Storage Requests NAND Flash Way Controller #0 NAND Flash Arrays NAND Flash Way Controller #1 NAND Flash Arrays NAND Flash Way Controller #2 NAND Flash Arrays Program Latency NAND Flash Channel Controller Read Latency Channel Utilization Buffer Occupation GC Latency … GC Invocation Software Execution Latency Performance Monitor Bit Error Status NAND Flash Way Controller #7 NAND Flash Arrays ∽ Storage Controller Flash Memory Summit 2014 Santa Clara, CA 16 Use of Performance Monitor Cosmos OpenSSD Platform Application (C/C++) CPU I/O Ports I2C / SPI UART Software module performance Software System Bus Storage performance Memory Controller Host I/F Controller (PCIe) Performance Monitor BCH Engine Host System Channel Controller Storage Controller DRAM NAND Array RTL (Verilog/VHDL) Hardware module performance Hardware Flash Memory Summit 2014 Santa Clara, CA 17 Example: Operation Time Breakdown Page Page ●●● Buffer (DRAM) Host NAND Page Data Register tPROG BUF2NAND HOST2BUF tPROG Response Time MSB (SLOW) MSB (FAST) CFLRU LSB AVG LSB Flash Memory Summit 2014 Santa Clara, CA MSB (FAST) MSB (SLOW) Page Number 18 Available FTLs (under GPL) TutorialFTL (by HYU ENC Lab) • Page-mapping FTL w/o GC • Device initialization and interface definition GreedyFTL (by HYU ENC Lab) • Page-mapping FTL w/ Greedy GC ⃰ DramDisk (by HYU ENC Lab) • DRAM Disk for measuring maximum read/write performance (PCIe + DRAM) Flash Memory Summit 2014 Santa Clara, CA 19 Common Operation Flow Device Initialization Used in TutorialFTL and GreedyFTL Firmware Start () Command Parsing CMD READY? Yes Yes No No CMD END? Select a page to op READ? No Yes IDLE OP? Not Available Available Background OP Flash Memory Summit 2014 Santa Clara, CA No BUF HIT? Yes No BUF HIT? Yes Call buf_read() Call buf_write() Call NAND_read() Call NAND_write() 20 Host Software AS-IS • Makes the storage work as a drive • Handles read/write requests from kernel • Needs to install storage-specific device driver – Windows7 64-bit device driver (by HYU ENC Lab) – Linux 3.2.X kernel device driver (by HYU ENC Lab) TO-BE • Compatible with PCIe system drivers – AHCI support – NVMe support Flash Memory Summit 2014 Santa Clara, CA 21 Some Use Cases Flash Memory Summit 2014 Santa Clara, CA 22 Cosmos Prototype (Tiger2) Architecture Exploration Sequential Read Simulator (FlashSim) Sequential Program ─ 16% Simulator (FlashSim) 22.3% Cosmos Prototype Throughput (MB/s) Throughput (MB/s) Cosmos Prototype When compared to the simulator, the performance of cosmos prototype is 16% lower and 22.3% higher in read and program operations, respectively Note: Cosmos prototype is used in this experiment Flash Memory Summit 2014 Santa Clara, CA C-Channel: Clustering-Channel *Ref.) FlashSim: A Simulator for NAND Flash-Based Solid-State Drives 23 X-FTL Transactional FTL for SQLite (SIGMOD 2013) • Atomic write of data pages – Offload the semantic of all-or-nothing propagation of data pages carried out in host system down to FTL layer – Avoid “redundant writes” • Originally on top of Jasmine OpenSSD; now in porting to Cosmos Flash Memory Summit 2014 Santa Clara, CA *Ref.) X-FTL: Transactional FTL for SQLite Databases 24 X-FTL (Continued) Architecture Update P1, P2, … , Pn, Commit/Abort Application File System Interface SQLite -Read(Pi), Write(Pi), fsync, ioctl(abort) File System Read(Ti, Pi) , Write (Ti, Pi), Commit(Ti), Abort(Ti) - Storage Interface Page Mapping Table (L2P) Traditional FTL with Garbage Collection LPN PPN : : P1 : : Pn : : P1 Transactional Page Mapping Table (X-L2P) Propagation at commit P2 Old copy of P1, … , Pn Flash Memory Summit 2014 Santa Clara, CA TID : Ti : Ti : Pn LPN : P1 : Pn : X-FTL Write/ Read PPNnew Status : Active : Active : Commit/ Abort Recovery P1 P2 Pn New copy of P1, … , Pn 25 ActiveSSD ActiveSort (HotStorage 2014) • Accelerates external sorting • Performs on-the-fly merge inside the SSD when the results are requested • Eliminates extra data transfer • Increases the lifetime of SSDs Request Active SSD Data Flash Memory Summit 2014 Santa Clara, CA On-the fly processing Result Next processing *Ref.) Accelerating External Sorting via On-the-fly Data Merge in Active SSDs 26 Stay Tuned Sources will be available soon at the OpenSSD webpage Sources could be updated by other users except us (welcome all the time!) And more activities will be posted to the webpage as well Flash Memory Summit 2014 Santa Clara, CA 27 Call For Participation Welcome any contributions from • SSD manufacturers • NAND flash vendors • Research groups • Individual developers • … Flash Memory Summit 2014 Santa Clara, CA 28 Contributors Prof. Jin-Soo Kim Ph.D. Sungkyunkwan Univ Prof. Yong Ho Song Ph.D. Hanyang University Prof. Sang-Won Lee Ph.D. Sungkyunkwan Univ Jaehyeong Jeong Ph.D. System Architecture & SSD HW Controller Sanghyuk Jung Ph.D. System Architecture & SSD SW Firmware Youngnam Kim SSD HW Architecture Taeyeong Huh SSD HW Controller Sangjin Lee Controller Architecture & PCIe Interface Ilyong Jung Controller Architecture & ECC Engine Gyeongyong Lee SSD SW Firmware Luis Cavazos Active SSD Gi-Hwan Oh xFTL Design Young-Sik Lee Active SSD Sung-Rae Kim Ph.D. ECC Algorithm Flash Memory Summit 2014 Santa Clara, CA Youngin Jo SSD Architecture & PCIe Interface 29 Thank you For further information, visit http://www.openssd-project.org Flash Memory Summit 2014 Santa Clara, CA 30
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