Memories general view - Moodle

Transcription

Memories
Microelectronic for System On Chip
R. Beuchat
LAP-EPFL
rene.beuchat@epfl.ch
1998-2015
R.Beuchat / Memories
1
General classification of electronic memories
 Volatile Memories
 Non-volatile Memories
 Static RAM (RAM/SRAM)
 ROM
 PROM
 EPROM
 EEPROM
 Flash EPROM






E lectrically
E rasable
P rogrammable
R ead
O nly
M emory
 S tatic
 S ynchronous
 Dynamic RAM
(DRAM/SDRAM, DDR)
NVRAM
 D ynamic
NonVolatile
RAM
 R andom
 A ccess
 M emory
MRAM
Magnetoresistive RAM  S ynchronous
 D ual
 D ata R ate
 Z-RAM (Zero transistor)
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Objectives
 Understanding of the different kinds of
memories on the market
 Understanding the internal architecture of
memories
 Understanding of the access protocol to
control them
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Memory Model
Random Access Memory :
at Address  DATA
Address
0x00
0000 0000
0110 1101
0x01
0000 0001
0100 0101
0000 0010
0010 1111
0000 0011
1101 0101
0000 0100
0110 1001
. . . .
. . . .
0111 1011
0x7F
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Data: Content
1010 1101
0111 1100
0011 1000
0111 1101
1100 0101
0111 1110
1010 1001
0111 1111
0111 1010
Write
Read
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Content
 Non Volatile Memories
 Volatiles Memories : Static
 Volatiles Memories : Dynamic
Asynchronous
Synchronous
Dual Data Rate
RamBus
Evolution / Market
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Non Volatile Memories
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Non-volatile Memories
Non-volatile Memories
 Content will NOT BE LOST when Power is
turn Off
 Content is NOT changeable or at the price
of special manipulation or programming
algorithm
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Non-volatile Memories
 Non-volatile Memories
 ROM
 Content write at factory
 PROM
 Programmable ONE time by user
 EPROM
 Programmable by user and Erasable by UltraViolet light (window)
 !! Need to be removed from board to a UV eraser
 !! Need specific programming equipment
 OTP (One time Programmable) same technology but, without
window  not erasable
 EEPROM
 Electrically Erasable  no windows, can be programmed in situ
(on board) but high price
Flash EPROM
 Erasable and programmable on board by block (page)
 USED on (almost) every device NOW
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Flash EPROM basic
 Used a floating gate to
memorized the information
 Erasable/Writable by page
 Density
 Mirror bit technology to
memorize 2-4 bits per
memory cell
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http://www.spansion.com/flash_memory_technology/index.html
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Flash EPROM conventional (Spansion/Amd)
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Flash EPROM conventional (Spansion/Amd)
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Flash EPROM
 MirrorBit technology to memorize 2-4 bits per memory cell
toward 1Gb memory chip
 Ex.: new Spansion memories
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Flash EPROM parallel (symbol)
 Typical signals
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Flash EPROM serial (symbol)
http://www.spansion.com/products/S30MS-P.html
 No address
 Serial access to the data
 Command to address a specific data
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Flash EPROM
 Programming need a
specific algorithm to be
implemented by specific
software on the
microprocessor using the
memory
 In programming process,
the data bus in reading
cycle provide STATUS
information
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Flash EPROM
 Read timing
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Flash EPROM
 Read timing, page mode
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Flash EPROM (Programming timing)
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Flash EPROM (Erase)
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Flash EPROM
 Programming by specific algorithms, proprietary or
CFI (Compact Flash Interface)
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Flash EPROM (status information)
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Flash EPROM serial (symbol)
 Big array to memorize the information
 Transfer to a read/write area
 Serial (consecutive) access in this area
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Flash EPROM serial (read access)
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Flash EPROM serial (column read access)
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Flash EPROM serial 1bit SPI
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Flash EPROM serial 1bit SPI
 Serial transfer line : Synchronous Peripheral Interface
 Transfers are done by command/data on SO, SI line
 Synchronously with SCK (Clock) when CS* activated
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MRAM
 Magneto resistive random access memory
 Use electrical field to change Magnetic
direction  0, 1 value
 Same interface as SRAM (x16)
 4 Mb (256kx16) Freescale
 2Mb (128kx16)
 1Mb (64kx16)
 35ns
 TSOP-44
 http://www.freescale.com/files/memory/doc/fact_sheet/
BRMRAMSLSCLTRL.pdf
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MRAM
 Announced to be the replacement of
SRAM/Flash/DRAM !!
 Not today
 We can dream
 Today :
35 ns access cycle (not bad, DDR : few ns)
4 Mb (too small, SDRAM  Gb : factor of 1000!)
No refresh (very nice)
Could replace medium SRAM/Flash
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MRAM
 NVE
 http://www.nve.com/mrampapers.php
 A lot of research in this area
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Volatile Memories
Static Memories
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RAM memories classification (RAM:
 Static
 Dynamic
 RAM Asynchronous
 SRAM Synchronous Ram
 Flow Through
 Pipeline
 SyncBurst
Flow-through
Pipelined
 Late Write
Latched
Pipelined
 ZBT, NoBL
 QDR
 Cache Tag memory
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Random Access Memory)
 DRAM
 Nibble mode
 Static Column Mode
 Page Mode
 Fast Page Mode (FPM)
 EDRAM
 Extended Data Out (EDO)
 VRAM
 DRAM synchronous






SDRAM
SLDRAM
SGRAM
DDR-I, DDR-II SDRAM
DDR SGRAM
RamBus RDRAM
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Asynchronous RAM
Address
 Address Bus
 Data Bus
 Control Bus
/CS: Selection
/Wr: Write Access
/OE: Read Access (Output Enable)
CS
Wr
OE
Adr.
/CS
/Wr
/OE
Data
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Data (x4, x8)
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RAM inside
A bit of static memory: 5-6 Transistors/bit of memory
Here Address mean that it is the validated address
of the bit to write :
• Address and CS and WR
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Asynchronous RAM x16
 Address Bus
 Data Bus
 Control Bus
Address
/CS: Selection
/Wr: Write Access
/OE: Read Access (Output Enable)
/BHE: Byte High Enable
/BLE: Byte Low Enable
CS
Wr
OE
BHE
BLE
 Available size  512k x 16
 Access time ~50-70 ns
Data (x16)
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Asynchronous RAM x16
Byte access with:
/BHE(15..0)
/BLE (7..0)
Example
Cypress IDT 71V416
Follow the Gate Logic…
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Synchronous static Memory
 Clk synchronization access
 All signals timing referenced by Clk edge
Less timing to validate
State machine design
Main use in cache memory
 Version :
Flow-through
Pipeline
 Read-Write Cycle :
Asymmetric
Symmetric
 ZBT Zero Bus Turnaround,
 NoBL, No Bus Latency
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SRAM Pipeline/Flow through
 "High performance", Clk  250MHz
  72Mbits (x16, x18, x36, x38, x72, data bus size)
 3.3V, 2.5V power supply
 Access time from Clk data 3.5ns
 Burst Mode (/ADV actif)
 Interlaced (/LBO = H)
 Linear (/LBO=L)
 Write Global
 Write Separated, global Enable
 TQFP 100 pins (x18, x36), BGA (x36, x72)
 Power down, pin ZZ
 Address Register
 Data Input Register
 Data Output Register (pipeline) on some devices
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Synchronous SRAM Flow-Through
 Ex: 32kx32 IDT 71V433
CLK
Clock Input
Input
A14-A0
Address Inputs
Input
Synchronous
/CE
CS0, /CS1
Chip Enable
Chips Selects
Input
Input
Synchronous
Synchronous
/OE
Output Enable
Input
Asynchronous
/GW
/BWE
/BW1-/BW4
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Input
Input
Input
Synchronous
Synchronous
Synchronous
/ADV
/ADSC
/ADSP
/LBO
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
DC
I/O31-I/O0
Data Input/Output
I/O
Synchronous
ZZ
Sleep Mode
Input
Asynchronous
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Ex: 32kx32 IDT71V433
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Synchronous SRAM Pipeline
Ex: 32kx32 IDT71V432 Cache Ram Clock 100MHz
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Pentium, PowerPC
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Processor
access
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Cache ctrl
access
42
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(Burst Read, IDT 71V433)
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Synchronous SRAM Flow-Through (Burst Write, IDT71V433)
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Synchronous SRAM Flow-Through (IDT 71V433)
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SRAM Pipeline
Ex: IDT71V432 32kx32 Cache Ram Clock 100MHz (Read/Write)
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SRAM Pipeline
Ex: IDT71V432 32kx32 Cache Ram Clock 100MHz, read
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SRAM SyncBurst
 Idem SRAM synchrone
 Mode Burst
 Pipeline/Flow-through
 Data at the same time than the address in write
cycle
 Data 2 or 1 clock after the address in writing
cycle
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SRAM ZBT, NoBL
 ZBT : Zero Bus Turnaround
 NoBL : No Bus Latency
 Same delay for read and write :
Flow-through
Pipeline
1 clk
2 clk
 Manufacturer proprietary name,
 Same function, same package
 Compatible
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SRAM ZBT, NoBL
 Flow Through
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 Pipeline
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SRAM ZBT
 Pin
A16..0
Address Inputs
Input
Synchronous
/CE1, CE2, /CE2
Three Chip Enables Input
Synchronous
/OE
Output Enable
Input
Asynchronous
R/W
Read / Write Signal Input
Synchronous
/CEN
Clock Enable
Input
Synchronous
/BW1, /BW2, /BW3, /BW4 Byte Write Selects Input
Synchronous
CLK
Clock
Input
N/A
ADV//LD
Advance burst address / Load new address
Input
Synchronous
/LBO
Linear / Interleaved Burst Order
Input
Static
I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O
Synchronous
VDD 3.3V
Power
Supply Static
VSS
Ground
Supply Static
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SRAM ZBT
Flow-through
Pipeline
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SRAM ZBT pipeline vs SRAM pipeline
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QDR Quad Data Rate
 2 Clk C and K
 Data transfers on each clock edge
 Data Bus: In / Out separated
 2 Address Bus
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QDR Quad Data Rate
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Volatile Memories
Dynamic Memories
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DRAM (asynchronous basic memory)
 Main characteristics:
Dynamic Memory
 Rom/Column Organization
 Control signals: /RAS, /CAS, /WR, (/OE)
Burst access possibilities:
 Nibble mode
 Static Column Mode
 Page Mode
 Fast Page Mode (FPM)
 Extended Data Out (EDO)
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DRAM
Memorization elements
All acceded on a row at the same time
 Power consummation
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DRAM
multiplexed Addresses: Row/Column
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DRAM
multiplexed Addresses: Row/Column
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DRAM
Data Bus :
Separated In/Out
Bi-directional
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DRAM
Memories controller
Processor interface : Address multiplexer
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DRAM, circuits multiples
Control signals organization on a memory module
Ex: 32 bits data bus width, with parity
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DRAM read access
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DRAM write access
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DRAM late write
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DRAM Read-Modify-Write
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DRAM Precharge time
 Between 2 access there is the recovery time
 The vertical (column) lines are precharge to an
intermediate voltage
 When access to the memory is done, the
driver is less stressed to transfer the high/low
logical level
 This take time !! ~30-50 ns
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DRAM Refresh
 The memory need to be refreshed to maintain
its content
 Particular Cycles :
RAS only
CAS before RAS
Hidden refresh
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DRAM Refresh
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DRAM Refresh
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DRAM Refresh
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DRAM Accès multiples, page
Page mode
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DRAM Accès multiples, nibble
Nibble mode
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DRAM Accès multiples, static column
Static column mode
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DRAM Accès multiples, static column
Static column mode
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DRAM Accès multiples, EDO
EDO
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VRAM (Video RAM)
 Asynchronous Dynamic Memory
 Added "Serial Register"
 Transfer between Dynamic array and serial
line
 Independent serial transfers
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VRAM (Video RAM)
Ex:
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First VRAM 64k x 4,
4 serial bits
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VRAM (Video RAM) simple model
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VRAM parallel register+counter+mux
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VRAM parallel register+counter+mux
 The serial register is build from a parallel
register  the full content of the selected line
(Row) is transferred in a large register
 During the column phase, the address is
transferred in a counter: the start address of
the line
 The counter select a multiplexer, thus the
parallel register is transform in a serial
register!
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SDRAM
Synchronous Dynamic RAM
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SDRAM (Synchronous DRAM)
 synchronous DRAM Memories
 16 Mbits..256 Mbits
 x4, x8, x16, x32
 3.3V, 2.5V  1.8V
 Clk 200MHz
 2 Banks / 4 Banks
 PC100 SDRAM standard
 Command ACTIVE to send with the Row and
Bank address
 Read, Write Command with Column address
 Concurrent Precharge between 2 banks
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SDRAM
 Clock to synchronized every signals
 Internal Pipeline
 New column address possible in every
transfer cycle
 Internal banks available to shadow the
precharge
 Self-refresh (Self-Refresh command )
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SDRAM
Bank0
Bank1
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SDRAM
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SDRAM
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SDRAM Cas Latency (CL) Read cycle
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SDRAM Write data with command
CL=3
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SDRAM
CL=2
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SDRAM 4 banks ex: IS42S32800B
 Nb row (12) ≠
Nb Column(9)
 4 banks
 x32 bits width (4x8bits)
 256 Mbits :
 4 x 2M x 32
 Masked by DQM<3..0>
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SDRAM 4 banks ex: IS42S32800B
See the full documentation
For all specific timings relationships
http://www.issi.com/pdf/42S32800B.pdf
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Module DIMM SDRAM
Module DIMM 100-Pin
Bus x32
Synchronous
SDRAM Memory
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SDRAM (x32, x36)
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SDRAM (x64, x72)
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PC100 SDRAM DIMM Dual In Line Memory module
 Specification from Intel for DIMM 100MHz
 EEPROM memory on the module for the
specification of the DIMM
 SPD : Serial Presence detect
 Specification for memory from 64Mbytes to
1024 Mbytes (1GBytes)
 Module without buffer
 Module with register to be used with up to 36
chips
 Old specification (historical)
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SGRAM Synchronous Graphic RAM
 128kx32, 256kx32, 512kx32
 Synchronous
 Double banque
 Burst 1, 2, 4, 8 ou pleine page
 Block Write, Write par bit
 Auto precharge, auto refresh
 3.3V
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SGRAM Synchronous Graphic RAM
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SGRAM
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SGRAM
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Graphics Memory GDDR
 Features

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2.2V +/-0.1V VDD/VDDQ power supply supports 900 / 800MHz
2.0V VDD/ VDDQ wide range min/max power supply supports 700MHz
1.8V VDD/ VDDQ wide range min/max power supply supports 500 / 600MHz
Single ended READ Strobe (RDQS) per byte
Single ended WRITE Strobe (WDQS) per byte
Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
Calibrated output driver
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
RDQS edge-aligned with data for READ; with WDQScenter-aligned with data for WRITE
Eight internal banks for concurrent operation
Data mask (DM) for masking WRITE data
4n prefetch
Programmable burst lengths: 4, 8
32ms, 8K-cycle auto refresh
Auto precharge option
Auto Refresh and Self Refresh Modes
1.8V Pseudo Open Drain I/O
Concurrent Auto Precharge support
tRAS lockout support, Active Termination support
Programmable Write latency(1, 2, 3, 4, 5, 6)
Boundary Scan Feature for connectivity test(refer to JEDEC std., not in this version of
Specifications)
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Graphics Memory
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DDR Dual Data Rate
http://wccftech.com/micron-compete-samsung-16-nm-dram/
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DDR Dual Data Rate
 DDR-I
PC1600 = DDR 200MHz Data-rate (100 Clk x 2) 1.6Gb/Sec
PC2400 = DDR 300MHz Date-rate (150 Clk x 2) 2.4Gb/Sec
DDR-II
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Clock in Synchronous DRAM
 SDRAM Clock: rising edge only
 DDR Clock:
both edge
internal bus size = 2* external
internal f = 1/2 *ext. f
 DDR2 Clock:
both edge
internal bus size = 4* external
internal f = 1/4 *ext. f
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DDR Clock use
SDRAM / DDR are synchronous DRAM
SDRAM are working on rising-edge only
DDR are working on both edge of the clk for
the burst data transfer on the same row of a
bank
They are external clk and internal clk
Internal bus width can is growing with new
generation
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Clk SDRAM
http://www.elpida.com/pdfs/E0437E40.pdf
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Clk DDR
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Clk DDR2
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DDR Dual Data Rate
 Synchronization for data transfers : DQs
 Burst transfer on 2 edges of DQs
 Synchronization with DQs :
DQs provided by the memory controller in write cycle
DQs provided by the memory in read cycle
DQs propagate in the same direction as data
DDR : power supply 2.5V
DDR-II : power supply 1.8V, ODT (On Die Termination)
DDR-III : power supply 1.5V, ODT
Data bus termination Vtt = Valim/2
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DDR Dual Data Rate
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DDR signaling
http://www.fairchildsemi.com/ms/MS/MS-6500.pdf
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DDR signaling
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DDR signaling
 The SSTL_2 input receiver is typically a differential pair
common source amplifier. This receiver provides better
gain and bandwidth, and the variation in threshold
voltage is much tighter, since the threshold voltage
offset is determined by identical size and technology
transistors in a differential pair configuration.
 The result is that smaller input signal swings can be
used reliably.
 Many variations and enhancements to this input
receiver topology are in use today.
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DDR signaling
Double terminated output
Single terminated output
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DDR signaling
VRef divider and filter
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VTT PCB
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VTT PCB
ML6554 Bus terminator Power
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VTT PCB
ML6554 Bus terminator Power
1A – 3A !!
~55°C
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DDR Dual Data Rate
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DDR/RamBus comparison
Memory name
Clock
speed
100MHz
Voltage
PC100
Type
name
.
PC133
.
PC1600
3.3v
DDR clock
speed
.
Data Bus &
Bandwidth
64-bit, 0.8GB/s
133MHz
3.3v
.
64-bit, 1.05B/s
DDR200
100MHz
2.5v
200MHz
64-bit, 1.6GB/s
PC2100
DDR266
133MHz
2.5v
266MHz
64-bit, 2.1GB/s
PC2700
DDR333
166MHz
2.5v
333MHz
64-bit, 2.7GB/s
PC3200
DDR400
200MHz
2.5v
400MHz
64-bit, 3.2GB/s
PC4200
DDR533
266MHz
2.5v
533MHz
64-bit, 4.2GB/s
RDRAM
PC800
RDRAM
PC1066
RDRAM
PC1200
400
400MHz
.
.
16-bit, 1.6GB/s
533
533MHz
.
.
16-bit, 2.1GB/s
600
600MHz
.
.
16-bit, 2.4GB/s
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SLDRAM (Synchronous Link DRAM )
 SLD4M18DR400
 4Mx18 (75Mbits)
 400MHz rate
 800MB/s peak
 8 internal banks
 Burst 4 or 8
 Protocol paquet oriented
 2 data clock
 1 command clock
 Programmable Delay
Read/Wite
 2.5V
 Configuration Register
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SLDRAM
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RamBus RDRAM (1989...)
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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Rambus
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus RDRAM
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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RamBus
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Some reference
 Flash: www.cs.washington.edu/homes/diorio/Publications/
CoAuthConfPapers/PaulHasler/Floatgate_dev.pdf
 www.amd.com
 www.fujistu.com
 www.spansion.com
www.spansion.com/flash_memory_technology/43704A
-Spansion-MirrorBit-Quad-Whitepaper.pdf
 www.rambus.com
 www.rambus.com/us/products/rdram/documentation/datasheets.html
 www.hynix.com
 www.elpida.com
 www.issi.com
 www.issi.com/pdf/42S32800B.pdf
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Dynamics Memory
Evolution
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Kind of memories for group of applications
 Computing Memory
 DDR3 SDRAM
 DDR2 SDRAM
1Gb
512Mb | 1Gb | 2Gb
 DDR SDRAM
128Mb | 256Mb | 512Mb
 DDR2 SDRAM
 DDR SDRAM
 SDR SDRAM
256Mb | 512Mb | 1Gb
128Mb | 256Mb | 512Mb
64Mb | 128Mb | 256Mb
 Consumer Memory
UBDIMM
UBDIMM | FBDIMM | VLP RDIMM |
RDIMM | SODIMM
UBDIMM | RDIMM | SODIMM
 Graphics Memory
 GDDR SDRAM 256Mb | 512Mb
 DDR2 SDRAM 256Mb | 512Mb
 GDDR3 SDRAM 256Mb | 512Mb
 Mobile Memory
 Mobile SDR
 Mobile DDR
 PSRAM
256Mb | 512Mb
256Mb | 512Mb
 Small Block
 Large Block
128Mb | 256Mb | 512Mb | 1Gb
1Gb | 2Gb | 4Gb | 8Gb | 16Gb | 32Gb
 NAND Flash
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Computing Memory
16Mb
32Mb
64Mb
128Mb
256Mb
512Mb
DDR3
1G
2G
4G
8G
16G
32G
X
X
X
X
X
DDR2
X
DDR
X
X
X
X
X
X
X
X
X
X
X
X
Consumer Memory
DDR2
DDR
SDRAM
X
X
Graphics Memory
GDDR5
GDDR4
GDDR3
X
X
GDDR2
X
X
GDDR
X
X
SDR
X
X
DDR
X
X
X
X
Mobile Memory
PSRAM
X
X
X
NAND Flash
Small Block
X
Large Block
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X
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Computing Memory
 DDR3
 COMPONENT : 1Gb
 MODULE : UBDIMM
 DDR2
 COMPONENT : 512Mb | 1Gb | 2Gb
 MODULE : UBDIMM | FBDIMM | VLP RDIMM | RDIMM | SODIMM
 DDR
 COMPONENT : 128Mb | 256Mb | 512Mb
 MODULE : UBDIMM | RDIMM | SODIMM
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Consumer Memory
16Mb
64Mb
128Mb
256Mb
512Mb
1Gb
x8
SDR
DDR
X16
3.3V
TSOP
FBGA
X16
x16
x16
x32
x32
x32
x8
x8
x8
x16
x16
x16
x8
x8
x8
x16
x16
x16
2.5V
TSOP
FBGA
x32
DDR2
1.8V
TSOP
FBGA
http://www.hynix.com/gl/products/consumer.jsp?menuNo=1&m=2&s=0 Nov. 2007
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Graphics Memory
256Mb
GDDR
GDDR2
GDDR3
GDDR4
512Mb
x16
1Gb
Fréq.
Bank
Pack.
Voltage
200300MHz
4
TSOPII
(66p.)
2.5V
x16
x16
300600MHz
4
FBGA
(84b.)
1.8V – 2V
x32
x32
500MHz1.2GHz
4/8
FBGA
(136b.)
1.8V – 2V
x32
1.1GHz1.6GHz
8
FBGA
(136b.)
1.8V – 2V
GDDR5
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Memories used
http://www.elpida.com/en/products/trend.html
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Memories used
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Memories used
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Last New : GDDR5
 Hynix Introduces Industry's First 1Gb GDDR5 DRAM

DATE 2007/11/15
Seoul, November 15, 2007 - Hynix Semiconductor Inc., (‘Hynix’ or ‘the Company’,
www.hynix.com) today introduced the industry’s first 1 Gigabit GDDR5 Graphics DRAM.
GDDR, Graphics Double Data Rate, is an ultra high speed Graphics DRAM that processes
graphic data in electronic devices such as personal computer and game consoles. As high
definition digital media players market continues to expand, demand for high-speed and high
density GDDR products is rapidly increasing.
The industry’s first 1Gb GDDR5 from Hynix is also the fastest and highest density graphics
memory available. It operates at 5Gbps bandwidth and processes up to 20 Gigabytes of data
per second with a 32-bit I/O, ideal in applications with high definition video and cinematic and
photo-realistic graphics content. A bandwidth of 20 Gigabytes per second offered by the Hynix
1Gb GDDR5 can process more than 20 hours of DVD quality video.
The newly introduced GDDR5 is built on the company’s leading edge 66nanometer process
technology and designed to minimize power consumption. In addition to its small form factor
and power saving characteristics, Hynix’s GDDR5 features time delay adjustments, error
correction and jitter control technology enabling more robust system designs.
The fifth generation graphics memory GDDR5 improves data processing speed by more than
two times than that of GDDR3, the current mainstream graphics DRAM device. With its
improved speed and power characteristics, GDDR5 is projected to succeed GDDR3 and
dominate the graphics DRAM market from the 2nd half of 2008.
Hynix plans to start mass production of GDDR5 in the first half of next year to meet the
increasing demand for high performance graphics DRAM.
 http://www.hynix.com
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Elpida- DDR2
 TOKYO, JAPAN, November 7, 2007 – Elpida Memory,
Inc. (Elpida), Japan's leading global supplier of
Dynamic Random Access Memory (DRAM), announced
today that it has completed development of a 1-Gigabit
DDR2 SDRAM based on new 65nm process
technology. The 65nm process allows Elpida to create
the world's smallest chip products.
 "The new 65nm process and our own storehouse of
design technology have made it possible for the 1Gigabit DDR2 SDRAM to become the world's smallest
chip," said Hideki Gomi, Officer of Process
Technology. "Given the imminent transition from 512Megabit to 1-Gigabit products, Elpida is now geared up
to produce high-performance 1-Gigabit DRAMs at
lower cost," he added.
http://www.elpida.com/en/news/2007/11-07.html
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Elpida - XDR
 ELPIDA INTRODUCES THE WORLD'S FASTEST DRAM BASED ON
THE RAMBUS XDR MEMORY ARCHITECTURE
 4.8GHz XDR DRAM achieves 6x performance increase over industrystandard DDR2 DRAMs
 TOKYO, Japan and LOS ALTOS, Calif., October 4, 2007 – Elpida
Memory, Inc. (Elpida) (Tokyo Stock Exchange Code 6665), Japan's
leading global supplier of Dynamic Random Access Memory
(DRAM) and Rambus Inc. (Nasdaq: RMBS), one of the world's
premier technology licensing companies specializing in highspeed chip architectures, today introduced the industry's fastest
DRAM, the 512 Megabit (Mb), 4.8GHz XDR™ DRAM, based on
Rambus' XDR memory architecture. This latest addition to the
XDR DRAM family provides an industry-leading data transfer rate
of 9.6 Gigabytes per second (GB/s) with a single device, making it
an ideal choice for high-performance, high-volume applications
such as high-definition televisions (HDTV), gaming consoles,
PCs, servers and workstations.
http://www.elpida.com/en/news/2007/10-04.html#page_top
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Elpida - XDR
Features of XDR DRAM
 Highest pin bandwidth



4.8/4.0/3.2Gbps Octal Data Rate (ODR) signaling
4.8/4.0/3.2GHz data rate, octuple the data transfer rate of 600/500/400MHz system clock
Bi-directional differential RSL (DRSL)
Flexible read / write bandwidth allocation
Minimum pin count
On-chip termination
Reduced system cost and routing complexity
 Highest sustained bandwidth per DRAM device





9.6GB/s (4.8E), 8.0GB/s (4.0D), 6.4GB/s (3.2A, 3.2B, 3.2C) peak data transfer rate
8 banks:
Bank-interleaved transactions at full bandwidth
Dynamic request scheduling
Early-read-after-write support for maximum efficiency
Zero overhead refresh



1.8V VDD
Small-swing I/O signaling (DRSL) (200mV)
Power-down self-refresh support


104-ball FBGA 15.18mm x 14.56mm
Ball-pitch 1.27mm / 0.8mm
 Low power
 Package
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Elpida – XDR internal
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Exercices
 Search some explanation for specifics topics on
SDRAM/DDR:
 Prepare un small presentation (10'/groupe)
 2 students/group
 Ppt presentation (or similar)
 1 hour to prepare
 Objective: You are able to search and found
particularities of memories and present it.
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Exercises











XDR bus transfers and connection
DDR / DDR2 / DDR3 main differences
DDR2 / DDR3  DDR4 evolution
GDDR3 architecture and capability
DDR package evolution chips and modules
Precharge and Bank on DDR
Access on DDR3
Write-Read-Write access on DDR / DDR2 / DDR3
Read-Write-Read access on DDR3
ODT on DDR2 vs ODT on DDR3
NAND/NOR Flash difference
 What's new with GDDR5 ?
 What are FRAM, MRAM, PRAM memory ?
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Memories general view - Moodle

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