ELE22MIC - Microprocessors.

ELE22MIC - Microprocessors.
Lecturer:
Email:
Room:
Paul Main.
paulm@ee.latrobe.edu.au.
BG 441
Laboratory Coordinator: Geoff Tobin.
Room:
Physical Sciences 2, Room 114
Email:
G.Tobin@latrobe.edu.au
Course Outline:
Aims:
Develop a working knowledge of digital logic and how those principles
can be applied to implement a microprocessor system.
Learn how to design, build, program and debug a useful basic
microcomputer system.
Familiarise students to basic architecture of modern microprocessors,
micro-controllers and common peripherals.
Learn interfacing techniques for simple transducers (via the Analog to
Digital Converter) and how to apply them to implement electronic
systems.
Develop an ability to write 68HC11 assembly language code to meet a
design goal.
Handbook Course Description
This is a first course in microprocessors and their applications. Topics
include introduction to microprocessors, microprocessor architecture,
microcomputers, assembly language programming, memory, parallel and
serial I/O, computer design, timing, address decoding, interrupts, memory
management, caches, virtual memory, mass storage devices, DMA,
systems programming and other processors.
Class Requirements:
Two lectures per week
(total of 26)
One problem class per fortnight
(total of 5 problem classes)
Three hours practical work per fortnight
(total of 5 sessions).
Three assignments.
Lectures:
26 One-Hour Lectures.
Tuesday 9:00am to 10:00am
Friday 9:00am to 10:00am
Weeks
HS1 136
PW 101
30-38, 40-43
Laboratory Sessions:
One 3-Hour Laboratory Session per fortnight.
Labs commence next week.
Duration: 3Hours
WEDNESDAY:
2:00 pm
THURSDAY:
2:00 pm
Weeks 30, 32, 34, 36, 38, 41, 43
Location: Beth Gleeson, Room 310 (Dry Lab)
Problem Classes:
TUESDAY:
WEDNESDAY:
Location:
Weeks
Consultation Times:
Tuesday 10:00am - Noon
Friday 10:00am - Noon
12noon, Duration: 1 Hours
12noon, Duration: 1 Hours
HS1, ROOM 302
30, 32, 34, 36, 38, 41, 43
BG441
BG441
Lecture Topics Include
Introduction to microprocessors
History & perspective
Digital Logic
Hexadecimal & Binary Arithmetic.
The CPU : What's inside ?
CPU operation: Instruction Pointer, Fetch-Execute cycle, jump
Microcomputers, Microprocessor architecture,
The Arithmetic and Logic Unit - ALU
Arithmetic & Logical Instructions : Add, Subtract, Shift Left/Right
Multiply & Divide
Assembly language programming
MC68HC11 Instruction set : Registers, Load, store, transfer, exchange,
Addressing Modes
The Condition Codes Register, Jumping, Conditional Branching,
Programming techniques and applications Flow charts
Interrupts & interrupt handlers
Memory,
Computer design Timing diagrams & meeting timing constraints
Address decoding,
Interrupts,
Computer memories (hardware aspect)
Computer memories (system application)
Memory management,
Virtual memory,
Mass storage devices,
Input/Output: Parallel and serial I/O, Grey codes
Serial Input/Output serial interface devices
UARTS, RS232, RS485
Simple computer networks
Designing a MC68HC11 based computer: memory
address space considerations
bus timing considerations
Expanded memory design & caches
The counter/timer subsystem on MC68HC11
The A to D converter subsystem on MC68HC11
Mass storage devices
Advanced Aspects
Caches, Direct memory access (DMA) and related issues, DMA,
Features of other micro-controllers
Assessment:
2-hour Examination (70%),
Laboratory work (20%)
Assignments (10%).
68HC11 Resources:
Textbook - Peter Spasov,
“Microcontroller Technology - The 68HC11 and 68HC12”, 5th Edition.
Library
Internal web site URLs:
http://thor.ee.latrobe.edu.au/~paulm/ele22mic/index.html
e-www.motorola.com
Motorola manuals cached locally:
68HC11 family glossy brochure:
http://thor.ee.latrobe.edu.au/~paulm/ele22mic/resources/11_bro.pdf
68HC11 reference manual:
http://thor.ee.latrobe.edu.au/~paulm/ele22mic/resources/11rm.pdf
68HC11 Technical Data
http://thor.ee.latrobe.edu.au/~paulm/ele22mic/resources/11a8td.pdf
68HC11 Programmers Reference Guide
http://thor.ee.latrobe.edu.au/~paulm/ele22mic/resources/f1rgr2.pdf
68HC11 Evaluation Board
http://thor.ee.latrobe.edu.au/~paulm/ele22mic/resources/11evb.pdf
ELE22MIC CDROM handed out in lecture 3.
Containing presentations, notes & relevent device datasheets.
Laboratory sessions cover:
Familiarisation with HCCOM hardware
Find out about the BUFFALO monitor program,
Use BUFFALO commands to view the contents of memory and processor registers.
Examine the directly addressable memory space of MC68HCll microprocessor and find
out how it is partitioned,
Explore various instructions and addressing modes of the M68HC11.
“Hello World” program.
Study the MC681HC11's
- addressing modes,
- registers,
- Reset vector and interrupt vectors.
Learn to make System Calls using the Buffalo resident monitor.
This lab involves designing and writing an application program in assembler. The aim
of the program is to non-destructively test an area of memory for corruption. The
problem is to be broken up into smaller parts which are much easier to manage...
The Stepper Motor Control Lab.
The timer counter subsystem.
System software development The analog to digital (AD) converter.
Applications of the AD Converter
Decoding Gray codes.
HISTORIC PERSPECTIVE - TIMELINE OF COMPUTING
The Abacus “Computing Tray” The first mechanical calculating machine. 28?
The Computing Tray - was used by Babylonian priests to keep track of their vast
storehouses of grain. Still in use today. Circa 3000BC.
In Roman times the board was given grooves to facilitate moving the counters in
the proper files.
Circa 1300BC Wire & Bead Abacus replaced the Chinese calculating rods.
A modern equivalent is an Accumulator it is used to accumulate intermediate
results of arithmetic calculations. Modern accumulator uses binary numbers.
Analog Calculators:
In 1612 John Napier uses the printed decimal point, devised logarithms and used
numbered sticks (or Napiers Bones) for calculating.
This principle lead to the invention of the slide rule.
Mechanical Calculators
In 1642: Blaise Pascal Invented the first mechanical calculator constructed of 10toothed gears, wheels & teeth. It was called
“Pascalene”.
The same principle is still in use in
automobile’s (mechanical) odometer
mechanism. The same principle was the
basis for all mechanical calculators.
Punched Cards
In 1801 Joseph Marie Jacquard invented a
machine to use a linked sequence of
punched cards programmed to control a
weaving machine and produce intricate
weaving patterns in cloth.
1823: The royal Astronomical Society of
Great Britain commissioned Charles Babbage to
produce a programmable calculating machine. He
was aided by Augusta Ada Byron, the countess
of Lovelace - the first programmer. The machine
was to produce navigational tables for the Royal
Navy.
1834 Babbage shifted his focus to work on The
Analytical Engine. The mechanical computer
stored 1000 20-digit decimal numbers and a
variable program that could modify the function of
the machine to perform various tasks.
Input to his engine was through punched cards. It is assumed that he obtained the
idea from Frenchman, Joseph Jaquard.
After many years of work, Babage’s dream faded when he realised that the
machinists of the day were unable to create the parts needed to complete his
work. The analytical engine required 50 000 precision machined parts to allow
his engine to function reliably.
Michael Faraday
Was the son of a blacksmith. He had limited formal education but attended
public lectures and became an avid reader. In 1813 Started working life at
the London Royal Institution as a laboratory assistant. In 1821
demonstrated the electric motor effect. In 1831 demonstrated
EMF(current) induced by motion of magnet by a nearby conductor.
Electric Motors became available.
Motor driven adding machines based on mechanical calculators developed
by Blaise Pascal became popular. Electrically driven mechanical
calculators were common office equipment until 1970s.
Telecommunication by Morse Code
1844 - Samuel Morse sent a telegraph from Washington to Baltimore.
George Boole
Publishes “Laws of Thought”, describing a system for symbolic & logical
reasoning which becomes the basis for computer design.
1858 A telegraph cable spans the Atlantic Ocean & provides service for a few
days.
Alexander Graham Bell
in 1876, invents and patents the telephone.
Herman Hollerith’s Tabulator
In 1889, Herman Hollerith developed punched cards for storing data.
Like babbage he also borrowed the idea of a punched card from Joseph
Jaquard. Hollerith developed a machine that counted, sorted and collated
information stored on punched cards. He founded the Tabulating Machine
Company. After a number of mergers, the Tabulating Machine Company
was formed into the International Business Machines Corporation - IBM.
The punched cards used in computer systems are often
called Hollerith cards.
The 12-Bit code used on a punched card is called the
Hollerith Code. Mechanical machines continued to
dominate the Information Processing world until 1941.
Guglielmo Marconi
In 1895, transmitted the first radio signal.
Claude Shannon
in 1937 publishes the principles for an electric adder using base two.
Conrad Zuse
German Inventor, created the first
electro-mechanical calculating computer in 1941.
It was used for aircraft & missile design during
World War II for the German war effort.
The Z3 used a 5.33Hertz clocking frequency and
was based on electro-mechanical relays.
World War II (WWII) commenced.
Great Britain’s survival depended on imports of fuel, food, weapons &
industrial raw materials. Germany’s Gossadmiral Doenitz’s planned to
sink the merchant ships that were bringing supplies to Brittain by using a
powerful submarine fleet. Doenitz calculated that sinking 800 000 tons of
merchant ships per month would bring Britain to starvation, surrender and
a request for peace would result.
Enigma:
1941 German Commands to the submarine fleet were initially encrypted
with a three rotor Enigma before being transmitted by radio to submarine
commanders.
Enigma is Greek for ‘puzzle’. An example of how it works:
For example the letters ‘e’ input might be connected to the first rotor’s ‘q’ output. So
an arriving ‘e’ pulse in the first rotor goes as ‘q’ to the second rotor where it might
depart as ‘g’ to the third rotor. When a key is pressed, the right hand motor advances
one notch, changing the encryption sequence.
After 26 advances, the next rotor is advanced, etc. Also Enigma had a plug board with
26 sockets, each with up to 10 holes interlinked by the operator’s choice of
connections. Enigma also had many extra rotors with different internal connections.
The configuration of rotors and plug-board was changed daily.
Enigma Code Breaking:
Capturing a 1940 Kurzchussel cipher from the weather ship, Muenchen,
enabled British code breakers at Bletchey Park to decrypt the messages
with the aid of a crude “Bombe” computer - A computer to decipher the
Enigma encryption machine settings for that day.
Four Rotor Enigma
In Feb 1 1942 Germans began encrypted communication with a four rotor
Enigma. British crypt-analysts were unable to decrypt these new
messages.
The cost of failure to decrypt Enigma messages:
1942 Jan-July
460 ships, 203000tons, sunk.
Jan 1943
29 ships per month
March 1943
the rate had increased to 95 ships per month totalling
627000tons - twice the rate of new-ship construction.
Capturing Enigma:
Oct 30, 1942: a 25-pound four-rotor Enigma machine, with short signal
code-book, was recovered from a sinking German submarine, U559, by
two sailors who swam into the submarine from the destroyer Petard. The
two sailors lost their lives as the submarine plunged to the bottom of the
sea.
The First Electronic Computer
June 1943: Alan Turing, Tommy Flowers & MHA Newman made
operational the first electronic computer, Colossus. Colossus was utilised
to break the cipher codes generated by the mechanical Enigma Machine;
German military communication security was compromised.
Radar
British centimeter wavelength radar assisted to provide British military
superiority.German submarine attacks ceased being a threat for the
remainder of WWII.
ENIAC
1945: The University of Pennsylvania created ENIAC, the Electronic
Numerical Integrator And Calculator.
Weight: 30 ton
Used 17 000 vacuum tubes
500 miles of wires.
ENIAC was re-programmed by rewiring, a process that took many
workers several days.ENIAC was programmed by electrical connections
on plug-boards that looked like early telephone switchboards.
ENIAC processed 100 000 Instructions Per Second.
ENIAC suffered reliability problems due to limited vacuum tube life.
William Shockley
1939 William Shockley observed P- and N- type regions in Silicon.
Shockley forecast that a semiconductor amplifier was possible, but WWII
interrupted further work.
John von Neumann
1945: John von Neumann described the principles for a general-purpose,
stored program computer.
William Shockley, John Bardeen & Walter Brittain
1948: The invention of the Germanium bipolar junction transistor at Bell Labs,
by William Shockley, John Bardeen & Walter Brittain
Texas Instruments (TI) commercialised the Transistor.
The First IC.
At Texas Instruments, Jack Kilby, In 1958
realised that
1. Resistors could be formed by cutting small bars of silicon,
2. Capacitors formed by wafers metalised on both sides, and
3. Silicon transistors could all be made on the same material.
In september 1958 he created a phase-shift oscillator - the first IC on one wafer.
1964: The first mass produced mini-computer was produced by Digital
Equipment Corporation - The Digital Equipment Corporation (DEC) PDP8 minicomputer
Robert Noyce & Gordon Moore - founders of Fairchild Semiconductor became disgruntled and left Fairchild Semiconductor to start N M Electronics.
Bob Noyce wrote a single page business plan on his typewriter one night.
Noyce went to see Fairchild’s Venture Capitalist Art Rock. He requested
$2.5Million Dollars as venture capital...which he received 2 Days Later and
Intel was founded on 18 July 1968 by Robert Noyce, Andy Grove & Gordon
Moore. Intel’s first product was the ‘3101’, a 64 Bit Schottky Barrier static
RAM.
Busicom, was Japanese calculator manufacturer, and wanted Intel to develop 12
custom chips for their calculators.
Ted Hoff, an engineer at Intel, recommended one chip to function as 12.
Busicom agreed & contracted Intel. Intel went ahead with a general purpose
logic chip capable of being programmed for instructions. First use of
‘Intelligence’ programmed by software. Intel bought the design (Intellectual
Porperty) back from Busicom.
The Intel 4004.
After 9 months development Intel’s first microprocessor is born, the 4004.
The Intel 4004.
First MicroProcessor.
November 1971
10 Micron technology
2300 Transistors
108 KKz Clock
60 000 Instructions/second
Bus width 4 bits
640 bytes addressable
12 Volt. Weighed < 1 Oz.
P-channel MOSFET
Applications: Busicom Calculator
The Intel 8008
April 1972
10 Micron technology
3500 Transistors
200 KKz Clock
0.06 Million Instructions Per Second (MIPS)
Bus width 8 bits
12 Volt
Address: 16 Kbytes
Apps: Terminals, Calculators, Bottling
Machines
The Intel 8080
April 1974
6 Micron Technology
4 500 transistors
2 MHz Clock
0.64 Million Instructions Per Second
Data Bus width: 8 bits
12 Volt
Addressable memory: 64 Kbytes
Apps: Traffic light controller,
Used in the Altair computer
(first PC)
Performance = 10 x 8008
Over six times the performance of ENIAC
Intel 8086/8088
June 1978/1979
3 Micron Technology
5, 8 &10 MHz clock
0.33, 0.66 & 0.75 MIPS
29 000 Transistors
16/8 bit data bus
20 bit address bus (1MB)
5 Volt
apps: IBM PCs & Clones
performance =10 x 8080
Segmented architecture,
Complex Instruction Set Computer.
(CISC. )
8087 external Maths Coprocessor
available.
Select instructions compatible with 8080 & 8085.
1981 The open-architecture IBM
PC is launched based on the
Intel 8088
1980 PCDOS sold to IBM
1980 Ada emerged
1980 dBaseII popular
1982 First Clone PC
1982 AutoCAD
1983 TCP/IP invented
1982 Original NMOS 80186
Intel 80286
February 1982
6 MHz -12 MHz clock
0.9 - 2.66 MIPS
1.5 micron technology
134 000 Transistors
16 bit data bus
16MB Physical, 1GB Virtual
Performance =3 to 6 x 8086
Software Backward Compatible with 8086
Competitors parts: NecV.20, AMD 286 &
Cyrix 286
Intel 80386
October 17, 1985
16 MHz - 33MHz
5 to 11 MIPS
1 Micron technology
275 000 Transistors
Data Bus width: 32 bits
Addressable memory: 4 GigaBytes (GB)
Virtual memory: 64 TeraBytes (TB)
Software Compatible with 8086 & 80286
New 32 bit “Flat Mode” available.
Performance =100 x Intel 4004
1987 80C186 converted to CMOS - uses 1/4 power at twice clock rate
Many popular peripherals included on-chip:
Oscillator, Timers, UARTs, DMA, DRAM controller etc
Used in Controllers, Security Systems, Terminals
Segmented architecture
Software Backward Compatible with 8086
Still popular
The Intel 80486
April 1989 - Intel 80486
25 MHz, 20 MIPS
June 1991 50 MHz, 41 MIPS
1.2 Million Transistors
1-0.8 Micron Technology
Bus width: 32 bits
Addressable memory: 4 GB
Virtual memory: 64 TB
50X performance of the 8086.
Software Compatible with 8086
486DX first CPU to include floating
point maths co-processor on-chip.
Intel Pentium
March 1993
60 MHz 100 MIPS
66 MHz 112 MIPS
3.1 million transistors
0.8 Micron technology
64-bit external data bus
32-bitmicroprocessor
32 bit address bus
4 GB physical
64 TeraBytes ( TB) virtual
Software Compatible with
8086/286/386/486.
BiCMOS
Intel Pentium Pro
November 1995
150-200 MHz
5.5 million transistors
0.35 micron technology
64 bits front side bus
64 bits to L2 cache
Addressable memory: 64 GB
Virtual memory: 64 TB
256K - 1MB L2 Cache
Software Compatible with 8086
Intel® Xeon™
Designed for dual- and multi-processor computers.
These dual processor workstations are expected toachieve between 30 to
90 percent performance increase over systems using Intel® Pentium® III
processors.
The Intel Itanium™
Revolutionary design 64-bit products
Explicitly Parallel Instruction Computing (EPIC) design technology.
2002: Itanium™ 2
The Intel® Pentium® M - 2003.
The Intel® Pentium® M (Mobile) processor, the Intel® 855 chipset
family, and the Intel® PRO/Wireless 2100 network connection are the
three components of Intel® Centrino™ mobile technology.
It enables extended battery life and thinner, lighter mobile computers
Figure 18 - Athlon XP interface diagram
The main competition for Intel is AMD.
AMD compete on price and performance.
AMD chips typically have higher performance per dollar.
However, Intel has been the clear leader in the dual/multi-cpu market with
experience dating back to the early 1980s with their 8086/8088.
Low Power Embedded Processors:
1991: 80186EC
Includes 22 peripherals on one chip including: Power-save clock divider,
PowerDown Idle, 80C187 interface, 8259 compatible Programmable
Interrupt Controller, Timer-counter unit, enhanced chip select unit, 4
channel DMA unit, Serial Communications unit, DRAM Refresh Control
Unit, Watchdog Timer Unit.
Motorola 68HC11 Microcontroller
Primarily used in applications performing a single task or single group of tasks,
controlling:
Microwave Ovens
Fridges
Toasters
Automobiles
In 1991, > 750 million 8-bit microcontrollers were delivered by chip
manufacturers
Motorola Part Numbering
MC 68HC x 11 yy
MC = Motorola Qualified,
XC = Tested Pre Production,
M = General Family Reference
68HC = Motorola HCMOS
(High density Complementary Metal-Oxide Semiconductor)
x =7=EPROM program memory
x =8=EEPROM program memory
none = ROM or NO program memory
11=HC11 family
yy = specific family part type A8, A2, A1, A0, E9, E2, E1, E0, D3, F1, etc
Ten major series of micro-controller units
All M68HC11 Family members have on-chip SCI and SPI, and
most have EEPROM and an A/D converter.
A8:
8-bit MCU
8 Kbytes ROM, 256 bytes of RAM, 512 bytes of EEPROM,
bus speed of 3 MHz.
8-bits, 8-channel A/D (Analog to Digital) converter.
A1 = as for A8 but with the 8K ROM disabled
C0:
chip selects and memory expansion to 256 Kbytes,
2PWM channels
4 A/D channels.
D3:
4 Kbytes ROM, RAM, A/D converter, SPI, SCI and
E:
EEPROM and EPROM on a single chip.
The E-series offers multiple memory sizes in a pin-compatible package.
F1
High-speed expanded systems required the development of the
68HC11F1. This particular chip series stands out with its extra I/O ports,
an increase in static RAM (1 Kbyte), chip-selects, and a 4 MHz nonmultiplexed bus. (Fast)
G5
10-bit A/D resolution.
sophisticated timer systems
K4
KA
high speed, large memories, an MMU, PWMs, I/O.
lower pin count Kseries
L6
Low-power, high-speed chip with a multiplexed bus capable of operation
up to 3 MHz. The L6’s high performance design is based on the
68HC11E9. It includes 16 Kbytes of ROM, plus an additional
bi-directional port. Its fully static design allows operation at frequencies
down to dc.
M series:
enhanced, high-performance microcontrollers are derived from the
68HC11K4 and include large Memory modules, a 16-bit math
coprocessor, and 4 channels of DMA.
P2
Power saving programmable PLL-based clock circuit along with many
I/O pins, large memory and 3 SCI ports
Figure 19 - Motorola 68HC11A8 Microcontroller Block Diagram
Description of 68HC11A8 Block Diagram - From Top-Left clockwise.
Figure 20 - Mode Control - Reference 3 - Page 19.
The 68HC11A8 can be configured to operate in four modes:
0. “Special Bootstrap”. Downloads a bootloader program via serial communications port.
1. “Special Test” mode. Disables register security- for software designers and factory testing.
2. “Single Chip” programmed held in internal EPROM /EEPROM only.
3. “Expanded Multiplexed” mode purpose:
RAM, ROM & Program are external to 68HC11 chip.
We are primarily interested in mode 3 - as this is the mode we will be using.
2. Single Chip mode.
This mode is used when no external data bus is selected, the extra pins can
be used as general purpose digital Input or Output (I/O) ports - Ports B &
C.
3. Expanded Multiplexed mode:
Port B becomes Address bus lines A15..A8, and
Port C Becomes a multiplexed address and data bus lines A7..A0 or D7 ..
D0 depending on the phase of the signal Address Strobe (AS).
When the AS line goes high, the Address is latched into an external
74HC373 latch (See Schematic Below); This occurs once every E clock
cycle.
If we wanted to use ports B and C there are some special chips designed
to provide the functionality of these ports externally. This would be useful
if we were designing a controller that would eventually run in single chip
mode and we wanted to develop the control software using an external
RAM.
Figure 21 - Address Data De-Mulitplexing Schematic. Reference 3 - Page 24
Figure 22 - 52Pin PLCC Pin Assignment.
Reference 3 Page 147
Figure 23- Mulitplexed Expansion Bus Timing - Reference 3 - Page 141
When the AS (Address Strobe) line is high, a valid address is output onto the
multiplexed address/data bus. The 74HC373 - a transparant latch (see Figure 20
above) - transmits this address as the low 8 bits of the CPU address bus, lines
A7..A0. When the AS goes low, the address is latched and held constant until the
AS line goes high again.
So the address lines A7..A0 are held valid from cycle to cycle by an external
74HC373 chip. These address lines become valid soon after the rising edge of
AS ( Time (27)- Time(24) ).
Oscillator & Clock Logic.
The 68HC11Ax contains an oscillator circuit that requires an external
crystal and capacitors. The crystal frequency is four times the E clock frequency.
The E clock signal is halted when the microcontroller is in STOP mode.
Figure 24 - External Crystal Connection - Reference 3 Page 18.
DIGITAL LOGIC REVISION
5V Standard Logic Levels:
Logic High, 1, or True
TTL family level > 2 Volts (greater than 2V)
CMOS , > 2/3 VCC (> 3.33V for VCC=5V)
Logic Low, 0, or False
TTL level < 0.8 Volts (less than 0.8V)
CMOS, < 1/3 VCC (< 1.66V for VCC=5V)
TTL logic level compatible families include: 74xx (plain ttl), F (fast), S
(Schottky), LS (Low Power Schottky), HCT (High speed CMOS Ttl
compatible), ABT (Advanced Bipolar Ttl compatible)
CMOS Compatible: 4000 series, 74C (CMOS) 74HC (High Speed CMOS),
74 Series logic is designed for 5 Volt Power Supply.
The 4000 series logic is designed for 3-15 Volt power supply.
CMOS is considered to be the Ideal Logic Family because it has near zero static
power dissipation. The input equivalent circuit of a CMOS transistor is a 1012
Ohm (1 Tera Ohm) resistor shunted by a 5pF or less capacitor.
Most CMOS inputs also contain diodes connected to power supply rails to protect
from overvoltage and undervoltage whilst in circuit (but out of circuit the supply
rails wont clamp over/under voltages).
Most modern microprocessors are fabricated using CMOS technology.
CMOS Power dissipation
Power Dissipation in CMOS chips arises from mainly from the following sources:
1. Current pulses that occur when both FETs are switched on - typically during
the transition period of a logic level change (I.e. High -> Low or Low -> High
transition).
2. Resistive power dissipation in the FET’s Source-Drain path due to charging
the capacitance on outputs. So lowering capacitance has a direct effect on
lowering power dissipation. Power dissipation is proportional to CV2f, where C is
total Capacitance switching, V is supply Voltage, f is switching frequency.
3. Resistive power dissipation in the load and the FET’s Source-Drain path due
to resistive loads placed on outputs - V2/R power dissipation.
Figure 26 - Charging parasitic capacitance
Figure 27 Discharging parasitic capacitance
4. Supply voltage variation. The greater supply voltage, the greater the CV2f and
V2/R power dissipation.
When CMOS chips are not switching (static operation), the main power
dissipation will be from items 3 and 4 above.
At high frequencies we can see that power dissipation rises proportionately with
switching frequency - refer item 1 and 2 above.
Both these sources of power dissipation necessitate the use of power supply
decoupling capacitors located adjacent (within 1 cm) to each chip. The decoupling
Capacitor supplies power for
1. Charge pumping into the bus and
2. the current pulse through the Complementary FET switches
(Sometimes power supply decoupling capacitors are referred to as power supply
bypass capacitors, )
To minimise power consumption in a system, the circuit should be run at
the lowest acceptable speed to get the job done. This is also good practice from
the perspective of achieving C-Tick approval as the lower the clock rate, the
lower the frequency of radiation, and the simpler the noise suppression techniques
required to gain C-Tick approval. At higher frequencies RF noise radiates readily
from short Printed Circuit Board (PCB) tracks.
Floating Inputs
Due to the exceptionally high input impedance any CMOS input left
disconnected, the input will drift back and forth between logic 1 and logic 0 floating. The floating inputs will cause unpredictable and unreliable outputs and
possibly result in some intriguing, insidious or unexplainable system bugs. The
parasitic capacitance of a clock signal wire passing near a floating input could
make the device dissipate more power at best, and cause the chip to self-destruct
at worst.
Not only will the logic functions be unreliable, but a floating input is more
susceptible to problems known as Zap and Latch-Up. ****
Unused inputs should always be connected to a valid logic level, preferably
by a 10k ohm resistor. In the event that you decide to use that input, a jumperwire connection can replace the resistor connection.
References:
1.
IEEE Timeline of computing History by Bob Carlson, Angela Burgess, and Christine Miller.
2.
http://www.intel.com/intel/intelis/museum/online/hist_micro/hof/index.htm
3.
MC68HC11A8 - “The Motorola HCMOS Single-Chip Microcontroller” TECHNICAL DATA,
11a8td.pdf
4.
“Microelectronic Circuits”, Fourth Edition Sedra/Smith.
Schematic Drawings created by Paul Main using Protel DXP 2004 or Protel 98.