Introduction to Microelectronics

Transcription

Economic impact
Concepts and terminology
Design flow in digital VLSI
Field-programmable logic
Appendix I: A brief glossary of logic families
Dr. Hubert Kaeslin
Microelectronics Design Center
ETH Zürich
VLSI I: Architectures of VLSI Circuits
last update: April 8, 2009
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zürich
Economic impact
Worldwide semiconductor market by vendors (2007)
Revenue Share Share
Vendor
[GUSD]
[%]
[%]
Intel
33.80
12.3
Samsung Electronics
20.46
7.5
Toshiba
11.82
4.3
Texas Instruments
11.77
4.3
Infineon + Qimonda
10.20
3.7
ST-Microelectronics
9.97
3.6
Hynix
9.10
3.3
Renesas
8.00
2.9
AMD
5.88
2.1
NXP
5.87
2.1
others
147.05
53.8
Total
237.91
100
0.49
for comparison World GDP (2006)
48 462
100
source: Gartner March 2008 and www.worldbank.org May 2008
Rank
1
2
3
4
5
6
7
8
9
10
...
Economic impact
Economic leverage of semiconductors I
Microelectronics has a much larger impact on world economy, however,
because it is acting as a technology driver for
I
Computer and software industry
I
Telecommunications and media industry
I
Commerce, logistics and transportation
I
Natural science and medicine
I
Power generation and distribution
I
Finance and administration
Economic impact
Economic leverage of semiconductors II
EDA software &
virtual components
2006: 248 GUSD/y
Semiconductor components
Electronic components
Electronic goods
(computers, mobile phones,
home entertainment equipment, etc.)
World-wide gross domestic product
2006: 48.2 TUSD/y
Applications:
• Goods with embedded electronics
(machines, cars, cameras, watches, etc.)
• Information technology services
(corporate IT, Internet, music download, etc.)
Figure: Impact of microelectronics on “downstream” industries and services.
Economic impact
Microelectronics drives the information age
I
Microelectronics has an enormous economic leverage as any progress
there spurs innovations in “downstream” industries and services.
I
While computing, telecommunication, and entertainment products
existed before the advent of microelectronics, today’s information
society would not have been possible without.
Economic impact
Microelectronics drives the information age
I
Microelectronics has an enormous economic leverage as any progress
there spurs innovations in “downstream” industries and services.
I
While computing, telecommunication, and entertainment products
existed before the advent of microelectronics, today’s information
society would not have been possible without.
⇒ Microelectronics is the enabler of information technology.
Economic impact
Impact of semiconductors on consumer goods I
Figure: Four products that take advantage of microelectronics.
Economic impact
Impact of semiconductors on consumer goods II
Figure: Similar products that include no large-scale integrated circuits.
Economic impact
Impact of semiconductors on consumer goods III
Figure: A product that has brought system integration to even higher levels.
Economic impact
The
The
The
The
The
Guiness book of records point of view
marketing point of view
fabrication point of view
design engineer’s point of view
business point of view
The Guiness book of records point of view
“How large is that circuit?”
I
Geometric chip size
I
Transistor count
I
Gate-equivalents
1 GE 7→ 1 two-input nand 7→ 4 MOSFETs in static CMOS logic
Economic impact
The
The
The
The
The
The Guiness book of records point of view
“How large is that circuit?”
I
Geometric chip size
I
Transistor count
I
Gate-equivalents
1 GE 7→ 1 two-input nand 7→ 4 MOSFETs in static CMOS logic
circuit complexity
small-scale integration (SSI)
medium-scale integration (MSI)
large-scale integration (LSI)
very-large-scale integration (VLSI)
ultra-large-scale integration (ULSI)
GEs of logic + bits of memory
1 ... 10
10 ... 100
100 ... 10 000
10 000 ... 1 000 000
1 000 000 ...
Hint: state storage capacities separately from logic complexity, e.g.
75 000 GE of logic + 32 Kibit SRAM + 512 bit flash ≈ 108 000 GE
Economic impact
The
The
The
The
The
What you ought to know about logic families
A logic family is a collection of digital subfunctions that
• assemble to arbitrary logic, arithmetic and storage functions
• are compatible among themselves electrically
• share a common fabrication technology
Acronym
MOS
FET
BJT
CMOS
static CMOS
dynamic CMOS
TTL
ECL
BiCMOS
Meaning
Metal Oxide Semiconductor.
Field Effect Transistor (n- or p-channel)
Bipolar Junction Transistor (npn or pnp)
Complementary MOS (circuit or technology)
data stored in bistable subcircuits and retained
data stored as electrical charges to be refreshed
Transistor Transistor Logic (BJTs & passive devices)
Emitter-Coupled Logic (non-saturating logic)
CMOS & bipolar devices on a single chip
Economic impact
2-input
nand
gate in
various
technologies
The
The
The
The
The
VDD
VCC
VDD
IN1
OUP
technological
evolution
IN2
OUP
IN1
IN2
IN2
OUP
IN1
b)
VSS
VSS
c)
GND
e)
VCC1
device
VCC2
(NAND)
OUP1
MOSFET
pnp
n-channel
npn
icon
(AND)
OUP2
IN1
approximate voltage-controlled current-controlled
current source
current source
behavior
IN2
depletion
device
variations
bias section
shared with
other gates
g)
BJT
p-channel
device
resistor
diode
icon
VEE
Figure: Static CMOS (c), NMOS (b), early TTL (e), and ECL circuit (g).
Economic impact
The
The
The
The
The
The marketing point of view
“How do functionality and target markets relate to each other?”
General-purpose IC. Examples are either very simple or very generic.
Simple circuit: gates, flip-flops, counters, etc.
Generic functionality: RAMs, ROMs, microcomputers,
FPL, etc.
Economic impact
The
The
The
The
The
The marketing point of view
“How do functionality and target markets relate to each other?”
General-purpose IC. Examples are either very simple or very generic.
Simple circuit: gates, flip-flops, counters, etc.
Generic functionality: RAMs, ROMs, microcomputers,
FPL, etc.
Application-specific integrated circuit (ASIC).
I
I
Application-specific standard product (ASSP):
designed for a specific task and sold to various
customers.
Examples: graphics accelerators, cellular radio chip
sets, smart card chips, etc.
User-specific integrated circuit (USIC):
designed and produced for a single company.
Examples: audio processor for hearing aids, etc.
Economic impact
The
The
The
The
The
A first IC classification scheme
SSI
general
purpose
MSI
LSI
counter
logic
gate
parallel
multiplier
VLSI
computer
interface
ULSI
hardware
complexity
. . . . memory [and still more memory] . . . .
. . . . program-controlled processor . . . .
. . . . field-programmable logic devices . . . .
(before getting programmed)
functionality
applicationspecific
mobile radio spatial diversity
base-band
transceiver
processor
error-correcting
video data
encoder/decoder
compressor
digital
filter
glue logic
. . . . "system on a chip (SoC) " . . . .
Figure: ICs classified as a function of functionality and hardware complexity.
Economic impact
The
The
The
The
The
A first glimpse at VLSI manufacturing
few masks
made to order
for one design
all masks
made to order
for one design
unprocessed
wafer
a)
most masks
shared with
other designs
preprocessed
wafer
b)
Figure: Full-custom (a) and semi-custom (b) masks sets compared.
Economic impact
The
The
The
The
The
Semi-custom fabrication I
preprocessed master
a)
Figure: Prefabricated gate array site.
Economic impact
The
The
The
The
The
Semi-custom fabrication II
+
custom metallization
b)
Figure: Custom contact and metal masks.
Economic impact
The
The
The
The
The
Semi-custom fabrication III
=
customized circuit
not used
not used
c)
Figure: Site customized into a 2-input NAND gate.
Economic impact
The
The
The
The
The
Evolution of semi-custom floorplans
row of prefabricated
gate-array sites
row of prefabricated
transistor pairs
predefined
routing channel
routing channel
only where needed
input/output
pad
utilized devices
unutilized areas
GA
a)
availability
of multiple
metal layers
SOG
b)
Figure: Channeled gate-array (a) versus channelless semi-custom circuits (b).
Economic impact
The
The
The
The
The
I
No dedicated layout structures, no dedicated photomasks.
Customization is via purely electrical means.
I
“Programmable” is a misnomer as there is no instruction sequence
to execute. “Configurable” is more accurate as pre-manufactured
subcircuits are made to form the target circuit.
I
All configuration technologies today have their roots in
semiconductor memory technology.
I
Benefits compared to mask-programmed ASICs:
I
I
Easy and extremely fast to modify (highly agile).
Solutions for testability, I/O subcircuits, clock and power
distribution, embedded memories, etc. all come at no extra effort
shut in the FPL component.
⇒ FPL can be thought as “soft hardware”.
Economic impact
The
The
The
The
The
The fabrication point of view (summary)
“To what extent is a circuit manufactured to user specs?”
Full-custom IC: all fabrication layers, full set of photomasks.
Semi-custom IC (gate array, sea-of-gates, structured ASIC):
a few metal layers only, subset of photomasks.
Field-programmable logic (SPLD, CPLD, FPGA):
customization occurs electrically, no masks involved.
Standard part: catalog part with no customization whatsoever
aka commercial off-the-shelf (COTS) component.
Economic impact
The
The
The
The
The
The design engineer’s point of view
“Which levels of detail are being addressed during a part’s design?”
Hand layout:
Desired geometric shapes manually drawn to scale.
Cell-based design by means of schematic entry:
Manual schematic entry
automatic place & route.
Automatic circuit synthesis:
Manual HDL or SW code writing
generation.
I
I
I
automatic netlist
Logic synthesis
Register transfer level (RTL) synthesis
Architecture or high-level synthesis
Design with virtual components:
Purchase of HDL code
automatic netlist generation.
Economic impact
The
The
The
The
The
Views of a library cell (or of any other subcircuit)
INA
INB
INC
entity nor3 is
generic (
tpd : time := 1.0 ns );
port (
INA, INB, INC : in StdLogic;
OUP : out StdLogic );
end nor3;
OUP
a)
b)
architecture procedural of nor3 is
begin
OUP <= not (INA or INB or INC) after tpd;
end procedural;
c)
stimuli
INA INB
0
0
0
0
1
0
0
1
0
0
1
1
INA INB INC OUP
INA
VDD
INC
0
1
0
0
0
1
responses
OUP
1
0
0
0
1
0
INA INB INC OUP
VDD
VDD
VDD
INB
INC
OUP
VSS
d)
e)
VSS
INA INB INC OUP
VSS
f)
VSS
INA INB INC OUP
Figure:
Icon (a), simulation model (b), test vector set (c), transistor-level
schematic (d), detailed layout (e), and cell abstract (f).
Economic impact
The
The
The
The
The
Typical cell mix in a full-custom IC
F1
A
F1
B
F1
C
F1
D
F2
A
F2
B
megacell
megacell
macrocell
F2
C
macrocell
F2
D
F3
D
standard cell row
with over-the-cell routing
std
cell
std std
cell cell
F3
C
std std
cell cell
megacell
F3
B
megacell
F3
A
CLK
RST
F4
A
F4
B
F4
C
F4
D
Economic impact
The
The
The
The
The
Automatic circuit synthesis I
Logic synthesis accepts logic equations, truth tables, and state graphs.
Generates gate-level netlists for combinational logic and
for finite state machines (FSM).
⇒ Absorbed in today’s EDA flows.
Register transfer level (RTL) modelling:
I
I
Circuit viewed as a network of storage elements
— registers and possibly also RAMs — that are held
together by combinational building blocks.
Behavioral specifications allowed to include arithmetic
functions, string operations, arrays, enumerated
types, and other more powerful constructs.
⇒ Introduced in the early 1990s, universally adopted.
Parametrized and portable designs favor reuse.
Economic impact
The
The
The
The
The
Automatic circuit synthesis II
architecture procedural of patternmatch is
signal PREST : Std_Logic_Vector(0 to 5);
begin
ROM
w
w
allbits : for i in 1 to 5 generate
process (CLK,CLR) is
begin
if CLR=’1’ then
PREST(i) <= ’0’;
elsif CLK’event and CLK=’1’ then
PREST(i) <= PREST(i-1);
end if;
end process;
end generate;
v
+1
*
+|-|0
PREST(0) <= INP;
OUP <= true when PREST(1 to 5)="11011"
else false;
2w+3
end architecture procedural;
b)
a)
CLK
CLR
CLK
CLR
CLK
CLR
CLK
CLR
CLK
CLR
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
c)
Figure: RTL diagram (a), RTL synthesis model (b), and gate-level schematic
(c) (simplified, note that (a) and (b) refer to different circuits).
Economic impact
The
The
The
The
The
Automatic circuit synthesis III
Architecture synthesis starts from a purely behavioral data processing
algorithm. Source code includes no explicit indications for
how to marshal data processing operations and hardware
resources. Works in five major phases:
1. Identify the computational and storage requirements.
2. From a virtual library, select a suitable building block for each kind
of processing and storage operation.
3. Establish a cycle-based schedule for carrying out the algorithm.
4. Decide on a hardware organization able to execute the resulting
work plan.
5. Keeping track of data moves and operations for each clock cycle,
translate into the necessary instructions for RTL synthesis.
⇒ Does not always yield optimal results, active field of research.
Economic impact
The
The
The
The
The
Virtual components
VCs (aka intellectual property modules or cores) are HDL
synthesis packages made available to others on a
commercial basis:
I
I
I
I
Vendor develops a major function into a synthesis model for sale.
Licensee buys VC, incorporates it into his design, then carries out
all the rest, i.e. synthesis, place and route (P&R), and overall
verification.
VCs are portable across fabrication technologies (soft modules),
standard/macro/megacells are process-specific (hard modules).
Most VCs implement fairly common subfunctions,
parametrization is sought to cover more applications.
Economic impact
The
The
The
The
The
Virtual components
VCs (aka intellectual property modules or cores) are HDL
synthesis packages made available to others on a
commercial basis:
I
I
I
I
I
Vendor develops a major function into a synthesis model for sale.
Licensee buys VC, incorporates it into his design, then carries out
all the rest, i.e. synthesis, place and route (P&R), and overall
verification.
VCs are portable across fabrication technologies (soft modules),
standard/macro/megacells are process-specific (hard modules).
Most VCs implement fairly common subfunctions,
parametrization is sought to cover more applications.
Examples: processor cores, all sorts of filters, audio and/or video
en/decoders, cipher functions, error correction en/decoders, USB,
FireWire, and other interfaces.
⇒ VCs have given rise to a new industry since the late 1990s.
Economic impact
The
The
The
The
The
A second IC classification scheme
Fabricat.
depth
Design
level
Product
name
Electrical
Semi-custom
Full-custom
configuration
fabrication
fabrication
Cell-based as obtained from
Hand layout
◦ synthesis with VCs in HDL form,
◦ synthesis from captive HDL code,
◦ schematic entry, or a mix of these
FieldGate-array,
Std. cell Full-custom
programmable
sea-of-gates,
IC
IC
logic device
or structured
(FPGA, CPLD)
ASIC
IC families as a function of fabrication depth and design abstraction level.
Economic impact
The
The
The
The
The
Electronic system-level (ESL) design automation
Pressure towards better design productivity has incited the industry to
look at design automation from a wider perspective.
I
Correct-by-construction methodology by supporting progressive
refinement starting with a virtual prototype
I
Explore the architectural solution space more systematically and
more rapidly than with RTL synthesis methods.
I
Make it possible to start software development before hardware
design is completed.
I
Improve the coverage and efficiency of functional verification by
dealing with system-level transactions and by taking advantage of
formal verification.
Economic impact
The
The
The
The
The
Players in semiconductor markets I
Our final question relates to business.
“How are the industrial activities shared between business partners?”
Traditional business model:
Integrated device manufacturer (IDM): a chip vendor who operates his
own wafer processing facilities.
Examples: Intel, Toshiba, Samsung, ST-Microelectronics,
IBM semiconductors, austriamicrosystems, etc.
Economic impact
The
The
The
The
The
Players in semiconductor markets II
More recent business models support more narrow specialization:
Silicon foundry: a company that operates a wafer processing line and
that offers its manufacturing services to others.
Examples: TSMC, UMC, etc.
Fabless chip vendor: develops and markets proprietary semiconductor
components but has their manufacturing commissioned to
an independent silicon foundry.
Examples: Altera and Xilinx (FPL), Broadcom
(networking), Cirrus Logic/Crystal (audio and video chips),
Nvidia (graphics chips), Ramtron (non-volatile memories).
Fab-lite chip vendor: retains just the limited and specialized
manufacturing capabilities to integrate sensors, actuators,
RF components, or photonic devices, in a silicon substrate
along with electronic circuitry.
Examples: Sensirion, Luxtera.
Economic impact
The
The
The
The
The
Players in semiconductor markets III
Virtual component vendor: a company that develops synthesis packages
and licenses them to others for incorporation into their
own ICs.
Examples: ARM, Sci-worx, Synopsys (former InSilicon).
System house: a company that integrates both hardware and software
into their products. Hardware is based on microprocessors,
memories, ASSPs and FPGAs. USICs are being designed
iff they provide a competitive advantage.
Examples: Apple (media players), Cisco (network
equipment), Landis+Gyr (energy meters), Valeo
(automotive).
Many small and medium-sized electronics companies (typical for Europe)
operate as system houses.
Economic impact
The
The
The
The
The
What has made these new business models possible?
Three factors came together to make fabless operation possible:
I
Generous integration densities at low costs.
I
Proliferation of high-performance engineering workstations and EDA
software
I
Availability of know-how in VLSI design outside IC manufacturing
companies (this course).
Economic impact
The Y-chart, a map of digital electronic systems
Major stages in VLSI design
Cell libraries
The Y-chart
system
levels of abstraction
architecture
behavioral
perspective
start
register transfer
structural
perspective
top blocks
and I/O
logic (aka gate-level)
subtasks
subblocks
data moves
ALUs, registers, memories
and operations
electrical
gates, latches, flip-flops
truth tables,
state graphs
transfer
transistors, wires
functions
algorithm
goal
behavioral
perspective
front-end
design
back-end
design
mask polygons,
detailed layout
standard cells,
macro cells
physical
perspective
placement
and routing
floorplan,
partitioning
chip or board
physical
perspective
structural
perspective
Economic impact
Cell libraries
More design views
b)
a)
architecture seriesexpansion of cosine is
begin
process (theta) is
variable sum, term : real;
variable n : natural;
begin
sum := 1.0;
term := 1.0;
n := 0;
while abs term > abs (sum / 1.0E6) loop
n := n+2;
term := (-term)*theta**2 / real(((n-1)*n));
sum <= sum+term;
end loop;
result <= sum;
end process;
end architecture seriesexpansion;
c)
path
metric
memory
I
Uoup
A
B
C
d)
addcompareselect
units
trellis
trace
back
unit
local
controller
local
controller
local
controller
supervisory
controller
Uinp
e)
survivor
memory
branch
metric
comput.
unit
data dependency graph
(models transformatorial behavior)
state graph
(models reactive behavior)
path
metric
memory
II
f)
Figure: Floorplan (a), software model (b), encapsulated chip (c), graphical
formalisms (d), transfer characteristic (e), and block diagram (f) (simplified).
Economic impact
Cell libraries
Electronic system-level design flow
from marketing
and customers
• exploration,
• fast prototyping, and
• validation
of algorithms and
system architectures
system
specifications
algorithms and
system architecture design
system -level design
implies addressing a subset
of the issues shown here
data networks,
congestions,
traffic, queues
is there any broadly accepted
formalism for specification?
UML may provide a workable solution
abstract mathematical models
subject to successive refinement
ciphering,
key distribution,
authentication
source coding,
data
compression
effects from
finite word sizes,
scaling
synchronization,
clock recovery
error correction
coding,
modulation
filter synthesis,
filtering,
correlation
collection of algorithms
along with data formats
bit-true
HDL model
protocols,
user interfaces
over a single consistent data base?
ASIC or programmable IC
HDL generator
for hardware
synthesis
ressource and/or
instruction set
planning
control flow,
cooperat. finite
state machines
code generator
for signal- or
microprocessor
machine code
to processor
behavioral
modelling and
simulation
is there an agreed-on
system-level design
language (SLDL)?
SystemC may provide an answer
program-controlled processor
- interactive resource allocation
- automatic scheduling
- automatic binding
- translation to RTL model
truly portable and amenable
to synthesis with good results?
model libraries
for various
subfunctions
Economic impact
Cell libraries
System-level design
Decisions taken at this stage determine the final outcome more than
anything else:
I
Specify the functionality and characteristics of the system to be
I
Partition the system’s functionality into subtasks
I
Explore alternative hardware and software tradeoffs
I
Decide on make or buy for all major building blocks
I
Decide on interfaces and protocols for data exchange
I
Decide on data formats, operating modes, exception handling, etc.
I
Define, model, evaluate and refine the various subtasks
Result: System-level model.
Economic impact
Cell libraries
Algorithm design
Streamline computations in view of their implementation in hardware:
I
Cut down computational burden and memory requirements
I
Find compromises between computational complexity and accuracy
I
Contain effects due to finite word-length computation
I
Decide on number representation schemes
I
Evaluate alternatives and selecting the one best suited
I
Quantify the minimum required computational resources
Result: Bit-true software model.
Economic impact
Cell libraries
Digital VLSI design flow (front-end)
from system-level development
specifications
high-level synthesis
HDL synthesis
autom. test insertion
front end design
behavioral
modelling
overall behavioral simulation
inp. to outp. mapping
software model
(algorithm with
data formats)
architecture
design
block-level behavioral simul.
transaction-based
preliminary
timing
estimation
estimation of die
size and major
cost factors
preliminary
power
estimation
high-level
block diagram
[or HDL code]
RTL design
incl. macrocell
preparation
floorplanning,
package selection
and pinout
register transfer
level simulation
cycle-true
code of regs and
arith./logic ops
[or schematics]
logic design and
optimization
gate-level
simulation
event-driven
pre-layout
timing
verification
gate-level
netlist (1)
insertion of
test structures
electrical
rule check
(ERC)
delay
calculation
cell and wire delays
formal
equivalence
check
test vector
generation
fault
grading
gate-level
netlist (2)
floorplan
Economic impact
Cell libraries
Architecture design I
Take important high-level decisions:
I
Partition a computational task in view of a hardware realization.
I
Organize the interplay of the various subtasks.
I
Allocate hardware resources to each subtask (allocation).
I
Define datapaths and controllers.
I
Decide between off-chip RAMs, on-chip RAMs and registers.
I
Decide on communication topologies and protocols (parallel, serial).
I
Define how much parallelism to provide in hardware.
I
Decide where to opt for pipelining and to what degree.
I
Decide on a circuit style and fabrication process.
I
Get a first estimate of the circuit’s size and cost.
Results: High-level block diagram and preliminary floorplan.
Economic impact
Cell libraries
Architecture design II
Work out lower-levels details of an architecture by deciding:
I
How to implement arithmetic and logic units?
I
Whether to use hardwired logic or microcode for a controller?
I
When to use a ROM rather than random logic?
I
What operations to perform during which clock cycle (scheduling)?
I
What operations to carry out on which processing unit (binding)?
I
What clocking discipline to adopt?
I
What time interval to use as the basic clock period?
I
Where to prefer a bidirectional bus over two unidirectional ones?
I
By what test strategy to ensure testability?
I
How to initialize the circuit?
Results: Set of more detailed diagrams and verified RTL code.
Economic impact
Cell libraries
gate-level
netlist (2)
Digital
VLSI
design flow
(back-end)
floorplan
padframe constr.,
power distribution,
initial placement
drawing of
bonding diagram
largely automated physical design tools
back end design
preliminary
cell placement
reoptimization
and rebuffering
of logic
formal
equivalence
check
bonding
diagram
placement and
gate netlist (3)
clock tree
insertion
placement and
gate netlist (4)
post-layout
timing
verification
post-layout
logic simulation
detailed
routing
event-driven
cell and wire
delays
delay
calculation
back-annotated
gate-level netlist
preliminary
abstract layout
rebuffering,
hold time fixing,
and rerouting
chip abstract layout
automatic layout merge
to IC packaging
final
gate-level
netlist (5)
substitution of
detailed layout
for cell abstracts
chip detailed layout
layout/design
rule check
(DRC)
extraction of
cell abstracts
and interconnect
signal integrity
analysis
power grid
analysis
DRC and/or
manufacturability
analysis
extraction of
devices and
interconnect
layout versus
schematic
(LVS)
substitution of
detailed circuits
for cell icons
back-annotated
transistor-level netlist
to IC manufacturing
layout versus
schematic
(LVS)
 hk 2.07.07
Economic impact
Cell libraries
Physical design
Steps
I
Floorplanning (begins during front-end design)
I
Padframe generation and power distribution
I
Intial placement of cells
I
Reoptimization and rebuffering
I
Clock tree insertion
I
Detailed routing
I
Rebuffering and hold time fixing
I
Chip assembly (global routing)
I
Substitution of detailed layout for cell abstracts
Result: Polygon layout data for mask preparation (GDS II).
Economic impact
Cell libraries
Physical design verification
Prior to fabrication, all layout data need to be checked to protect against
fatal mishaps. The set of instruments available includes:
I
Check conformity of layout with geometric rules (DRC)
I
Search for patterns likely to be detrimental to yield
I
Layout extraction [re-]obtains the actual circuit netlist
I
Layout-versus-schematic (LVS)
I
Post-layout timing verification
I
Post-layout simulation
Result: Either proof of geometric integrity or error list.
Economic impact
Cell libraries
The leitmotiv of VLSI design
I
Any design flaw found after tapeout or, even worse, after prototype
fabrication wastes important amounts of time and money.
Economic impact
Cell libraries
The leitmotiv of VLSI design
I
Any design flaw found after tapeout or, even worse, after prototype
fabrication wastes important amounts of time and money.
I
Redesigns are so devastating that the entire semiconductor industry
is committed to “first-time-right” design as a guiding principle.
I
VLSI engineers typically spend much more time verifying a circuit
than actually designing it.
Economic impact
Cell libraries
Cell libraries I
list of leaf cells to be
library development
purchase of cell library
behavioral
modelling
leaf cell
functional models
circuit
simulation
transistor level
design
continuous time
layout versus
schematic
(LVS)
transistor-level
schematics
transistor-level netlists
with layout parasitics
DRC and/or
manufacturability
analysis
layout design
at detail level
circuit
extraction
cell
characterization
leaf cell
timing models
leaf cell layouts
 hk 18.4.02
construction verification
behavioral aspects
flow of design data
structural aspects
corrective action by designer
based on feedback information
physical aspects
design automation shortcuts
Figure: Library design flow.
target cell library
and/or process data
directly contribute
to design decisions
Economic impact
Cell libraries
Cell libraries II
The views required for each cell in a library include:
I
Datasheet with functional, electrical and timing specs.
I
Graphical icon or symbol.
I
Accurate behavioral models for simulation and timing analysis.
I
Set of simulation and test vectors.
I
Transistor-level netlist or schematic.
I
Detailed layout.
I
Simplified layout showing only cell outline and connector locations
(known as cell abstract, floorplanning abstract, or phantom cell).
Economic impact
Cell libraries
Cell libraries III
I
Designing, characterizing, documenting, and maintaining a cell
library is a considerable effort.
I
To protect their investments, library vendors are not willing
to disclose how their cells are constructed internally.
I
Vendors thus supply only cell abstracts.
I
Detailed layouts are to be substituted for all abstracts
by the vendor before mask preparation can begin.
Economic impact
Configuration technologies
Organization of hardware resources
Commercial products
Design flow
Field-programmable logic (FPL) configuration technologies
static memory cell
control gate
(used for programming only)
floating gate
(acting as charge trap)
metal
electronic
switch
source
metal
thin dielectric layer
(to be ruptured or not
during programming)
narrow constriction
(to be blown or not
during programming)
metal
drain
layout view
cross section
metal
base material
cross section
a)
b)
c)
d)
Figure: Configuration storage is adapted from semiconductor memories.
◦ SRAM: Switch steered by static memory cell (a),
◦ Flash: MOSFET controlled by trapped charge (b),
◦ PROM: fuse (c) and antifuse (d).
Economic impact
Commercial products
Design flow
Field-programmable logic (FPL) configuration technologies
(continued)
Configuration
technology
SRAM
UV-erasable
EPROM
Electr. erasable
EEPROM
Flash memory
Antifuse PROM
Ideal
Non
volatile
no
yes
Live at
power
up
no
yes
yes
yes
yes
yes
yes
yes
Reconfigurable
in ckt
out of
circuit
in ckt
no
in ckt
Unlimit.
endurance
yes
no
Area
occupation
per link
large
small
in array
no
no
n.a.
yes
2·EPROM
≈EPROM
small
zero
Extra
fabr.
steps
0
3
>5
3
0
Economic impact
Commercial products
Design flow
Unlimited reprogrammability has its drawback
I
Storing the FPL configuration is an SRAM-type memory implies that
the configuration gets lost whenever the circuit is powered down.
I
The problem is solved in one of three possible ways:
(a) by reading from a dedicated off-chip ROM (bit-serial or bit-parallel),
(b) by downloading a bit stream from a host computer, or
(c) by long-term battery backup.
Economic impact
Commercial products
Design flow
Complex programmable logic devices (CPLD)
outputs
equivalent to
one SPLD
technological
evolution
AND
plane
programmable
logic
flip-flops & feedback
programmable
feedback
inputs
b)
SPLD
programmable
interconnect
technological
evolution
OR
plane
flip-flops & feedback
inputs
PLA
configurable
I/O cell
programmable
logic
OR
plane
OR
plane
AND
plane
a)
AND
plane
outputs
c)
CPLD
Figure: General architecture of CPLDs (c) along with precursors (a,b).
Economic impact
Commercial products
Design flow
Field-programmable logic devices (FPGA)
Overall organization patterned after mask-programmed gate-arrays.
config.
logic
cell
wires
configurable
I/O cell
conf.
wires switch
box
FPGA
Figure: General architecture of FPGAs.
Economic impact
Commercial products
Design flow
Fine-grained FPGAs
A few logic gates and/or one bistable per configurable logic cell.
Actel logic tile
subcircuits
controlled by
configuration bits
INP1
OUP1
to local routing
INP2
may serve
as clock
OUP2
to long routing
INP3
may serve
as reset
a)
Figure: Example: logic tile from Actel ProASIC.
Economic impact
Coarse-grained FPGAs
Commercial products
Design flow
Xilinx slice
YB
FXINA
FXINB
FX
YMUX
G4
G3
G2
Y
config.
LUT
SR
REV
ENA
CLK
G1
Combinational
functions of
four or more
variables,
or
D
Q
YQ
BY
XB
F5
two or more
bits stored per
configurable
logic cell.
XMUX
F4
F3
F2
X
config.
LUT
SR
REV
ENA
CLK
F1
or
D
Q
XQ
BX
CE
CLK
SR
b)
CIN
Figure: Example: logic slice from Xilinx Virtex-4 (4-input LUTs, 2 bistables).
Economic impact
Commercial products
Design flow
There is a general trend towards coarser granularities
Figure: LUT granularity trade-offs at the 65 nm technology node.
I
The optimum trade-off for LUTs has shifted from 4 to 6 inputs
over the last couple of process generations.
Economic impact
Commercial products
Design flow
Example I:
Logic slice
from Xilinx
Virtex-5
Economic impact
Commercial products
Design flow
Example II: Adaptive logic module from Altera Stratix II
Economic impact
Commercial products
Design flow
Commercial products
configuration
technology
static
memory
(SRAM)
UV-erasable
(EPROM)
electrically
erasable
(flash)
antifuse
(PROM)
overall organization of hardware resources
CPLD
FPGA
coarse grained
fine grained
Xilinx Spartan, Virtex.
Atmel AT6000,
Lattice SC, EC, ECP.
AT40K.
Altera FLEX, APEX,
Stratix, Cyclone.
eASIC Nextreme SL
Cypress MAX340
(discontinued)
Xilinx XC9500,
Lattice XP
Actel ProASIC
CoolRunner-II.
MACH XO.
ProASICPLUS ,
Altera MAX3000, 7000.
Fusion
Lattice MACH 1,...,5.
Igloo.
Cypress Delta39K,
Ultra37000.
QuickLogic Eclipse II,
Actel MX,
PolarPro.
Axcelerator AX.
Economic impact
Commercial products
Design flow
Watch out!
Capacity figures of FPL and of semi-custom ICs may be confusing.
Manufactured gates: Total number of GEs physically present on a die.
Usable gates: Maximum number of GEs that are usable under typical or
best case conditions. The exact percentage depends on
the application, advertisements tend to exaggerate.
Actual gates: GEs that are indeed put to service by a given design,
corresponds to the GEs for a cell-based full-custom IC.
GEmanufactured > GEusable > GEactual
Economic impact
Commercial products
Design flow
Watch out!
Capacity figures of FPL and of semi-custom ICs may be confusing.
Manufactured gates: Total number of GEs physically present on a die.
Usable gates: Maximum number of GEs that are usable under typical or
best case conditions. The exact percentage depends on
the application, advertisements tend to exaggerate.
Actual gates: GEs that are indeed put to service by a given design,
corresponds to the GEs for a cell-based full-custom IC.
GEmanufactured > GEusable > GEactual
⇒ Carry out benchmarks with representative designs as this helps to
I
make better cost calculations,
I
obtain realistic timing figures,
I
avoid misguided choices.
Economic impact
Commercial products
Design flow
Some FPGAs also include wide datapath units (MAC)
Figure: Example: DSP48E slice from Xilinx Virtex-5.
Economic impact
Commercial products
Design flow
Further extensions
Many commercial parts include field-programmable logic plus
I
hardwired SRAMs, FIFOs, clock recovery circuits, etc.
I
hardwired microprocessor and DSP cores (e.g. PowerPC, ARM),
I
hardwired standard interface circuits
(PCI, USB, FireWire, Ethernet, WLAN, JTAG, LVDS, etc.)
I
hardwired analog-to-digital and digital-to-analog converters,
I
configurable analog building blocks (such as filters, for instance),
I
field-programmable analog arrays (FPAA)
built from OpAmps, capacitors, resistors and switchcap elements,
I
combinations of the above.
Economic impact
Commercial products
Design flow
FPL design flow
I
Front-end flow (architecture design, HDL coding, functional
verification) is much the same for FPGAs and CPLDs as for ASICs.
I
Back-end flow differs to some extent.
1. Netlist obtained from HDL synthesis is mapped onto
configurable blocks available in the target device.
2. Interconnect gets implemented using the wires, switches and
drivers available.
3. Result is converted into a configuration bit stream for download
into the FPL device.
4. FPL vendors make available proprietary tools for the above
procedure.
Economic impact
Commercial products
Design flow
FPL design flow
I
Front-end flow (architecture design, HDL coding, functional
verification) is much the same for FPGAs and CPLDs as for ASICs.
I
Back-end flow differs to some extent.
1. Netlist obtained from HDL synthesis is mapped onto
configurable blocks available in the target device.
2. Interconnect gets implemented using the wires, switches and
drivers available.
3. Result is converted into a configuration bit stream for download
into the FPL device.
4. FPL vendors make available proprietary tools for the above
procedure.
⇒ Hierarchy of required skills:
Field-programmable logic ⊂ Semi-custom ICs ⊂ Full-custom ICs.
Let us begin with topics that matter independently of fabrication depth.
Economic impact
Major semiconductor technologies and logic families
The alphabet soup explained.
Acronym
MOS
FET
BJT
NMOS
PMOS
CMOS
static CMOS
dynamic CMOS
TTL
ECL
BiCMOS
Meaning
Metal Oxide Semiconductor.
Field Effect Transistor (n- or p-channel)
Bipolar Junction Transistor (npn or pnp)
n-channel MOS (transistor, circuit or technology)
p-channel MOS (transistor, circuit or technology)
Complementary MOS (circuit or technology)
data stored in bistable subcircuits and retained
data stored as electrical charges to be refreshed
Transistor Transistor Logic (BJTs & passive devices)
Emitter-Coupled Logic (non-saturating logic)
CMOS & bipolar devices on a single chip
Economic impact
2-input nand gate in TTL technology
TTL invented 1961 as an improvement over DTL and RTL.
VCC
IN1
OUP
IN2
d)
VCC
IN1
technological
evolution
OUP
IN2
IN1
IN2
e)
OUP
GND
GND
f)
Figure: Icon (d), original multi-emitter circuit (e), and more recent F generation
circuit (f). The auxiliary devices serve clamping and speed-up purposes.
Economic impact
2-input nand gate in ECL technology
ECL invented 1956 as fast non-saturating current switching logic.
VCC1
device
MOSFET
BJT
VCC2
p-channel
pnp
n-channel
npn
icon
(NAND)
OUP1
(AND)
OUP2
IN1
approx. voltage-controlled current-controlled
current source
current source
behavior
IN2
depletion
device
variations
bias section
shared with
other gates
g)
device
resistor
diode
icon
VEE
Figure: Circuit (g) with schematic symbols used.
Switching is by current steering without transistors entering saturation.
Schottky
device
varicap
Economic impact
2-input nand gate in MOS technologies
CMOS invented 1963 as an improvement over NMOS and PMOS
with (close-to) zero quiescent power.
VDD
VDD
VDD
IN1
IN1
OUP
IN2
OUP
IN2
technological
evolution
OUP
IN2
IN1
a)
VSS
b)
VSS
c)
VSS
Figure: PMOS (a), NMOS (b), and static CMOS (c) circuits.
Economic impact
Why does CMOS technology dominate VLSI today?
As first observed in 1972 by Robert Dennard
I
Geometric down-scaling benefits
I
I
I
I
I
layout density,
operating speed,
energy efficiency, and
manufacturing costs per function.
Simplicity and comparatively low power dissipation have allowed
for integration densities not possible on the basis of BJTs.
⇒ After a start as a low-power but slow circuit alternative, CMOS
has gradually displaced competing technologies and logic families.

Introduction to Microelectronics

Transcription

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