dockrm-3k5-carrier_ds_1_0 - Knowledge Resources GmbH, Switzerland
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krm-3k5-carrier_ds_1_0 - Knowledge Resources GmbH, Switzerland
KRM-3500-CARRIER Data sheet Knowledge Resources GmbH Uhlandstrasse 10 CH – 4053 Basel Switzerland www.knowres.com Table of Contents Revision History....................................................................................................................................................... 3 Disclaimer................................................................................................................................................................ 3 Assumptions ............................................................................................................................................................ 4 Acronyms ................................................................................................................................................................ 4 Reference documents ............................................................................................................................................. 4 Introduction ............................................................................................................................................................ 5 Board dimensions ................................................................................................................................................... 6 Features .................................................................................................................................................................. 7 Overview ............................................................................................................................................................. 7 Power supply and power considerations............................................................................................................ 8 Reset ................................................................................................................................................................... 8 MIO Peripherals .................................................................................................................................................. 9 Ethernet .......................................................................................................................................................... 9 USB ................................................................................................................................................................ 10 USB HUB ........................................................................................................................................................ 11 USER LED ....................................................................................................................................................... 12 SD .................................................................................................................................................................. 13 UART to USB Bridge....................................................................................................................................... 14 PL IO .................................................................................................................................................................. 15 PL BANK X1_1 ................................................................................................................................................ 16 PL BANK X1_2 ................................................................................................................................................ 17 PL BANK X2_1 ................................................................................................................................................ 18 PL BANK X2_2 ................................................................................................................................................ 19 MGT IO .............................................................................................................................................................. 20 Thermal specification ............................................................................................................................................ 21 KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 2 of 21 Revision History Document revision Date HW revision Changes th 0.1 REV A First draft th 1.0 REV A Edits to first public release Oct.21 2014 Feb 18 2015 Disclaimer Copyright © Knowledge Resources GmbH. All rights reserved. All provided data is for information purposes only and not guaranteed for legal purposes. Information has been carefully checked and is believed to be accurate; However, no responsibility is assumed for inaccuracies. Specifications are subject to change without notice. Trademark Acknowledgement: Brand and product names are trademarks or registered trademarks of their respective owners. KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 3 of 21 Assumptions The reader is familiar with Xilinx FPGA and SoC components and the related terminology in common use. Acronyms FOM: FU: KR: MIG: MGT: NA: PL: PS: SoC: FPGA on Module Future Use Knowledge Resources GmbH Memory Interface Generator, a tool of Xilinx to easily implement a DDR3 controller Multi Gigabit Transceiver Not Applicable Programmable Logic Processing Subsystem System on Chip Reference documents ZYNQ all programmable SoC, Xilinx, www.xilinx.com i MARVELL Ethernet PHY : http://www.marvell.com/transceivers/fast-ethernet-phy/ SMSC USB PHY: http://ww1.microchip.com/downloads/en/DeviceDoc/3320.pdf Sil UART to USB: http://www.silabs.com/products/interface/usbtouart/Pages/usb-to-uart-bridge.aspx ENPIRION Regulator: http://www.enpirion.com/products-dcdc-converter-step-down-buck-12v-en2340qi.htm LANSING enclosure: http://www.lansing-enclosures.com/main/micropak/c-style/index.html Tektronix P6960: http://www.tek.com/datasheet/logic-probe-tektronix-logic-analyzer-probes-2 i Marvell requires registration and NDA on order to grant access to the datasheet KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 4 of 21 Introduction With the KRM-3500-CARRIER, KR provides a highly flexible and cost-efficient evaluation board for embedded systems prototyping with KRM3k family modules. The carrier board offers all of the essential infrastructure elements that are required to operate a KRM-3k family module. Furthermore, the PL ports are readily accessible via 50 pin expansion connectors and 2.54mm sockets. The carrier has a Euro-card form factor of 100x160mm and fits into a Lansing “micropack c-style” Enclosure, thereby facilitating the fabrication of complete small run projects without significant investments into custom Enclosures. X2 GbE ZIFF 50 ZIFF 50 PL USER LED PL 4xUSB HUB UART USB BRIDG E MIO1 MICRO SD JTAG 1V8 3V3 KRM3k MODULE PWR CONTRO L PL HR PL HR MGT PL HR FX10A-168P 5V0 2.54mm FIELD 2.54mm FIELD PWR IN ZIFF 50 KRM-3500-CARRIER Data sheet Document Rev. 1.0 ZIFF 50 February 18, 2015 Page 5 of 21 Board dimensions (in mm) - Altium PCB and Schematic templates are available KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 6 of 21 Features Overview Accepts KRM3k series modules Dual UART to USB bridge 1 x Micro SD Slot 4 x USB port (via 4 port hub) 1 x Gb Ethernet Port 4 x 50Pin Ziff Headers (one per PL Bank) 2 groups of 2.54mm sockets (two banks of PL) supporting PMODS User LED (RGB) with light pipes to rear panel KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 7 of 21 Power supply and power considerations -The KRM-3000-CARRIER is designed to accept 12V DC. In order to fully support the range of modules and daughter cards that can be paired with the KRM-3000-CARRIER a 12V power supply able to source at least 4A is recommended. The KRM-3000-CARRIER generates three “global” Voltages: 5V, 3V3 and 1V8. Each is capable of sourcing up to 6A. The inputs of the regulators are globally fused; the power OK signals are used to activate power good indicators. The 3V3 Supply powers the KRM-3K Module and several I/O peripheral circuits (such as the UART to USB bridge and SD card socket) the 3V3 supply may also be selected as a bank I/O supply voltage for each of the modules four PL I/O banks. The 1V8 supply powers a multitude of peripherals such as the USB Phy, Ethernet Phy, and parts of the SD card interface chip. 1V8 supply may also be selected as a bank I/O supply voltage for each of the modules four PL I/O banks. Reset The KRM-3k modules generate their own on board power on reset. A user reset button for the PS of the Zync on a KRM-3k module is available. The reset signal is also routed to the JTAG connector therefore enabling full debug support for the ARM cores. KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 8 of 21 MIO Peripherals Ethernet The Ethernet port is implemented with a Marvell 88E116R, a full resistor field to configure any possible setting of the mode pins, and a low profile Belfuse Mag Jack L829-1J1T-43. The resistor field is populated to put the Phy on Address 01011, and delayed RX/TX clocks. These settings are supported by the Linux BSP that KR provides for the evaluation carrier. The Primary power supply is sourced from 1V8 Global, the 1V2 core Voltage is generated by the PHY’s internal LDO. Ethernet Schematic: Ethernet Signal Table: ETH PIN GROUP Signal name X2_163 X2_164 X2_159 X2_122 X2_127 X2_128 X2_123 X2_124 X2_121 X2_130 X2_133 X2_134 X2_131 X2_132 X2_129 MIO_53 MIO_52 MIO_49 MIO_16 MIO_21 MIO_20 MIO_19 MIO_18 MIO_17 MIO_22 MIO_27 MIO_26 MIO_25 MIO_24 MIO_23 ETH_PHY_MDIO ETH_PHY_MDC ETH_PHY_RESETn ETH_TX_CLK ETH_TX_CTRL ETH_TX_D3 ETH_TX_D2 ETH_TX_D1 ETH_TX_D0 ETH_RX_CLK ETH_RX_CTRL ETH_RX_D3 ETH_RX_D2 ETH_RX_D1 ETH_RX_D0 KRM-3500-CARRIER Data sheet Document Rev. 1.0 Direction FPGA MDIO FPGA => MDIO FPGA => MDIO FPGA <= MDIO FPGA <= MDIO FPGA => MDIO FPGA => MDIO FPGA => MDIO FPGA => MDIO FPGA <= MDIO FPGA => MDIO FPGA <= MDIO FPGA <= MDIO FPGA <= MDIO FPGA <= MDIO Remark Pull up on Carrier Pull up on Carrier I/O Level 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 February 18, 2015 Page 9 of 21 USB The USB interface is implemented with a ULPI connected USB3320C USB PHY chip from SMSC (now Microchip). R906 forces the port into Host mode. A downstream hub expands the USB connectivity to 4 ports. USB Schematic: USB Signal Table: USB PIN XZ2 MIO X2_160 X2_146 X2_139 X2_142 X2_141 X2_144 X2_143 X2_136 X2_145 X2_148 X2_147 X2_140 X2_135 MIO_48 MIO_36 MIO_31 MIO_32 MIO_33 MIO_34 MIO_35 MIO_28 MIO_37 MIO_38 MIO_39 MIO_30 MIO_29 KRM-3500-CARRIER Data sheet Document Rev. 1.0 Signal name ZYNQ_USB_RST_n ZYNQ_USB_CLK ZYNQ_USB_NXT ZYNQ_USB_D0 ZYNQ_USB_D1 ZYNQ_USB_D2 ZYNQ_USB_D3 ZYNQ_USB_D4 ZYNQ_USB_D5 ZYNQ_USB_D6 ZYNQ_USB_D7 ZYNQ_USB_STP ZYNQ_USB_DIR Direction FPGA => USB FPGA <= USB FPGA => USB FPGA <=> USB FPGA <=> USB FPGA <=> USB FPGA <=> USB FPGA <=> USB FPGA <=> USB FPGA <=> USB FPGA <=> USB FPGA => USB FPGA => USB Remark Pull up on Carrier I/O Level 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 February 18, 2015 Page 10 of 21 USB HUB The USB Hub expands the USB port to four interfaces, implemented with standard stacked type A connectors. The 4 USB ports support the easy connection of Keyboard, Mouse, Wifi and a USB drive when the host Module is running Linux. USB HUB Schematic: KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 11 of 21 USER LED The 3 RGB LED are used to indicate an over current event on the USB ports (LED 954 R and 956 R) or are available as User LED on a range of Signals on X2 of the SoC module. USER LED Schematic: USER LED Signal Table: USER LED PIN X2 BANK X2_83 X2_81 X2_79 X2_77 X2_75 X2_73 X2_71 X2_2 X2_2 X2_2 X2_2 X2_2 X2_2 X2_2 KRM-3500-CARRIER Data sheet Document Rev. 1.0 Signal name X2_2_300 X2_2_301 X2_2_302 X2_2_303 X2_2_304 X2_2_305 X2_2_306 Direction FPGA => USER LED FPGA => USER LED FPGA => USER LED FPGA => USER LED FPGA => USER LED FPGA => USER LED FPGA => USER LED Remark I/O Level Red Green Blue Green Blue Green Blue 1V8 1V8 1V8 1V8 1V8 1V8 1V8 February 18, 2015 Page 12 of 21 SD The SD card interface is implemented with a simple buffer, the TXS02612 from TI. While this chip supports the attachment of up to two SD card connectors and a card select pin, only one micro SD card slot is physically implemented and the select pin is tied to low with a 0R resistor. Since the micro SD card does not support a Write protect flag, the write protect function is implemented as a resistor solder option on the carrier. WP is off by default but can be set by moving a resistor. SD Schematic: SD Signal Table: SD PIN XZ2 MIO Signal name Direction X2_152 X2_151 X2_156 X2_155 X2_149 X2_150 X2_158 X2_157 MIO_42 MIO_43 MIO_44 MIO_45 MIO_41 MIO_40 MIO_46 MIO_47 ZYNQ_SD_D0 ZYNQ_SD_D1 ZYNQ_SD_D2 ZYNQ_SD_D3 ZYNQ_SD_CMD ZYNQ_SD_CLK ZYNQ_SD_CD ZYNQ_SD_WP FPGA <=> SD FPGA <=> SD FPGA <=> SD FPGA <=> SD FPGA => SD FPGA => SD FPGA <= SD FPGA <= SD KRM-3500-CARRIER Data sheet Document Rev. 1.0 Remark Resistor on Carrier not on connector I/O Level 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 February 18, 2015 Page 13 of 21 UART to USB Bridge The USARTs of the Processing subsystems are available via a dual channel UART to USB Bridge from Silabs. One UARTs RX and TX signals are connected via the MIO pins of the PS, a second UART can be implemented via EMIO routing to Bank 35. The second UART also features HW flow control. While the Silabs I/O’s operate on a local 3V3 which is generated from the 5V0 USB, two level-shifters isolate the signals and convert the levels to 1V8 for the MIO and a selectable I/O voltage for the Logic I/O signals. The first UART channel can also be routed (via jumpers) to communicate with the controller of the KRM3500's power manager. In future FW releases, this path will offer advanced features such as FPGA driven power management. UART to USB Bridge Schematic: UART MIO Signal Table: PIN X2 MIO UART X2_162 X2_161 MIO_50 MIO_51 UART PMGR Signal Table: PIN XMOD KRMPA UART 8 6 RX TX UART FAB Signal Table: PIN X2 KRM_3A UART X2_7 X2_11 X2_9 X2_13 X2_1_311 X2_1_309 X2_1_310 X2_1_308 KRM-3500-CARRIER Data sheet Document Rev. 1.0 Signal name Direction UART_MIO_RXD UART_MIO_TXD FPGA_PS <= SIL FPGA_PS => SIL Signal name Direction UART_PMGR_RXD UART_PMGR_TXD Remark 1V8 1V8 Remark <= SIL => SIL Signal name Direction UART_FAB_RXD UART_FAB_TXD UART_FAB_CTS UART_FAB_RTS <= SIL => SIL <= SIL => SIL I/O Level I/O Level 3V3 3V3 Remark I/O Level 1V8-3V3 1V8-3V3 1V8-3V3 1V8-3V3 February 18, 2015 Page 14 of 21 PL IO All PL I/O Banks support multiple I/O voltages, 2 of which are provided by the on-board regulators; others may be added by the user design. Use the 5V0 on-board regulator as the source for any additional I/O voltage regulator. Supported/Provided I/O voltages are: 1V35,1V5, 1V8, 2V5 and 3V3. I/O voltages below 1V35 are NOT supported by the KRM3K modules as the I/O voltage is isolated by a high side P-FET switch which is only active after the FPGA has been configured or the modules power sub system reports power OK. Gate Voltages that do not at least reach -1V35 do not turn the P-FET on sufficiently, therefore 1V2 I/O voltages cannot be used reliably. KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 15 of 21 PL BANK X1_1 The PL Bank that is mapped to X1_1 is one of the two, full featured I/O Banks. All the 48 I/O’s that are available on the KRM Module are accessible via PMOD compatible 2.54mm sockets. Furthermore a subset of the signals is available on the 50pin ZIFF expansion connector. The signal assignment of the 50 pin Ziff connectors is identical in terms of byte group and pin sequence on the connectors for Bank X1_2, X2_1 and X2_2. The Banks I/O Voltage is selected by populating either R850 for 3V3 operation or R851 for 1V8 operation. If other operating voltages are desired, both resistors must be removed. The target I/O voltage must be jumped to one of the open resistor pads with a wire. By default, the 3V3 option is populated. In addition to the I/O voltage for the FPGA bank and the expansion modules I/O logic, a 5V supply on the two outermost pins is provided. This voltage is designed to provide a power source for the expansion module that is independent of the I/O Voltage of the FPGA bank. The symmetry of the signal and power assignments ensure that even an accidentally flipped flex cable cannot cause damage to the FPGA or expansion module due to Power pins being attached to sensitive signal pins. PL BANK X1_1 Schematic: KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 16 of 21 PL BANK X1_2 The PL Bank that is mapped to X1_2 is one of the two, full featured I/O Banks. All the 48 I/O’s that are available on the KRM Module are accessible via 2.54mm sockets. Furthermore a subset of the signals is available on the 50pin ZIFF expansion connector. The signal assignment of the 50 pin Ziff connectors is identical in terms of byte group and pin sequence on the connectors for Bank X1_1, X2_1 and X2_2. The Banks I/O Voltage is selected by populating either R852 for 3V3 operation or R853 for 1V8 operation. If other operating voltages are desired, both resistors must be removed. The target supply voltage must be jumped to one of the open resistor pads with a wire. By default, the 3V3 option is populated In addition to the I/O voltage for the FPGA bank and the expansion modules I/O logic, a 5V supply on the two outermost pins is provided. This voltage is designed to provide a power source for the expansion module that is independent of the I/O Voltage of the FPGA bank. The symmetry of the signal and power assignments ensure that even an accidentally flipped flex cable cannot cause damage to the FPGA or expansion module due to Power pins being attached to sensitive signal pins. PL BANK X1_2 Schematic: KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 17 of 21 PL BANK X2_1 The PL Bank that is mapped to X2_1 is one of the two special purpose PL I/O banks. While the 50 pin Ziff header connectivity matches that of banks X1_1 and X1_2, there is no 2.54mm socket field available. It’s primary purpose is to allow the connection of a touch display which is available as an add on to the KRM3500-CARRIER. The signals that go unused for the display operation are assigned to the UARTB with HW flow control signals. The Banks I/O Voltage is selected by populating R801 for 1V8 operation. If other operating voltages are desired, both resistors must be removed. The target supply voltage must be jumped to one of the open resistor pads with a wire. By default only the 1V8 Supply is an assembly option in order to ensure I/O Bank Voltage constraints are enforced for all of the KRM-3k Modules. If a Module with Artix fabric is used, the supply may be jumped to Voltages other than 1V8 PL BANK X2_1 Schematic: KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 18 of 21 PL BANK X2_2 The PL Bank that is mapped to X2_2 is one of the two special purpose banks. While the 50 pin Ziff header connectivity matches that of banks X1_1 and X1_2, there is no 2.54mm socket field available. Signals not used on the expansion Ziff connector are used to drive user LEDs and the reset signal for the USB hub. The Banks I/O Voltage is selected by populating R807 for 1V8 operation. If other operating voltages are desired, the resistor must be removed. The target supply voltage must be jumped to one of the open resistor pads with a wire. By default, the 1V8 option is populated PL BANK X2_2 Schematic: KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 19 of 21 MGT IO While the KRM3500 carrier has no direct support for MGT attached peripherals, all the signals of the X1 connector are forwarded via a mirror of X1 (X1B) with direct via connections. Via X1B, it is therefore possible to attach a sub-carrier (such as KRM3510) where all the MGT related connectivity is then implemented. The KRM3500 sub carrier offers the following connectivity: 2X SDI in 2X SDI out 4X SFP+ 2X SATA Low Jitter, programmable reference clock generator X1_B Schematic: KRM-3500-CARRIER Data sheet Document Rev. 1.0 February 18, 2015 Page 20 of 21 Thermal specification Standard version: Industrial version: KRM-3500-CARRIER Data sheet Document Rev. 1.0 Commercial operating range, 0°C to 70°C. Not available February 18, 2015 Page 21 of 21
