here - FPL 2015

Transcription

here - FPL 2015

Conference Guide
25th International Conference on
Field-programmable Logic and Applications
and associated Workshops and Tutorials
London, United Kingdom
31 August – 4 September 2015
24 years ago...
The 1st International Workshop on Field-programmable Logic
and Applications
4 – 6 September 1991
Oxford, United Kingdom
Conference Guide
Contents
Welcome.................................................................................. 4
General Information................................................................. 6
Venues.................................................................................... 8
Social Programme................................................................... 9
Royal Institution Map.............................................................10
Programme............................................................................ 12
Keynotes............................................................................... 20
Programme Detail
Monday 31 August 2015................................................... 28
Tuesday 1 September 2015............................................. 29
Wednesday 2 September 2015........................................ 30
Thursday 3 September 2015............................................ 36
Friday 4 September 2015................................................. 43
Special Session..................................................................... 48
Committees........................................................................... 49
City Map................................................................................ 58
Underground Map................................................................. 60
About London........................................................................ 62
London Sights....................................................................... 64
About Imperial College.......................................................... 72
About the Royal Institution.....................................................74
3
Welcome
Our warmest welcome to FPL 2015, celebrating 25 years of
the International Conference on Field-programmable Logic
and Applications!
The 25th FPL conference is hosted by Imperial College London
from 2 to 4 September 2015 at the Royal Institution in London,
where Michael Faraday conducted his famous experiments on
electromagnetism. The FPL 2015 conference is accompanied
by two-and-a-half days of tutorials and workshops taking place
on 31 August, 1 and 4 September. In addition to three industrial
workshops, there are four academic half- and full-day workshops and four half-day tutorials.
Highlights of FPL 2015 include keynotes from academia, funding agencies and industry. We are grateful to
Professor Steve Furber (University of Manchester, UK),
Dr Mike Hutton (Altera, US), Professor David Lariviere (Columbia University, US), Dr Salil Raje (Xilinx, US) and
Dr Panagiotis Tsarchopoulos (European Commission, BE) for
accepting our invitations to be keynote speakers.
This year’s Technical Program Committee had 188 members
organised into five tracks, with one track chair assigned to
each. There were 303 abstract submissions and 240 submissions were received by the submission deadline, including 216
regular papers, 12 PhD Forum papers and 12 demos. The
Technical Program Committee meeting was held at Imperial
College London on 29 May 2015. The final outcome of the review process was that 48 submissions were accepted as full
papers with oral presentation (22.2% full paper acceptance
rate) and 41 submissions were accepted as poster papers
(41.2% acceptance rate including full and poster papers). Furthermore, ten submissions were accepted for the PhD Forum
and ten were accepted for the Demo Night session.
Conference Guide
To commemorate the quarter-century contribution of the FPL
conference, the most significant papers from its first 25 years
have been selected to represent those which have most strongly influenced theory and practice in the field. Selection was
determined by an international Significant Papers Committee
(SPC), chaired by Professor Philip Leong (University of Sydney, AU). In addition, a special session on the past 25 years
and the next 25 years of FPL has been organised with distinguished speakers.
We are grateful to our sponsors for their support. We express
our sincere thanks to everyone involved with conference organisation and the technical committees for their efforts in making FPL 2015 a success. The Technical Program Committee
members provided valuable assessments for paper selection
and feedback to authors. The workshop and tutorial organisers
came up with attractive topics and put together an interesting
collection of satellite events. Last but not least, our thanks
extend to all the authors who sent submissions to FPL 2015,
whose research ideas have allowed us to put together an exciting programme.
The first 25 years of FPL have included many outstanding contributions to field-programmable logic and applications. With
the support of the FPL community, we are confident that FPL
will continue to flourish for the next 25 years and beyond.
Thank you for attending FPL 2015.
Peter Cheung and Wayne Luk (General Chairs)
Cristina Silvano (Programme Chair)
5
General Information
This conference guide aims to give you all the information you
should need during your attendance at FPL 2015. General information on the conference can also be found on the conference website, http://www.fpl2015.org.
Conference contact
Mrs Wiesia Hsissen
Department of Electrical and Electronic Engineering
Imperial College London
SW7 2BT
Phone: +44 (0)207 594 6261
E-mail: w.hsissen@imperial.ac.uk
Wi-fi
For the duration of the conference and the associated workshops/tutorials, free Wi-fi Internet access is provided.
At the Royal Institution, use the following wireless network:
SSID:RIGB-Guest
Key:Cavendish
At Imperial College, either use Eduroam or:
1. Connect to the wireless network with SSID Imperial.
2. Open a Web browser. You will see a log-in page.
3. Open the Guest Registration link in a new tab.
4. Enter the Unique ID conf35272 and click Proceed.
5. Enter your details and click Proceed.
6. Note down the Login Name and Password assigned to you.
7. In the original tab, enter those credentials and click Login.
Proceedings
A link to download the proceedings was emailed to you before
arrival. If you did not receive this or cannot find it, you can request a new link at http://www.fpl2015.org/?page=proceedings.
Conference Guide
Transport
London boasts one of the most extensive and frequented public transport networks in the world. Underground (subway or
tube), Overground (surface trains), light rail, trams, buses, coaches, river taxis and short-hire bicycles are integrated and managed by Transport for London (TfL). National Rail (mainline
train) services within London are also integrated.
Payment for TfL services is made by contactless (RFID) cards
called Oyster cards. These can be obtained, in exchange for
a £5.00 refundable deposit per card, from automated ticket
machines at all TfL stations or staffed ticket windows at major
stations (such as those at airports, train stations or important
landmarks). Oyster cards can be ‘topped up’ with credit using
cash, credit or debit cards at ticket machines or windows.
Many convenience stores also service Oyster top-ups; those
that do are externally marked with TfL branding. When buying
new cards or topping up using ticket machines, remember to
press the ‘print receipt’ button if you wish to receive a receipt;
they are not printed automatically.
When starting a journey on Underground, Overground or light
rail, ‘touch in’ using your Oyster card by holding it against a yellow card reader. A single short beep will indicate that your card
was read successfully, and the ticket gate (if present) will open.
Two long beeps indicate a problem; usually lack of sufficient
funds. Remember to touch in even if ticket gates are open or
not present to be charged the correct fare. Repeat this process
to ‘touch out’ at the end of your journey. Interchange between
Underground, Overground and light rail lines at appropriate
stations does not incur additional cost.
Oyster is based on a zonal fare system, with zones approximately comprising concentric circles emanating from the centre of the city. Due to this, fares for most services become higher the further you travel. Fares are also different depending on
the time you start your journey: those started between 06:30
and 09:30 or 16:00 and 19:00 on weekdays typically attract
higher (peak) fares, while all others are off-peak.
7
Venues
FPL 2015 is split across two venues: the Royal Institution,
where talks will be delivered, and the Electrical Engineering
building (number 16 on the campus map on page 9) of Imperial
College London’s South Kensington campus, where tutorials
and workshops will take place. The Royal Institution and Imperial College are approximately two miles apart. Inter-venue
travel is possible by direct Underground (Piccadilly line) or bus
(routes 9 and 14) link as well as on foot or by bicycle.
Addresses
Imperial College London
Exhibition Road
SW7 2AZ
Royal Institution
Albermarle Street
W1S 4BS
Conference Guide
Social Programme
Demo Night and Reception
Royal Institution, 18:15 Wednesday 2 September 2015
A demo night and accompanying canapé reception will be held
at the Royal Institution. There will be ten demos on display
from academia and industry.
Banquet
Imperial College London, 18:15 Thursday 3 September 2015
The banquet will take place at Imperial College. We will be
having the dinner in the the Queen’s Tower Rooms, located
on the ground floor of the Sherfield Building (number 20 on
the campus map, below). The papers that won this year’s best
paper awards will also be announced at the event.
9
Royal Institution Map
Conference Guide
11
Programme
Monday 31 August 2015
Electrical Engineering, Imperial College London
Room 611
08:30 – 09:00
09:00 – 10:30
Room 1109
Room 507
Registration
Workshop
Tutotial
Industrial workshop
W1: ReC4P 2015
T1: NetFPGA – Rapid
IW1: Xilinx System
– First International
Prototyping of High-
Design with Zynq
Workshop on Recon-
bandwidth Devices in
figurable Computing
Open Source
for HPC and HPDA
10:30 – 11:00
Coffee break
Room 509
11:00 – 12:30
Workshop
Tutotial
Industrial workshop
W1: ReC4P 2015
T1: NetFPGA – Rapid
IW1: Xilinx System
Prototyping of High-
Design with Zynq
Workshop on Recon-
bandwidth Devices in
figurable Computing
Open Source
for HPC and HPDA
12:30 – 13:30
Lunch
Room 509
13:30 – 15:00
Tutorial
Industrial workshop
T2: Rapid Develop-
IW1: Xilinx System
ment of Real-time
Design with Zynq
Applications with
National Instruments
LabVIEW
15:00 – 15:30
Coffee break
Room 509
15:30 – 17:00
Tutorial
Industrial workshop
T2: Rapid Develop-
IW1: Xilinx System
ment of Real-time
Design with Zynq
Applications with
National Instruments
LabVIEW
Conference Guide
Tuesday 1 September 2015
Electrical Engineering, Imperial College London
Room 611
08:30 – 09:00
09:00 – 10:30
Room 1109
Room 304
Room 507
Registration
Workshop
Tutotial
W3: FSP 2015
T3: Under-
workshop
workshop
– Second
neath the
IW2: Overview
IW3: Xilinx SD-
Industrial
Industrial
International
FPGA Clothes
of Altera‘s Cy-
SoC: Building
Workshop on
– Enhancing
clone V SoC
Software-defi-
FPGAs for SW
Security
Devices and
ned Systems-
Design Tools
on-Chip
Programmers
10:30 – 11:00
Coffee break
Room 509
11:00 – 12:30
Workshop
Tutotial
Industrial
Industrial
W3: FSP 2015
T3: Under-
workshop
workshop
– Second
neath the
IW2: Overview
IW3: Xilinx SD-
International
FPGA Clothes
of Altera‘s Cy-
SoC: Building
Workshop on
– Enhancing
clone V SoC
Software-defi-
FPGAs for SW
Security
Devices and
ned Systems-
Design Tools
on-Chip
Programmers
12:30 – 13:30
Lunch
Room 509
13:30 – 15:00
Workshop
Tutorial
Industrial
Industrial
W3: FSP 2015
T4: The LEAP
workshop
workshop
– Second
Run-time
IW2: Overview
IW3: Xilinx SD-
International
System –
of Altera‘s Cy-
SoC: Building
Workshop on
Rapid System
clone V SoC
Software-defi-
FPGAs for SW
Integration of
Devices and
ned Systems-
Programmers
HLS Kernels
Design Tools
on-Chip
15:00 – 15:30
Coffee break
Room 509
15:30 – 17:00
Workshop
Tutorial
Industrial
Industrial
W3: FSP 2015
T4: The LEAP
workshop
workshop
IW3: Xilinx SD-
– Second
Run-time
IW2: Overview
International
System –
of Altera‘s Cy-
SoC: Building
Workshop on
Rapid System
clone V SoC
Software-defi-
FPGAs for SW
Integration of
Devices and
ned Systems-
Programmers
HLS Kernels
Design Tools
on-Chip
13
Wednesday 2 September 2015
Royal Institution
Theatre
Conversation Room
Demo Room
08:15 – 08:45
Registration
08:45 – 09:00
Welcome session
09:00 – 10:00
Keynote 1: Salil Raje (Xilinx, US)
10:00 – 10:40
Coffee break & poster session: PhD Forum
Theatre
Theatre
Georgian Room
10:40 – 12:00
Technical session
Technical session
Applications 1: Linear
Architectures & Tech-
Design Methods &
Algebra and Control
nology 1: Energy-ef-
Tools 1: Parallelism
Applications
ficient and Low-power
and Logic Design
Technical session
Architectures
12:00 – 13:00
Lunch
Library & Georgian Room
13:00 – 14:00
Keynote 2: David Lariviere (Columbia University, US)
14:00 – 15:00
Special session: FPL – The Past 25 Years and the Next 25 Years
Theatre
Theatre
15:00 – 15:40
Coffee break & poster session: Applications
15:40 – 17:00
Special session: FPL – The Past 25 Years and the Next 25 Years
Georgian Room
Theatre
18:00 – 18:15
Introduction to significant papers: Philip Leong (University of Sydney, AU)
18:15 – 20:00
Demo Night & reception
Library
Library
Conference Guide
Thursday 3 September 2015
Royal Institution (morning & afternoon)
Electrical Engineering, Imperial College London (evening)
Theatre
Conversation Room
Demo Room
08:30 – 09:00
Registration
09:00 – 10:00
Keynote 3: Mike Hutton (Altera, US)
10:00 – 10:40
Coffee break & poster session: Architectures & Technology
Theatre
Georgian Room
10:40 – 12:00
Technical session
Technical session
Technical session
Applications 2:
Architectures &
Design Methods &
Computer Vision
Technology 2: Crypto-
Tools 2: Accelera-
and Numerical Appli-
graphy and Security
tors and High-level
cations
Architectures
Synthesis
12:00 – 13:00
Lunch
13:00 – 14:00
Keynote 4: Panagiotis Tsarchopoulos (European Commission, BE)
Library & Georgian Room
Theatre
14:00 – 15:00
Technical session
Technical session
Applications 3:
Architectures &
Design Methods &
Pattern-matching and
Technology 3: Recon-
Tools 3: Simulation
Search Applications
figurable Computing
and Emulation
Technical session
and Architectures
15:00 – 15:40
Coffee break & poster session: Design Methods & Tools
Georgian Room
15:40 – 17:00
Technical session
Technical session
Applications 4: High-
Architectures & Tech-
Design Methods
level Synthesis and
nology 4: Architectu-
& Tools 4: Hybrid
Optimisation
res and Synthesis
FPGA-based
Technical session
Systems
Location change: Royal Institution → Imperial College London
18:15 – 21:00
Banquet & best paper awards
Queen‘s Tower Rooms
15
Friday 4 September 2015
Royal Institution (morning)
Electrical Engineering, Imperial College London (afternoon)
Theatre
Conversation Room
Demo Room
08:30 – 09:00
Registration
09:00 – 10:00
Keynote 5: Steve Furber (University of Manchester, UK)
10:00 – 10:40
Coffee break & poster session: Self-aware & Adaptive Systems
Theatre
Georgian Room
10:40 – 12:15
Workshop
Workshop
Technical session
W4: RC4Masses –
W5: WCS-IoT 2015
Architectures &
Workshop on Recon-
Technology 5:
figurable Computing
Workshop on Com-
Memory Management
for the Masses,
ponents and Services
and Customised
Really?
for IoT platforms
Architectures
12:15 – 12:30
Closing session
Theatre
Location change: Royal Institution → Imperial College London
Room 408
13:00 – 13:30
Room 611
Lunch (for workshop attendees only)
Room 509
13:30 – 15:00
Workshop
Workshop
W4: RC4Masses –
W5: WCS-IoT 2015
Workshop on Recon-
figurable Computing
Workshop on Com-
for the Masses,
Really?
for IoT platforms
15:00 – 15:30
Coffee break
Room 509
15:30 – 17:00
Workshop
Workshop
W4: RC4Masses –
W5: WCS-IoT 2015
Workshop on Recon-
figurable Computing
Workshop on Com-
for the Masses,
Really?
for IoT platforms
Conference Guide
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Keynotes
Extending the Power of FPGAs to Software Developers
Salil Raje (Xilinx, US)
Royal Institution Theatre, 09:00 Wednesday 2 September 2015
FPGAs have evolved from simple programmable logic arrays
to complex SoCs with millions of programmable elements. As
the FPGA device has evolved, so has the programming paradigm. The industry has made significant progress in raising
the abstraction level of FPGA design by leveraging a large set
of IP blocks, enabling abstract IP integration, and exploiting
high-level synthesis technology that allows users to work at
the algorithmic level. While these innovations have increased
the productivity of FPGA designers, they have not unleashed
the full potential of FPGAs to the software programmers of the
world. If we are intent on expanding the reach of FPGAs, we
need to drive towards fully software-programmable FPGAs that
can be used for heterogeneous computing. The programming
solution needs to have the same look and feel as standard
IDEs and abstract away the complexities of the underlying
hardware while exploiting the massive parallelism of FPGAs
for hardware acceleration. Key to enabling the era of software
programmability will be the concept of the programmable platform – an abstraction that will allow the FPGA to take on the
persona of the application domain. The journey to embrace the
software developer community has begun.
Salil Raje is Corporate Vice President of Software and IP Products Development at Xilinx, where he has held a variety of
roles in the development organisation since 2004. Prior to joining Xilinx, he was the founder and CTO of Hier Design, an
EDA startup focussed on hierarchical design methodology and
design planning tools for the FPGA market. Prior to that, Salil
was a director at Monterey Design Systems, an EDA startup
working on place and route technology for standard-cell ASIC
design. Salil began his career at IBM Research Center at Yorktown Heights, New York, working on high-level synthesis. He
holds a BTech in Electrical Engineering from IIT, Madras and
an MS and a PhD in Computer Science from Northwestern
University.
Conference Guide
Applications of FPGAs to the Financial Trading Industry
David Lariviere (Columbia University, US)
Royal Institution Theatre, 13:00 Wednesday 2 September 2015
Programmable logic is having a profound and increasingly
dominant role in modern financial markets. This talk will present an overview of electronic trading systems, trends in the
underlying technologies, and explore areas of opportunity for
researchers and industry to become more involved.
Professor David Lariviere teaches at Columbia University in
the City of New York as an adjunct professor in the Departments of Computer Science and Electrical Engineering. His
research focusses on the application of next-generation technologies towards the intersection of electronic trading and ultra
low-latency packet processing. In industry, Prof. Lariviere is a
consulting expert in the electronic trading space, architecting
systems responsible for safely and quickly processing packets
worth trillions of dollars daily.
21
Architectural Paths to Faster and More Robust FPGAs
Mike Hutton (Altera, US)
Royal Institution Theatre, 09:00 Thursday 3 September 2015
For most of the 25 years of the FPL Conference, FPGA technology has successfully ridden Moore’s Law to greater density,
higher performance and lower power. We’re still getting density and power benefits, but more performance is required by
the end markets and spending more power to get there isn’t
acceptable. On other fronts: the need for memory is growing
but we don’t get more pins for DDR, and development effort
and complexity is also increasing, making it harder to build a
single device where everything just works first time and inside
a reasonable budget. When you can’t count on only riding the
process curve, architecture needs to come to the rescue! In
this presentation, I will highlight several fundamental changes
for FPGAs that are introduced in the new Stratix 10 family:
(1) HyperFlex – a fresh re-design of routing fabric architecture
allowing logic to be heavily pipelined without resource penalties and targetting twice the performance of existing FPGAs;
(2) modularity and software-controlled FPGA configuration –
allowing independent housekeeping and re-configuration for
device sectors; and (3) extensive use of 3D integration across
Intel’s embedded multi-die interconnect bridge (EMIB) technology – allowing not just in-package memory and heterogeneous devices but mixed-process development to de-risk and
optimise analogue and digital design on different technology
processes.
Mike Hutton is an IC design architect at Altera and principal investigator in the Altera Technology Office. He is responsible for
product architecture definition for new devices, most recently
the Stratix 10 family, and research within the Technology Office. He received a BMath and MMath in Computer Science
from Waterloo and a PhD from the University of Toronto. He
is Associate Editor of IEEE Trans. CAD, past Programme and
General Chair of the Int’l Symposium on FPGAs and has served on the Technical Programme Committees for many research conferences, including DAC, DATE, FPGA, FPL and
FPT.
Conference Guide
Title unavailable at time of printing
Panagiotis Tsarchopoulos (European Commission, BE)
Royal Institution Theatre, 13:00 Thursday 3 September 2015
Abstract unavailable at time of printing.
23
Field-programmable Neurocomputing
Steve Furber (University of Manchester, UK)
Royal Institution Theatre, 09:00 Friday 4 September 2015
SpiNNaker is a massively parallel computer system, ultimately to incorporate a million ARM processor cores (the largest
machine to date has 100,000 cores) with an innovative, lightweight packet-switched communications fabric capable of supporting typical biological connectivity patterns in biological real
time. One of the key principles in the design of SpiNNaker,
based on the observation that different brain regions have different connectivity patterns, is to virtualise topology, effectively
decoupling the topology of the network being modelled from
the topology of the machine itself. As a result, SpiNNaker can
be viewed as a large field-programmable neurocomputer, where the neural circuit can be configured flexibly at run-time. The
network can be described using a neural HDL such as PyNN
or Nengo, and then the design tools compile the network onto
the machine where it runs in biological real time.
Steve Furber CBE FRS FREng is ICL Professor of Computer
Engineering in the School of Computer Science at the University of Manchester, UK. After completing a BA in mathematics
and a PhD in aerodynamics at the University of Cambridge,
UK, he spent the 1980s at Acorn Computers, where he was a
principal designer of the BBC Microcomputer and the ARM 32bit RISC microprocessor. Over 60 billion variants of the ARM
processor have since been manufactured, powering much of
the world‘s mobile and embedded computing. He moved to
the ICL Chair at Manchester in 1990 where he leads research
into asynchronous and low-power systems and, more recently,
neural systems engineering, where the SpiNNaker project is
delivering a computer incorporating a million ARM processors
optimised for brain modelling applications.
Conference Guide
BYU London Centre
Brigham Young University’s base of operations in the United Kingdom
The London Centre houses a study abroad program for up to
forty-two students and two faculty during each academic term.
In addition, the London Centre sponsors and cosponsors
events with academic institutions in the UK and on the European continent.
London Centre
David Kirkham
Academic Director
27 Palace Court
London W2 4LP
25
Programme Detail for
Monday 31 August 2015
Workshop
W1: ReC4P 2015 – First International Workshop on Reconfigurable Computing for HPC and HPDA
Imperial College London EE room 611, 09:00 – 12:30
Antonino Tumeo (Pacific Northwest National Laboratory, US)
Gianluca Palermo (Politecnico di Milano, IT)
Tutorial
T1: NetFPGA – Rapid Prototyping of High-bandwidth Devices in Open Source
Andrew Moore (University of Cambridge, UK)
Noa Zilberman (University of Cambridge, UK)
Yury Audzevich (University of Cambridge, UK)
Tutorial
T2: Rapid Development of Real-time Applications with National Instruments LabVIEW
Dustyn Blasig (National Instruments, US)
Industrial workshop
IW1: Xilinx System Design with Zynq
Cathal McCabe (Xilinx, IE)
Conference Guide
Tuesday 2 September 2015
Workshop
W3: FSP 2015 – Second International Workshop on FPGAs
for Software Programmers
Tobias Becker (Maxeler, UK)
Frank Hannig (Universität Erlangen-Nürnberg, DE)
Dirk Koch (University of Manchester, UK)
Daniel Ziener (Universität Erlangen-Nürnberg, DE)
Tutorial
T3: Underneath the FPGA Clothes – Enhancing Security
Viktor Fischer (University of Saint-Etienne, FR)
Lilian Bossuet (University of Saint-Etienne, FR)
Jean-Luc Danger (TELECOM ParisTech, FR)
Tutorial
T4: The LEAP Run-time System – Rapid System Integration of Your HLS Kernels
Michael Adler (Intel, US)
Kermin Fleming (Intel, US)
Hsin-Jung Yang (Massachusetts Institute of Technology, US)
Felix Winterstein (Imperial College London, UK)
Industrial workshop
IW2: Overview of Altera’s Cyclone V SoC Devices and Design Tools
Blair Fort (Altera, US)
Industrial workshop
IW3: Xilinx SDSoC: Building Software-defined Systemson-Chip with Zynq All-programmable SoCs
29
Wednesday 2 September 2015
Poster session
PhD Forum
Royal Institution Georgian Room, 10:00 – 10:40
Greedy Approach-based Heuristics for Partitioning SpMxV on
FPGAs
Jiasen Huang, Weina Lu and Junyan Ren
Scheduling-aware Interconnect Synthesis for FPGA-based
Multi-processor System-on-Chip
Edoardo Fusella, Alessandro Cilardo and Antonino Mazzeo
Rapid Prototyping and Design Space Exploration Methodologies for Many-accelerator Systems
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos and Dimitrios Soudris
Towards a Guided Design Flow for Heterogeneous Reconfigurable Architectures
Timm Bostelmann and Sergei Sawitzki
High-level Synthesis Extensions for Scalable Single-chip Many-accelerators on FPGAs
Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios and
Dimitrios Soudris
FPGA-based All-digital Software-defined Radio Receiver
André Prata, Arnaldo Oliveira and Nuno Carvalho
Over Effective Hard Real-time Hardware Tasks Scheduling
and Allocation
Zakarya Guettatfi, Omar Kermia and Abdelhakim Khouas
FPGA-based All-digital Transmitters
Rui Cordeiro, Arnaldo Oliveira and José Vieira
A Framework for Integrated Monitoring of Real-time Embedded SoC
Giacomo Valente
Conference Guide
Technical session
Applications 1: Linear Algebra and Control Applications
Royal Institution Theatre, 10:40 – 12:00
Efficient Assembly for High-order Unstructured FEM Meshes
Pavel Burovskiy, Paul Grigoras, Spencer Sherwin and Wayne
Luk
A Scalable FPGA Architecture for Non-negative Least Squares
Problems
Alric Althoff and Ryan Kastner
Towards Heterogeneous Solvers for Large-scale Linear Systems
Stylianos Venieris, Grigorios Mingas and Christos-Savvas
Bouganis
A Software Configurable Coprocessor-based State-space
Controller
Aaron Mills, Pei Zhang, Sudhanshu Vyas, Phillip Jones and
Joseph Zambreno
Technical session
Architectures & Technology 1: Energy-efficient and Lowpower Architectures
Royal Institution Conversation Room, 10:40 – 12:00
Automatic Generation of High-throughput Energy-efficient
Streaming Architectures for Arbitrary Fixed Permutations
Ren Chen and Viktor Prasanna
Using FPGA-style Intra-CLB Routing in Low-power FPGAs
Oluseyi Ayorinde and Benton Calhoun
Energy Optimization of FPGA-based Stream-oriented Computing with Power Gating
Mohammad Hosseinabady and Jose Nunez-Yanez
Energy-efficient Partitioning of Dynamic Reconfigurable
MRAM-FPGAs
Ali Ahari, Mojtaba Ebrahimi and Mehdi Tahoori
31
Technical session
Design Methods & Tools 1: Parallelism and Logic Design
Royal Institution Demo Room, 10:40 – 12:00
Automatic Support for Multi-module Parallelism from Computational Patterns
Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun and Paolo Ienne
ParaLaR: A Parallel FPGA Router Based on Lagrangian Relaxation
Chin Hau Hoo, Akash Kumar and Yajun Ha
Fine-tuning CLB Placement to Speed Up Reconfigurations in
NVM-based FPGAs
Yuan Xue, Patrick Cronin, Chengmo Yang and Jingtong Hu
A Technology Mapper for Depth-constrained FPGA Logic Cells
Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo,
Liqun Yang, Zhihong Huang, Haigang Yang and Paolo Ienne
Conference Guide
Poster session
Applications
An FPGA Implementation of a Phylogenetic Tree Reconstruction Algorithm Using an Alternative Second-pass Optimization
Henry Block and Tsutomu Maruyama
Ultra Low-latency Dataflow Renderer
Sebastian Friston, Anthony Steed, Simon Tilbury and Georgi
Gaydadjiev
Exploring with Pipe Implementations using an OpenCL Framework for FPGAs
Vincent Mirian and Paul Chow
Parallel Feature Extraction and Heterogeneous Object Detection for Multi-camera Driver Assistance Systems
Stefan Wonneberger, Peter Muehlfellner, Pedro Ceriotti,
Thorsten Graf and Rolf Ernst
A Transport Layer Network for Distributed FPGA Platforms
Sang-Woo Jun, Ming Liu, Shuotao Xu and Arvind Arvind
Generating FPGA Accelerators for Chemical Similarity Assessment
Nikolaos Alachiotis
rrBox: A Remote Dynamically Reconfigurable Network-processing Middlebox
Tze Tan, Chia Ooi and Nadzir Marsono
FPGA-based Nonlinear Support Vector Machine Training
Using an Ensemble Learning
Mudhar Rabieah and Christos-Savvas Bouganis
33
Demo Night
Royal Institution Library, 18:15 – 20:00
AmBRAMs – An Analysis Tool, Method and Framework for
Advanced Measurements And Reliability Assessments on Modern Nanoscale FPGAs
Petr Pfeifer
7 MOPS/Lemon-battery Image Processing Demonstration with
an Ultra Low-power Reconfigurable Accelerator CMA-SOTB-2
Koichiro Masuyama, Yu Fujita, Hayate Okuhara and Hideharu
Amano
Design and Simulation Tools for Embedded NoCs on FPGAs
Mohamed Abdelfattah, Andrew Bitar, Ange Yaghi and Vaughn
Betz
NetFPGA – Rapid Prototyping of High-bandwidth Devices in
Open Source
Noa Zilberman, Yury Audzevich, Georgina Kalogeridou, Neelakandan Manihatty-Bojan, Jingyun Zhang and Andrew Moore
Building a Distributed Key-value Store with FPGA-based Micro-servers
Zsolt Istvan, David Sidler and Gustavo Alonso
High-Level FPGA Logic Synthesis from .NET Programs for
Software Developers
Zoltán Lehóczky, Richárd Tóth and Krisztián Somogyi
Hierarchical Library-based Power Estimator for Versatile FPGAs
Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen and Hai
Li
FPGA-based All-digital Software-defined Radio System Demonstration
Rui Cordeiro, André Prata, Arnaldo Oliveira, Nuno Carvalho
and José Vieira
Computing to the Limit with CPU-FPGA Hybrids and Adaptive
Voltage Scaling
Jose Nunez-Yanez
Dynamic Voltage and Frequency Scaling: a Real-world Example
James Davis, Joshua Levine, Edward Stott, George Constantinides and Peter Cheung
Conference Guide
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Thursday 3 September 2015
Poster session
Architectures & Technology
Optimizing Energy-efficient Low-swing Interconnect for Subthreshold FPGAs
He Qi, Oluseyi Ayorinde, Yu Huang and Benton Calhoun
An Automated Technique to Generate Relocatable Partial Bitstreams for Xilinx FPGAs
Roel Oomen, Tuan Nguyen, Akash Kumar and Henk Corporaal
Pipelined and Customized NoC Router Architecture Design on
FPGA
Qi Chen and Qiang Liu
Accurate Power Analysis for Near-Vt RRAM-based FPGA
Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli
OpenCL Computing on FPGA Using Multi-ported Shared Memory
Tahsin Türker Mutlugün and Sheng-De Wang
Adaptive MRAM-Based CGRAs
Xiaobin Liu, Tedy Thomas, Alan Boguslawski and Russell Tessier
Reduction Calculator in an FPGA-based Switching Hub for
High-performance Clusters
Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa and Hideharu Amano
Serial and Parallel Interleaved Modular Multipliers on FPGA
Platform
Khalid Javeed, Xiaojun Wang and Mike Scott
Data Protection Using Recursive Inverse Function
Teng Xu, Hongxiang Gu and Miodrag Potkonjak
Conference Guide
Technical session
Applications 2: Computer Vision and Numerical Applications
A Deep Convolutional Neural Network using Nested Residue
Number System
Hiroki Nakahara and Tsutomu Sasao
A Fast Hierarchical Implementation of Sequential Tree-reweighted Belief Propagation For Probabilistic Inference
Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José Martínez and Rob Rutenbar
A Scalable Pipelined Architecture for Biomimetic Vision Sensors
Daniel Llamocca and Brian Dean
FPGA Implementation to Estimate the Number of Endmembers in Hyperspectral Images
Carlos Gonzalez, Sebastian Lopez, Daniel Mozos and Roberto Sarmiento
Technical session
Architectures & Technology 2: Cryptography and Security
Architectures
Compact Dual-block AES core on FPGA for CCM Protocol
João Resende and Ricardo Chaves
Towards Efficient Discrete Gaussian Sampling for Latticebased Cryptography
Chaohui Du and Guoqiang Bai
An Efficient Many-core Architecture for Elliptic Curve Cryptography Security Assessment
Marco Indaco, Fabio Lauri, Andrea Miele and Pascal Trotta
High-speed ECC Implementation on FPGA over GF(2m)
Zia Khan and Mohammed Benaissa
37
Technical session
Design Methods & Tools 2: Accelerators and High-level
Synthesis
SPINE: From C Loop-nests to Highly Efficient Accelerators
using Algorithmic Species
Mark Wijtvliet, Shakith Fernando and Henk Corporaal
Optimised OpenCL Workgroup Synthesis for Hybrid ARM-FPGA Devices
Mohammad Hosseinabady and Jose Nunez-Yanez
An Interface and Mechanism Efficiently Supporting Key Memory Access Patterns in FPGA Computing
Gabriel Weisz and James Hoe
Scavenger: Automating the Construction of Application-optimized Memory Hierarchies
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein and Joel Emer
Technical session
Applications 3: Pattern-matching and Search Applications
Power-efficient Range Match-based Packet Classification on
FPGA
Yun Qu and Viktor Prasanna
A Variable-length Hash Method for Faster Short Read Mapping
on FPGA
Yoko Sogabe and Tsutomu Maruyama
Hybrid Breadth-first Search on a Single-chip FPGA-CPU Heterogeneous Platform
Yaman Umuroglu, Donn Morrison and Magnus Jahre
Conference Guide
Technical session
Architectures & Technology 3: Reconfigurable Computing
and Architectures
A Fully Pipelined Kernel-normalised Least Mean Squares Processor For Accelerated Parameter Optimisation
Nicholas Fraser, Duncan Moss, Jun-Kyu Lee, Stephen Tridgell,
Craig Jin and Philip Leong
An Efficient Reconfigurable Architecture by Characterizing
Most Frequent Logic Functions
Iman Ahmadpour, Behnam Khaleghi and Hossein Asadi
Static Hardware Task Placement on Multi-context FPGA using
Hybrid Genetic Algorithm
Hao Liang, Sharad Sinha, Rakesh Warrier and Wei Zhang
Technical session
Design Methods & Tools 3: Simulation and Emulation
Domain-specific Optimisation for the High-level Synthesis of
Cell Simulation Accelerators
Julian Oppermann, Andreas Koch, Ting Yu and Oliver Sinnen
Software-in-the-loop Simulation of Embedded Control Applications based on Virtual Platforms
Stephan Werner, Leonard Masing and Juergen Becker
Ultra-fast NoC Emulation on a Single FPGA
Thiem Van Chu, Shimpei Sato and Kenji Kise
39
Poster session
Design Methods & Tools
In-field Vulnerability Analysis of FPGA-realized Computer Vision Applications
Ioannis Chadjiminas, Christos Kyrkou, Christos Ttofis, Theocharis Theocharides and Maria Michael
A Rapid Prototyping Framework for Nano-photonic Accelerators
Alberto Garcia-Ortiz, Wolfgang Büter, A. Ali, S. Mahmood, S.
Arefin, V. Sreenivas and R. Bergman
Fast FPGA System for Microarchitecture Optimization on Synthesizable Modern Processor Design
Libo Huang, Yongwen Wang, Qiang Dou, Caixia Sun, Chengyi
Zhang and Chao Xu
An LZ77-style Bit-level Compression for Trace Data Compaction
Kai-Uwe Irrgang and Thomas Preußer
Mind The (Synthesis) Gap: Examining Where Academic FPGA
Tools Lag Behind Industry
Eddie Hung
Rapid Evaluation of FPGA Architecture Routability Without
Benchmarks
Oleg Petelin and Vaughn Betz
Temperature-triggered Behavioral IPs Hardware Trojan Detection Method with FPGAs
Xiaotong Li and Benjamin Schafer
Estimating Circuit Delays in FPGAs after Technology Mapping
Berg Severens, Elias Vansteenkiste, Karel Heyse and Dirk
Stroobandt
Conference Guide
Technical session
Applications 4: High-level Synthesis and Optimisation
From Low-architectural Expertise Up to High-throughput Nonbinary LDPC Decoders: Optimization Guidelines using Highlevel Synthesis
Joao Andrade, Nithin George, Kimon Karras, David Novo, Vitor
Silva, Paolo Ienne and Gabriel Falcao
A study of Data Partitioning on OpenCL-based FPGAs
Zeke Wang, Bingsheng He and Wei Zhang
Limits of FPGA Acceleration of 3D Green‘s Function Computation for Geophysical Applications
Nachiket Kapre, Selvakumar Jayakrishnan, Parjanya Gupta,
Sagar Masuti and Sylvain Barbot
Recursive Pipelined Genetic Propagation for Bilevel Optimisation
Shengjia Shao, Liucheng Guo, Ce Guo, Thomas Chau, Wayne
Luk and Stephen Weston
Technical session
Architectures & Technology 4: Architectures and Synthesis
Synthesizable FPGA Fabrics Targetable by the Verilog-to-Routing (VTR) CAD
Jin Hee Kim and Jason Anderson
Hoplite: Building Austere Overlay NoCs for FPGAs
Nachiket Kapre and Jan Gray
FPGA-based Low-overhead Speculative Addition for Signed
Operands
Alessandro Cilardo
Inter-procedural Resource-sharing in High-level Synthesis
through Function Proxies
Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo and
Fabrizio Ferrandi
41
Technical session
Design Methods & Tools 4: Hybrid FPGA-based Systems
Enabling Seamless Execution on Hybrid CPU/FPGA Systems:
Challenges & Directions
Meena Belwal, Madhura Purnaprajna and Sudarshan TSB
Hybrid FPGA Debug Approach
Zdravko Panjkov
A High-performance Protocol for Exposing IP Cores as Functions in a Shared-bus SoC
David Thomas, George Constantinides, Shane Fleming and
Ivan Beretta
Conference Guide
Friday 4 September 2015
Poster session
Self-aware & Adaptive Systems
A Run-time Interpretation Approach For Creating Custom Accelerators
Sen Ma, Zeyad Aklah and David Andrews
Data-triggered Breakpoint for In-circuit Debug without Re-implementation
Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba and Kaoru
Kawamura
Characterisation of Feasibility Regions in FPGAs Under Adaptive DVFS
Nizar Dahir, Pedro Campos, Gianluca Tempesti, Martin Trefzer
and Andrew Tyrrell
A Resilient, Flash-free Soft Error Mitigation Concept for the
CBM-ToF Read-out Chain via GBT-SCA
Andrei-Dumitru Oancea, Christian Stuellein, Jano Gebelein
and Udo Kebschull
UniStream: A Unified Stream Architecture Combining Configuration and Data Processing
Jian Yan, Jifang Jin, Ying Wang, Xuegong Zhou, Philip Leong
and Lingli Wang
Placing Partially Reconfigurable Stream-processing Applications on FPGAs
Nicolae Grigore and Dirk Koch
A Portable Open-source Controller for Safe Dynamic Partial
Reconfiguration on Xilinx FPGAs
Jan Andersson, Stefano Di Carlo, Paolo Prinetto and Pascal
Trotta
43
Workshop
W4: RC4Masses – Workshop on Reconfigurable Computing for the Masses, Really?
Paolo Ienne (École Polytechnique Fédérale de Lausanne, CH)
David Andrews (University of Arkansas, US)
Walid Najjar (University of California Riverside, US)
Workshop
W5: WCS-IoT 2015 – First International Workshop on Components and Services for IoT platforms
Michael Hübner (Ruhr-Universität Bochum, DE)
Nikolaos Voros (Technological Educational Institute of Western
Greece, GR)
Georgios Keramidas (Technological Educational Institute of
Western Greece, GR)
Technical session
Architectures & Technology 5: Memory Management and
Customised Architectures
SysAlloc: A Hardware Manager for Dynamic Memory Allocation in Heterogeneous Systems
Zeping Xue and David Thomas
Efficient Data-Stream Management for Shared Memory Manycore Systems
Nuno Neves, Pedro Tomás and Nuno Roma
A Scalable Architecture for Multi-class Visual Object Detection
Siddharth Advani, Yasuki Tanabe, Kevin Irick, Jack Sampson
and Vijaykrishnan Narayanan
Enhancing Stochastic Computations via Process Variation
Rui Duarte, Mário Véstias and Horácio Neto
Conference Guide
Workshop
W4: RC4Masses – Workshop on Reconfigurable Computing for the Masses, Really?
Workshop
W5: WCS-IoT 2015 – First International Workshop on Components and Services for IoT platforms
Greece, GR)
Georgios Keramidas (Technological Educational Institute of
Western Greece, GR)
45
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Conference Guide
47
Special Session
Special session
FPL – The Past 25 Years and Next 25 Years
Royal Institution Theatre, 14:00 Wednesday 2 September
As this is the 25th edition of FPL, we are pleased to have a
special session focussing on the past and especially on the
next 25 years of field-programmable technology. The session
will contain seven talks from key industrial players.
Reconfiguring the Datacenter: Building the Infrastructure for
Enterprise-class FPGA
Salem Derisavi (Huawei)
From Data to Information to Flow
Oskar Mencer (Maxeler)
Early Reconfigurable Computing and the Changing Technological Landscape
Mark Shand (Google)
The Impact of System-on-Chips on Your Design Methods
Rieny Rijnen (Topic Embedded Systems)
The Future: Not What it Used to be
John Watson (Micron)
Gateware Defined Neworking (GDN) Goes Mainstream
John Lockwood (Algo-Logic)
The Golden Age of FPGAs
Kubilay Atasu (IBM)
Conference Guide
Committees
Organising Committee
General Chairs
Peter Cheung (Imperial College London, UK)
Wayne Luk (Imperial College London, UK)
Programme Chair
Cristina Silvano (Politecnico di Milano, IT)
Track Chairs
Architectures and Technology
Jason Anderson (University of Toronto, CA)
Applications and Benchmarks
Dirk Koch (University of Manchester, UK)
Design Methods and Tools
Dirk Stroobandt (Universiteit Gent, BE)
Self-aware and Adaptive Systems
Marco Platzner (Universität Paderborn, DE)
Surveys, Trends and Education
Workshop and Tutorial Chairs
Guy Gogniat (Université de Bretagne Sud, FR)
Bob Stewart (University of Strathclyde, UK)
Industrial Workshop Chair
Christos Bouganis (Imperial College London, UK)
Panel Chairs
Simon Moore (University of Cambridge, UK)
PhD Forum Chairs
Dimitrios Soudris (National Technical University of Athens, GR)
Andy Tyrell (University of York, UK)
Demo Night and Project Presentation Chairs
Koen Bertels (Technische Universiteit Delft, NL)
Jose Nunez-Yanez (University of Bristol, UK)
49
Proceedings Chair
Walter Stechele (Technische Universität München, DE)
Local Arrangement Team
Wiesia Hsissen (Imperial College London, UK)
Joshua Levine (Imperial College London, UK)
Xinyu Niu (Imperial College London, UK)
Edward Stott (Imperial College London, UK)
Webmaster
James Davis (Imperial College London, UK)
Submissions Chair
David Boland (Monash University, AU)
Publicity Chairs
Europe and Africa
Kubilay Atasu (IBM, CH)
Central and South America
Claudia Feregrino (Instituto Nacional de Astrofísica, Óptica y
Electrónica, MX)
North America
Henry Styles (Xilinx, US)
Asia
Terence Mak (Chinese University of Hong Kong, HK)
Australasia
Olivier Diessel (University of New South Wales, AU)
Conference Guide
Steering Committee
Jürgen Becker (Karlsruher Institut für Technologie, DE)
Koen Bertels (Technische Universiteit Delft, NL)
Eduardo Boemo (Universidad Autónoma de Madrid, ES)
João Cardoso (Universidade do Porto, PT)
Peter Cheung (Imperial College London, UK)
Martin Danek (Daiteq, CZ)
Apostolos Dollas (Technical University of Crete, GR)
Fabrizio Ferrandi (Politecnico di Milano, IT)
Manfred Glesner (Technische Universität Darmstadt, DE)
John Gray (Consultant, UK)
Reiner Hartenstein (Technische Universität Kaiserslautern,
DE)
Andreas Herkersdorf (Technische Universität München, DE)
Udo Kebschull (Goethe Universität Frankfurt, DE)
Wayne Luk (Imperial College London, UK)
Patrick Lysaght (Xilinx, US)
Jari Nurmi (Tampereen Teknillinen Yliopisto, FI)
Lionel Torres (Université de Montpellier 2, FR)
Jim Tørresen (Universitetet i Oslo, NO)
Technical Programme Committee
Norbert Abel (Endace, NZ)
Tanvir Ahmed (Tokyo Institute of Technology, JP)
Hideharu Amano (Keio University, JP)
Kubilay Atasu (IBM Research, CH)
Peter Athanas (Virginia Tech, US)
Jürgen Becker (Karlsruher Institut für Technologie, DE)
Tobias Becker (Maxeler Technologies, UK)
Pascal Benoit (Université Montpellier 2, FR)
Mladen Berekovic (Technische Universität Braunschweig, DE)
Neil Bergmann (University of Queensland, AU)
Dustyn Blasig (National Instruments, US)
Michaela Blott (Xilinx, IE)
Christophe Bobda (University of Arkansas, US)
Eduardo Boemo (Universidad Autónoma de Madrid, ES)
Cristiana Bolchini (Politecnico di Milano, IT)
51
Christos-Savvas Bouganis (Imperial College London, UK)
Eli Bozorgzadeh (University of California Irvine, US)
Gordon Brebner (Xilinx, IE)
Philip Brisk (University of California Riverside, US)
Steve Brown (Altera, CA)
Oswaldo Cadenas (University of Reading, UK)
João Cardoso (Universidade do Porto, PT)
Benjamin Schafer (Hong Kong Polytechnic University, HK)
Luigi Carro (Universidade Federal do Rio Grande do Sul, BR)
Jerónimo Castrillón (Technische Universität Dresden, DE)
Deming Chen (University of Illinois at Urbana-Champaign, US)
Ray Cheung (City University of Hong Kong, HK)
Kiyoung Choi (Seoul National University, KR)
Paul Chow (University of Toronto, CA)
Christopher Claus (Bosch, DE)
Jason Cong (University of California Los Angeles, US)
Philippe Coussy (Université de Bretagne Sud, FR)
José Coutinho (Imperial College London, UK)
René Cumplido (Instituto Nacional de Astrofisica, MX)
Martin Danek (Daiteq, CZ)
Anup Das (University of Southampton, UK)
Eduardo De La Torre (Universidad Politécnica de Madrid, ES)
Christian De Schryver (Universität Kaiserslautern, DE)
Steven Derrien (Université de Rennes 1, FR)
Oliver Diessel (University of New South Wales, AU)
Giorgos Dimitrakopoulos (Democritus University of Thrace,
GR)
Pedro Diniz (University of Southern California, US)
Apostolos Dollas (Technical University of Crete, GR)
Adam Donlin (Xilinx, US)
Carl Ebeling (Altera, US)
Peeter Ellervee (Tallinna Tehnikaülikool, EE)
Suhaib Fahmy (Nanyang Technological University, SG)
Claudia Feregrino (Instituto Nacional de Astrofísica, Óptica y
Electrónica, MX)
Fabrizio Ferrandi (Politecnico di Milano, IT)
William Fornaciari (Politecnico di Milano, IT)
Blair Fort (Altera, US)
Georgi Gaydadjiev (Maxeler Technologies, UK)
Roberto Giorgi (Università di Siena, IT)
Conference Guide
Manfred Glesner (Technische Universität Darmstadt, DE)
Diana Göehringer (Ruhr-Universität Bochum, DE)
Guy Gogniat (Université de Bretagne Sud, FR)
Maya Gokhale (Lawrence Livermore National Laboratory, US)
Kees Goossens (Technische Universiteit Eindhoven, NL)
Ann Gordon-Ross (University of Florida, US)
Marcel Gort (Altera, CA)
David Greaves (University of Cambridge, UK)
Jonathan Greene (Microsemi, US)
Yajun Ha (National University of Singapore, SG)
Peter Hallschmid (University of British Columbia, CA)
Ilker Hamzaoglu (Sabanci Üniversitesi, TR)
Yuko Hara-Azumi (Tokyo Institute of Technology, JP)
Reiner Hartenstein (Technische Universität Kaiserslautern,
DE)
Martin Herbordt (Boston University, US)
Andreas Herkersdorf (Technische Universität München, DE)
Eddie Hung (Imperial College London, UK)
Arpith Jacob (IBM Research, US)
Nachiket Kapre (Nanyang Technological University, SG)
Sinan Kaptanoglu (Microsemi, US)
Wolfgang Karl (Karlsruher Institut für Technologie, DE)
Ryan Kastner (University of California San Diego, US)
Alireza Kaviani (Xilinx, US)
Tom Kean (Algotronix, UK)
Udo Kebschull (Goethe Universität Frankfurt, DE)
Andrew Kennings (University of Waterloo, CA)
Kenneth Kent (University of New Brunswick, CA)
Yoonjin Kim (Sookmyung Women‘s University, KR)
Kenji Kise (Tokyo Institute of Technology, JP)
Vipin Kizheppatt (Mahindra École Centrale, IN)
Andreas Koch (Technische Universitát Darmstadt, DE)
Jan Korenek (Brno University of Technology, CZ)
Farinaz Koushanfar (Rice University, US)
Yana Krasteva (Universitat Politècnica de València, ES)
Wolfgang Kühn (Justus-Liebig-Universität Gießen, DE)
Akash Kumar (National University of Singapore, SG)
Jan Kuper (Universiteit Twente, NL)
53
Georgi Kuzmanov (Electronic Components and Systems for
European Leadership Joint Undertaking, BE)
Martin Langhammer (Altera, US)
Luciano Lavagno (Politecnico di Torino, IT)
Jongeun Lee (Ulsan National Institute of Science and Technology, KR)
Miriam Leeser (Northeastern University, US)
Guy Lemieux (University of British Columbia, CA)
Philip Leong (University of Sydney, AU)
Enno Lübbers (Intel Labs, DE)
Mikel Luján (University of Manchester, UK)
Patrick Lysaght (Xilinx, US)
Roman Lysecky (University of Arizona, US)
Wai-Kei Mak (National Tsing Hua University, TW)
Terrence Mak (The Chinese University of Hong Kong, HK)
Liam Marnane (University College Cork, IE)
Andrea Marongiu (Eidgenössische Technische Hochschule
Zürich, CH)
Tsutomu Maruyama (University of Tsukuba, JP)
Konstantinos Masselos (Imperial College London, UK)
Nele Mentens (Katholieke Universiteit Leuven, BE)
Antonio Miele (Politecnico di Milano, IT)
Tulika Mitra (National University of Singapore, SG)
Andrew Moore (University of Cambridge, UK)
Carlos Morra (Siemens, DE)
Brent Nelson (Brigham Young University, US)
Smail Niar (Université de Valenciennes, FR)
David Novo (École Polytechnique Fédérale de Lausanne, CH)
Gianluca Palermo (Politecnico di Milano, IT)
Ioannis Papaefstathiou (Technical University of Crete, GR)
Sri Parameswaran (University of New South Wales, AU)
Joonseok Park (Inha University, KR)
Yongjun Park (Hongik University, KR)
Cameron Patterson (Virginia Tech, US)
Christian Pilato (Columbia University, US)
Sébastien Pillement (Université de Nantes, FR)
Thilo Pionteck (Universität zu Lübeck, DE)
Christian Plessl (Universität Paderborn, DE)
Dionisios Pnevmatikatos (Technical University of Crete, GR)
Conference Guide
Mario Pormann (Universität Bielefeld, DE)
Dan Poznanovic (Cray, US)
Viktor Prasanna (University of Southern California, US)
Rodric Rabbah (IBM Research, US)
Teresa Riesgo (Universidad Politécnica de Madrid, ES)
Jonathan Rose (University of Toronto, CA)
Kyle Rupnow (Advanced Digital Sciences Center, SG)
Mazen Saghir (Texas A&M University at Qatar, QA)
Chiara Sandionigi (Commissariat à l‘Énergie Atomique et aux
Énergies Alternatives, FR)
Kentaro Sano (Tohoku University, JP)
Marco Santambrogio (Politecnico di Milano, IT)
Ron Sass (University of North Carolina at Charlotte, US)
Martin Schoeberl (Danmarks Tekniske Universitet, DK)
Paul Schumacher (Xilinx, US)
Donatella Sciuto (Politecnico di Milano, IT)
Lukas Sekanina (Brno University of Technology, CZ)
Olivier Sentieys (Université de Rennes 1, FR)
Muhammad Shafique (Karlsruher Institut für Technologie, DE)
Lesley Shannon (Simon Fraser University, CA)
Nicolas Sklavos (University of Patras, GR)
Ioannis Sourdis (Chalmers Tekniska Högskola, SE)
Walter Stechele (Technische Universität München, DE)
Henry Styles (Xilinx, US)
Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg, DE)
Russell Tessier (University of Massachusetts Amherst, US)
David Thomas (Imperial College London, UK)
Tim Todman (Imperial College London, UK)
Hiroyuki Tomiyama (Ritsumeikan University, JP)
Lionel Torres (Université de Montpellier 2, FR)
Jim Tørresen (Universitetet i Oslo, NO)
Steve Trimberger (Xilinx, US)
Tom VanCourt (Altera, US)
Wim Vanderbauwhede (University of Glasgow, UK)
Ana Lucia Varbanescu (Universiteit van Amsterdam, NL)
Milan Vasilko (Aeon Ventures, UK)
Tanya Vladimirova (University of Leicester, UK)
Greece, GR)
55
Qiang Wang (Huawei, US)
John Wawrzynek (University of California Berkeley, US)
Norbert Wehn (Technische Universität Kaiserslautern, DE)
Markus Weinhardt (Hochschule Osnabrück, DE)
Steve Wilton (University of British Columbia, CA)
Mike Wirthlin (Brigham Young University, US)
Stephan Wong (Technische Universiteit Delft, NL)
Roger Woods (Queen‘s University Belfast, UK)
Sotirios Xydis (National Technical University of Athens, GR)
Yoshiki Yamaguchi (University of Tsukuba, JP)
Wei Zhang (Hong Kong University of Science and Technology,
HK)
Daniel Ziener (Friedrich-Alexander-Universität Erlangen-Nürnberg DE)
Peter Zipf (Universität Kassel, DE)
Conference Guide
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City Map
Conference Guide
59
Underground Map
Conference Guide
61
About London
London is the capital and most populous city of England and
the United Kingdom. Standing on the River Thames, London
has been a major settlement for two millennia, its history going
back to its founding by the Romans, who named it Londinium.
London’s ancient core, the City of London, largely retains its
1.12-square mile (2.9 km2) medieval boundaries and in 2011
had a resident population of 7,375, making it the smallest city
in England. Since at least the 19th century, the term London
has also referred to the metropolis developed around this core.
The bulk of this conurbation forms Greater London, a region
of England governed by the Mayor of London and the London
Assembly. The conurbation also covers two English counties:
the City of London and the county of Greater London.
Greater London consists of 33 districts: the 32 London boroughs and the City of London. The Greater London Authority
is responsible for strategic local government across the region
and consists of the Mayor of London and the London Assembly. Greater London is a ceremonial county of England. It was
created on 1 April 1965 and it covers 607 square miles (1,572
km2) and had a population of 8,174,000 at the 2011 census.
“Sir, when a man is tired of London, he is tired of life;
for there is in London all that life can afford.”
Samuel Johnson
Conference Guide
Elizabeth Tower (often incorrectly called Big Ben)
Bridge Street
SW1A 0AA
63
London Sights
British Museum
Founded in 1753, the British Museum’s remarkable collection
spans over two million years of human history. Enjoy a unique
comparison of the treasures of world cultures under one roof,
centred around the magnificent Great Court.
World-famous objects such as the Rosetta Stone, Parthenon
sculptures and Egyptian mummies are visited by up to six million visitors per year. In addition to the vast permanent collection, the museum’s special exhibitions, displays and events are
all designed to advance understanding of the collection and
cultures they represent.
The nearest Underground stations are Tottenham Court Road,
Holborn and Russell Square.
Entrance is free.
National Gallery
The National Gallery displays over 2,000 Western European
paintings from the middle ages to the 20th century. Discover inspiring art by Botticelli, Leonardo da Vinci, Rembrandt, Gainsborough, Turner, Renoir and Van Gogh. There are special exhibitions, lectures, video and audio-visual programmes, guided
tours and holiday events for children and adults.
The nearest Underground stations are Embankment, Charing
Cross and Leicester Square.
Entrance is free.
Conference Guide
British Museum
Great Russell Street
WC1B 3DG
National Gallery
Trafalgar Square
WC2N 5DN
65
Natural History Museum
See hundreds of exciting, interactive exhibits in one of London’s most beautiful landmark buildings. Highlights include the
popular Dinosaurs Gallery, Mammals Display with the unforgettable model blue whale and the spectacular Central Hall.
Don’t miss the state-of-the-art Darwin Centre Cocoon where,
on a self-guided tour, you can see hundreds of fascinating
specimens and look into laboratories where scientists are at
work.
The museum offers a wide-ranging programme of temporary
exhibitions and events, including chances to join experts in the
Darwin Centre’s high-tech Attenborough Studio in topical discussions about science and nature.
The nearest Underground station is South Kensington.
Entrance is free.
Tate Modern
A visit to London isn’t complete without a trip to the Tate Modern.
Britain’s national museum of modern and contemporary art
from around the world is housed in the former Bankside Power
Station on the banks of the Thames. The awe-inspiring Turbine Hall runs the length of the entire building and you can see
amazing work by artists such as Cézanne, Bonnard, Matisse,
Picasso, Rothko, Dalí, Pollock, Warhol and Bourgeois.
The nearest Underground stations are Southwark and Blackfriars.
Entrance is free.
Conference Guide
Natural History Museum
Cromwell Road
SW7 5BD
Tate Modern
Bankside
SE1 9TG
67
London Eye
Standing at 135 metres, the London Eye is the world’s tallest
cantilevered observation wheel. A feat of design and engineering, it has become the modern symbol representing the capital and a global icon. The experience showcases breathtaking
360-degree views of the capital and its famous landmarks.
The gradual rotation in one of the 32 high-tech glass capsules
takes approximately 30 minutes and gives you an ever-changing perspective of London. Within each capsule, interactive
guides allow you to explore the capital’s iconic landmarks in
several languages.
An experience on the London Eye will lift you high enough to
see up to 40 kilometres on a clear day and keep you close
enough to see the spectacular details of the city.
The nearest Underground stations are Westminster and Embankment.
Tickets start from £20.70.
Science Museum
The Science Museum is the most visited science and technology museum in Europe. There are over 15,000 objects on
display, including world-famous objects such as the Apollo 10
command capsule and Stephenson’s Rocket.
The interactive galleries bring to life first scientific principles
and contemporary science debates. Plus, you can experience
what it’s like to fly with the Red Arrows or blast off into space
on an Apollo space mission in the stunning 3D and 4D simulators or watch a film on a screen taller than four double-decker
buses in the IMAX 3D Cinema.
The nearest Underground station is South Kensington.
Entrance is free.
Conference Guide
London Eye
South Bank
SE1 7PB
Science Museum
Exhibition Road
SW7 2DD
69
Tower of London
Despite the Tower of London’s grim reputation as a place of
torture and death, within these walls you will also discover the
history of a royal palace, an armoury and a powerful fortress.
Don’t miss Royal Beasts and learn about the wild and wonderous animals that have inhabited the Tower, making it the first
London Zoo.
Discover the priceless Crown Jewels newly displayed in 2012,
join an iconic Beefeater on a tour and hear their bloody tales,
stand where famous heads have rolled, learn the legend of the
Tower’s ravens, storm the battlements and get to grips with
swords and armour and much more!
The nearest Underground station is Tower Hill.
Tickets start from £22.00.
Tower of London
Mansell Street
EC3N 4AB
Conference Guide
71
About Imperial College London
Imperial College London is a public research university in the
United Kingdom. Its royal patron and founder, Prince Albert,
envisioned an area for public education composed of the Natural History Museum, Victoria and Albert Museum, Science Museum, Royal Albert Hall and the Imperial Institute. The Imperial
Institute was opened by his wife, Queen Victoria, who laid the
first brick. Continuing their parents’ and grandparents’ vision,
Queen Elizabeth II and the Duke of York recently opened the
Imperial College Business School. The university has grown
through mergers including with St Mary’s Hospital Medical
School, Charing Cross and Westminster Medical School, the
Royal Postgraduate Medical School and the National Heart
and Lung Institute. A former constituent college of the University of London, Imperial became independent during its centennial celebration.
Imperial is organised into four faculties of science, engineering, medicine and business. The main campus is located in
South Kensington. The university is a major biomedical research centre and formed the first academic health science
centre in the United Kingdom. Imperial is a member of the Russell Group, G5, Association of Commonwealth Universities,
League of European Research Universities and the “Golden
Triangle” of British universities along with the Universities of
Cambridge and Oxford.
Imperial is consistently included among the top universities in
the world. According to The New York Times, recruiters consider its students among the 10 most valued groups of graduates in the world. Imperial faculty and alumni include 15 Nobel
laureates, 2 Fields Medalists, 70 Fellows of the Royal Society,
82 Fellows of the Royal Academy of Engineering and 78 Fellows of the Academy of Medical Sciences.
Conference Guide
Imperial College London Royal School of Mines
Prince Consort Road
SW7 2BP
Imperial College London Business School
Exhibition Road
SW7 2AZ
73
About the Royal Institution
The Royal Institution was founded in 1799 by the leading British scientists of the age, including Henry Cavendish and its
first president, George Finch, the 9th Earl of Winchilsea, for
diffusing the knowledge, and facilitating the general introduction, of useful mechanical inventions and improvements; and
for teaching, by courses of philosophical lectures and experiments, the application of science to the common purposes of
life.
Much of its initial funding and the initial proposal for its founding were given by the Society for Bettering the Conditions and
Improving the Comforts of the Poor, under the guidance of
philanthropist Sir Thomas Bernard and American-born British
scientist Sir Benjamin Thompson, Count Rumford. Since its
founding it has been based at 21 Albemarle Street in Mayfair.
Its Royal Charter was granted in 1800.
Throughout its history, the Institution has supported public
engagement with science through a programme of lectures,
many of which continue today. The most famous of these are
the annual Royal Institution Christmas Lectures, founded by
Michael Faraday.
The Institution has had an instrumental role in the advancement of science since its founding. Notable scientists who
have worked there include Sir Humphry Davy (who discovered
sodium and potassium), Michael Faraday, James Dewar, Sir
William Henry Bragg and Sir William Lawrence Bragg (who
jointly won the Nobel Prize for their work on X-ray diffraction),
Max Perutz, John Kendrew, Antony Hewish and George Porter. In the 19th century, Faraday carried out much of the research which laid the groundwork for the practical exploitation
of electricity at the Royal Institution. In total, fifteen scientists
attached to the Royal Institution have won Nobel Prizes. Ten
chemical elements including sodium were discovered there,
the electric generator was devised at the Institution, and much
of the early work on the atomic structure of crystals was carried
out within it.
Conference Guide
Royal Institution
Albermarle Street
W1S 4BS
75
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