Catapult C Synthesis Work Flow Tutorial

Catapult C Synthesis Work Flow Tutorial
ELEC 522 Advanced VLSI Design, Rice University
Version 1.3
10/14/2010, Guohui Wang
Introduction
In this tutorial, you will go through the complete work flow of Catapult C Synthesis, including bit
accurate C program simulation, HDL generation, ModelSim/ISE Simulator simulation/verification, and
integration with System Generator. You will build a simple sum of square computation block using
Catapult C tool.
Objectives
After this tutorial lab, you will be able to:




Write C/C++ code in Catapult C. Compile and simulate the C/C++ code using GCC;
Use Catapult C to generate HDL code;
Simulate/Verify the generated HDL model in ModelSim/ISE built-in Simulator;
Integrate the HDL model into System Generator design by using the Black-box block. Then simulate
a complete system in System Generator.
Design Description
Use Catapult C Synthesis to implement a “sum of square” computation:


Computation equation: c = a*a + b*b;
Data type: a and b are both 16bit fixed-point numbers; c is 34bit number.
Tools Used in This Lab
In this lab, we will use the following tools:






Mentor Graphics Catapult C Synthesis 2009a.85
GCC 4.2.2
Xilinx ISE 10.1.3
ModelSim SE6.5c
Xilinx System Generator 10.1
MATLAB 2008a
ELEC 522 Catapult C Synthesis Work Flow Tutorial
ECE Department, Rice University
Page 1
Procedure
This tutorial comprises 6 primary steps:
1.
2.
3.
4.
5.
6.
Create a new Catapult project. Write C++ code in Catapult C;
Simulate C++ code using GCC;
Generate Verilog HDL code in Catapult;
Simulate/Verify HDL model in ModelSim/ISE-simulator;
Synthesize your HDL model using Xilinx ISE;
Use black-box to integrate the HDL model into System Generator and simulate the complete system
in System Generator.
Please notice that the goal of this document is only to show the basic tool flow. Therefore, we do not
optimize our design. In your project design, you might need to go back and forth for a couple of iterations
between step 1 and step 4 to optimize your design. Besides, in this simple tutorial I have not considered
the interface optimization. In your project, you need to consider the interface design, for example, pointer
VS non-pointer interfaces.
STEP 1: C Programming in Catapult C Synthesis
 Create a new folder. Start the Catapult tool on the Linux server. Then create a new project in Catapult.
Click “Set Working Directory”, in the popup dialog select the folder you just created.
 In the menu, select File->New to create a new file. Type in the code below:
Select File->Save as, to save this file as “example.h”.
//Include Catapult bit accurate types
#include "ac_int.h"
int34 sumsquare(int16 a, int16 b);
Data type uint34 has been defined in ac_int.h: typedef ac_int<34, true> uint34;
 Then create another new file, type in the following code, then save it as “example.cpp”.
#include "example.h"
#pragma hls_design top
int34 sumsquare(int16 a, int16 b)
{
int34 c = 0;
c = a * a + b* b;
return c;
}
ELEC 522 Catapult C Synthesis Work Flow Tutorial
ECE Department, Rice University
Page 2
In thhe cpp file, thhe header fille is includedd at the beginning. Then ‘hls_design top’ pragmaa is used to ttell
Cataapult tool thaat this kernell function is the top leveel design forr the HDL model.
m
Finally, the functiion
sumssquare( ) is ddefined.
 From
m the task baar, click “Settup Design”. If Catapult says “Passedd Analyze”, it means there is no synttax
errorr in your codde. Otherwiise, the tool shows you tthe error(s). This could help
h
you quicckly debug the
t
syntaax error in yoour code.
S
Step 2: Siimulate C
C++ Code
e Using GC
CC
 Thenn we need too use GCC too simulate yyour C++ codde. Create a new file, typpe the follow
wing code, aand
savee it as “exam
mple_tb.cpp””. This is ouur testbench in C++ langguage. Basiccally, in this testbench, we
w
geneerate some test values, andd then print tthe calculatioon results on the terminal.
#include <
<stdio.h>
#include "
"example.h"
"
int
main(
() {
int16 aa = 0;
int16 bb = 0;
int34 cc = 0;
for ( int i = 0;
; i < 10; i++
i
) {
aa
a = i;
bb
b = i+1;
cc
c = sumsqua
are(aa, bb);
pr
rintf ( "#%
%d: %d^2 + %d^2 = %d\
\r\n", i, a
aa.to_int(), bb.to_int
t(),//
cc.to_int6
64());
}
return
n 0;
}
o
In this fi
file, ‘//’ is ussed when yoou need to brreak one staatements intoo two lines, and it tells tthe
compilerr that the stattement is not finished andd will continuue in the nextt line.
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
Page 3
o
Since aa, bb, cc are all Algorithmic C datatypes, they are not supported by standard printf( )
function. In order to print the values of aa and bb, you need to use a member method to_int( ) of
the Class int16 to convert int16 datatype to the C++ int datatype, so that we could print the value
through printf( ) function. Because cc is a 34bit number, if you convert it to the C++ int type, you
will lose 2bits’ information. Therefore, you should use the member method to_int64( ) to convert
int34 into C++ long long int datatype. (Please refer to the Chapter 2 in the document
“Algorithmic C Datatypes”)
 In order to compile the code using GCC, we need a Makefile. We could modify the Makefile from tutorial
lab2. Finally, your Makefile will look like this:
# Makefile for example_tb.cpp
CPP
= /usr/bin/g++
INCLUDE = -I ${MGC_HOME}/shared/include
TARGET
OBJECTS
= example
= example.o example_tb.o
${TARGET}: ${OBJECTS}
${OBJECTS}: example.cpp example_tb.cpp example.h Makefile
%.o : %.cpp
${CPP}
-c ${INCLUDE} $<
${TARGET}: ${OBJECTS}
${CPP} ${OBJECTS} ${LINKARGS} -o $@
clean:
rm -rf *.o ${TARGET}
Notice that, ${MGC_HOME} is an environment variable that points to the install path of Mentor
Graphics Catapult C Synthesis. This environment varialble has been set when you log in the Linux server.
In the .tcshrc file under your home directory, you source several setup scripts, and one of them sets the
MGC_HOME environment variable.
 At the Linux prompt, use “make” command to compile the testbench code. You will get an executable file
named “example”. Run the executable file, you can see the printed results.
ELEC 522 Catapult C Synthesis Work Flow Tutorial
ECE Department, Rice University
Page 4
 It is clear that thee simulation results are coorrect. So farr, we have finnished the C+
++ code simuulation.
S
Step 3: Generate V
Verilog H
HDL Code
e in Catap
pult C Syn
nthesis
 Conffigure your design
d
for Xiilinx FPGA, V
Virtex-II Proo 2VP30ff8966-7, set the fr
frequency to 100MHz. Thhen
clickk Apply buttoon.
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
Page 5
 Sincce you have more than one cpp filee, you need to set one as the HLS top level fiile. Select “IInt
sumssquare” funcction, and cheeck the “Top Design” boxx. Then clickk Apply.
 Clickk “Architectuure constrainnts” in the taask bar on thhe left. Confi
figure the arcchitecture parrameters. Thhen
clickk “Schedule”” to check thee Gantt chartt. In your prooject design, you need too check the tiiming scheduule
in thhe Gantt charrt. Based on the
t schedule results, you might need tto go back too “Architectuure constraintts”
to chhange the arcchitecture parrameters to ooptimize yourr design.
Heree, we just sim
mply change tthe Design goal
g from ‘areea’ to ‘latenccy’.
Thenn we pipelinee the ‘sumsquuare_main’ loop.
 From
m the menu, in Tools->Seet options->O
Output->Outpput format, ccheck the boxx for “Veriloog”. Then cliick
Apply & Save.
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C 522 Catapultt C Synthesis W
Work Flow Tu
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ECE Departmentt, Rice Univerrsity
Page 6
Generate RTL”. In the Output
O
Files folder, you can check the reports ffor timing aand
 Finaally, click “G
resouurce usage. Verilog
V
HDL
L RTL modell is generatedd. You can also check the schematics ffor your desiign
as well
w as the crittical path.
S
Step 4: Siimulate//Verify HD
DL Model in Mode
elSim/ISE
E-simulattor
In orrder to simullate/verify thhe Verilog HD
DL code gennerated by Caatapult, you could write a Verilog HD
DL
testbbench. However, the ISE tool providees a graphic-based testbennch editor thhat could hellp you generaate
the ttestbench eassily. In this sstep, you willl use ISE to generate a ttestbench waaveform. Theen you can edit
the waveform
w
annd use it to sim
mulate the H
HDL model.
Afteer that, you w
will generate a Verilog HD
DL testbenchh based on the testbench w
waveform. Y
You will modiify
DL
the ttestbench fille and use iit to simulate our modell. The reasoon why you still need a Verilog HD
testbbench is thaat the text-baased testbennch is muchh more flexiible so that you could generate moore
compplicated testt vectors. A
Another reasoon is that bby using a ttext-based teestbench you could insert
breakkpoints in thhe testbench and debug thhe testbench just like debbugging a C+
++ program in Visual C+
++.
You are allowed to step over your testbennch and checkk the value inn each registeer.
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
Page 7
Sttep (1): Creaate a new ISEE project Step
p (2): Impo
ort RTL fiile Sttep (5): Geenerate V
Verilog Tesstbench Step
p (6): Modiffy the Verilog Testb
bench Step (3): Createe a testbench orm wavefo
Step (4): Simulaate using tthe wavefo
orm Step (7): Simulatee using the Veerilog Testbench In thhis step, you w
will learn to use Xilinx IS
SE, ISE simuulator and MoodelSim to siimulate yourr HDL modell.
ISE simulator (IS
Sim) is a sim
mulation tools which is buuilt in the Xiilinx ISE toool. It has a w
waveform edittor
that allows you to generate a simulation teestbench quiickly in an innteractive wayy. The HDL simulation can
c
be ann even more fundamentall step within your designn flow with thhe tight integgration of thee ISE Simulattor
withhin your desiggn environmeent. For moree details, please check htttp://www.xilinx.com/toolls/isim.htm.
ModdelSim is onee of the mostt powerful siimulation andd verificationn tools in thee CAD indusstry. It providdes
a unnified debug environmentt for Verilog, VHDL andd SystemC. Good
G
standarrds and platfform support in
the iindustry makke it easy too adopt in thhe majority of
o process annd tool flows. For more details, pleaase
checck www.moddel.com/conteent/modelsim
m-se-high-perrformance-simulation-andd-debug.
In thhis step, you will first usee ISE to buildd a new project. Then thee methods off using ISim and ModelSim
to sim
mulate the H
HDL model arre introducedd, respectivelly.
 Startt Xilinx ISE on the Winndows PC. C
Create a new ISE projectt. Set the prooject configuuration like the
t
figurre below.
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
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 Copyy rtl.v and rrtl_mgc_iopoort.v from thhe Catapult pproject foldeer into the ISE project ffolder (we juust
creatted in the prrevious step)). The reasonn why we need
n
the rtl_m
mgc_ioport.vv file is that we have ussed
‘mgcc_in_wire’, ‘mgc_out_sstdreg’ interrfaces in oour design (please reffer to lab3 for detaills).
rtl_m
mgc_ioport.vv defines the V
Verilog moddel for these iinterfaces.
 Now
w your top moodule shouldd be ‘sumsquaare’. The moodule with a
If noot, please righht click ‘sum
msquare’ and select ‘Set ass top modulee’.
 Righht click
‘exam
mple_rtl_tb’.
icon in front of it is the top moduule.
, select ‘A
Add new sourrce’. Add a new
n Test Beench Waveforrm. Name it as
 Clickk Next buttonn, then you nneed to assign the Unit U
Under Test (U
UUT) for thiss testbench. H
Here, since yyou
wantt to verify thee top level m
module, selectt ‘sumsquaree’, click Nextt, then click F
Finish.
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C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
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 In thhe ‘Initial Tim
ming and Cloock Wizard’,, just keep thhe default vallue and clickk Finish. Oncce finished, yyou
will see the waveeform as beloow:
This is the testbeench waveforrm. The clocck is already set for you. You could edit the input value for ‘rsst’,
‘a_rssc_z’ and ‘b__rsc_z’. Youu might noticce that the sim
mulation tim
me is a little short.
s
We couuld change thhis
by right clickingg the wavefoorm; select ‘S
Set the end of Test Bench’. In the ppop-up dialog, input a neew
simuulation time. In this exam
mple, input 50000 ns.
 Righht click the w
waveform, inn the menu, sselect Decim
mal for the daata display foor each inputt. Then edit the
t
waveeform as thee picture beloow (*). Notiice that the module
m
is reeset at the beeginning of tthe simulatioon.
Thenn some inputt values are ggiven to ‘a_rssc_z’ and ‘b__rsc_z’ input ports. Finallly, save the w
waveform.
(*Please refer to the ISim Useer Guide for the details aabout using thhe ISim GUI.
I.)
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
Page 10
ISim and MoodelSim simulation, the procedures above are the same; tthe
(*Please notice:: for both IS
folloowing steps w
will be differeent.)
ISim
m Simulaation Proccedure:
 In thhe source tabb, select ‘Beehavior simuulation’. Seleect ‘examplee_rtl_rb’ by clicking it. Then you will
w
noticce under the P
Process tab, there is a new
w item calledd ‘Xilinx ISE
E Simulator’.
 Doubble click ‘Sim
mulate Behaavioral Model’ to start thee simulation. You can seee that the ressults are correect
and the timing aalso met ourr expectationn. By far, yoou have finiished simulaation/verificattion using IS
SE
simuulator.
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
Page 11
 Nextt, you will geenerate a Verrilog HDL teestbench and use it to runn the simulatiion. Select ‘eexample_rtl_ttb’
in Soource tab in the process tab.
t Double cclick ‘View Generated T
Testbench As HDL’, yourr testbench will
w
be oppen as a textt, but it is reaad-only now.. From the m
menu, select F
File->Save ass, save it as a Verilog HD
DL
file ((extension .vv) using a diffferent name, such as ‘exaample_rtl_tb__text.v’. Now
w you are alloowed to edit it.
 From
m the menu F
File->Projectt->Add Sourrce, add the ffile ‘examplee_rtl_tb_text..v’ into the project.
p
Modify
the testbench
t
as bbelow. In this example, tw
wo new grouups of input vvalues are addded. Save yoour changes.
 Select the Veriloog HDL testtbench in Soource tab by clicking it. Then doublee click ‘Sim
mulate Behavior
Moddel’, you coulld see the sim
mulation resuults for your new
n input.
By ffar, you have finished sim
mulation usingg ISim. Nextt, you will leaarn how to siimulate usingg ModelSim.
ELEC
C 522 Catapultt C Synthesis W
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utorial
ECE Departmentt, Rice Univerrsity
Page 12
MoodelSim Siimulation
n Procedu
ure:
Assuume you havve two testbbench files nnow: one is the waveforrm testbenchh, and the otther is the teext
Veriilog testbenchh. You couldd start the MoodelSim simuulation with eeither testbennch, since thee method is tthe
samee.
u need to sett the path oof ModelSim
m simulatorr. Then selecct ModelSim
m as the sim
mulator in tthe
You
projject propertties*. You allso need to compile thee HDL simu
ulation libraaries that will
w be used by
Mod
delSim*. (*N
Notice: these settings needd to be done only once forr each ISE prroject.)
 Righht click the prroject name ‘xc2vp30-7fff896’, select ‘Properties’ in the pop-uup menu. Sett the ‘Simulattor’
optioon to ‘ModellSim-SE Veriilog’.
 Nextt, you need to set the paath for ModelSim simulaator in ISE tool so that you could start
s
ModelSim
simuulation from ISE projectt. Go to mennu Edit->Preeferences->ISE General-->Integrated Tools, for tthe
optioon ‘Model Teech Simulatoor’, click the browse buttoon, then selecct ‘modelsim
m.exe’ in the ffollowing paath :
C:\m
modeltech_6.5c\win32. Once you finissh, It should be like this:
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
Page 13
M
sim
mulation. Sellect the curreent
 Nextt you need too compile thhe HDL simuulation libraries for the ModelSim
projeect by clickinng its name. In the ‘Processes’ panel,, expand the menu under the ‘Design Utilities’. Y
You
will see ‘Compille HDL Simuulation Libraaries’. Right click it, seleect the ‘Propperties’ optioon in the mennu.
Set tthe “Simulatoor Path” to thhe folder wheere ModelSim
m.exe is instaalled.
 Startt compiling H
HDL simulattion libraries by double cllicking ‘Com
mpile HDL Simulation Liibraries’. If yyou
havee configured all the settinggs above corrrectly, the coompiling process will finiish in a whilee.
u have finished all the coonfiguration
ns needed to start a Mod
delSim simullation. Now,, you can staart
You
the ssimulation. T
The followin
ng steps are almost the ssame as you did in the IS
Sim simulation.
 Channge the ‘Souurces for’ opttion in the ‘S
Sources’ paneel to ‘Behaviioral Simulattion’. Click your
y
simulatiion
testbbench ‘exampple_rtl_tb’. Either
E
the texxt testbench oor the wavefform testbencch is fine, beecause they are
a
essenntially the saame.
ELEC
C 522 Catapultt C Synthesis W
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utorial
ECE Departmentt, Rice Univerrsity
Page 14
Finaally, double cclick ‘Simulaate Behavioraal Model’ too start the MoodelSim sim
mulation. Youu can check tthe
simuulation results in the ModdelSim windoows (*). ModdelSim has m
more powerfuul debugging and simulatiion
toolss that can heelp you speed up your design/simula
d
ation processs. (*Please reefer to the M
ModelSim Usser
Guidde for the dettails about ussing the ModdelSim GUI.)
By nnow, you havve become fa
familiar with simulating aan RTL moddel using ISim
m and ModeelSim. And yyou
havee also learnt how to gennerate and modify
m
the V
Verilog testbbench from a graphic-baased waveforrm
testbbench. Therefore, you aree able to dessign more coomplicated ttestbenches ffor your ownn design in tthe
samee way.
ELEC
C 522 Catapultt C Synthesis W
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ECE Departmentt, Rice Univerrsity
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S
Step 5: Sy
ynthesis Your Dessign in IS
SE & Post--route Sim
mulation
n
In thhe previous sttep, you havee learnt how to simulate tthe HDL moodel. In this step, you willl synthesize tthe
HDL
L model so that
t
you couuld get the syynthesis resuults for timinng and hardw
ware resourcce informatioon.
Afteer synthesizinng the HDL model,
m
you ccould also doo post-route ssimulation (in the previouus step you ddid
a behhavioral simuulation).
 Still in ISE, channge Source taab back to ‘IImplementatiion’, then select ‘sumsquuare’ modulee in Source taab.
w.
Doubble click ‘Syynthesize-XST’ in the proocess window
 Norm
mally, you w
will pass the ‘Synthesize-X
XST’ step.
How
wever, sometiimes, you wiill get errors as
a below:
Go tto the line whhich causes thhe error, youu will notice tthe followingg statements:
The reason why you got thiss error is thaat ‘X’ (“Unkknown”) or ‘Z’
‘ (“High impedance”) values are nnot
synthhesizable, allthough they could be ussed in simulaation/verificaation (A synnthesizable model
m
is a veery
impoortant conceppt in Verilogg HDL. Pleasse refer to thee Verilog tuttorial or mannual for detaiils.). Therefoore,
you need to modify the HDL code.
Usuaally, there arre around 5~66 these kind of errors in tthe code. Thhe modificatioon is simple,, just removee “|
32’bbX”, as show
wn below. Deebug all the errors using this methodd, and you will
w now get a synthesizabble
HDL
L model.
 Syntthesize your m
model, and thhen check thhe synthesis report.
r
 Oncee you have synthesized the model, you can staart post-routte simulationn by selectinng ‘Post-Rouute
Simuulation’ in thhe ‘Source’ panel. In poost-route sim
mulation, yourr design is ssimulated wiith all kinds of
delayys (circuit, roouting, load etc)
e so that itt is able to prrovide more accurate
a
simuulation resultts to you.
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C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
Page 16
Post-route simulaation result iss shown beloow:
Let uus look at thiis waveform more closelyy:
Betw
ween the clocck rising edgge and the chhanging poinnt of out_rsc__z (from 0 too 5), there iss a 4ns latenccy,
that is because thhe post-routee simulation model alreaady counts thhe latency off the actual ddata path. Y
You
could compare thhe post-routee simulation result with the behaviorral simulation result by zzooming in tthe
waveeform closelyy.
Simiilarly, you coould also run the post-rouute simulationn in ModelSiim. The methhod is the sam
me as in Stepp 4.
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C 522 Catapultt C Synthesis W
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ECE Departmentt, Rice Univerrsity
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Step 6: Integrate HDL Model into System Generator
In this step, you will integrate the HDL model into System Generator by using the Black-Box block. Then
you could verify your design in a System Generator project.
At first, you need to create a skeleton file, which contains the Verilog HDL module with only module
definition and interface declaration. This skeleton will tell System Generator Black Box block the basic
information of you HDL model, so that System Generator will generate a configuration file for your HDL
Black Box automatically. Once you have the configuration file for your Black Box, you need to replace
the skeleton file with your synthesizable Verilog HDL file from Step 5.
 Create a new folder for the System Generator project. Create a new skeleton file, and name it as ‘rtl.v’
(*Notice: the name should be the same as your RTL model.). Copy your RTL model definition into this
file (Please just copy the module definition; in other words, there is only an empty module with interface
definition but doing nothing). In our example, the definition of the RTL model is shown as below:
module sumsquare (
a_rsc_z, b_rsc_z, sumsquare_out_rsc_z, clk, rst
);
input [15:0] a_rsc_z;
input [15:0] b_rsc_z;
output [33:0] sumsquare_out_rsc_z;
input clk;
input rst;
endmodule
 Add an input ‘ce’ (clock enable signal) in the model, your code should look like this:
module sumsquare (
a_rsc_z, b_rsc_z, sumsquare_out_rsc_z, clk, ce, rst
);
input [15:0] a_rsc_z;
input [15:0] b_rsc_z;
output [33:0] sumsquare_out_rsc_z;
input clk;
input ce;
input rst;
endmodule
Clock and clock enable ports in black box HDL must appear as pairs . Each clock name (respectively,
clock enable name) must contain the substring clk, for example my_clk_1 and my_ce_1.
(Please refer to System Generator User Guide, Chapter 4: Importing HDL Modules.)
 Run MATLAB. Create a new System Generator model in the same folder with your empty module
definition file. Add a ‘Black Box’ from the Simulink Library Browser. In the pop-up dialog, select the
empty module ‘rtl.v’. System Generator will generate a Black Box block for you.
ELEC 522 Catapult C Synthesis Work Flow Tutorial
ECE Department, Rice University
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Now
w, you are cloose to finisheed.  There are only a few more stepss left.
 Copyy your synthhesizable HD
DL model ‘rtll.v’ into this folder, replaace the emptyy module file. Copy all tthe
codee in ‘rtl_mgcc_ioport.v’ too the end off ‘rtl.v’. Rem
member to addd the ‘ce’ iinput port foor the top levvel
moddule of your design,
d
since clock enablee is expected by System Generator.
G
 Doubble click the black box bllock, select ‘IISE simulatoor’ for simulaation mode.
Now
w you have suuccessfully m
made a Blackk Box for ourr Catapult design. It is reaady for simullation. You can
c
use tthis Black Boox just as youu use other S
Simulink bloccks.
 Creaate a complette System Geenerator systeem, and simuulate it:
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C 522 Catapultt C Synthesis W
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ECE Departmentt, Rice Univerrsity
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We could
c
also geet the resourcce estimationn from System
m Generator:
Conggratulations! By now, youu have finishhed the compplete work floow of Catapuult.
For the
t next step, you could ggo back to Caatapult, try too change the architecture constraints ffor the Catapult
projeect and simullate your new
w model.
ELEC
C 522 Catapultt C Synthesis W
Work Flow Tu
utorial
ECE Departmentt, Rice Univerrsity
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