Allegro Sigrity Update

Allegro Sigrity Update
Brad Griffin
Sigrity Product Marketing
CDNLive Taiwan 2015
Agenda
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Review Allegro® Sigrity™ solution—2012 to 2015
What’s new with 2015 Sigrity signal integrity
What’s new with 2015 Sigrity power integrity
New products: 2015 Sigrity solution
Roadmap
Summary
© 2015 Cadence Design Systems, Inc. All rights reserved.
Sigrity solution—release history and roadmap
• Sigrity™ Solution
(2012)
• Sigrity Solution
(2013 – 2014)
− 12.0: Sigrity tools
available in SAM
catalog
− Cadence “branding”
− 12.06: Sigrity tools
available in SAM
catalog
− Established poweraware SI, serial-link
SI, power integrity
optimization and
signoff, and
package
assessment and
extraction bundles
− Sold through
Cadence pricebook
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© 2015 Cadence Design Systems, Inc. All rights reserved.
‒ New SI product line
featuring Allegro®
Sigrity SI Base +
options
‒
‒
Sigrity products
launched from Allegro
design/analysis
environment
Bundles sold as options
to base
‒ Four update
releases
‒
‒
‒
Sigrity PI Base + option
released
SPD interface enhanced
to save time and provide
enhanced integration
SI solution advanced
with DDR4 support
‒
‒
SerDes compliance kits
System Explorer added
to Sigrity SystemSI™ and
package modeling
solution
• Sigrity Solution
(2015)
‒
New products
‒ Four-packs
‒ System Explorer
‒ Combo products
‒
New features
‒
‒
‒
‒
LPDDR4 support
HDMI 2.0 compliance kit
Package partitioning
Adding decoupling
capacitors (decaps)
‒ Three quarterly
updates planned
‒ Mid-May, mid-August,
mid-November
‒ Sigrity PowerSI® Wizard
‒ Quasi-static solver
‒ AMI model building
technology
‒ Power integrity flow
enhancements
Roadmap data is provided for informational purposes only and does not
represent a commitment to deliver any of the features or functionality discussed
What’s New: Allegro Sigrity SI Base +
Options
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity signal integrity solution
Base + option
• Allegro® Sigrity™ SI Base solution enables constraint-driven design
• Options for detailed analysis, compliance, and assessment using Sigrity technology
• Sigrity
package
analysis
technology
• Sigrity
memory
interface
analysis
technology
• Sigrity
multi-gigabit
analysis
technology
Allegro Sigrity SI Base
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Options for Allegro Sigrity SI Base
Power-Aware SI
Option
Serial Link SI Option
Package Assessment and
Model Extraction Option
• SIGR011 Broadband SPICE
• SIGR011 Broadband SPICE
• SIGR031 CAD Translators
• SIGR021 T2B
• SIGR021 T2B
• SIGR201 Sigrity™ PowerDC™
technology
• SIGR031 CAD Translators
• SIGR031 CAD Translators
• SIGR301 Sigrity™ PowerSI®
technology
• SIGR301 Sigrity PowerSI
technology
• SIGR311 Sigrity 3DEM
• SIGR311 Sigrity 3DEM
• SIGR401 Sigrity SPEED2000™
technology
• SIGR506 Sigrity SystemSI
technology – SLA II
• SIGR311 Sigrity 3DEM
• SIGR801 Sigrity XtractIM™
technology
• SIGR570 Sigrity System
Explorer
• SIGR556 Sigrity SystemSI™
technology – PBA II
Note: Each option is a single-user license. Only one of the products listed in each option can be run at a time.
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Released in SPB 16.6-2015 - June
For PCB designers, IC package designers, and signal integrity engineers
needing to perform a quick scan of a design for potential signal quality
and crosstalk issues
• Crosstalk checking
without any models
• Near-end crosstalk
• Far-end crosstalk
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Identify top 10 contributors to crosstalk
Allegro Sigrity SI Base
Allegro Sigrity SI Base adds simulation
“rule checks”
What’s New:
Allegro Sigrity Power-Aware SI Option
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© 2015 Cadence Design Systems, Inc. All rights reserved.
For signal integrity engineers requiring large S-parameter extractions
from PCBs or IC packages
PowerSI Technology
Industry-leading hybrid extraction is now
faster and more accurate
Updated algorithms improve accuracy, and multi-processor functionality
accelerates extraction time
• Multi-processor support
extended to support
4-pack licenses
• Improved handling of
“trace-like” shapes
PowerSI technology – the best just keeps getting better
– Sigrity™ PowerSI® technology
correlation with Sigrity 3DEM
→
• Connectivity display in port
window easier to use and
consistent use model with
other Sigrity tools
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© 2015 Cadence Design Systems, Inc. All rights reserved.
For signal integrity engineers looking to verify system-level design
compliance with the latest memory interface standards
SystemSI™ PBA
Expanded support of power-aware SI
simulation
• Low-power DDR4 support
– Analysis results compared
against the LPDDR4 compliance
standard
– Eye mask checking for address
and data bus
– Bit-error rate (BER) reporting
• Current and voltage probes
now supported
• Worst-case pattern generation
• High-capacity simulation for
parallel bus now supports
– LPDDR4 / DDR4 dData bus)
–
Data write / data read
– LPDDR4 address/command bus
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Sigrity™ SystemSI™ parallel bus analysis performs BER
testing through high-capacity simulation
What’s New: Allegro Sigrity System
Serial Link Analysis
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Supports enhanced interconnect models and new
interface standard
For signal integrity engineers looking to verify design compliance with the
latest multi-gigabit serial link standards
• HDMI 2.0 support
– HDMI 2.0 (up to 6Gbps)
compliance kit supplements
existing HDMI 1.4b version
– Support for “TP2”
compliance checks
• Surface roughness added to
W-element models created
by TLine editor
– Huray and Modified
Hammerstad models both
supported
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© 2015 Cadence Design Systems, Inc. All rights reserved.
New HDMI 2.0 compliance kit provides
“virtual plug-fest” for compliance standard
SystemSI™ SLA
Multi-gigabit serial link SI simulation
What’s New:
Allegro Sigrity Package Assessment
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© 2015 Cadence Design Systems, Inc. All rights reserved.
For IC package designers and package characterization engineers
wanting to perform either first-order or signoff signal integrity analysis
• Improved usability
– Sigrity 3DEM partitions are
now automatically created
– Sigrity 3DEM runs on each
partition and the models are
stitched together
– Available when licensed with
Assessment and Extraction
Option
• Faster assessment
– New algorithm generates LC
pwr/gnd net pair values in
one pass
• Improved accuracy
– Sigrity™ PowerDC™ used to
provide better accuracy at
DC
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Package assessment calculates power/ground
LC in approximately half the time
XtractIM™ technology
Assessment and modeling of IC
packages enhanced
For PCB and IC package analysis experts requiring detailed 3D modeling
of complex 3D structures
• New Sigrity 3DEM full-wave
spatial flow
– Computes far- and near-field
distribution by exciting a current
source at ports
• Enhanced port setup wizard
– Components on inner layers are
now supported
• Parallel processing
– New 4-pack licenses supported
– KMOR frequency sweeping
simulation can now be distributed
across multiple computers (with
appropriate licenses)
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Sigrity™ 3DEM
Detailed 3D modeling of complex 3D
structures improved
Accelerate time to results with multiple computers
What’s New:
Allegro Sigrity PI Base + Options
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity power integrity solution
Base + option
• Allegro® Sigrity™ PI Base product enables constraint-driven PI design
• Option for cost-performance optimization and detailed analysis
Allegro Sigrity PI Base
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Key components of
Sigrity PI Base
Floorplanner
• Allegro® based editor for .brd, .mcm,
or .sip
• Layout editing and routing
DC Analysis
• Sigrity™ technology
with cross-probing
to layout
Power Feasibility Editor
• New unique constraintdriven decap flow
Constraint Manager
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity PI
Constraint-driven decap flow
• Two key use models
– No simulation and simulation-based
• Results of either option are passed to layout as PICSet
Power Feasibility Editor
• PFE has a multi-step workflow
for decap selection
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Constraint Manager
• PICSet applies decap scheme or
“template” to IC
• Optional vehicle for adding decaps to
design
• Contains placement guidance details
© 2015 Cadence Design Systems, Inc. All rights reserved.
Allegro is a registered trademark and Sigrity is a trademark of Cadence Design Systems, Inc. in the United States and other countries.
Allegro Sigrity PI
Constraint-driven decap flow—decap placement
• Command in floorplanner uses guidance data in PICSet to
place decaps
• circle
Effective radius
Same layer and
opposite layer
placement distance
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Options for Allegro Sigrity PI Base
Power Integrity Signoff
and Optimization Option
Package Assessment and
Model Extraction Option
• SIGR031 CAD Translators
• SIGR031 CAD Translators
• SIGR051 Sigrity™
OptimizePI™ technology
• SIGR201 Sigrity PowerDC
technology
• SIGR201 Sigrity PowerDC™
technology
• SIGR311 Sigrity 3DEM
• SIGR301 Sigrity PowerSI®
technology
• SIGR801 Sigrity XtractIM™
technology
• SIGR311 Sigrity 3DEM
• SIGR570 Sigrity System
Explorer
• SIGR570 Sigrity System
Explorer
Note: Each option is a single-user license. Only one of the products listed in each option can be run at a time.
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© 2015 Cadence Design Systems, Inc. All rights reserved.
What’s New:
PI Signoff and Optimization Option
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© 2015 Cadence Design Systems, Inc. All rights reserved.
For PCB and IC package designers that need to ensure voltage drop
specifications are met on their designs
• 3D display for via distribution
report
– Easy to identify hotspots
caused by vias
• Wide traces simulated as
shapes
– Meshing the trace adds
accuracy to simulation
• Cross probing from report to
layout view
– Quickly identify cause of
violations
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© 2015 Cadence Design Systems, Inc. All rights reserved.
3D Via Distribution Report
PowerDC™ Technology
IR drop analysis provides new 3D
display for via distribution
For PCB designers and power integrity engineers in need of decap placement
and selection advice
Optimize decaps to maximize performance and minimize cost
• New approach to
calculating the threshold
impedance
– Impedance of all decaps
shorted is now used for
the default threshold
• When objectives cannot
be met with existing
decaps, a new workflow
advises where to place
additional decaps
– Location selected based
on loop inductance
– Decap location can be
same side, opposite side
or under the device
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© 2015 Cadence Design Systems, Inc. All rights reserved.
User-adjustable grid of new capacitor
locations is applied to the device’s location
OptimizePI™ Technology
Industry-leading decoupling capacitor advisor
helps you meet objectives
New Products:
2015 Sigrity Solution
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© 2015 Cadence Design Systems, Inc. All rights reserved.
For signal and power integrity engineers with big extraction requirements
and tight schedules
Sigrity™ four-packs can be used to distribute Sigrity PowerSI® and 3DEM
jobs across multiple computers
• Previous distributed
processing solution
required multiple
Sigrity PowerSI or
3DEM licenses
– New solution allows
four additional
machines to be
added to the job with
a single license
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© 2015 Cadence Design Systems, Inc. All rights reserved.
One four-pack can speed extraction time by 3X
Four-Pack
Accelerate extraction time through multiple
computers and a single license
For signal and power integrity engineers that need a desktop what-if
analysis tool for estimating power-aware signal and power quality
• Sandbox for signal and
power integrity
– Previous Cadence® solutions
are SI only
• Sigrity™ System Explorer is
version of Sigrity SystemSI™
technology for any
topology—single or multifabric
– Previously SystemSI
technology just for serial links
or memory interfaces
• Analyze either signal (power
aware) or (transient) power
• Available with all Allegro®
Sigrity options and with all
SystemSI products
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Power-aware signal integrity can now be
explored with greater efficiency
System Explorer
Sigrity System Explorer: New “general” version
of Sigrity SystemSI technology analyzes any
topology
QIR #1 updates
Common functionality
•Backdrilling data now read in from Allegro® platform (SPDIF only)
•Trace checking now includes RLC
•Feature created to help DUT design teams
Sigrity™ PowerSI® technology
•Improved accuracy/detection for co-planer conditions (trace couples to shape on same layer)
Sigrity OptimizePI™ technology
•HTML reports contain new colorplot results multiple items
Sigrity PowerDC™ technology
•Package electrical / thermal resistance network model now created
•Creates a non-proprietary PKG model PCB users can use to perform Pkg/PCB E/T co-simulation
Sigrity PowerSI 3D EM Full-Wave Extraction Option
•New cut and stitch (mix and match hybrid and 3D extraction)
•Five times faster with 90% accuracy for typical serial links compared to full 3D extraction
Sigrity XtractIM™ technology
•Easier to connect package model to Voltus™ solution
Sigrity SystemSI™ technology
•Current source block available in Sigrity System Explorer for PI analysis
•Inject current into PDN and observe power ripple
•Spectre® solution now available as a circuit simulation option (Linux only)
•AMI builder beta testing begins
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Future of Cadence Analysis Solutions
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity
Integration …
2014 , 2015, 2016
Allegro Sigrity flow vision
Initial Setup
(Model Assignments,
Constraints, Thresholds)
Model Changes,
DRC/ERC Markers.
Decap Placement,
Etc.
Limited Additional Setup
Simulation
.spd Generation
(no extracta)
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Roadmap data is provided for informational purposes only and
does not represent a commitment to deliver any of the features or
functionality discussed
Post-layout decap changes backannotated from OptimizePI technology to
Floorplanner
Sigrity® Solution
late 2015 / 2016
Decap device changes
and decap deletions
• Today this process is entirely manual
OptimizePI™ Postlayout Simulation
• New process would automate updating
Floorplanner with all decap changes
from selected OPI scheme
• Changes are reviewed in layout database before being back-annotated
to schematic
Roadmap data is provided for informational purposes only and does not
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© 2015 Cadence Design Systems, Inc. All rights reserved.
represent a commitment to deliver any of the features or functionality
discussed
High-speed release roadmap – 2015/2016
Allegro Sigrity SI/PI products
• Sigrity™ 2015 release: new products and new features
1H
2015
‒LPDDR4 support
‒HDMI 2.0 compliance kit
‒Package partitioning
‒Adding decaps
• Beta programs (QIR #1)
• Simulation rule checks in SI base (June)
• Place replicate in PI Base (June)
2015
• AMM support in PowerDC™ technology / Sigrity PI Base
• Hybrid solver wizard
• Quasi-static 3D field solver introduction
• Algorithmic model interface (AMI) builder introduction
1H
2016
•Support for Allegro® 17.x database updates
•Native 64-bit support for Sigrity SI Base and PI Base floorplanners
•Scalable SI solution (Sigrity SI Base migration to Sigrity engines)
2H
This roadmap is provided for informational purposes only and does not represent a
commitment to deliver any of the features or functionality discussed in the materials
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© 2015 Cadence Design Systems, Inc. All rights reserved.
Sigrity
2015 /
QIR #1
QIR #2 /
QIR #3
Sigrity
2016
Summary
• Investment in Allegro® Sigrity™ integration is strong
– Leading-edge SI / PI technology also continues to advance
• Latest releases (SPB 16.6-2015 and Sigrity 2015 QIR 1)
contain numerous integration and technology improvements
– Accelerating time to analysis and improving interpretation of analysis
results (waveforms and reports)
• Strong roadmap for both technology and integration
– Sigrity and Allegro solutions to share models and constraints
– Solvers, simulators, and flows all have significant improvements
planned
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© 2015 Cadence Design Systems, Inc. All rights reserved.
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Allegro, PowerSI, and Spectre are registered
trademarks and OptimzePI, PowerDC, Sigrity, SPEED2000, SystemSI, Voltus, and XtractIM are trademarks of Cadence Design Systems, Inc. in the
United States and other countries. All other trademarks are the property of their respective owners.