GR16™ Technical Manual

GR16™
10 M SPS, 16-bit Analog Signal Digitizer
up to 8MB FIFO
Technical Manual
1950 5th Street, Davis, CA 95616, USA
Tel: 530-758-0180
Fax: 530-758-0181
Email: sales@tern.com
web site: www.tern.com
COPYRIGHT
GR16, EL, Grabber, and A-Engine are trademarks of TERN, Inc.
Am188ES and Am186ES are trademarks of Advanced Micro Devices, Inc.
Version 2.00
October 7, 2010
No part of this document may be copied or reproduced in any form or by any means
without the prior written consent of TERN, Inc.
© 2010
1950 5 Street, Davis, CA 95616, USA
Tel: 530-758-0180 Fax: 530-758-0181
th
Email: sales@ tern.com
Web site: www.tern.com
Important Notice
TERN is developing complex, high technology integration systems. These systems are
integrated with software and hardware that are not 100% defect free. TERN products are
not designed, intended, authorized, or warranted to be suitable for use in life-support
applications, devices, or systems, or in other critical applications. TERN and the Buyer
agree that TERN will not be liable for incidental or consequential damages arising from
the use of TERN products. It is the Buyer's responsibility to protect life and property
against incidental failure.
TERN reserves the right to make changes and improvements to its products
without providing notice.
`GR16™
1.1 Functional Description
The GR16™ is an inexpensive high speed (up to 10M samples per second), 16-bit analog signal
digitizer, designed to be driven by a host TERN 16-bit controller, such as 586-Engine, AE86, or
EE.
The GR16™ supports a 16-bit Delta-Sigma ADC (ADS1610). With its outstanding high-speed
performance, it is well-suited for demanding applications in data acquisition, scientific
instruments, test equipment and communications.
The GR16™ is designed as an expansion board, measuring 2.3 by 3.6 inches, for TERN 16-bit
controllers such as A-Engine86, 586-Drive, EE, and FN. The GR16™ interfaces to TERN host
controller via 20x2 pins at J1, and 5x2 pins at J2.
1.2 ADS1610 16-Bit, 10 MSPS Analog-to-Digital Converter
The ADS1610 is a high-speed, high-precision, delta-sigma analog-to-digital converter (ADC)
with 16-bit resolution. Inputs INP (H00.8) and INN (H00.6) are directly routed to the differential
inputs of the ADS1610 without buffer circuits. The GR16™ also has two buffered inputs, A(H0.3) and A+ (H0.5). A- and A+ are routed to INN and INP via 10 Ohm resistors. Analog input
signals must be able to handle the load presented by the switching capacitors within ADS1610.
The GR16™ configures the ADS1610 with VREF = 3V (VREFN = 1V and VREFP = 4V). The 16-bit
ADC data format is in binary two's complement. With VREFN = 1V and VREFP = 4V, the resulting
input reference VREF = (4V - 1V) = 3V. In this case, ADC outputs are:
•
When INP > INN, the ADC outputs 0-0x7FFF
•
When INP < INN, the ADC outputs 0x8000-0xFFFF.
•
When INP – INN = 3V, the ADC outputs 0x7FFF.
•
When INN – INP = 3V, the ADC outputs 0x8000.
•
When INN = INP, the ADC outputs 0 or 0xFFFF.
To achieve the highest analog performance, the recommended differential analog input voltage
range is 3V x 0.891 = 2.67V. The absolute input voltage with respect to GND, on either INN or
INP pin, must be within VREFN = 1V to VREFP = 4V range.
Recommended circuit designs are available when using single-ended or differential op amps,
respectively. See ADS1610 data sheet for details (www.ti.com). The GR16™ has an array of
through-hole pads (H0, H00, H01) to allow installing user custom analog signal conditioning
circuits.
1
`GR16™
1.3 ADC Sampling Modes
Three operation modes are available: ADC-read, ADC-FIFO, and FIFO-read. Figure 1.1 show
the various sampling modes.
FIFO-Read
TERN
HOST
CPU
8MB
FIFO
ADC-Read
ADC-FIFO
16-bit ADC
ADS1610
Analog Input
Figure 1.1 ADC Sampling Modes
In ADC-read mode, application software running on the host can read the 16-bit ADC data at
any time. Sampling rate would be limited to CPU and application processing speed.
In ADC-FIFO mode, the GR16 can sample at far faster speeds (up to 10M samples per second).
This data is recorded into the on-board FIFO SRAM. The ADC-FIFO operation is done entirely
in hardware, without using any host CPU time.
Finally, the system can be set to FIFO-read mode. The host CPU can then read as much FIFO
data as desired via I/O or DMA access.
2
`GR16™
1.4 ADC Sampling Frequency
The ADC sampling clock can be driven by on-board clock oscillator, as default, or an external
clock. With a 60MHz on-board oscillator, the sample rate is 10M samples per second maximum.
User can control the sampling rate by using an external clock, or selecting different dividers
using onboard jumpers (H1). The default setting for H1 is H1.7 = H1.8 which is CLK/6 or
10MHz sample rate. In order to change the default setting, the trace on H1 must be cut before
wiring a new jumper. Figure 1.2 shows the H1 header and default trace jumper on the back of the
GR16™. Table 1.1 the various sample rates for each H1 setting.
H1
Figure 1.2 Frequency Divisor Jumper H1
Jumper Pins
Clock Divisor
Sample Rate for
60 MHz Oscillator
H1.8 (RDY) = H1.7 (CKI) * DEFAULT *
CLK / 6
10 MHz
H1.10 (CK1) = H1.7 (CKI)
CLK / 12
5 MHz
H1.9 (CK2) = H1.7 (CKI)
CLK / 24
2.5 MHz
H1.6 (CK3) = H1.7 (CKI)
CLK / 48
1.25 MHz
H1.5 (CK4) = H1.7 (CKI)
CLK / 96
625 kHz
Table 1.1 H1 Jumper Settings
3
`GR16™
1.5 ADC-FIFO Operation
The ADC-FIFO operation runs when signals SA=0 and TR is active*. The ADC-FIFO
operation will stop immediately when SA=1. Setting AST low causes the FIFO counter to reset.
When AST=1, SA=0 and TR is active* the GR16™ continues filling up the FIFO with ADC
readings until the selected recording length is reached forcing SA high (SA=1). The record
length of the FIFO can be configured via jumper block H3. Available data lengths include 8MB
(H3.4 = H3.3), 4MB (H3.4 = H3.2), or 512KB (H3.4 = H3.6).
The hardware trigger signal (TR) is routed to header locations H2.7 and H1.2. By default H2.7
and H2.8 are jumpered (H2.7=H2.8=GND) forcing TR=0*. It is important that the external
hardware trigger signal (TR) must stay active while the GR16™ is recording ADC readings.
The FIFO will retain recorded data until it’s powered-off or a new ADC-FIFO operation is
initiated. To read data from the FIFO, reset the counter by bringing AST low then high, then read
from the FIFO. Every FIFO-read increments FIFO address.
1.6 GR16™ Stacks
Multiple GR16™ units can be stacked via pass through sockets on J1 and J2. H2 pin 10=/PCS is
the host I/O chip select. While H2.10=H2.9, as default, the Host controller J1.19 is the base I/O
chip select. For each /PCS setting, there are 4 GAL chips available: GRAB1600, GRAB1640,
GRAB1680, and GRAB16C0. Base I/O address are 0x00, 0x40, 0x80, and 0xC0 for these 4
GALs.
Stacked GR16™ units can share a common external CK and SYNC signal on H1 header. With
the CK inputs running, pulse the common shared SYNC line for the units to synchronize
simultaneous conversions. Be aware that CK and SYNC signals are directly routed to ADS1610,
with a voltage range of 0V-3.3V. Over voltage will damage ADS1610 ADC.
1.7 GR16-LM™ Version
GR16-LM version uses a different GAL set (GR16-00, GR16-40, GR16-80, and GR16-C0) that
have an active high trigger TR. This version operates when TR=1. By using an active high
trigger, the SA output from one GR16 can trigger the TR signal of another GR16 allowing
uninterrupted analog acquisition between GR16s. By default, H2.7 (TR) is not jumpered to GND
at H2.8 on the GR16-LM version.
*The original version of GR16 uses an active low (TR=0) trigger. The GR16-LM version uses a
different GAL that has an active high trigger. This version operates when TR=1. GR16-LM
versions can be identified by the GAL labels: GR16-00, GR16-40, GR16-80, and GR16-C0.
4
`GR16™
1.8 GR16 Photos
Figure 1.3 Front view of a EL controller with 4 GR16s.
Figure 1.4 Back view of an EL controller with 4 GR16s.
5
`GR16™
Figure 1.5 Side view of a EL controller with 4 GR16s.
Figure 1.6 UD with GR16TM
6
`GR16™
Figure 1.7 E-Engine with VE232 stacked on five GR16s powered by 9-30V
Figure 1.8 E-Engine with stacked on five GR16s powered by external 5V
7
`GR16™
1.9 Features
• 2.3 x 3.6 x 0.5 inches
• 200 mA at 5V DC power per GR16
• High-Speed Delta-Sigma ADC (ADS1610)
• User Programmable Sample Rate, up to 10M SPS
• On-Chip Digital Filter Simplifies Anti-Alias
• User configurable FIFO data size, up to 8MB.
• Stackable multi units sharing Sync, and Trigger.
• On-board oscillator or external host clock.
• Driven by a 16-bit TERN controller
• Support ADC read, ADC-FIFO, FIFO-read modes
• Software programmable Power off mode controlled by PD signal.
8
`GR16™
1.10 GR16 Physical Description
The figure below shows the physical layout of the GR16 board.
Step 2 Jumper
H1
TR, CK, SYNC and
Sample Rate Divisor
60 MHz OSC
Remove if using
external CK
H3
FIFO Size
10Ω Resistor
A- to INN
A+ to INP
H2.10
Chip Select
/PCS = P16
Analog Inputs
A-, A+ (1V-4V)
9
H2.7
Trigger = GND
Host I/O
GAL
GRAB16C0
GRAB1680
GRAB1640
GRAB1600
`GR16™
1.11 GR16-LM Physical Description
The GR16-LM version is the same hardware as the regular GR16, but uses a different GAL set.
The jumpers are set differently to accommodate the active high trigger TR.
H3
FIFO Size
8MB
H2.7 (TR)
Trigger is not
jumpered to GND
10
GAL
GR16-C0
GR16-80
GR16-40
GR16-00
`GR16™
1.12 GR16 Fifth Board Physical Description
When stacking more than four GR16s, a different chip select must be used to operate boards 5
through 8. The image below shows the jumper setting for the 5th GR16.
H2.10
Chip Select
/PCS = /RTS1
11
U3
SA1 1
SA2 2
SA3 3
SA4 4
SA5 5
/RAM0 6
AD0 7
AD1 8
AD2 9
AD3 10
VCC 11
GND 12
AD4 13
AD5 14
AD6 15
AD7 16
/AD 17
SA6 18
SA7 19
SA8 20
SA9 21
SA17 22
SA1 1
SA2 2
SA3 3
SA4 4
SA5 5
/RAM4 6
AD0 7
AD1 8
AD2 9
AD3 10
VCC 11
GND 12
AD4 13
AD5 14
AD6 15
AD7 16
/AD 17
SA6 18
SA7 19
SA8 20
SA9 21
SA17 22
U13
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
U16
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SA16
SA1 1
SA15
SA2 2
SA14
SA3 3
/RDF
SA4 4
GND
SA5 5
GND /RAM1 6
AD15
AD0 7
AD14
AD1 8
AD13
AD2 9
AD12
AD3 10
VCC 11
GND
GND 12
VCC
AD11
AD4 13
AD10
AD5 14
AD9
AD6 15
AD8
AD7 16
SA22 /AD 17
SA13
SA6 18
SA12
SA7 19
SA11
SA8 20
SA10
SA9 21
SA18 SA17 22
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SA16
SA1 1
SA15
SA2 2
SA14
SA3 3
/RDF
SA4 4
GND
SA5 5
GND /RAM5 6
AD15
AD0 7
AD14
AD1 8
AD13
AD2 9
AD12
AD3 10
GND
VCC 11
VCC
GND 12
AD11
AD4 13
AD10
AD5 14
AD9
AD6 15
AD8
AD7 16
SA22 /AD 17
SA13
SA6 18
SA12
SA7 19
SA11
SA8 20
SA9 21
SA10
SA18 SA17 22
VCC
R0
5V
10
R8
5V
GND 1
2
5V
GND 3
AIN 4
AIP 5
GND 6
7
5V
RBIAS 8
GND 9
5V 10
GND 11
5V 12
REFEN13
M0 14
M1 15
16
5V
C0
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SA16
SA1 1
SA15
SA2 2
SA14
SA3 3
/RDF
SA4 4
GND
SA5 5
GND /RAM2 6
AD15
AD0 7
AD14
AD1 8
AD13
AD2 9
AD12
AD3 10
GND
VCC 11
VCC
GND 12
AD11
AD4 13
AD10
AD5 14
AD9
AD6 15
AD8
AD7 16
SA22 /AD 17
SA13
SA6 18
SA12
SA7 19
SA11
SA8 20
SA10
SA9 21
SA18 SA17 22
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SA16
SA1 1
SA15
SA2 2
SA14
SA3 3
/RDF
SA4 4
GND
SA5 5
GND /RAM6 6
AD15
AD0 7
AD14
AD1 8
AD13
AD2 9
AD12
AD3 10
GND
VCC 11
VCC
GND 12
AD11
AD4 13
AD10
AD5 14
AD9
AD6 15
AD8
AD7 16
SA22 /AD 17
SA13
SA6 18
SA12
SA7 19
SA11
SA8 20
SA10
SA9 21
SA18 SA17 22
H0
1V-4V, ANALOG INPUT1V-4V, ANALOG INPUT+
AV2
RBIAS R9
10
20K
VCAP
AV2 GND
C13
VCAP
CK
V10
GND V3
V25
GND
V40
V3
5V
C4
U14
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
U17
GND 1
A3
5
A+
7
9
11
13
GND 15
U4
RRMV VVAAC ADDDD DD
PPIR RCVGL GGVVG VV
AG D E E A 2 2 K
NC
F FP
AV
NC
NN
AG
NC
AIN
NC
AIP
D15
AG
D14
AV
D13
BIAS
D12
AG
D11
AV
D10
AG
D9
AV
D8
NC
D7
M0
D6
S
D
M1
D5
OR
NCP D D Y
N C R T D D D N N D D D D D4
DVGC SDRYG VCC01 23
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SA16
SA1 1
SA15
SA2 2
SA14
SA3 3
/RDF
SA4 4
GND
SA5 5
GND /RAM3 6
AD15
AD0 7
AD14
AD1 8
AD13
AD2 9
AD12
AD3 10
GND
VCC 11
VCC
GND 12
AD11
AD4 13
AD10
AD5 14
AD9
AD6 15
AD8
AD7 16
SA22 /AD 17
SA13
SA6 18
SA12
SA7 19
SA11
SA8 20
SA10
SA9 21
SA18 SA17 22
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SA16
SA1 1
SA15
SA2 2
SA14
SA3 3
/RDF
SA4 4
GND
SA5 5
GND /RAM7 6
AD15
AD0 7
AD14
AD1 8
AD13
AD2 9
AD12
AD3 10
GND
VCC 11
VCC
GND 12
AD11
AD4 13
AD10
AD5 14
AD9
AD6 15
AD8
AD7 16
SA22 /AD 17
SA13
SA6 18
SA12
SA7 19
SA11
SA8 20
SA10
SA9 21
SA18 SA17 22
H01
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
HDRD16
6666 65555 55555 54
4321 09876 54321 09
U15
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
U18
2
4
6
8
10
12
14
16
5V
M0
1
3
5
7
9
11
13
15
HDRD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
10UF
ADS1610
1112 22222 22223 33
ADS1610
CK4
7890 12345 67890 12
AD3
CK3
PD
V3
V3
AD2
CK2
GND
GND
AD1
R12
SYNC
RDY
AD0 V3
SYNC
/ADL
10K
2
4
6
8
10
12
14
16
C10
U12
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
LM285
1
+5V
4 V3
2
GND CLK
3 CK
AAIN
AIP
A+
GND
REFEN
M1
3
4 SA
SA12
5
6 SA19
C9
V25
C03
100UF
V25
V40
C23
C24
10UF
10UF
V40
V10
4
V25A
V10A
R5
150K
100K
SA19 1
SA20 2
SA21 3
C8
5V
C7
CAPNP
3
I0R2
160K
VCC 6
/RAM 4
AST 5
/AD
R10
1K
2K
R13
PD
R14
V10A 5
PDN
2K
15
14
13
12
11
10
9
7
/RAM0
/RAM1
/RAM2
/RAM3
/RAM4
/RAM5
/RAM6
/RAM7
U10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
/RDB
1
19
1G
2G
100K
SA18
SA17
SA19
SA16
SA15
SA14
1
1
LMC660
U11B
7 V10
LMC660
U11C
8 V25
VCC
1
2 /PCS
3 /RDB
4 /AD
5 /RDF
6 TR
7 AST
8 /RAM
AIP
R4
AIN R3
AIN
C25
A+
10
A10
AIP
C26
10PF
10K
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
D8
D9
D10
D11
D12
D13
D14
D15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
2
4
6
8
11
13
15
17
/RDB 1
19
74HC244
2
V25 9
1K
Y0
Y1
Y2
Y3
Y4
G1
Y5
G2A
Y6
G2B
Y7
74HC138
2
4
6
8
11
13
15
17
R1
V10 6
V25A10
U8
A
B
C
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
LMC660
U11A
1 V40
RN1
/ADL
R11
D0
D1
D2
D3
D4
D5
D6
D7
GND
A7
A6
A5
A4
A3
A2
A1
A0
H3.4 = H3.6, 512KB
H3.4 = H3.3, 8 MB
H3.4 = H3.2, 4 MB
C6
5V
2K
R6
V25A
VCC
16
15
14
13
12
11 GND
10 RDY
9 CK1
SA23
GND
CLK
HDRD6
VCC
VCC
R7
V25A
BB1117
4040
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
J1
U1
VCC
39 VCC
2
SA16
CLK RDY 1 CK 5V 20
GND 40
VCC 1
2 I1 O7 19 /RDB
SA15
TR
P4 38
37 P14
3
4
3 I2 O6 18 SA
36
35 P6
5
6
SA14
A4
34
33 /INT4
7
8
/RDF
A5
4 I3 O5 17 D0
5 I4 O4 16 /AD
32
31 /RTS1
9
10
GND
A6
6
15 /RDF
30
29
11
12
GND
A7
I5 O3
AD15
/PCS 7 I6 O2 14 PDN
28
27
D15 13
14
AD14
/RD 8 I7 O1 13 AST
26
25
/RST 15
16
AD13
/WR 9 I8 O0 12 /RAM
24
23
RST 17
18
21
20
GND 10 G /OE 11
/CTS1 22
P16 19
AD12
D14 21
GND
20
19
22
D13 23
VCC
PAL16V8
18
17
24
AD11
16
15
25
26
D12 27
AD10 AD-FF:/AD=0,/RDF=1,PDN=1,AST=0,/RDB=1,TR=0 14
13
28
12
11
30
/WR 29
AD9 RD_FF:/AD=1,/RDF=0,PDN=0,AST=0,/RDB=0
/RD 31
AD8 RD_AD:/AD=0,/RDF=1,PDN=1,AST=1,/RDB=0
10
9
32
D11 33
SA22
8
7
34
D10 35
SA13
GRAB1600.PDS BASE I/O 0X00
6
5
36
D9 37
SA12
GRAB1640.PDS BASE I/O 0X40
4
3
38
2
1
40
D8 39
SA11
GRAB1680.PDS BASE I/O 0X80
SA10
GRAB16C0.PDS BASE I/O 0XC0
J2
HDRD40
HDRD40
SA18
H1
GND 1
2 TR
CK=ADC CLOCK, 60MHZ DEFAULT
3
4 SYNC
CK
SYNC=MULTIPLE GR16/ADS1610 SYNC
SA16
CK4 5
6 CK3
TR=EXTERNAL TRIGGER, ACTIVE LOW
SA15
RDY 7
8 RDY
DEFAULT TRACE H1.8 = H1.7, 10M SPS
10 CK1
SA14
CK2 9
CUT TRACE, WIRE H1.7 = H1.10, 5M SPS
/RDF
CUT TRACE, WIRE H1.8 = H1.6, 1.25M SPS
HDRD10
GND
GND
AD15
AD14
H2
AD13
2 /AD
AD12
/RDB 1
GND
/RDF 3
4 RDY
TR=EXTERNAL TRIGGER, ACTIVE LOW
VCC
AST
5
6 /RAM
TR=H2.7 = H2.8=GND, SOFTWARE START SAMPLE
AD11
TR
7
8 GND
H2.9 = H2.10 = J1.19 HOST SELECT
10 /PCS
AD10
P16 9
H2.12 = H2.10 = J2.31 HOST SELECT
11
12
AD9
/CTS1
/RTS1 RDY=0: ADC DATA READY
AD8
AST=1: SAxx ADDRESS RESET
SA22
HDRD12
P16=J1.19 HOST I/O SELECT
SA13
/RTS1=J2.31 HOST I/O SELECT
SA12
SA11
SA10
H3
SA18
SA14 1
2 SA22
H3 = FIFO SIZE SELECT
HDRD16
C11
V3=3.3V
4 V3
C1
K1
NC
OS
OS_SMT
U2
1 Q12VCC
2
Q11
3 Q6
Q5 Q10
4 Q7 Q8
5 Q4 Q9
6 Q3 RST
7
Q2 CLK
8 GND Q1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5V 5V 5V 5V V25
C12 C15 C16 C17 C22
10F
V10
U5
GNG
VOVO
VI
A15
A14
A13
/OE
/UB
/LB
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
NC
A12
A11
A10
A9
A17
H00
AV2 V40 V25 V10 V3 V3 V3
C14 C18 C19 C20 C21 C3 C5
GND 1
V3
2
VCC 3
C2
A0
A1
A2
A3
A4
/CS
D0
D1
D2
D3
VCC
GND
D4
D5
D6
D7
/WR
A5
A6
A7
A8
A16
RAM44
U19
10PF
1
2
3
4
5
6
7
8
U7
Q12VCC
Q6 Q11
Q5 Q10
Q7 Q8
Q4 Q9
Q3 RST
Q2 CLK
GND Q1
4040
U9
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
D0
D1
D2
D3
D4
D5
D6
D7
1G
2G
74HC244
VCC
16
15 SA23
14 SA22
13 SA20
12 SA21
11 AST
10 SA12
9 SA13
SA12
SA6
SA5
SA7
SA4
SA3
SA2
1
2
3
4
5
6
7
8
U6 4040 VCC
Q12VCC 16
SA11
Q6 Q11 15
SA10
Q5 Q10 14
13
SA8
Q7 Q8
SA9
12
Q4 Q9 11
AST
Q3 RST
10
/RAM
Q2 CLK
9 SA1
GND Q1
AST=1 SAxx=0
STE/TERN
Title
HIGH SPEED 16-BIT ADC GRABBER
Size Document Number
B
GRAB16.SCH
Date:
June 19, 2009 Sheet
REV
1 of
1