What is New in IPC-7351C

Transcription

by Tom Hausherr
CEO & Founder of PCB Libraries, Inc.
www.pcblibraries.com
Through-Hole Technology
PCB Libraries Presents:
3-Tier IMD (Inserted Mount Device)
The original IPC-7251 Concept for 3-Tier Pad Stack
Joint Characteristics
Maximum
(Most)
Density
Level A
Median
(Nominal)
Density
Level B
Minimum
(Least)
Density
Level C
Hole Diameter Factor (over max lead)
0.25
0.20
0.15
Int. & Ext. Annular Ring Excess
(added to hole dia.)
0.50
0.35
0.30
Anti-pad Excess (added to hole dia.)
1.00
0.70
0.50
Courtyard Excess from Component
Body and/or Pads
(which ever is greater)
0.50
0.25
0.12
Courtyard Round-off factor
Round up to the nearest even two place decimal,
i.e., 1.00, 1.01, 1.02, 1.03 etc.
3-Tier Pad Stack Concept
Proportional Pad Stack
Small Hole
Same Annular Ring
Large
Hole
Proportional
Annular Ring
No 3-Tier Library System
IPC-7351C Proportional Pad Stacks
IPC-7351C Proportional Pad Stacks
Rounded Rectangle Pad Shape
• Most Component Manufacturer’s
Recommended Pad Shape is Rectangle
• IPC-SM-782 and IPC-7351B
Recommended Pad Shape is Oblong
• IPC-7351C – Rounded Rectangle Pad
Land Width =
Shortest Side
Corner Radius =
25% Land Width
1 Mil (0.01 mm)
Round-off
Maximum Radius =
10 Mil (0.25 mm)
Surface Mount Component Lead Styles
Ball Grid Array
Bump Grid Array
Land Grid Array
Flat Side
Convex Side
Concave Side
Gull Wing
Outward L
J-Lead
Column Grid Array Pillar Grid Array
Corner Concave
End Cap
Inward L
Under Body L
Flat Lug
Flat Bottom
No-Lead
Lead Styles and Rounded Rectangle Pads
Under Body “L”
End Cap
PQFN D-Shape Corner Concave
Gull Wing
QFN D-Shape
Sharp Corner pads are not good for RF design
Lead Styles Exempt from Rounded Rectangle Pads
Under Body Terminal Leads where a
Periphery Pad is required:
•
•
•
•
•
Ball Grid Array
Column Grid Array
Land Grid Array
Dual Flat No-lead
Thermal Pads
Guidelines for Drafting Items
•
•
•
•
•
•
Silkscreen Outline and Polarity Marking
Assembly Outline and Polarity Marking
Courtyard Outline
Land Pattern Origin Marker
Component Outline
Terminal Lead Outline
Silkscreen Outline Guidelines
1.
2.
3.
4.
5.
6.
No silkscreen outline under the component body; these get covered up
during assembly and don’t provide any useful purpose (waste of good ink)
Silkscreen outlines visible after assembly process and provide a functional
use as alignment marking for assembly registration accuracy
Silkscreen outlines should be inside placement courtyard
Silkscreen outlines should be mapped to the Maximum Component Body
with one exception, the Silkscreen to Pad spacing rule “overrides” the
Component Body Mapping
Silkscreen outlines should map the component body and not go around
pads. Excess silkscreen outlines should be avoided to make room for ref
des locations. Silkscreen outlines should perform a “hatch” outline along
the component package body.
Pin 1 is identified by extending the silkscreen along Pin 1 length of pads
when component leads extend outward. Bottom only terminals Pin 1 is
identified by a missing line.
3-Tier Silkscreen Outlines
• The recommended guidelines for 3-Tier line widths and
Silkscreen to Pad Gap are illustrated in the pictures below
representing a SOT23-6 component package
• The Silkscreen to Pad Clearance is the same as the Line Width
Least Density Level
0.10 mm Line Width
Nominal Density Level
0.12 mm Line Width
Most Density Level
0.15 mm Line Width
IPC-7351B Rectangular Courtyards
The recommended courtyard outline line widths are 0.05 mm or 0.01 mm
IPC-7351C Contour Courtyard Outlines
The recommended courtyard outline line widths are 0.05 mm or 0.01 mm
IPC-7351C Contour Courtyard Outlines
Silkscreen Outline Pkg. Body Hatching
• The Maximum Component Body tolerance is the starting place for
mapping a silkscreen outline inside edge
• Silkscreen should only be applied to edges of the plastic component
package or hatched (corner cropping) larger component packages like
BGA, CGA and LGA packages
• It is not recommended to map silkscreen outlines to land pattern pads
Quad Flat Package
QFP
Pull-back Quad Flat No-lead
PQFN
Ball Grid Array
BGA
Silkscreen Polarity Marking
Gull Wing & J-Lead, Bottom Only & Chip
Gull Wing & J-Lead Polarity
Bottom Only Polarity
Absence of Silkscreen
2-pin Component Polarity
2-pin Component Non-polarity
Silkscreen Visible After Assembly
Quad Flat No-lead (QFN)
Ball Grid Array (BGA)
Quad Flat Pack (QFP)
SOT23
Axial Resistor
Alternate Silkscreen Polarity Marking
Assembly Shops Like Dots but, They Consume Space
Gull Wing & J-Lead Polarity
Bottom Only Polarity
Outside Courtyard
2-pin Diode/LED Polarity
2-pin Capacitor Polarity
Assembly Outline & Polarity Guidelines
Non-polarized Chip,
Crystal, Molded Body
Polarized Chip, SOD,
LED, SOT. Molded Body
0.10 mm
Line Width
1.00 mm
Small Outline Package
SOP, SON, QFN, QFP
Plastic Leaded Chip Carrier
PLCC, LCC, 4-sided Chip Array
1.00 mm
1.00 mm
Component Body & Terminal Outlines
• The Nominal Component Body and Terminal Lead Outlines
• Output to CAD tool on a mechanical layer
3-Tier Silkscreen Reference Designators
• Silkscreen reference designators are normally placed inside the
courtyard during library construction and typically located on the
land pattern origin. After part placement has been approved, the
silkscreen ref des are relocated outside the component body so
they are visible after assembly.
• The ref des line width is normally 10% of the text height
REFDES
• In the past, we made all silkscreen reference designators 1.50 mm
height. Fabrication technology has improved it’s time to support a
3-Tier reference designator option
• New recommendations for the 3-Tier ref des
– Least Density Level: 1.00 mm Height
– Nominal Density Level: 1.20 mm Height
– Most Density Level: 1.50 mm Height
Assembly Reference Designators
• The default assembly Ref Des height is 2.00 mm
• For miniature components the text height must be scalable to fit
• The default rotation of the assembly reference designator is
associated with the component body length
0.6 x 0.3
0201
1.0 x 0.5
0402
1.6 x 0.8
0603
2.0 x 1.2
0805
REFDES
REFDES
Ref Des Height
0.50 mm
Ref Des Height
0.70 mm
REFDES
REFDES
Ref Des Height
1.00 mm
Ref Des Height
0.12 mm
These Chip assembly Ref Des are scaled down to fit inside assembly outlines
Land Pattern Origin Guidelines
• The land pattern origin is typically located at the center of gravity of the
component, but sometimes this is difficult to calculate with irregular
shaped components, so Pin 1 is used in these cases. Also Pin 1 in most
through-hole connectors.
• The centroid origin marking in the picture below is an unfilled 0.50 mm
diameter circle with a 0.05 line width with a 0.70 crosshair for cursor
alignment.
Snap Grid & Feature Round-off 0.01 mm
Footprint Features in 0.01 mm increments
*Japanese 80% rule
0.01
0.01
0.01
0.01 0.01
0.01
0.005 for 0.65 pitch
0.01
0.01
Line Widths
0.01
0.01
0.01
Corner Radius
0.01
3-Tier Local Fiducials
• Local Fiducials have been used only on fine pitch QFP and BGA
Land Patterns
•
•
Fine pitch QFP = Less than 25 mil (0.635 mm) pitch
Fine pitch BGA = Less than 32 mil (0.8 mm) pitch
• Future Local Fiducial sizes will be:
•
•
•
Level A (Most) = 40 mil (1.0 mm) with 80 mil (2.0 mm) solder mask & keep-out
Level B (Nominal) = 30 mil (0.75 mm) with 60 (1.5 mm) solder mask & keep-out
Level C (Least) = 20 mil (0.5 mm) with 40 mil (1.0 mm) solder mask & keep-out
Zero Component Orientation – Levels A & B
Zero Orientation with Pin 1 in Upper Left Corner Introduced
in 2007 in the IPC-7351A Publication – IPC-7351C “Level A”
Zero Orientation with Pin 1 in Lower Left Corner Introduced
in 2009 in the IEC 61188-7 publication – IPC-7351C “Level B”
EIA & JEDEC
EIA Component Dimensions vs: JEDEC
Dimensional Letters
JEDEC Dimensional Characters
Land Pattern Naming Convention
Extended Names Eliminate Duplication I
• The original IPC-7351 footprint naming convention does not include Gull Wing
component lead tolerances, Thermal Pad sizes, BGA Ball sizes or Chip Terminal
Lead Width into account. Therefore, the same component with different
tolerances can produce a different land size and spacing with the same
footprint name.
• A footprint name of SOP50P710X120-14N can have version A, B, C, D which do
not indicate the variances in Thermal Tab or Lead Length
• There are 3 component features that affect the footprint name
• Square/Rectangle Thermal Tab Size = SOP50P710X120-14T300/T300X500
• Gull Wing Lead Length Tolerance = SOP50P710X120-14L50
• BGA Ball Size = BGA121C50P11X11_600X600X100B23
• Chip Terminal Lead Width = CAP3216X135L45
• For component mfr. recommended footprint drop the environment level
character after the pin qty. - SOP50P710X120-14
Land Pattern Naming Convention
Extended Names Eliminate Duplication II
• The existing IPC-7351 land pattern naming convention does not take into
consideration component package tolerances.
• Package tolerances affect the pad, silkscreen and courtyard sizes
• You can have several packages with the same dimensions but different
tolerances but the IPC-7351 naming convention will name all the parts with
the same land pattern name
• In order to save the IPC-7351 naming convention and eliminate duplicate
land pattern names for parts with different tolerances, we need to add the
component manufacturer abbreviation as a prefix to the IPC-7351 name
• Example: SOP50P710X120-14L50T300X500 will become these names –
• TI_SOP50P710X120-14L50T300X500
• MAXIM_SOP50P710X120-14L50T300X500
• ANALOG_SOP50P710X120-14L50T300X500
New Land Pattern Naming Convention
Extended Names Eliminate Duplication III
• Component manufacturer’s apply different tolerances on
the package dimensions which creates a different footprint
pattern. So a new Naming Convention must be created for
each mfr. Case Code
• Standard Packages – MfrNameAbr_MfrCaseCode
• Unique Packages – MfrNameAbr_MfrPartNumber
• This new naming convention is exclusive to all footprints,
so instead of having one naming convention for Standard
Packages and a different naming convention for Unique
packages, a universal naming convention is needed
New Land Pattern Naming Convention
Manufacturer Names and Abbreviations
Abbreviation Manufacturer’s Name
Abbreviation
Manufacturer’s Name
TI
Texas Instruments
LATTICE
Lattice Semiconductor
AMD
Advanced Micro Devices SA
State of the Art
ST
ST Microelectronics
CDE
Cornell Dubilier Electron
TE
TE Connectivity
CTS
CTS
KOA
KOA Speer Electronics
MOLEX
Molex
NXP
NXP Semiconductors
ALD
Advanced Linear Devices
HTK
Honda Tsushin Kogyo
CYPRESS
Cypress Semiconductor
JAE
Japan Aviation Electron.. FOX
Fox Electronics
IQD
IQD Frequency Products
IDT
Integrated Device Tech..
KEMET
Kemet
DIODES
Diodes, Inc.
New Solder Joint Goal Recommendations
Proportional SMD Pad Stack
Gullwing Lead Shape
2.54 mm Pitch (DPAK)
1.27 mm Pitch
1.00 mm Pitch
0.08 mm Pitch
0.65 mm Pitch
0.50 mm Pitch
0.40 mm Pitch
0.35 mm Pitch
Component Families
Small Outline IC (SOIC)
Small Outline Package (SOP)
Quad Flat Package (QFP)
Small Outline Transitor (SOT23)
Small Outline Diode (SOD)
Ceramic Flat Package (CFP)
Ceramic Quad flat Package (CQFP)
TO (DPAK)
25% Pitch 30% Pitch 5% Pitch
20% Pitch
Toe
Heel
Side
Courtyard Excess
0.63
0.76
0.13
0.50
0.30
0.35
0.06
0.25
0.25
0.30
0.05
0.20
0.20
0.25
0.04
0.16
0.16
0.20
0.03
0.13
0.13
0.15
0.02
0.10
0.10
0.12
0.01
0.08
0.09
0.10
0.00
0.07
Pad Length = Nominal Lead Length + Toe + Heel
Pad Width = Nominal Lead Width + Side
Old/New Solder Joint Goal Recommendations
1.00 pitch
0.35 Toe / Heel
1.00 pitch
0.25 Toe / 0.35 Heel
0.80 pitch
0.35 Toe / Heel
0.80 pitch
0.20 Toe / 0.30 Heel
Toe
Heel
0.65 pitch
0.35 Toe / Heel
0.65 pitch
0.16 Toe / 0.20 Heel
0.50 pitch
0.35 Toe / Heel
0.50 pitch
0.13 Toe / 0.15 Heel
Toe
Heel
0.40 pitch
0.35 Toe / Heel
Toe
Heel
0.40 pitch
0.10 Toe / 0.12 Heel
0.35 pitch
0.35 Toe / Heel
0.35 mm pitch
0.09 Toe / 0.10 Heel
Solder Joint Goals for Gull Wing
• Perfect Pad Centering
• Visible Wetting Under Lead
• Heel Larger Than Toe
• Bad Pad Centering
• Wetting Under Lead Unachievable
• Possible Short Circuit with Trace
New Pad Center Calculation
Nominal “E”
Nominal “L”
Heel
Toe
Pad Length
CL
Pad Centers
Pad Length = Nom “L” + Heel + Toe
Pad Centers = Nom “E” + 2 Toes – Pad Length
Solder Joint Goals for Chip Components
Chip Inductor
Chip Non-polarized Diode
Chip Varistor
Chip Fuse
Chip Resistor
Chip Capacitor
Chip Thermistor
Chip LED
Chip Diode
Polarized Chip Capacitor
Solder Joint Goals for Chip Components < 0603
Maximum (Most)
Median (Nominal) Minimum (Least)
Density Level A
Density Level B
Density Level C
Toe (JT)
0.55
0.35
0.15
Heel (JH)
0.00
0.00
0.00
Side (JS)
0.05
0.00
-0.05
Round-off factor
Round off to nearest two place decimal, i.e., 1.00, 1.01, 1.02
Courtyard excess
0.50
0.25
0.12
Rectangular Chip Components Smaller than 1608 (0603) (unit: mm)
Toe (JT) 0402
0.15
Toe (JT) 0201
0.12
Toe (JT) 01005
0.10
Heel (JH)
0.00
Side (JS)
0.00
Round-off factor
Round off to nearest two place decimal, i.e., 1.00, 1.01, 1.02
Courtyard excess
0.15
Lead Part
New Solder Joint Goal Recommendations
Proportional SMD Pad Stack 50% Height 10% Height 15% Height
Rectangular End Cap
Toe
Heel
Side
Inch 01005, Metric 0402
0.075
0.015
0.023
0.150
0.030
0.045
0.185
0.037
0.056
0.275
0.055
0.083
0.300
0.060
0.090
0.325
0.065
0.098
0.350
0.070
0.105
0.350
0.070
0.105
0.375
0.075
0.113
0.400
0.080
0.120
Inch 2010 , Metric 5025
0.400
0.080
0.120
0.400
0.080
0.120
0.400
0.080
0.120
Package Dimensions
40% Height
Length
Width
Height Courtyard
0.40 mm 0.20 mm 0.25 mm
0.10
0.60 mm 0.30 mm 0.30 mm
0.12
1.00 mm 0.50 mm 0.40 mm
0.16
1.60 mm 0.80 mm 0.50 mm
0.20
2.00 mm 1.25 mm 0.60 mm
0.24
2.50 mm 2.00 mm 0.65 mm
0.25
3.20 mm 1.60 mm 0.70 mm
0.25
3.20 mm 2.50 mm 0.70 mm
0.25
4.50 mm 1.60 mm 0.75 mm
0.25
4.50 mm 3.20 mm 0.80 mm
0.25
5.00 mm 2.50 mm 0.80 mm
0.25
6.40 mm 3.20 mm 0.80 mm
0.25
7.40 mm 5.10 mm 0.80 mm
0.25
Limit Maximum Courtyard setting to
0.25 mm but make it User Definable
J-STD-001 Chip Component Solder Joints
•
•
•
•
Visible Wetting Evident on the vertical surfaces of the component termination
Minimum End Solder Fillet 25% of Height or 0.50 mm Whichever is Less – Class 3
Minimum End Solder to be 75% of the Length. The Pad Width is Critical – Class 3
The Side and Heel are Nominal Values But Must Insure Centering
• The Pad Spacing Center to Center is Critical To Avoid Excess Heel
New Pad Center Calculations
Nominal “E”
Nominal “L”
Toe
Heel
Pad Length
CL
Pad Centers
Pad Length = Nom “L” + Heel + Toe
Pad Centers = Nom “E” + 2 Toes – Pad Length
Old BGA Solder Joint Goal Recommendations
Nominal Ball Diameter Reduction Nominal Land Diameter
Land Variation
0.75
25%
0.55
0.60 - 0.50
0.65
25%
0.50
0.55 - 0.45
0.60
25%
0.45
0.50 - 0.40
0.55
25%
0.40
0.50 - 0.40
0.50
20%
0.40
0.45 - 0.35
0.45
20%
0.35
0.40 - 0.30
0.40
20%
0.30
0.35 - 0.25
0.35
20%
0.28
0.33 - 0.23
0.30
20%
0.25
0.25 - 0.20
0.25
20%
0.20
0.20 - 0.17
0.20
15%
0.17
0.20 - 0.14
New Collapsing BGA SJG Recommendations
A Single Simple Ball Diameter to Pad Size Calculation
Collapsing Ball Grid Array (BGA) Pin Pitch Adj. % New Pad SizeOld Pad Size Pad Round-off Courtyard Excess
Nominal Ball (mm)
Fixed
Fixed
80% of Pin Pitch
0.75
1.27
80%
0.60
0.60
0.01
1.00
0.60
1.00
80%
0.48
0.50
0.01
0.80
0.55
1.00
80%
0.44
0.45
0.01
0.80
0.50
0.80
80%
0.40
0.45
0.01
0.65
0.45
0.80
80%
0.36
0.40
0.01
0.65
0.35
0.65
80%
0.28
0.33
0.01
0.50
0.30
0.65
80%
0.24
0.25
0.01
0.50
0.25
0.50
80%
0.20
0.20
0.01
0.40
0.20
0.45
80%
0.16
0.20
0.01
0.35
New Non-collapsing BGA SJG Recommendation
Non-Collapsing Ball Grid Array Pin Pitch Adj. % Pad Size Pad Round-off Courtyard Excess
Nominal Ball (mm)
Fixed
Fixed
80% of Pin Pitch
0.75
1.27
100%
0.75
0.00
1.00
0.60
1.00
100%
0.60
0.00
0.80
0.55
1.00
100%
0.55
0.00
0.80
0.50
0.80
100%
0.50
0.00
0.65
0.45
0.80
100%
0.45
0.00
0.65
0.35
0.65
100%
0.35
0.00
0.50
0.30
0.65
100%
0.30
0.00
0.50
0.25
0.50
100%
0.25
0.00
0.40
0.20
0.45
100%
0.20
0.00
0.35
0.17
0.40
100%
0.17
0.00
0.30
0.15
0.35
100%
0.15
0.00
0.30
Chapters 8 & 9 – Total Rewrite
•
•
•
•
•
•
•
•
Component Family Grouping by Pin Quantity
3D Model Picture of Each Component
Land Pattern Pictures with Level A & B Rotations
Updated Solder Joint Goal Tables
Naming Convention: Mfr. Part Number or Case
New Chapter on Aspects of 3D Modeling
Appendix Introduces Drafting Outline Guidelines
Relocating all Assembly Related Data to the new
IPC-7070 Component Mounting Issues and
Recommendations
PCB Library Expert
The “Footprint (FP) Designer” Module
• Traditional footprint software only calculates standard parts,
constraining usage to only 50% of the components in the industry.
• PCB Library Expert also creates mfr. recommended footprints for
components with the following characteristics:
– Asymmetrical
– Various sizes of pads
– Different pad shapes
PCB Library Expert CAD Tool Interfaces
Allegro
OrCAD PCB Editor
OrCAD Layout
Board Station
Expedition
PADS Layout
Altium Designer
P-CAD
Eagle
CADSTAR
CR-5000
Ultiboard
Pantheon
Other formats
in development
Questions?
Tom.Hausherr@PCBLibraries.com
www.pcblibraries.com

What is New in IPC-7351C

Transcription

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