iTUTOR Introduction and Quick Tutorial

Transcription

iTUTOR Introduction
and Quick Tutorial
Dynalith Systems
http://www.Dynalith.com
contact@Dynalith.com
March 2006
PPT file is available on request.
Overall agenda
iTUTOR introduction
Design, simulation and synthesis
Co-emulation using iTUTOR
Intro iTUTOR
(2)
1
iTUTOR Introduction
Dynalith Systems
www.Dynalith.com
Objectives and agenda
Understand background of iTUTOR
HW design flow in general
Conventional design flow
FPGA prototyping involved
What are required
What to be improved
Where iTUTOR fits
What is iTUTOR
iTUTOR hardware
iTUTOR software
iTUTOR environment
What can do with iTUTOR
New design flow with iTUTOR
iTUTOR product package
iTUTOR additional features
iTUTOR summary
Intro iTUTOR
(4)
2
HW design flow in general
Logic (RTL) design
Logic simulation
RTL code
(Verilog)
Logic debugging
Specifications
Logic synthesis
RTL code &
Target
library
Netlist
(EDIF)
Gate-level simulation
Gate-level debugging
Netlist &
Gate delay
(SDF)
Placement & routing
Timing simulation
GDSII
Timing analysis
Semiconductor fabrication
GDSII &
Test-vector
Intro iTUTOR
(5)
Conventional design flow (1/2)
Intro iTUTOR
(6)
3
Conventional design flow (2/2)
Intro iTUTOR
(7)
FPGA prototyping involved
Logic (RTL) design
Logic simulation
Logic debugging
RTL code
(Verilog)
Specifications
RTL code &
FPGA
library
Logic synthesis
Placement & routing
FPGA
Debugging
FPGA
bit-stream
FPGA board
RTL code &
Target
library
Netlist &
Gate delay
(SDF)
GDSII &
Test-vector
Logic synthesis
Netlist
(EDIF)
Placement & routing
Timing simulation
GDSII
Timing analysis
Intro iTUTOR
(8)
4
What are required
HDL simulator
HDL linter
HDL coverage analysis
Logic (RTL) design
Logic simulation
Logic debugging
HDL synthesizer
FPGA development environment (P&R)
FPGA board
Logic analyzer & Oscilloscope
Logic synthesis
Placement & routing
Logic synthesis
HDL synthesizer
Target library
HDL simulator
Placement & routing
P&R
Static timing simulator
Timing simulation
Timing analysis
Intro iTUTOR
(9)
What to be improved
Potential drawbacks from conventional hardware design flow
Need more simulation performance as design size and complexity increase.
Need a unified environment to deal with design blocks in different abstract levels
and languages.
Soft-IP: design in HDL such as Verilog, VHDL, and SystemC.
Hard-IP: design as a hardware, i.e., block in FPGA or even real-chip.
Behavioral-IP: design in high-level language such as C, C++, and SystemC.
Intro iTUTOR
( 10 )
5
Where iTUTOR fits
Logic (RTL) design
Logic simulation
Logic synthesis
RTL code
(Verilog)
iTUTOR compilation
Placement & routing
Logic debugging
RTL code &
FPGA
library
RTL code &
Target
library
Netlist &
Gate delay
(SDF)
GDSII &
Test-vector
Logic synthesis
Placement & routing
FPGA
Debugging
FPGA
bit-stream
FPGA board
Logic synthesis
Netlist
(EDIF)
Placement & routing
Timing simulation
GDSII
Timing analysis
Intro iTUTOR
( 11 )
What is iTUTOR
iTUTOR is an educational version of iPROVE.
iTUTOR is a kind of hardware-assisted logic simulation environment.
iTUTOR consists of hardware and software.
Hardware: PCI card containing an FPGA
Software: Development environment and handling API
Intro iTUTOR
( 12 )
6
iTUTOR hardware
FPGA
(Spartan-3 1M gate)
Buffers for DPP
JTAG connector
DPP connector
Serial number
SSRAM
(1M Byte)
Reset switch
PCI controller
PCI
(33MHz, 32-bit)
Intro iTUTOR
( 13 )
iTUTOR software
Intro iTUTOR
( 14 )
7
iTUTOR environment
Test-bench
rest blocks
in HDL, C,
SystemC
IP (DUT)
simulator
PCI bus
Intro iTUTOR
( 15 )
What can do with iTUTOR
Co-emulation
Virtual prototyping
iTUTOR provides a seamless
communication channel between HDL
simulator and FPGA.
Intro iTUTOR
iTOTOR provides a painless path to build
virtual prototype environment.
( 16 )
8
New design flow with iTUTOR
New Design Flow using iTUTOR
Conventional Design Flow
HDL coding
Testbench
HDL coding
HDL logic
simulator
HDL debugging
User
design
HDL debugging
Test bench
User
design
HW design
(Redesign)
Logic syntheis
HDL logic
simulator
iTUTOR S /W
P &R
P&R
Logic Synthesis
HDL logic
simulator
Logic analyzer
PCI
FPGA Board
Simulation and FPGA environment are separated.
Test-bench must be implemented into HW.
FPGA board design and debugging are required.
HW debugging using logic analyzer is required.
Simulation environment and FPGA environment are
co-working throughout whole design flow.
No need to re-design test-bench into HW.
No need to design and debug FPGA board.
Debugging features from HDL simulators are supported.
Intro iTUTOR
( 17 )
iTUTOR product package
(1) Software
(2) iTUTOR Hardware
(3) Traning Material
1. iTUTOR development SW:
Device driver, API, and GUI
2. Diagnosis program
3. Example designs
4. Manuals:
Installation guide, user guide,
tutorial, training book
Intro iTUTOR
( 18 )
9
iTUTOR additional features
iGnite
Verilog front-end
Automatic connection to logic synthesizer, FPGA P&R, and simulator
Easy-to-use debugging
SystemC supporting package
Supporting system-level design through SystemC
SystemC simulator supported
AMBA supporting package
Supporting SoC design flow through AMBA-lite
Intro iTUTOR
( 19 )
iTUTOR summary
DPP
48pin User IO
3.3V LVTTL
PCI bus
Platform
PC Windows
SRAM
1Mbyte
Additional
SystemC
C Compilers
Visual C++
HDL interface
PLI/VPI
FLI/VHPI
HDL simulators
ModelSim SE/PE/AE/XE,
NC-Sim
Synthesizer
Design Compiler, FPGA Compiler II,
XST, LeonardoSpectrum,
Synplify pro, Precision
Interface (PCI)
33MHz
32bit
5V
Devices (FPGA)
Xilinx Spartan 3
Xilinx gates: 1M
P&R
Xilinx ISE
Intro iTUTOR
( 20 )
10
Design, Simulation and Synthesis
Dynalith Systems
www.Dynalith.com
Know about a simple example design,
which is used through iTUTOR tutorial.
How to design using Verilog-HDL.
How to simulate the design using
ModelSim.
How to synthesize the design using
Xilinx XST.
Design
Euclid GCD
Design strategy
IO plan
FSM
Verilog programming for the design
Simulation
Simulation steps using ModelSim
Simulation with command line mode
Simulation with GUI
Synthesis
Intro iTUTOR
( 22 )
11
Euclid GCD
An example that computes the greatest common divisor (GCD) of two nonnegative integers.
Euclid algorithm
For given two integers A and B, where A>=0 and B>0,
GCD(A, B) is
B, if B divides A;
Otherwise, GCD(A, B) is equal to GCD(B, R),
where R is the reminder of A divided by B.
////for
forgiven
givenpositive
positiveinteger
integerAAand
andBB
Euclid_GCD(A,
Euclid_GCD(A,B)
B)
ifif(B==0)
(B==0)then
thenreturn(A);
return(A);
else
elseEuclid_GCD(B,
Euclid_GCD(B,A%B);
A%B);
‘%’ is the modulus operator and it
produces the remainder after division.
Intro iTUTOR
( 23 )
Euclid GCD example
////for
forgiven
givenpositive
positiveinteger
integerAAand
andBB
Euclid_GCD(A,
Euclid_GCD(A,B)
B)
ifif(B==0)
(B==0)then
thenreturn(A);
return(A);
else
Euclid_GCD(B,
else Euclid_GCD(B,A%B);
A%B);
Euclid_GCD(20,
Euclid_GCD(20,4)
4)
Euclid_GCD(4,
Euclid_GCD(4,0);
0);
ifif(B=0)
then
(B=0) thenreturn(4);
return(4);
Euclid_GCD(4,
Euclid_GCD(4,20)
20)
Euclid_GCD(20,
Euclid_GCD(20,4);
4);
Euclid_GCD(4,
Euclid_GCD(4,0)
0)
ifif(B=0)
(B=0)then
thenreturn(4);
return(4);
Euclid_GCD(211,
Euclid_GCD(211,31)
31)
Euclid_GCD(31,
Euclid_GCD(31,25);
25);
Euclid_GCD(25,
Euclid_GCD(25,6)
6)
Euclid_GCD(6,
Euclid_GCD(6,1)1)
Euclid_GCD(1,
Euclid_GCD(1,0)
0)
ifif(B=0)
(B=0)then
thenreturn(1);
return(1);
Intro iTUTOR
( 24 )
12
Design strategy
A
B
tester
generator
C
gcd
checker
DUT (Design Under
Test) implementing
Euclid GCD.
Test-bench (tester) consisting of
‘generator’ and ‘checker’ module.
‘generator’ makes
two integer values.
‘checker’ validates
the result.
Intro iTUTOR
( 25 )
IO plan
GCD block needs a handshake
mechanism in order to indicate valid
cycle for the data.
tester
A[11:0]
B[11:0]
valid
GCD requires variable length of cycles to
complete.
C[11:0]
done
gcd
clk
reset
clk
reset
A, B
valid
C
done
reset
valid input
GCD cycles
Intro iTUTOR
valid result
( 26 )
13
Ex 1: Euclid Simulation & Synthesis
Directory structure
…\itutor_project\ex1_euclid_simsyn
ex1
ex1
design
design
Verilog source code folder
sim
sim
HDL simulation folder
syn
syn
Synthesis folder
Intro iTUTOR
( 27 )
FSM for GCD (an example)
IDLE
reset
valid?
TÅA
RÅB
R!=0?
doneÅ0
FOUND
R==0?
CÅT
doneÅ1
MODULOS
T<R?
TÅR
RÅT
T>=R?
TÅR
RÅT-R
DONE
Intro iTUTOR
always @ (posedge clk or posedge reset) begin
if (reset==1'b1) begin
C <= 12'b0; done <= 1'b0;
T <= 12'b0; R
<= 12'b0; state <= IDLE;
end else begin
case (state)
IDLE: if (valid) begin
T <= A; R <= B; state <= FOUND;
end // if (valid)
FOUND: if (R==12'b0) begin
C <= #1 T; done <= #1 1'b1;
state <= DONE;
end else begin
state <= MODULUS;
end // if (R==12'b0)
MODULOS: if (T<R) begin
T <= R; R <= T;
end else begin
T <= R; R <= T - R; state <= FOUND;
end // if (T<R)
DONE: begin
done <= #1 1'b0; state <= IDLE;
end // DONE
endcase
end // if (reset==1'b1)
end
( 28 )
14
Verilog design: gcd.v
module gcd ( clk, reset, A, B, valid, C, done );
case (state)
//-----------------------------------------------------IDLE: begin
// IO ports
if (valid) begin
input
clk;
T <= A; R <= B;
input
reset;
state <= FOUND;
input [11:0] A;
end end // IDLE
input [11:0] B;
FOUND: begin
input
valid;
if (R==12'b0) begin
output [11:0] C; reg [11:0] C;
C <= #1 T;
output
done; reg
done;
done <= #1 1'b1;
//-----------------------------------------------------state <= DONE;
// internal registers
end else begin
reg [11:0] T; // temporal
state <= MODULUS;
reg [11:0] R; // remainder
end end // FOUND
reg [1:0] state; // FSM state
MODULUS: begin
//-----------------------------------------------------if (T<R) begin
parameter IDLE = 2'h0;
T <= R; R <= T;
swapping T & R using
parameter FOUND = 2'h1;
end else begin
non-blocking
parameter MODULUS = 2'h2;
T <= R;
assignment
parameter DONE = 2'h3;
R <= T - R;
//-----------------------------------------------------state <= FOUND;
// FSM
end end // MODULUS
always @ (posedge clk or posedge reset) begin
DONE: begin
if (reset==1'b1) begin
done <= #1 1'b0;
C <= 12'b0;
state <= IDLE;
done <= 1'b0;
end // DONE
T <= 12'b0;
endcase
R <= 12'b0;
end // if (reset==1'b1)
state <= IDLE;
end
end else begin
endmodule
Intro iTUTOR
A
B
valid
C
done
gcd
clk
reset
( 29 )
Verilog design: top.v
module top ;
//-----------------------------------------------------//-----------------------------------------------------// signals
initial begin
$dumpfile("wave.vcd");
wire
clk;
$dumpvars(1, clk);
wire
reset;
wire [11:0] A;
$dumpvars(1, reset);
waveform file
$dumpvars(1, A, B, valid);
wire [11:0] B;
$dumpvars(1, C, done);
wire
valid;
wire [11:0] C;
$dumpvars(1, Ugcd);
$dumpvars(1, Utester);
wire
done;
//-----------------------------------------------------//
#1000;
gcd Ugcd (.clk (clk),
//
$finish;
end // initial
.reset(reset),
endmodule
.A (A),
.B (B),
.valid(valid),
A
.C (C),
tester
.done (done));
B
tester #(5,10) Utester (
.clk(clk),
valid
.reset(reset),
parameter setting
C
.A (A),
.B (B),
done
.valid(valid),
.C (C),
clk
.done (done));
gcd
reset
Intro iTUTOR
( 30 )
15
Verilog design: tester.v (1/2)
system task
module tester ( clk, reset, A, B, valid, C, done );
parameter num = 10;
parameter period = 10;
//------------------------------------------------------ parameters
// IO ports
output
clk; reg
clk;
output
reset; reg
reset;
output [11:0] A;
reg [11:0] A;
output [11:0] B;
reg [11:0] B;
output
valid; reg
valid;
input [11:0] C;
wire [11:0] C;
input
done; wire
done;
//-----------------------------------------------------always #(period/2) clk <= ~clk;
initial begin
clk = 1'b0;
reset = 1'b0;
A = 12'b0;
B = 12'b0;
valid = 1'b0;
@ (posedge clk);
reset = 1;
@ (posedge clk);
reset = 0;
@ (posedge clk);
repeat (num) begin //forever begin
fork generator;
checker;
concurrent
join
activities
end // forever
$finish;
finish here
end // initial
//-----------------------------------------------------task generator;
tester
begin
@ (posedge clk);
A <= #1 $random&8'hFF;
B <= #1 $random&8'hFF;
valid <= #1 1'b1;
@ (posedge clk);
A <= #1 12'b0;
B <= #1 12'b0;
valid <= #1 1'b0;
while (done==1'b0) @ (posedge clk);
end
endtask // generator
//-----------------------------------------------------task checker;
task
reg [11:0] Ta, Tb, Tc;
begin
while (valid==1'b0) @ (posedge clk);
Ta <= A;
Tb <= B;
function
Tc <= euclid_gcd(A, B);
while (done==1'b0) @ (posedge clk);
if (C==Tc) $display($time,,"GCD(%d, %d)=%d", Ta,
Tb, Tc);
else
$display($time,,"Error: GCD(%d, %d)=%d,
but %d was received!", Ta, Tb, Tc, C);
end
endtask // checker
Intro iTUTOR
A
B
valid
C
done
clk
reset
( 31 )
Verilog design: tester.v (2/2)
//-----------------------------------------------------// Euclid_GCD(A, B)
// if (B==0) then return(A);
// else Euclid_GCD(B, A%B);
function
function [11:0] euclid_gcd;
input [11:0] A;
input [11:0] B;
reg [11:0] T, R, tmp;
begin
T = A;
R = B;
while (R) begin
tmp = T;
T = R;
modulus
R = tmp%R;
end // while (R)
euclid_gcd = T;
end
endfunction // euclid_gcd
endmodule
Intro iTUTOR
( 32 )
16
Simulation
Simulation using Mentor Graphics ModelSim
Simulation steps using ModelSim
Simulation with command line mode
Simulation through GUI
Intro iTUTOR
( 33 )
Simulation steps
1. Compile
Convert the Verilog source code into an internal format that is ready for ModelSim
to simulate.
2. Simulate
the internal format by instantiating all the design modules and using a top level
stimulus file to drive test signals onto the inputs of your design and inspecting the
outputs.
Intro iTUTOR
( 34 )
17
Simulation with command-line (1/3)
Go to …\itutor_project\ex1_euclid_simsyn\sim\ms_cmd
Windows batch command file
“RunMe_short.bat”
Create a design library (directory)
with the name of ‘work’
vlib work
vlog ../../design/gcd.v
vlog ../../design/tester.v
vlog ../../design/top.v
vsim -c -do "run -all; quit" work.top
Compile Verilog design files
Run simulator
Commands for simulator
Design top module
Intro iTUTOR
( 35 )
Windows command prompt> RunMe_short.bat
Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10 2004
-- Compiling module gcd
Top level modules:
gcd
-- Compiling module tester
Top level modules:
tester
-- Compiling module top
Top level modules:
top
Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
Intro iTUTOR
( 36 )
18
# 6.0a
# vsim -do {run -all; quit} -c work.top
# Loading C:\iTUTOR\eda\modelsim\5.7c\iprvpi.dll
# Loading work.top
# Loading work.gcd
# Loading work.tester
# run -all; finish
#
#
285 GCD( 36, 129)= 3
#
645 GCD( 9, 99)= 9
#
1185 GCD( 13, 141)= 1
#
1515 GCD( 101, 18)= 1
#
1935 GCD( 1, 13)= 1
# ** Note: $finish : ../../design/tester.v(38)
# Time: 1935 ns Iteration: 0 Instance: /top/Utester
Windows command prompt> dir
make.bat transcript wave.vcd
work
Intro iTUTOR
( 37 )
VCD Waveform (1/3)
Intro iTUTOR
( 38 )
19
VCD Waveform (2/3)
Intro iTUTOR
( 39 )
VCD Waveform (3/3)
Intro iTUTOR
( 40 )
20
Simulation through GUI
Enter the name
of project
Intro iTUTOR
( 41 )
Intro iTUTOR
( 42 )
21
Intro iTUTOR
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Intro iTUTOR
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22
Intro iTUTOR
( 45 )
Intro iTUTOR
( 46 )
23
Intro iTUTOR
( 47 )
Synthesis
Synthesis using Xilinx Synthesis Technology (XST) of Integrated Software
Environment (ISE)
Synthesis with command line mode
Synthesis through GUI
Refer to “iPROVE EDIF Generation Guide” to generate the proper EDIF
for iTUTOR/iPROVE.
Intro iTUTOR
( 48 )
24
Synthesis with command-line
Go to …\itutor_project\ex1_euclid_simsyn\syn\xst_cmd
“RunMe.bat”
set target=gcd
xst -ifn compile.xst -ofn compile.log
ngc2edif -bd angle -w compile.ngc %target%.edif
“compile.xst”
set -tmpdir .
run
-ifmt VERILOG
-top $target
-p xc3s1000-fg456
-ifn compile.prj
-vlgincdir ../../design
-ofn compile
-ofmt NGC
……
-iobuf NO
-fsm_encoding User
……
-iob auto
“compile.prj”
`include "../../design/gcd.v"
Important notice:
iTUTOR does not need IO pads.
FSM encoding can be changed
without this option
Intro iTUTOR
( 49 )
Synthesis through GUI (1/9)
Invoke
‘Project Navigator’
Intro iTUTOR
( 50 )
25
Specify syn folder
Next
Intro iTUTOR
Cancel
( 51 )
Previous
Next
Cancel
Previous Next
Intro iTUTOR
Cancel
( 52 )
26
Select gcd.v in design folder
Previous
Intro iTUTOR
Finish
Cancel
( 53 )
Disable I/O Buffer
Ok
Intro iTUTOR
Cancel
( 54 )
27
Intro iTUTOR
( 55 )
Intro iTUTOR
( 56 )
28
Intro iTUTOR
( 57 )
Intro iTUTOR
( 58 )
29
Run ngc2edif manually
ngc2edif -bd angle -w compile.ngc gcd.edif
Intro iTUTOR
( 59 )
Co-emulation using iTUTOR
Dynalith Systems
www.Dynalith.com
30
Understand iTUTOR design flow.
Understand terminologies of iTUTOR.
How to use iTUTOR software.
How to co-emulate user design using
iTUTOR.
Design flow using iTUTOR
Prerequisites for iTUTOR
Card identification number
Emulation mode: cycle and transaction
Proxy
Clock sensitivity
Clock domain
EIF
Prepare design for iTUTOR
HDL co-emulation using iTUTOR
Intro iTUTOR
( 61 )
Design flow using iTUTOR
Test-bench
DUT
Logic design & simulation
Logic synthesis
Logic
synthesizer
EDIF
iTUTOR
libraries
iTUTOR
compilation
FPGA
P&R
EIF
iTUTOR compilation
HDL
simulator
PCI bus
Co-emulation
Intro iTUTOR
( 62 )
31
Prerequisites for iTUTOR
Emulation mode: cycle and transaction
Proxy
Clock sensitivity
Clock domain
Combinational path
EIF
Intro iTUTOR
( 63 )
Each iPROVE card is assigned a unique number from 0 to 9, since more than
one iPROVE cards can be plugged into PCI slots,
However, iTUTOR has a fixed card identification number and it is 0.
Note that iTUTOR is an educational version of iPROVE.
As a result, only one iTUTOR card can be used in a host computer.
But, iPROVE in addition to iTUTOR can be used in a host computer as far as its
card identification number is not 0.
Intro iTUTOR
( 64 )
32
Emulation modes
Cycle mode
Transaction mode
Gate/
RTL/
BCA
UTF/
TF
Intro iTUTOR
BFM/
Transactor
Gate/
RTL/
BCA
Gate/
RTL/
BCA
( 65 )
iTUTOR emulation modes
HDL
design
HDL
simulator
Host Computer
High-level
program
(C/C++)
Host Computer
High-level
program
(C/C++)
Host Computer
Signal
information
PCI
Signal
information
PCI
Transaction
commands
PCI
Automatically
generated
interface
DUT
(IP)
Hardware-assisted
HDL simulation acceleration
DUT
(IP)
Cycle-controlled verification
using high-level languages
DUT
(IP)
Transaction-level verification
for higher performance
iPROVE H/W
Automatically
generated
interface
iPROVE H/W
Transactor
(User
provided)
iPROVE H/W
Intro iTUTOR
( 66 )
33
Proxy module
Ordinary logic simulation
Co-emulation using FPGA
Proxy module represents the module in the FPGA
and takes care of synchronization between the
event-driven logic simulator and actually-running
hardware block in aids of co-emulation interface.
Intro iTUTOR
( 67 )
Clock sensitivity
Use ‘positive’ clock edge if there are only
positive-edge triggering Flip-Flops in
DUT.
Use ‘negative’ clock edge if there are
only negative-edge triggering Flip-Flops
in DUT.
Use ‘both’ clock edge if there are both
positive & negative-edge triggering FlipFlops in DUT.
Each clock sensitive event incurs
synchronization between logic simulator
and iTUTOR, i.e., both sensitivity will
cause more communication overhead.
Intro iTUTOR
….
always @ (posedge clk) begin
……
end
D
….
always @ (negedge clk) begin
……
end
D
Q
clk
Q
clk
….
always @ (posedge clk) begin
……
end
…
always @ (negedge clk) begin
……
end
( 68 )
34
Clock domain
Each independent clock is represented as a clock domain.
Intro iTUTOR
( 69 )
EIF
EIF stands for ‘Emulation Information File’.
EIF is defined by Dynalith Systems for iPROVE/iTUTOR.
EIF contains all necessary information for co-emulation as follows.
Module information
Pin information of each module
FPGA mapping data, i.e., bit-stream
Intro iTUTOR
( 70 )
35
Example design
A
B
tester
generator
C
gcd
checker
DUT (Design Under
Test) implementing
Euclid GCD.
Test-bench (tester) consisting of
‘generator’ and ‘checker’ module.
‘generator’ makes
two integer values.
‘checker’ validates
the result.
Intro iTUTOR
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Prepare design for iTUTOR
Basic steps for preparing design for iTUTOR
Logic design and simulation Æ done at EX1
Logic synthesis Æ done at EX1
iTUTOR compilation
Invoking iTUTOR GUI
Make a new project
Importing EDIF as iTUTOR library
Importing design from iTUTOR library
iTUTOR compilation
Intro iTUTOR
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36
Ex 2: Euclid Emulation
Directory structure
…\itutor_project\ex2_euclid_itutor
ex2
ex2
design
design
syn
syn
Verilog source code folder
Synthesis folder
itutor
itutor
iTUTOR P&R folder
coemul
coemul
Co-emulation folder
Intro iTUTOR
( 73 )
Invoking iTUTOR
From desktop icon
From start menu
Double click the iTUTOR icon on the
desktop
Select iTUTOR program from start menu
Intro iTUTOR
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37
iTUTOR windows
Menu bar
Tool bar
Status window
Message window
Intro iTUTOR
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Make a new project
Go to itutor folder
It determines the followings
Project file: euclid.ips
EIF file: euclid.eif
Intro iTUTOR
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38
New project opened
Intro iTUTOR
( 77 )
Import library (1/2)
Intro iTUTOR
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39
Import library (2/2)
Select the post synthesis data, i.e. EDIF.
It will be …\itutor_project\ex2_euclid_itutor\syn\xst_cmd\gcd.edif
Intro iTUTOR
( 79 )
Import design
Intro iTUTOR
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40
Import design: selecting design
It determines the proxy
file name: gcd_proxy.v
Intro iTUTOR
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Import design: setting design
Intro iTUTOR
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41
Import design: setting clock
Select a clock port, specify
clock domain, and click
‘Assign’ button.
Intro iTUTOR
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Import design: done
Click ‘Ok’ button
Intro iTUTOR
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42
Compile all
Intro iTUTOR
( 85 )
End of compilation
Intro iTUTOR
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43
Save project
Intro iTUTOR
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Exit project
Intro iTUTOR
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44
After compilation
EIF file
Project file
Proxy for Verilog
Proxy for VHDL
Intro iTUTOR
( 89 )
HDL co-emulation
Test-bench modification
Define ‘iPROVE_EIF_FILE’ parameter as EIF file (See top.v)
Intro iTUTOR
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45
Verilog design: top.v for iTUTOR
module top ;
//-----------------------------------------------------//-----------------------------------------------------initial begin
// signals
$dumpfile("wave.vcd");
wire
clk;
$dumpvars(1, clk);
wire
reset;
$dumpvars(1, reset);
wire [11:0] A;
$dumpvars(1, A, B, valid);
wire [11:0] B;
$dumpvars(1, C, done);
wire
valid;
$dumpvars(1, Ugcd);
wire [11:0] C;
$dumpvars(1, Utester);
wire
done;
//
#1000;
//-----------------------------------------------------//
$finish;
parameter iPROVE_EIF_FILE=“../../itutor/eculid.eif”;
end // initial
gcd Ugcd (.clk (clk),
endmodule
.reset(reset),
.A (A),
.B (B),
A
.valid(valid),
Specify where EIF locates
tester
.C (C),
B
.done (done));
tester #(5,10) Utester (
valid
.clk(clk),
C
.reset(reset),
.A (A),
done
.B (B),
.valid(valid),
clk
.C (C),
.done (done));
gcd
reset
Intro iTUTOR
( 91 )
Proxy model for iTUTOR for Verilog
module gcd (
clk,
reset,
valid,
A,
B,
done,
C
);
input
input
input
input
input
output
output
clk;
reset;
valid;
[11:0]
[11:0]
done;
[11:0]
A;
B;
C;
initial $iProveEmulation;
endmodule
Intro iTUTOR
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46
HDL-HW Co-Simulation/Emulation
tester
A
B
synthesizer
valid
C
gcd
(proxy
model)
done
gcd
(verilog)
clk
iTUTOR S/W
reset
HDL
simulator
PCI bus
HDL-HW Co-Simulation/Emulation
Intro iTUTOR
( 93 )
Emulation with command-line (1/5)
Go to ‘coemul’ folder
…\itutor_project\ex2_euclid_itutor\coemul
“RunMe.bat”
Create a design library (directory)
with the name of ‘work’
vlib work
vlog ../../itutor/gcd_proxy.v
vlog ../../design/tester.v
vlog ../../design/top.v
vsim -c -do "run -all" work.top
Compile the proxy module
Run simulator
Commands for simulator
Design top module
Intro iTUTOR
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47
Windows command prompt> RunMe.bat
-- Compiling module gcd
Top level modules:
gcd
-- Compiling module tester
Top level modules:
tester
-- Compiling module top
Top level modules:
top
Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
Intro iTUTOR
( 95 )
# 6.0a
Loading iTUTOR related library
# vsim -do {run -all} -c work.top
# Loading C:\iTUTOR\eda\modelsim\5.7c\iprvpi.dll
# Loading work.top
# Loading work.gcd
# ** Warning: (vsim-3009) [TSCALE] - Module 'gcd' does not have a `timescale directive in
effect, but previous modules do.
Starting of iTUTOR initialize
#
Region: /top/Ugcd
# Loading work.tester
# run -all
# INFO: Loading iprvpi.so(dll)
# INFO: Reading emulation information file '../../itutor/euclid.eif'
# INFO: Version of iPROVE API : 3.161
#
# INFO: Version of Emulation Information File(EIF) : 1.01
#
# INFO: Card ID 0: Version of iProveBaseBoard Controller : 4.38
#
Intro iTUTOR
( 96 )
48
# INFO: Card ID 0: Version of device driver : 3.14
iTUTOR card open
#
iTUTOR card information
# INFO: Card ID 0: Card share-mode is disabled.
#
# INFO: Card ID 0: iPROVE PCI Card was opened successfully.
#
# INFO: Card ID 0: Target Device of TCF file
:spartan3 3s1000fg456
#
# INFO: Card ID 0: Device of AppBoard
:SPARTAN3 3s1000fg456 (0)
#
Configuring iTUTOR
# INFO: Card ID 0: Configuring FPGA.......Done
#
# INFO: Card ID 0: Checking FPGA configuration...Done
#
# INFO: Card ID 0: Version of iProveAppBoard Controller : 1.87
#
# INFO: CYCOPT_MMAP: Cycle-level optimization is enabled.
#
# INFO: Cleaning up...
Intro iTUTOR
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# INFO: Instance 'gcd' is mapped to HDL module 'top.Ugcd.'
# INFO: Clock(Card ID:0, Domain ID:0) is operating in 'Positive-edge sensitive' mode.
# INFO: iPROVE is sucessfully ready for simulation.
Clock sensitivity report
# INFO: Start time: Thu Jul 14 17:45:31 2005
#
#
285 GCD( 36, 129)= 3
#
645 GCD( 9, 99)= 9
Co-emulation result
#
1185 GCD( 13, 141)= 1
#
1515 GCD( 101, 18)= 1
#
1935 GCD( 1, 13)= 1
# ** Note: $finish : z:/iTutorTutorial/examples/euclid/coemul/ms_cmd/../../design/tester.v(57)
# Time: 1935 ns Iteration: 0 Instance: /top/Utester
# INFO: End time: Thu Jul 14 17:45:32 2005
# INFO: Total time: 1.000000 secs
# INFO: CPU time: 0.040000 secs in simulation
# INFO: Closing iPROVE Cards
# INFO: Cleaning up...
iTUTOR card close
Intro iTUTOR
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49
Note
Intro iTUTOR
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Note
Intro iTUTOR
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50

iTUTOR Introduction and Quick Tutorial

Transcription

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