Wafer Level Packaging – New achievements of technical

Transcription

Arcsis Micropackaging Days
29th-30st November 2007
Gardanne, France
Wafer Level Packaging – New achievements
of technical feasibility & reliability by using
an electroless UBM
T. Oppert, Dr. E. Zakel, Dr. T. Teutsch
oppert@pactech.de
Certified ISO 9001: 2000 & ISO TS 16949
Confidential
Content
•
Overview on Semiconductor Markets
–
–
•
ENIG UBM – History & Now
–
–
–
–
–
•
The early days of eless NiAu
Licenses & worldwide wafer bumping capacity
Pac Tech and eless NiAu now
Yield, CpK etc.
Equipment for eless NiAu
Soldering
–
•
1970 to 2010
Applications and usage/implementation of eless NiAu
Paste Printing
Reliability Data
Confidential
Overview on
Semiconductor Markets
Confidential
Evolution Semiconductor Market 1970 - 2010
Consumer/Wireless
Internet
Enterprise
Government
Military/ Aerospace
Source: SIA
Confidential
Semiconductor Market 2006
Cell Phone/ mobil
17,00%
Wired Comm
7,00%
PC/ Computer
43,70%
Industrial/ Military
7,30%
Automotive 8,70%
Consumer
17,20%
Confidential
Worldwide use of Pac Tech ENIG
& solder printing
LCD Driver/
ASIC; 5,00%
Memory;
5,00%
RFID; 20,00%
Medical;
10,00%
Mobile Phone;
40,00%
MOSFET;
20,00%
Confidential
Electroless NiAu
History & Now
Confidential
History of electroless Ni/Au @ Pac Tech
•
•
•
•
•
•
Basic studies & publications in 1985
First active electroless bumped wafer in 1989
Formation of Pac Tech in 1995
Further developments of the eless Ni UBM
Pilot production line in 1997
Start of customer qualification & production in 1998
2007…Pac Tech Wafer Bumping facilities in
Germany, USA, Japan, Malaysia
…10x Pac Tech eless NiAu Bumping process
licensed and equipment installed worldwide
Confidential
…more electroless Ni/Au
• ENIG NOT only for Al, also for Cu pads
• ENIG UBM for FC and Wire Bonding
• Eless Ni/Pd/Au for Wire Bond of Power
Devices
Confidential
Business Development
– Installed Equipment for ENIG UBM & Technology Transfer/Licenses of Pac Tech
Germany
Growth
Telecom.
France
Telecom.
USA
(PacTech)
Japan
(ABT)
Subcon
Korea
(STW)
LCDDriver
USA
Memory
30
0m
m
SubCon
30
0m
Philippines
Telecom.
30
0m
30
0m
m
USA
Power
Dev.
Malaysia
Japan
Q4/07
Nagase
30
0m
m
30
0m
m
France
Q4/07
m
m
Year
2000
2001
2002
2003
2005
2006
2007
2008
Confidential
Pac Tech Group Worldwide
Wafer Bumping Capacity
2006
<4-8" Wafer>
<12" Wafer>
Pac Tech GmbH
600k
100k
Pac Tech USA
600k
150k
ABT ("Pac Tech Japan")
450k
2007
<4-8" Wafer>
-
<12" Wafer>
Pac Tech GmbH
600k
100k
Pac Tech USA
600k
150k
600k
-
Pac Tech Asia
300k
100k
2008
<4-8" Wafer>
<12" Wafer>
Pac Tech GmbH
600k
100k
Pac Tech USA
600k
150k
600k
150k
Pac Tech Asia
600k
150k
Confidential
Wafer Level UBM
Electroless NiAu & NiPdAu
Confidential
Design Rules for Electroless Ni/Au Bumping
wafer size
4” - 12”
wafer thickness
175 µm (7 mil) (up to 8“)
pad geometry
any (square, rectangular, round)
pad size
40 µm (10 µm)
pad spacing
20 µm (5 µm)
metallization
AlSi1, AlSi1Cu0.5, AlCu2
Al thickness
1 µm (0.5 µm)
passivation
defect-free nitride, oxide, polyimide
scribe line
insulating (test structures acceptable)
probing
before or after Ni/Au plating
laser trimming
depending on technology
Confidential
Process Flow - Electroless Ni/Au Bumping
Al Pad
Cu Pad
Zinkating
Pd Seed
Ni Plating
Flash Au
FCB
Pd Barrier
Flash Au
Flash Au
Thick Au
Wire Bonding
Wire Bonding
Confidential
Under Bump Metal Process
Electroless Plating of Ni/Au Bumps on Al pad 1/2
Backside Coating
Pad Cleaning
Pad Activation
Electroless Nickel
Flash Gold
Coating Removal
Confidential
Under Bump Metal Process
Electroless Plating of Ni/Au Bumps on Al pad 2/2
Confidential
300 m
Electroless Ni/Au on Copper Pad
m Ca
pabi
lity
!
Backside Coating
Pad Cleaning
Pd Treatment
Electroless Nickel
Flash Gold
Coating Removal
Confidential
Electroless Ni/Pd/Au Bumping on Al
Backside Coating
Aluminum Cleaning
Zincate Pretreatment
Electroless Nickel
Electroless Palladium
Immersion Gold
Coating Removal
Confidential
Flip Chip Modules for contactless Smart Cards
UBM: Electroless NiAu
Assembly: Flip chip attach by Laplace soldering
Confidential
Eless NiAu UBM
Yield, Cpk
Confidential
Chip yield
• Average chip yield for all customer prodcuts
– 2005: 99.65
– 2006: 99.73
– 2007 (Jan-Sep): 99.91
Yield (%)
Yield (% )
100,20
100,00
99,80
99,60
99,40
99,20
99,00
98,80
98,60
Jan
Feb
März
April
Mai
Juni
Juli
Aug
Sept
Monate (2007)
Confidential
CpK – bump height
Average CpK 2007 for all processed wafers
(Jan-Sep): 1.78
Cpk- Werte Bump-Höhe
2,50
Cpk-Wert
2,00
1,50
1,00
0,50
0,00
Jan
Feb
M ärz
A pril
M ai
Juni
Juli
A ug
Sept
Monate (2007)
Confidential
CpK – shear force
Average CpK 2007 for all processed wafers
(Jan-Sep): 2.42
Cpk- Werte Scherkraft
3,50
3,00
Cpk-Wert
2,50
2,00
1,50
1,00
0,50
0,00
Jan
Feb
M ärz
A pril
M ai
Juni
Juli
A ug
Sept
Monate (2007)
Confidential
Equipment for ENIG UBM
Confidential
Advantages of ENIG UBM using PacLine 300 A50
•
Low Capital Investment Cost
10-20 Mio US$
ElectroPlating:
Electroless UBM + Solder Print/Ball:
3-5 Mio US$
•
High Throughput
600.000 wafers per year 8“; 312.000 wafers 12“ per year
•
Maskless Process
No tooling required
•
Low Process Cost compared to Electroplating
Low Cost Process cost per wafer
•
Compatible for wafers from 4“ to 12“
no additional invest for different wafer sizes
•
Proven Reliability
•
Compatibility with all FC-Assembly processes
Soldering
ACF
NCP
•
Suitable for Al and Cu pad metallization
•
Suitable for NiAu and NiPdAu
•
Compatibility with Wire Bonding
Confidential
Pacline 300 - A50
10 ENIG Plating Systems in the Field @ major OEM’s
300 mm
Confidential
Pacline 300 - A50
Parallel processing of 3 carriers with each 50 wafers 8“ or 3 carriers with 26 wafers 12”
- UPH: max. 150 Wafers 8"/hour or max. 78 wafers 12”/hour (5µm Ni/Au UBM)
- Thick Au ability for wire bonding reliability
- Ni bath control with ConPac 2.0 (bath conditioner) and ConPac control set
- Central Computer Control Unit (CCCU)
- PLC with Profi Bus system
- Additional security tanks for each module and pump system
- Design will be adapted to customer’s facility
- SECS GEM Interfacing
- The system fulfils the fire safety standard FM 4910
Confidential
Wafer Level Solder Printing
Confidential
Comparison of Solder Bumping Technologies
Evaporated Solder
Bump
C4 Solder
Sputtered UBM +
Plating
Sputtered UBM +
Print (FCT)
Electroless UBM (+)
Print or Ball Attach
Solder
Solder
Au
Solder
Ni/Au
Confidential
Stencil Solder Printing Process Flow
SnPb37, Lead-free: SnAgCu
Electroless Ni/Au Bumping
PbSn
Solder Paste Printing
Reflow
Wafer Cleaning
Wafer Inspection
Pack & Ship
Confidential
Applications
GSM Phone: Battery Control
Wafer: Si-Ge Technology
Protection Devices
Confidential
Solder Printing on 300mm Wafer
• 740.000 I/O per Wafer
• 680 I/O per Chip
• 225µm pitch
• 100µm pad size
• 70µm solder ball height
Confidential
Reliability Data
Confidential
TYPICAL WAFER LEVEL CSP TEST CONDITIONS
1.ACLV (Autoclave)
@ 121 °C, 15 PSIG, 100% RH with 3x Reflow @ 260°C, 96 Hrs
2.TMCL (Temperature Cycle) – Component Level
@ -65 to +150 °C, 15min Dwell with 3x Reflow @ 260°C, 500 Cycles
3.B-TMCL (Board Level Temperature Cycle)
@ -10 to +100 °C, 15min Dwell with 2x Reflow @ 260°C, 2000 Cycles
4.PRCL (Power Cycle)
2 mins on/off (others), Delta Tj >=100°C, 10,000 Cycles
5.HAST (Highly Accelerate Stress Test)
@ 85% RH, 130 °C, Vr = 80%Bv with 2x Reflow @ 260°C, 96 Hrs
6.HTRB (High Temperature Reverse Bias)
@ Ta = 150 °C, 80% Rated BVDSS, 1000 Hrs
7.HTGB (High Temperature Gate Bias)
@ Ta = 150 °C, 100% Rated VGS, 1000 Hrs
Confidential
1) Wafer Level CSP MOSFET – Customer A
Die size:
1 x 1.5 mm
Number of I/O's:
6 bumps per chip
Pitch / Ball Dia.
500 µm / 300 µm
Wafer size:
6 inch
Assembly: Soldering on organic PCB w/o underfill
Reliability:
•
•
•
•
•
•
•
TMCL, -65°C / + 150°C
HAST, 130°C /85% rH
HTRB, 150°C
HTGB, 150°C
PRCL, Tj=100°C
ACLV, 121°C, 15 PSI
B-TMCL, -10°C / + 100°C
Lot size:
500 cycles
96 hours
1000 hours
1000 hours
10k cycles
96 hours
2000 cycles
- no failure
- no failure
- no failure
- no failure
- no failure
- no failure
- no failure
77 parts per test conditions
Confidential
2) Wafer Level CSP MOSFET – Customer B
Die size:
1 x 1.5 mm
Number of I/O's:
6 bumps per chip
Pitch / Ball Dia.
500 µm / 300 µm
Wafer size:
6 inch
Reliability:
•
•
•
•
•
•
•
TMCL, -65°C / + 150°C
HAST, 130°C /85% rH
HTRB, 150°C
HTGB, 150°C
PRCL, Tj=100°C
B-TMCL, -55°C / + 125°C
Lot size:
1000 cycles
100 hours
1000 hours
1000 hours
10k cycles
96 hours
1000 cycles
- no failure
- no failure
- no failure
- no failure
- no failure
- no failure
- no failure
Confidential
3) Wafer Level CSP - FM Radio
Die size:
3.5 x 3.5 mm
Number of I/O's:
34 bumps per chip
Pitch / Ball Dia.
500 µm / 300 µm
Wafer size:
6 / 8 inch
Reliability:
•
•
•
•
•
•
•
TMCL, -55°C / + 125°C
U-HAST, 130°C /85% rH
HTOL, 125°C, biased
HTSL, 150°C
THB, 85°C/85% RH, biased
B-TMCL, -40°C / + 125°C
Drop Test (84 devices/7 boards)
1000 cycles
192 hours
2000 hours
1000 hours
2000 hours
500 cycles
300 drops
- no failure
- no failure
- no failure
- no failure
- no failure
- no failure
- < 5%*
*Required: 100 drops < 5%
Lot size: 77 parts – HTSL, UHST, TMCL, 44 parts – HTOL, THB
Confidential
TYPICAL LEAD FRAME BGA TEST CONDITIONS
1.ACLV (Autoclave)
@ 121°C, 100%RH, 15psi with 3x Reflow @ 260°C Peak Temperature
2.Component Level TMCL (Temperature Cycle)
@ -65 to 150°C, 15min Dwell with 3x Reflow @ 260°C Peak Temperature
3.Board Level TMCL (Temperature Cycle)
@ -25 to 125°C, 9min dwell with Sony-Ericsson Precondition flow
4.PRCL (Power Cycle)
@ 125°C Tjc, delta Tj of 100°C, 2min ON & 2min OFF
5.HAST (Highly Accelerated Stress Test)
@ 130°C, 85%RH, Vr = -16V
6.UHAST (Unbiased Highly Accelerated Stress Test)
@ 130°C, 85%RH
7.HTRB (High Temperature Reverse Bias)
@ 150°C, Vr = -16V
8.HTGB (High Temperature Gate Bias)
@ 130°C, 85%RH, Vgs = -12V
Confidential
4) Lead-frame MOSFET BGA
Die size:
1 x 1.5 mm
Number of I/O's:
6 bumps per chip
Pitch / Ball Dia.
500 µm / 300 µm
Wafer size:
6 inch
Reliability:
•
•
•
•
•
•
•
TMCL, -65°C / + 150°C
HAST, 130°C /85% rH
HTRB, 150°C
HTGB, 150°C
PRCL, Tj=100°C
B-TMCL, -25°C / + 125°C
Lot size:
500 cycles - no failure
96 hours
- no failure
1000 hours - no failure
10k cycles - no failure
96 hours
- no failure
Confidential
5) Lead-frame MOSFET BGA
Die size:
3.5 x 4 mm
Number of I/O's:
20 bumps per chip
Pitch / Ball Dia.
650 µm / 300 µm
Wafer size:
6 inch
Reliability:
•
•
•
•
•
•
•
TMCL, -65°C / + 150°C
HAST, 130°C /85% rH
HTRB, 150°C
HTGB, 150°C
PRCL, Tj=100°C
B-TMCL, -25°C / + 125°C
Lot size:
96 hours
- no failure
96 hours
- no failure
Confidential
6) Lead-frame BGA
Die size:
4.3 x 5.5 mm
Number of I/O's:
20 bumps per chip
Pitch / Ball Dia.
800 µm / 500 µm
Wafer size:
6 inch
Reliability:
•
•
•
•
•
•
•
TMCL, -65°C / + 150°C
HAST, 130°C /85% rH
HTRB, 150°C
HTGB, 150°C
PRCL, Tj=100°C
B-TMCL, -25°C / + 125°C
Lot size:
96 hours
- no failure
96 hours
- no failure
Confidential
7) PowerMOSFET (Clip Attach)
Die size:
Number of I/O's:
Wafer size:
Assembly:
multiple layouts
2 pads per chip (gate & source)
6 inch / 8 inch
soldering, clip attach,
Au wire bonding (gate)
Reliability:
•
HTSL, 150°C
Preconditioning: 168hrs 85%/85C + 3 solder reflow @ 260°C (peak)
•
•
•
•
•
TMCL, -65°C / + 150°C
HAST, 130°C /85% rH
Parametric Drift
Bond Integrity , 150°C, N2
1000 cycles
100 hours
96 hours
250 cycles
500 hours
- no failure
- no failure
- no failure
- no failure
- no failure
Lot size: HTSL (82 pcs), HAST, TMCL, ACLV (55 pcs), PD (200 pcs), BI (40 pcs)
Confidential
Summary
•
Overview on Semiconductor Markets
•
Electroless NiAu UBM – History & Now
– Eless NiAu & NiPdAu for Al and Cu
– Eless Equipment
•
Soldering Process
•
Reliability Data
Confidential
Thank you!
Confidential

Wafer Level Packaging – New achievements of technical

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