(Nehalem and Westmere) Into the Mainstream

Tr a n sit ion in g t h e I n t e l® N e x t
Ge n e r a t ion M icr oa r ch it e ct u r e s
( N e h a le m a n d W e st m e r e ) in t o t h e
M a in st r e a m
Lily Looi, St ephan Jourdan
I nt el Corporat ion
Hot Chips 21
August 24, 2009
1
Age n da
• Next Generat ion Mainst ream CPU’s
• New Technologies for I nt egrat ion for
2009 and beyond
2
2
I n t e l ® Cor e ™ i7 Re ca p
• Cor e m icr oa r ch it e ct u r e
– I ncreased parallelism
Misc I O
– e.g. 33% larger out of order window, handle m ore cache m isses
sim ult aneously
– Enhanced algorit hm s
Core
– e.g. fast er “ unaligned” cache accesses, fast er sync prim it ives,
loop st ream ing det ect or, m acro- fusion
Mem ory Cont roller
– Bet t er branch predict ion
– e.g. 2nd level branch predict or, renam ed RSB
Core
Queue
Shared
L3
Cache
Core
Core
Misc I O
QPI 0
QPI: Intel® QuickPath
Interconnect (Intel® QPI)
3
3
– New I nst ruct ions ( SSE4)
– I nt el ® Hyper- Threading Technology
• Un cor e m icr oa r ch it e ct u r e a n d con n e ct ivit y
– Scalable m ult i- core fabric
– Shared last level Cache
– I nt egrat ed m em ory cont roller
– I nt el ® QuickPat h I nt erconnect
• Pow e r m a n a ge m e n t t e ch n ologie s
– PCU Microcont roller
– I nt el ® Turbo Boost Technology
– I nt egrat ed power gat es
En a blin g N e h a le m for Eve r y Se gm e n t
2009+
2008
4 Cor e s / 8 Thr e a ds
2 Cor e s / 4 Thr e a ds w it h
I nt e gr a t e d Gr a phics
Mainstream
Desktop
Thin & Light
Laptop
4 5 n m H igh - K
3 2 n m H igh - K
D e live r ing Out st a nding N e ha le m Pe r for m a nce t o
M a inst r e a m D e sk t ops a nd La pt op Com put e r s
4
4
I nt el ® Microarchit ect ur e codenam ed Nehalem
M a in st r e a m Pla t for m Pa r t it ion in g
I n t e l ® Cor e ™2 Pr oce ssor
ba se d 3 - Ch ip Solu t ion
N e h a le m / W e st m e r e ba se d
2 - Ch ip Solu t ion
Processor
Processor
PCIe*
Graphics
iGFX
IMC
FSB
PCIe*
Graphics
IMC
DDR2/3
ME
Display
I
Fle x ible
D ispla y
I nt e r fa ce
( I nt e l ® FD I )
DMI
Intel® 5 series
Chipset
DMI
ICH10
DISPLAY
Clock s
M e m or y
Con t r olle r
m ove s in t o t h e
Pr oce ssor
nt e l ®
iGFX
DISPLAY
DDR3
Intel® 4 Series Chipset
Gr a ph ics m ove s
in t o Pr oce ssor 1
D ispla y m ove s int o
I nt e l ® 5 se r ie s chipse t
( I be x Pe a k )
ME
Display
I/O
Clock
Bu ffe r
I/O
I nt e l ® M a na ge a bilit y
Engine m ove s int o I nt e l ®
5 se r ie s chipse t ( I be x
Pe a k )
Gr e a t e r Pe r for m a n ce a n d Low e r Pow e r t h r ou gh I n t e gr a t ion
1. I nt egrat ed graphics on Clarkdale/ Arrandale
5
5
I nt el ® Microarchit ect ur e codenam ed Nehalem
West m ere: 32nm version of I nt el ® m icroarchit ect ur e codenam e Nehalem
M a in st r e a m M icr opr oce ssor s
Lynnfield/Clarksfield
Clarkdale / Arrandale
4 5 n m pr oce ssor
( sin gle die )
D D R3
D D R3
3 2 nm
W e st m e r e
pr oce ssor
cor e
D iscr e t e
Gr a phics
DMI
Intel®
FDI
1 x 1 6 or 2 x 8 ,
Ge n 2
DMI
Processor
Graphics
or
Discrete /
Switchable
Graphics
4 5 n m iGfx
Intel® 5 series
Chipset
Discrete graphics
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Manageabilit y, Securit y,
Display, PCI e, SATA, et c.
Intel® 5 series
Chipset
Integrated or discrete graphics
Age n da
• Next Generat ion Mainst ream CPU’s
• New Technologies for I nt egrat ion for
2009 and beyond
Integrated Power Gates
Intel® Turbo Boost Technology
Intel® Hyper-Threading Technology
Energy Efficient
performance
Single Thread
Multi-threads
7
7
I n t e gr a t e d Pow e r Ga t e s
• I nt egrat ed Power Gat es ( swit ches) are crit ical for int egrat ion,
t urning individual com ponent blocks on/ off
– Zero leakage power, low lat ency t o wake block
– Key benefit s in bot h idle and act ive power
VCC
• Nehalem t urns individual cores on/ off
– Transparent t o OS
– Reduces lat ency t o wake a core
– Modular/ Scalable Clocking
Core0
Core1
Core2
Core3
Memory System, Cache, I/O
– Cores, Mem ory Syst em , I / O can run at independent volt age/ frequency
• Ext ended in 2009 plat form s as I nt egrat ed Power Gat es also used in
shared cache and I / O logic t o dynam ically power down when
inact ive
I n t e gr a t e d Pow e r Ga t e s e n a ble En e r gy Efficie n t I n t e gr a t ion
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8
I nt el ® Microarchit ect ur e codenam ed Nehalem
VTT
I n t e l ® Tu r bo Boost Te ch n ology
• I nt egrat ion split s power allocat ion am ong m ore com ponent blocks
• I nt el ® Turbo Boost Technology is crit ical t o dynam ically m anage
power allocat ion and seam lessly m axim ize perform ance
– Higher benefit s in sm aller form fact ors
H ighe r Fr e que ncy
Lynnfie ld/ Cla r k sfie ld
Awake:
Lower core activity
Sleep
Core 1 Core 2
Core 3 Core 4
D yn a m ica lly Sca le d Pe r for m a n ce Boost
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9
I n t e l ® H ype r - Th r e a din g Te ch n ology
• Nehalem is a scalable m ult i- core archit ect ure
• Hyper- Threading Technology augm ent s benefit s
– Power- efficient way t o boost perform ance in all form fact ors: higher
m ult i- t hreaded perform ance, fast er m ult i- t asking response
Hyper-Threading
Multi-cores
Shared or
Partitioned Replicated
Replicated
Without HT
Technology
Register State
Return Stack
With HT
Technology
•
X
X
X
X
Reorder Buffer
X
X
Instruction TLB
X
X
Reservation Stations
X
X
Cache (L1, L2)
X
X
Data TLB
X
X
Execution Units
X
X
Next generat ion Hyper- Threading Technology:
–
–
–
Low- lat ency pipeline archit ect ure
Enhanced cache archit ect ure
Higher m em ory bandwidt h
En a ble s 8 - w a y pr oce ssin g in Qu a d Cor e syst e m s,
4 - w a y pr oce ssin g in Sm a ll For m Fa ct or s
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1 0 I nt el ® Microarchit ect ur e codenam ed Nehalem
En e r gy Efficie n t Pe r for m a n ce
• Many innovat ions in energy efficiency such as loop- st ream ing det ect or
and dynam ic loadline
• As looping is very com m on t o every t ype of applicat ions, Nehalem loopst ream ing det ect or capt ures bigger loops and saves m ore energy
l® Cor
Coree™
™2i7 Pr
IInntteel®
Proce
ocessor
ssor Pipe
Pipelin
linee
Braannch
ch
Br
Preedict
diction
ion
Pr
Fettch
ch
Fe
Qu e u e
D e code
( Loop)
Qu e u e
D
Deecode
code
( Loop)
Ex e cu t e
V
P= V x I
W or st
ca se
• Dynam ic only loadline ( PCU)
Cur r e nt cdt n
– Power = Volt age x Current
– I n prior processor s, volt age line is anchored based on worst case
– Nehalem lowers Volt age based on current condit ions: # act ive cores,
t em perat ure, and saves m ore energy.
M a j or I n n ova t ion s in En e r gy Efficie n cy
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1 1 I nt el ® Microarchit ect ur e codenam ed Nehalem
I
Su m m a r y
• I n t e l m a in t a in s pa ce of in n ova t ion a n d e x e cu t ion
– Next generat ion perform ance
– 32nm : Anot her Process Technology Breakt hrough
• En a blin g N e h a le m for e ve r y se gm e n t
– Delivering out st anding Nehalem perform ance t o m ainst ream deskt ops
and lapt op com put ers
• Re de sign in g m or e e fficie n t pla t for m s
– Best perform ance across all segm ent s
– Low power and bet t er power m anagem ent
– Higher levels of int egrat ion
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1 2 I nt el ® Microarchit ect ur e codenam ed Nehalem
Q& A
13
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Ba ck u p
14
14
D D R3
– x16 PCI e configurable t o 2x8
– 2.5 GT/ s ( Gen1) and 5 GT/ s ( Gen2)
– Flexible int erface: lane reversal, dynam ic speed and
link widt h changes, peer t o peer post ed writ es
– Power Opt im izat ion: L0s/ L1 support , low- volt age swing
m ode and de- em phasis
– x4 DMI I nt erface – Series 5 enhancem ent s
– Ext ended power m anagem ent
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Cor e Cor e
Th r e a d
Th r e a d
Th r e a d
Th r e a d
Pow e r
Cor e Cor e
Gr a phics
D D R3 I M C
• Built on m odularit y of I nt el ® Core™ i7
• Furt her int egrat ion t o support new m ainst ream
plat form s:
– VTd and I O virt ualizat ion support
– PCI Express* int erface
PCI - E
Lyn n fie ld/ Cla r k sfie ld M icr oa r ch it e ct u r e
8M
Th r e a d
Th r e a d
Th r e a d
Th r e a d
DMI
I nt e l® 5 se r ie s
Chipse t
I n t e gr a t e d Gr a ph ics a n d M e dia
Ar ch it e ct u r e ( Cla r k da le , Ar r a n da le )
• Unified Shader Archit ect ure
VS/GS
Vertex
Setup/Rasterize
Fetch
– Evolut ion of G965 & GM965
Add’l 3D Fixed Fxn
– DX10 & Shader Model 4.0 in HW
Shaded Vertices
– Full HD Decode, High Qualit y Video
EU
•
•
•
EU
EU
•
•
Ca che
Mathbox
•
Mathbox
EU
EU
•
•
•
Mathbox
Dedicated HD Decode Pipelines
MPEG2
IT
VLD
VLD
16
16
MC
VC1
IT
MC
AVC
IT
Post Process
LF
MC
LF
– Hierarchical Dept h Buffer
• Mult i- funct ional; m ult i- t hreaded
• Enables scalabilit y and flexibilit y
• I m proved Ext ended Mat h, larger
caches
MC/LF in EUs
VLD
– 6 t hreads/ EU
• Dynam ic load balanced
Pixel
backend
EU
Texture
Unit
Unified Execution Unit Array
Le ga l D iscla im e r
• I NFORMATI ON I N THI S DOCUMENT I S PROVI DED I N CONNECTI ON WI TH I NTEL® PRODUCTS. NO LI CENSE,
EXPRESS OR I MPLI ED, BY ESTOPPEL OR OTHERWI SE, TO ANY I NTELLECTUAL PROPERTY RI GHTS I S GRANTED
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COPYRI GHT OR OTHER I NTELLECTUAL PROPERTY RI GHT. I NTEL PRODUCTS ARE NOT I NTENDED FOR USE I N
MEDI CAL, LI FE SAVI NG, OR LI FE SUSTAI NI NG APPLI CATI ONS.
• I nt el m ay m ake changes t o specificat ions and product descript ions at any t im e, wit hout not ice.
• All product s, dat es, and figures specified are prelim inary based on current expect at ions, and are subj ect t o
change wit hout not ice.
• I nt el, processors, chipset s, and deskt op boards m ay cont ain design defect s or errors known as errat a, which
m ay cause t he product t o deviat e from published specificat ions. Current charact erized errat a are available on
request .
• Nehalem , Lynnfield, Clarkdale, Clarksfield, Arrandale, West m ere, I bex Peak and ot her code nam es feat ured are
used int ernally wit hin I nt el t o ident ify product s t hat are in developm ent and not yet publicly announced for
release. Cust om ers, licensees and ot her t hird part ies are not aut horized by I nt el t o use code nam es in
advert ising, prom ot ion or m arket ing of any product or services and any such use of I nt el's int ernal code nam es
is at t he sole risk of t he user
• Perform ance t est s and rat ings are m easured using specific com put er syst em s and/ or com ponent s and reflect t he
approxim at e perform ance of I nt el product s as m easured by t hose t est s. Any difference in syst em hardware or
soft ware design or configurat ion m ay affect act ual perform ance.
• I nt el, Core and t he I nt el logo are t radem arks of I nt el Corporat ion in t he Unit ed St at es and ot her count ries.
• * Ot her nam es and brands m ay be claim ed as t he propert y of ot hers.
• Copyright © 2009 I nt el Corporat ion.
• I nt el ® Act ive Managem ent Technology requires t he com put er syst em t o have an I nt el ® AMT- enabled chipset ,
net work hardware and soft ware, as well as connect ion wit h a power source and a corporat e net work
connect ion. Set up requires configurat ion by t he purchaser and m ay require script ing wit h t he m anagem ent
console or furt her int egrat ion int o exist ing securit y fram eworks t o enable cert ain funct ionalit y. I t m ay also
require m odificat ions of im plem ent at ion of new business processes. Wit h regard t o not ebooks, I nt el AMT m ay
not be available or cert ain capabilit ies m ay be lim it ed over a host OS- based VPN or when connect ing wirelessly,
on bat t ery power, sleeping, hibernat ing or powered off. For m ore inform at ion, see
www.int el.com / t echnology/ plat form - t echnology/ int el- am t /
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Risk Fa ct or s
The above st at em ent s and any ot hers in t his docum ent t hat refer t o plans and expect at ions for t he first quart er, t he year and t he fut ure are forwardlooking st at em ent s t hat involve a num ber of risks and uncert aint ies. Many fact ors could affect I nt el’s act ual result s, and variances from I nt el’s current
expect at ions regarding such fact ors could cause act ual result s t o differ m at erially from t hose expressed in t hese forward- looking st at em ent s. I nt el
present ly considers t he following t o be t he im port ant fact ors t hat could cause act ual result s t o differ m at erially from t he corporat ion’s expect at ions.
Current uncert aint y in global econom ic condit ions pose a risk t o t he overall econom y as consum ers and businesses m ay defer purchases in response t o
t ight er credit and negat ive financial news, which could negat ively affect product dem and and ot her relat ed m at t ers. Consequent ly, dem and could be
different from I nt el's expect at ions due t o fact ors including changes in business and econom ic condit ions, including condit ions in t he credit m arket t hat
could affect consum er confidence; cust om er accept ance of I nt el’s and com pet it ors’ product s; changes in cust om er order pat t erns including order
cancellat ions; and changes in t he level of invent ory at cust om ers. I nt el operat es in int ensely com pet it ive indust ries t hat are charact erized by a high
percent age of cost s t hat are fixed or difficult t o reduce in t he short t erm and product dem and t hat is highly variable and difficult t o forecast . Revenue
and t he gross m argin percent age are affect ed by t he t im ing of new I nt el product int roduct ions and t he dem and for and m arket accept ance of I nt el's
product s; act ions t aken by I nt el's com pet it ors, including product offerings and int roduct ions, m arket ing program s and pricing pressures and I nt el’s
response t o such act ions; I nt el’s abilit y t o respond quickly t o t echnological developm ent s and t o incorporat e new feat ures int o it s product s; and t he
availabilit y of sufficient supply of com ponent s from suppliers t o m eet dem and. The gross m argin percent age could vary significant ly from expect at ions
based on changes in revenue levels; capacit y ut ilizat ion; excess or obsolet e invent ory; product m ix and pricing; variat ions in invent ory valuat ion,
including variat ions relat ed t o t he t im ing of qualifying product s for sale; m anufact uring yields; changes in unit cost s; im pairm ent s of long- lived asset s,
including m anufact uring, assem bly/ t est and int angible asset s; and t he t im ing and execut ion of t he m anufact uring ram p and associat ed cost s, including
st art - up cost s. Expenses, part icularly cert ain m arket ing and com pensat ion expenses, as well as rest ruct uring and asset im pairm ent charges, vary
depending on t he level of dem and for I nt el's product s and t he level of revenue and profit s. The recent financial crisis affect ing t he banking syst em and
financial m arket s and t he going concern t hreat s t o invest m ent banks and ot her financial inst it ut ions have result ed in a t ight ening in t he credit m arket s,
a reduced level of liquidit y in m any financial m arket s, and ext rem e volat ilit y in fixed incom e, credit and equit y m arket s. There could be a num ber of
follow- on effect s from t he credit crisis on I nt el’s business, including insolvency of key suppliers result ing in product delays; inabilit y of cust om ers t o
obt ain credit t o finance purchases of our product s and/ or cust om er insolvencies; count erpart y failures negat ively im pact ing our t reasury operat ions;
increased expense or inabilit y t o obt ain short - t erm financing of I nt el’s operat ions from t he issuance of com m ercial paper; and increased im pairm ent s
from t he inabilit y of invest ee com panies t o obt ain financing. I nt el's result s could be im pact ed by adverse econom ic, social, polit ical and
physical/ infrast ruct ure condit ions in t he count ries in which I nt el, it s cust om ers or it s suppliers operat e, including m ilit ary conflict and ot her securit y
risks, nat ural disast ers, infrast ruct ure disrupt ions, healt h concerns and fluct uat ions in currency exchange rat es. I nt el's result s could be affect ed by
adverse effect s associat ed wit h product defect s and errat a ( deviat ions from published specificat ions) , and by lit igat ion or regulat ory m at t ers involving
int ellect ual propert y, st ockholder, consum er, ant it rust and ot her issues, such as t he lit igat ion and regulat ory m at t ers described in I nt el's SEC report s.
Rev. 1/ 15/ 09
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