BGA User`s Guide - Data Device Corporation

Transcription

BGA User's Guide
AN/B-49
Application Note
This application note will assist the PCB design engineer in integrating DDC's BGA Multi-Chip modules (Hybrids) into a
design.
For more information: www.ddc-web.com
© 2009 Data Device Corporation. All trademarks are the property of their respective owners.
BGA USER’S GUIDE
1
DIE-UP OR FLIP CHIP MULTI-CHIP MODULE (MCM) BGA
PACKAGE
BGA packaging technology utilizes a symmetrical array of solder balls at the bottom of
the package making electrical and mechanical contact with the system circuit board.
The solder ball array reduces the package size considerably when compared to DDCs
ceramic quad flat-pack leaded products.
DDC BGA packages have a full or partial matrix of solder balls utilizing either 1.0mm
or 0.8mm ball pitch (depending on series) shown in Figure 1. The PCB substrate
consists of a multilayer, Hi TG-FR4 epoxy material that closely matches the coefficient
of thermal expansion (CTE) of most system circuit boards. Signal, power, and ground
balls are interspersed throughout the matrix for routing ease.
Note: These images are not to scale
Figure 1. Bottom View of BGA Packages
Data Device Corporation
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Chip and Wire Package Construction is shown in the cross section of Figure 2. The
Die-Up BGA package contains multiple, wire bonded dies on a printed circuit board
with a hard pot epoxy encapsulation. Beneath the die are the thermal vias which
conduct and help to dissipate the heat through a portion of the solder ball array and
finally into the thermal/ground plane of the system circuit board.
Figure 2. Solder Ball Matrix
Flip Chip package construction is shown in the cross section of Figure 3. A flip chip
BGA package also contains multiple, silicon dies on a printed circuit board with hard
pot epoxy encapsulation, but uses solder bumps instead of wire bonds to connect
signals from the die to the substrate.
In order to attach the die within the BGA, solder balls are first attached to the signal
pads on the top side of the die, then it is flipped over so that its top side faces down,
and aligned so that its pads align with matching pads on the substrate. The BGA is
then heated to reflow the solder and complete the interconnect.
Heat transfer in the finished system is achieved through two paths: from the backside
of the silicon dies into the encapsulant and then into the surrounding air, optionally
through a heat sink and through ground signal pads and solder balls into the
groundplane of the substrate, and from there through the identified thermal ground
balls to the PCB ground plane.
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Figure 3. Solder Ball Matrix (Flip Chip construction)
1.1
Daisy Chain Mechanical Samples
Daisy chain mechanical samples of BGA components are available for purchase
through DDC (see Table 1). These are used to verify both the electrical and
mechanical integrity of the solder joints during board environmental evaluations (such
as shock/vibration and temperature cycling) to see how well the solder balls withstand
varying mechanical stress conditions.
Alternating ball pairs are internally wired (connected; A1-A2, A3-A4, etc.) so that the
user can test for electrical continuity between balls and board. Internal daisy chain
interconnections are made by copper PWB traces.
Although these test units are inert, they are fully populated with silicon die (and
isolation transformers in Total-ACE version) so that they closely match the thermal
and mechanical characteristics of standard production units.
Table 1. Daisy Chain Mechanical Sample
Package Type
Description
Ball Pitch
Series
Daisy Chain
Mechanical Sample
Part Number
312-Ball BGA
24 x 13 Full-Matrix
1.0mm
Total-ACE
BU-64843T8-600
324-Ball BGA
18 x 18 Full-Matrix
1.0mm
Micro-ACE-TE
BU-64863B8-600
128-Ball BGA
18 x 18 Partial-Matrix
1.0mm
Micro-ACE
BU-61860B3-601
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2
THERMAL CONSIDERATIONS
2.1
Thermal Specifications
Table 2 indicates thermal resistance data obtained via simulation for the active
transceiver (hottest die). The data includes junction-to-ambient “θJA” in still air (Per
JESD 51-2 standard at 25°C), junction-to-case “θJC” at differing air flows (Per JESD
51-6 standard at 25°C), and junction-to-board “θJB” (Per JESD 51-8).
Table 2. Thermal Specifications
Package
Type
Description
324-Ball BGA 18 x 18 Full-Matrix
312-Ball BGA 24 x 13 Full-Matrix
2.2
Ball Pitch
Series
θJA
θJA
(°C/W) θJA
θJA (°C/W)
θJB
θJC in Still (°C/W) (°C/W)
@
(°C/W) (°C/W)
Air @ 1M/S @ 2M/S 3M/S
0.8mm Total-AceXtreme 46.9
26.5
1.0mm
Total-ACE
24.5
68.8
52.9
47.1
43.6
26.2
37.8
31.4
29.8
29
Power Management Strategy
The user’s specific operational environment and conditions makes it difficult for DDC
to apply a standard thermal solution other than to recommend that all package thermal
connections (balls) performing the dual function of transceiver circuit ground and
thermal heat sink be utilized to the maximum extent possible.
It is strongly recommended that these thermal balls (not applicable to all package
options) be directly soldered to a circuit ground/thermal plane (a circuit trace is
insufficient). Operation without an adequate ground/thermal plane is not
recommended and extended exposure to these conditions may affect device
reliability.
2.3
System Level Heat Sinking Solutions
Heat sinking of DDC BGA components via custom or off-the-shelf external devices is
best left to the system engineer who can modify the design and develop a custom
solution within the constraints of the specific application.
2.4
Thermal Management Options
The system board on which the BGA is mounted has a significant impact on thermal
performance, as a high percentage of the generated heat will flow through the thermal
BGA balls (not applicable to all package options) and into the board when properly
designed. Table 2 listed the thermal resistance data (via simulation) for the active
transceiver (hottest die) for selected BGA devices. Users should be aware that the
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heat path from the hottest die (transceiver) to the board is bi-directional, thus an
improperly cooled system board could actually heat the active transceiver.
Under certain conditions it may be advantageous to attach passive heat sinks and
heat spreaders to the top of the BGA with thermally conductive double-sided tapes or
mechanical retainers. The mass of the heat sink might cause stress cracking of the
BGA balls or package under high shock & vibration conditions. It is advisable when
using larger, high mass heat sinks that they be mechanically fastened to the PCB in
order to prevent component damage.
3
RECOMMENDED PCB DESIGN RULES FOR BGA PACKAGES
3.1
Surface Land Pad
The surface land pad is the area on the printed circuit board (PCB) to which the BGA
solder ball adheres. Pad size affects the space available for vias and for escape
routing. Surface land pads are typically available in two basic designs; non-solder
mask defined (NSMD), aka “copper defined” and solder mask defined (SMD) (See
Figure 4). The major differences between the two types are the resulting size of the
signal trace and available routing space, the type of vias one can use, and the final
shape of the solder ball after solder reflow (see Figure 5 and Figure 6).
•
With NSMD pads, the solder mask opening is larger than the copper pad (pad
is fully exposed) resulting in a greater surface area for the BGA solder ball to
adhere to.
•
With SMD pads, the solder mask partially covers the copper pad surface. This
provides better adhesion between the copper pad and the PCB but reduces the
amount of copper surface area for the BGA solder ball to adhere to.
Figure 4. Surface Land Pads
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Figure 5. Surface Land Solder Joints
Figure 6. BGA Pad Dimensions
DDC recommends that for BGA packages, non-solder mask defined (NSMD) pads be
utilized for the board land pad as this allows for clearance between the land metal
(diameter SL) and the solder mask opening (diameter SM) as shown in Figure 7 and
Table 3. This design prevents creation of a stress point in the solder connection by
pulling the soldermask away from the pads. The opening between the NSMD pad,
solder mask, and signal trace width is dependent upon the manufacturing capabilities
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of the PCB vendor. The cost of a PCB typically increases as trace line widths and
spaces decrease.
DDC has determined that the best solder joint reliability and fatigue life is obtained
when the PCB land pad design provides a balanced stress on the solder joint. BGA
pads on most DDC components are solder mask defined. However, DDC
recommends the use of NSMD pads on the PCB, with dimensions as specified in
Table 3 below to achieve a balanced stress on solder joints. Any overlapping of the
solder mask on pad metal by design or mis-registration is strongly discouraged. If
solder mask defined pads (SMD) must be used then the surface land pads should be
the same size as the BGA pad to provide a balanced stress upon solder joints.
The diameter of the BGA solder mask defined (SMD) component land pad is provided
by DDC. This information is necessary before the start of board layout so that board
pads are designed to match BGA side land geometry. Typical values of DDC BGA
component land pads and the recommended board pad are listed and identified in
Table 4.
*4 x 4 Matrix shown for illustration “One land pad shown with via connection”.
Figure 7. BGA Pad Outline Drawing
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Table 3. PCB BGA Design
324-Ball BGA
312-Ball BGA
324-Ball BGA
128-Ball BGA
18 x 18 FullMatrix
24 x 13 FullMatrix
18 x 18 FullMatrix
18 x 18 PartialMatrix
Total-AceXtreme
Total-ACE
Micro-ACE-TE
Micro-ACE
0.46 (SMD)
0.56 (SMD)
0.56 (SMD)
0.5 (NSMD)
Component solder ball (SB) diameter
0.53
0.71
0.71
0.71
Solder land (SL) diameter
0.45
0.5
0.5
0.5
Opening in solder mask (SM) diameter
0.57
0.57
0.57
0.57
Solder (ball) land pitch (lp)
0.80
1.00
1.00
1.00
Line width between via and land (LW)
0.10
0.13
0.13
0.13
Distance between via and land (VLD)
0.56
0.70
0.70
0.70
Via land (VD) diameter
0.45
0.61
0.61
0.61
Through hole (TH) diameter
0.245
0.300
0.300
0.300
Recommended PCB Design Rules
(Dimensions in mm)
Component land pad diameter (CL) (1)
Note (1): For SMD pads, the component land pad diameter refers to the size of the opening in the solder mask on the
component. For the NSMD pads on the Micro-Ace component, the number provided is the size of the copper land.
3.2
Board Level Signal Routing
DDC’s BGA packages are a mixture of full matrix and partial matrix of solder balls
(Figure 1). These packages are made of multilayer Hi TG-FR4 laminate substrates.
Signal, power, and ground balls are interspersed throughout the matrix for routing
ease. The number of layers required for routing of BGA packages is dictated by the
layout of pins on each package. Figures 10 - 15 provide a visual representation of
Package Ball Assignments.
Available via and routing space for 1.00mm & 0.8mm ball pitch BGA NSMD PCB Land
Pads is shown in Figure 8 and Figure 9 respectively.
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Figure 8. Available Via & Routing Space for 1.00-mm BGA NSMD PCB Land Pads
Figure 9. Available Via & Routing Space for 0.8-mm BGA NSMD PCB Land Pads
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A
B
C
D
E
F
G
H
J
K
M
P
R
T
U
V
NC
CHB_15 CHB_15 CHB_15 CHB_15
53
53
53_L
53_L
NC
NC
18
NC
NC
CHB_15 CHB_15 CHB_15 CHB_15
53
53_L
53_L
53
NC
NC
17
L
N
18
NC
NC
NC
CHA_15 CHA_15 CHA_15 CHA_15
53_L
53_L
53
53
17
NC
NC
NC
CHA_15 CHA_15 CHA_15 CHA_15
53_L
53_L
53
53
16
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
16
15
GND_
LOGIC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND_
LOGIC
15
14
GND_
LOGIC
GND_
LOGIC
DISAB
_BC
DISAB
_MULT
_RT
GND_
LOGIC
GND_
LOGIC
RTAD
0
RTAD
4
GND_
LOGIC
GND_
LOGIC
DISC
IO (6)
DISC
IO (0)
IRIG_ TX_INH nSSFLA
DIG_IN
_B
G
NC
GND_
LOGIC
GND_
LOGIC
14
13
NC
GND_
LOGIC
DISAB_B
IST
nRT
BOOT
TEMP_
DIODE
GND_
LOGIC
RTAD
1
RTAD
P
DISC
IO (4)
DISC
IO (1)
DISC
IO (3)
TAG_
CLK
TAG_ TX_INH nSNGE
ENABLE
_A
ND
USER_
OUT_1
USER_
OUT_2
NC
13
12
GND_
LOGIC
GND_
LOGIC
+3.3V
LOGIC
NC
GND_
XCVR
GND_
XCVR
RTAD
3
DISC
IO (7)
DISC
IO (5)
DISC
IO (2)
nMCRST/
nINCMD
TAG_LO
AD
NC
GND_
XCVR
GND_
XCVR
NC
NC
NC
12
TXDATA
TXINH_
TXDATA
_OUT_A_
IN_A
_IN_A_L
L
TXINH_
OUT_B
TXINH
_IN_B
NC
GND_
XCVR
GND_
XCVR
EXT_
TRIG
NC
NC
11
TXINH_
OUT_A
TXDATA
_OUT_A
TXDATA
_OUT_B
TXDATA
_IN_B
NC
NC
NC
NC
+3.3V
XCVR
GND_
XCVR
10
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
NC
NC
9
11
GND_
LOGIC
GND_
LOGIC
PCI_nC
PU
GND_
LOGIC
GND_
XCVR
GND_
XCVR
RT_AD
_LAT
10
JTAG
TMS
JTAG
TDI
+3.3V
LOGIC
+3.3V
LOGIC
GND_
LOGIC
GND_
LOGIC
RTAD
2
9
PCI_INT JTAG
A#
nTRST
8
CLOCK_I
N
JTAG
TDO
NC
NC
NC
NC
NC
NC
NC
TXDATA
_IN_A
+3.3V
LOGIC
GND_LO
GIC
GND_
LOGIC
GND_
LOGIC
GND_
LOGIC
+3.3V
LOGIC
TXDATA
RXDATA RXDATA_
TXDATA
_OUT_B_
_IN_A_L OUT_A_L
_IN_B_L
L
+3.3V
LOGIC
GND_
LOGIC
1.8V
PLL
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
RXDATA RXDATA
_IN_A
_OUT_A
TRIG_
SEL
NC
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
NC
NC
8
POL_
SEL
CPU_
AD_
MULTI
+3.3V
LOGIC
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
RXDATA
_IN_B_L
RXDATA_
OUT_B_L
7
DATA32
_n16
MSW_
nLSW
nDATA_
STRB
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
RXDATA RXDATA
_IN_B
_OUT_B
6
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
PCIREQ#/
CPU_ADD
R(12)
+3.3V
LOGIC
GND_
LOGIC
1.8V
CORE
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
CPU_AS
YNC_nS
YNC
6 /CPU_AD nMSTCLR
RST#/
+3.3V
LOGIC
GND_
LOGIC
1.8V
CORE
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
RD_
nWR
5
PCI_AD31/ PCI_AD29/
DATA31
DATA29
+3.3V
LOGIC
GND_
LOGIC
1.8V
CORE
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
C/BE1#/C
PCI_AD0/
PCI_AD17/
PU_ADDR
DATA0
DATA17
(1)
PCI_AD3/
DATA3
+3.3V
XCVR
4
PCI_AD30/ PCI_AD28/
DATA30
DATA28
+3.3V
LOGIC
GND_
LOGIC
GND_
LOGIC
GND_
LOGIC
GND_
LOGIC
+3.3V
LOGIC
C/BE2#/C
PCI_AD1/
PU_ADDR
DATA1
(2)
PCI_AD5/
DATA5
PCI_AD6/
DATA6
7
JTAG
TCK
PCI_GNT#
DR (13)
NC
NC
5
CPU_W CPU_ CPU_A
DEN1 nBLAST DDR15
NC
NC
4
C/BE0#/
PCI_IRDY
PCI_FRA PCI_TRDY
PCI_AD27/
PCI_AD24/ PCI_AD21/ PCI_AD20/ PCI_AD18/
PCI_AD4/ PCI_AD11/
PCI_AD7/ CPU_W ADDR_L CPU_A
ME#/CPU_ #/CPU_AD
#/CPU_AD
CPU_A
DATA24
DATA21
DATA20
DATA18
DATA11
DATA7
DATA27
DATA4
DEN0
AT
DDR14
DR(6)
DR(7)
ADDR(5)
DDR(0)
NC
NC
3
nSELEC
T
NC
NC
2
NC
NC
NC
1
T
U
V
3
NC
2
NC
NC
1
NC
NC
NC
A
B
C
PCI_IDSE
PCI_AD25/
PCI_AD22/
L/CPU_AD
DATA25
DATA22
DR(10)
PCI_AD2/
DATA2
HOST_ PCI_PERR PCI_STOP PCI_SE PCI_AD10/ PCI_PAR/ PCI_AD14/ PCI_AD8/
CPU_ADD
#/CPU_AD #/CPU_AD
DATA10
DATA14
DATA8
CLK
RR#
DR(8)
R(4)
DR(11)
DEVSEL#/
C/BE3#/C
PCI_AD26/
PCI_AD23/ PCI_AD19/ PCI_AD16/
PCI_AD15/ PCI_AD13/ PCI_AD9/ PCI_AD12/
PU_ADDR
CPU_ADD
DATA26
DATA23
DATA19
DATA16
DATA13
DATA9
DATA12
DATA15
(3)
R(9)
D
E
F
G
H
J
K
L
M
nINT
MEM_
nREG
CPU_ nDATA_
nSTOP
RDY
N
P
R
MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM
PCI BUS
CPU BUS
1553 MISC
MISC
TEST / PROGRAM PAD
CONFIG PAD (STATIC)
XCVR MISC
Figure 10. Total-AceXtreme (0.8mm Ball Pitch) BGA Pin Assignments
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A
B
C
24
LOGIC_
GND
LOGIC_
GND
LOGIC_
GND
D
F
G
H
L
M
D14
D10
D04
D00
(LSB)
RT_AD_
RTAD3 _LAT
LOGIC_
GND
LOGIC_
GND
LOGIC_
24
GND
23
LOGIC_
GND
LOGIC_
GND
LOGIC_ TAG_CL
GND
K
D12
D08
D06
D02
RTADP RTAD1
LOGIC_
GND
LOGIC_
GND
LOGIC_
23
GND
22
LOGIC_
GND
LOGIC_
GND
LOGIC_ TRANS/
GND
BUFF*
D13
D09
D05
D01
RTAD2
RSTBIT
EN
LOGIC_
GND
LOGIC_
GND
LOGIC_
22
GND
21
SNGL_E BC_DIS
ND*
ABLE
READY D15
D*
(MSB)
D11
D07
D03
INCMD*
RTAD4 RTAD0
(MSB) (LSB)
NC
NC
20
TX_INH_ LOGIC_
A
GND
TX_INH_
NC
B
NC
NC
LOGIC_
GND
LOGIC_
GND
NC
IOEN*
UPADD
INT*
E
J
K
NC
TXDATA
MCRST LOGIC_ LOGIC_ LOGIC_ LOGIC_ LOGIC_
_OUT_B
GND
GND
GND
GND
GND
*
*
NC
SELEC MEM/R MSTCL LOGIC_ LOGIC_ LOGIC_ LOGIC_ LOGIC_ TXDATA
18 STRBD*
GND
GND
GND
GND
GND
_IN_B*
T*
EG*
R*
NC
19 REN/LO
NC
NC
GIC 1
A15/ LOGIC_ LOGIC_ LOGIC_ LOGIC_ LOGIC_
17 RD/WR* +3.3v_L +3.3v_L CLK_S GND
GND
GND
GND
GND
OGIC OGIC EL_1
A14/CLK
16 _SEL_0
A13/LO
+3.3v_L +3.3v_L
GIC "1"
OGIC OGIC
NC
A00
(LSB)
NC
NC
A02
NC
NC
15
A10
A12/RT A11
BOOT* (MSB)
A06
A04
14
A09
TXDATA
TXDATA
_OUT_A A08
_IN_A*
*
A01
+3.3v_L +3.3v_L
OGIC OGIC
NC
A05
+3.3v_L +3.3v_L
OGIC OGIC
RXDAT
RXDAT
A_OUT_
A_IN_A*
A*
NC
TXINH_
13 OUT_A
NC
NC
NC
NC
16/8*/D
TREQ*
ADDR_
TXDATA TXDATA
LAT/ME
_IN_B _OUT_B
MOE*
N
NC
21
TXINH_I
+3.3v_L 20
N_B
OGIC
TXINH_
+3.3v_L 19
OUT_B
OGIC
TRIG_S
CLOCK
18
EL/ME
_IN
MENA_I
POL_S
+3.3v_L EL/DTA 17
OGIC
CK*
ZERWA
+3.3v_L IT*/ME 16
OGIC MWR*
LOGIC_
GND
LOGIC_
GND
NC
15
MSB/LS SSFLAG
LOGIC_
B/DTGR */EXT_T
GND
T*
RIG
LOGIC_
GND
NC
14
NC
NC
NC
NC
NC
RXDAT RXDAT
13
A_IN_B* A_IN_B
RXDAT RXDAT
+3.3V_X +3.3V_X A03
NC
NC +3.3V_X +3.3V_X A_OUT_ A_OUT_ 12
CVR
CVR
CVR
CVR
B*
B
XCVR_T XCVR_T XCVR_T XCVR_T RXDATA RXDATA
XCVR_T XCVR_T XCVR_T XCVR_T
11 NC
HERMA HERMA HERMA HERMA _OUT_A _IN_A
NC HERMA HERMA HERMA HERMA NC 11
L_GND L_GND L_GND L_GND
TXDATA
SLEEPI
10 _OUT_A HERMA HERMA HERMA HERMA NC
NC
HERMA HERMA HERMA HERMA NC 10
N
XCVR_T
XCVR_T
XCVR_T
XCVR_T
XCVR_T
XCVR_T XCVR_T XCVR_T
TXDATA
9 _IN_A HERMA HERMA HERMA HERMA NC +3.3V_X NC HERMA HERMA HERMA HERMA +3.3V_X 9
CVR
L_GND L_GND L_GND L_GND CVR
XCVR_T XCVR_T
XCVR_T XCVR_T
8
8
NC +3.3V_X HERMA HERMA NC
NC +3.3V_X NC
NC
HERMA HERMA NC
NC
CVR L_GND L_GND
CVR
L_GND L_GND
12
TXINH_I
N_A
7
NC
+3.3V_X +3.3V_X
CVR
CVR
NC
NC
NC
+3.3V_X
CVR
NC
NC
NC
+3.3V_X +3.3V_X
CVR
CVR
NC
7
6
NC
+3.3V_X +3.3V_X
CVR
CVR
NC
NC
NC
+3.3V_X
CVR
NC
NC
NC
+3.3V_X +3.3V_X
CVR
CVR
NC
6
5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
4
NC
NC
NC
CHA_15 CHA_15 CHA_15
53-DIR 53-DIR 53-DIR
NC
A07
NC
NC
NC
5
CHB_15 CHB_15 CHB_15
NC
NC
NC
4
3
XCVR_ XCVR_
GND
GND
NC
53-DIR* 53*
53
NC
53-DIR* 53*
53
NC
XCVR_ XCVR_
3
GND
GND
2
XCVR_ XCVR_
GND
GND
NC
53-DIR* 53*
53
NC
53
53-DIR* 53*
NC
XCVR_ XCVR_
2
GND
GND
1
XCVR_ XCVR_
GND
GND
NC
53-DIR* 53*
53
NC
53-DIR* 53*
53
NC
XCVR_ XCVR_
1
GND
GND
A
B
C
D
E
F
G
H
J
K
L
M
N
XCVR MISC
1553 MISC
CPU INTERFACE
No Connect
GND
+3.3V Power
Figure 11. Total-ACE (1.0mm Ball Pitch) BGA Pin Assignments
www.ddc-web.com
11
AN/B-49
5/13-0
BGA USER’S GUIDE
A
B
C
D
E
F
G
H
J
K
L
M
N
24
GND
GND
GND
AD11
SERR#
AD14
AD19
AD16
AD23
AD24
GND
GND
GND
24
23
GND
GND
GND
AD21
C/BE(2)
#
AD18
AD17
GND
GND
GND
23
22
GND
GND
GND
AD13
STOP#
IRDY#
AD20
INTA#
CLK_SE
L_0
GND
GND
GND
22
SNGL_E CLK_SE
ND*
L_1
AD12
AD15
C/BE{1} DEVSE
FRAME3
#
L#
AD28
AD22
IDSEL#
NC
NC
NC
21
21
TAG_CL
PERR# TRDY#
K
PAR
20
AD9
BC_DISA
BLE
AD10
AD8
NC
NC
NC
GND
GND
NC
NC
TXINH_I
+3.3v_L 20
N_B
OGIC
19
RTBOO
T*
NC
NC
NC
GND
GND
GND
GND
GND
TXDATA
_OUT_B*
NC
TXINH_
+3.3v_L 19
OUT_B
OGIC
18
AD7
GND
GND
GND
GND
GND
TXDATA
_IN_B*
NC
AD26
17
AD6
AD4
GND
GND
GND
GND
GND
NC
AD29
+3.3v_L
OGIC
RTAD4
+3.3v_L +3.3v_L
(MSB)
OGIC
OGIC
AD0
NC
TX_INH_
A/B
NC
NC
AD1
AD31
INCMD*
1553_C
/MCRST
LK
*
NC
NC
NC
NC
GND
+3.3v_L +3.3v_L
OGIC
OGIC
NC
AD5
C/BE{3}
#
GND
+3.3v_L +3.3v_L
OGIC
OGIC
RXDAT
RXDAT
RTADP A_OUT_
A_IN_A*
A*
XCVR_
RXDATA RXDATA
THERM
_OUT_A _IN_A
AL_GN
XCVR_
THERM
NC
NC
AL_GN
XCVR_
THERM
NC
+3.3V_X
AL_GN
CVR
NC
NC
NC
NC
NC
NC
+3.3V_X
CVR
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
+3.3V_X
CVR
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
16
15 RTAD2
C/BE(0) RTAD0 MSTCL
#
(LSB) R/RST#
+3.3v_L +3.3v_L
OGIC
OGIC
RTAD1
TXDAT
TXDAT
A_OUT_ RTAD3
A_IN_A*
A*
14
AD2
13
TXINH_O
UT_A
12
TXINH_I RT_AD_
+3.3V_X +3.3V_X
N_A
LAT
NC
NC
NC
CVR
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
+3.3V_X THERM
CVR
AL_GN
CVR
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
NC
11
AL_GN
XCVR_
TXDATA
THERM
10
_OUT_A
AL_GN
XCVR_
TXDATA
THERM
9
_IN_A
AL_GN
AD27
AD3
NC
GND
NC
NC
NC
+3.3V_X
CVR
NC
NC
NC
NC
NC
+3.3V_X
CVR
NC
NC
NC
NC
NC
NC
+3.3V_X
CVR
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
8
NC
7
NC
+3.3V_X +3.3V_X
CVR
CVR
6
NC
+3.3V_X +3.3V_X
CVR
CVR
5
NC
NC
NC
4
NC
NC
NC
NC
3
GND
GND
NC
53-DIR*
53
53*
2
GND
GND
NC
1
GND
GND
NC
A
B
C
AD25
17
AD30
16
GND
NC
15
GND
NC
14
SSFLA
TXDAT TXDATA
G*/EXT +3.3v_L
A_IN_B _OUT_B
_TRIG
OGIC
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
XCVR_
THERM
AL_GN
PCI_CL
18
K
RXDAT RXDAT
13
A_IN_B* A_IN_B
RXDAT RXDAT
A_OUT_ A_OUT_ 12
B*
B
XCVR_
THERM
NC
11
AL_GN
XCVR_
THERM
NC
10
AL_GN
XCVR_
THERM +3.3V_X 9
AL_GN
CVR
NC
NC
8
+3.3V_X +3.3V_X
CVR
CVR
NC
7
+3.3V_X +3.3V_X
CVR
CVR
NC
6
NC
NC
NC
5
NC
NC
NC
4
NC
CHB_15 CHA_15 CHB_15
53-DIR*
53
53*
NC
GND
GND
3
53
53-DIR*
53*
NC
53
53-DIR*
53*
NC
GND
GND
2
53
53-DIR*
53*
NC
53
53-DIR*
53*
NC
GND
GND
1
J
L
M
N
D
E
F
G
H
K
XCVR MISC
1553 MISC
PCI INTERFACE
No Connect
GND
+3.3V Power
Figure 12. PCI-Total-ACE (1.0mm Ball Pitch) BGA Pin Assignments
www.ddc-web.com
12
AN/B-49
5/13-0
BGA USER’S GUIDE
A
B
C
D
E
F
G
H
D12
D08
D06
D02
J
K
18
NC
NC
NC
TAG_CL
K
17
NC
NC
NC
INT*
D14
D07
D04
D00
(LSB)
16
NC
NC
NC
TRANS/
BUFF*
D13
D10
D05
INCMD*
15
SNGL_E
ND*
NC
READY
D*
D15
(MSB)
D11
D09
D03
NC
NC
14
TX_INH_
A
NC
IOEN*
NC
GND
GND
GND
GND
13
VDD_Lo MCRST TX_INH_
B
w*
*
NC
GND
GND
GND
12 STRBD*
UPADD
SELEC
REN/LO
T*
GIC 1
NC
GND
GND
11 RD/WR*
MSTCL MEM/R
R*
EG*
NC
NC
A15/CL
RXDAT
A14/CL
A13/Vc
RXDAT
K_SEL_
A_OUT_
10 K_SEL_
A_IN_A*
c
1
A*
0
9
A12/RT
BOOT*
8
A10
7
+3.3/+5
V Logic
A09
6
NC
NC
5
TXINH_
OUT_A
NC
4
TXINH_I
N_A
NC
3
NC
NC
2
NC
NC
1
NC
NC
NC
A
B
C
A11
A08
TXDATA TXDATA
_OUT_A _IN_A
NC
L
M
RT_AD_ RSTBIT
RTADP RTAD1
LAT
EN
P
R
T
U
V
NC
NC
NC
NC
NC
NC
18
RTAD3 RTAD2
NC
NC
NC
NC
NC
NC
NC
17
RTAD4 RTAD0 +3.3/+5
(MSB) (LSB) V Logic
NC
NC
NC
NC
NC
NC
NC
16
NC
+3.3/+5
V Logic
NC
NC
NC
NC
NC
RXDAT RXDAT
A_OUT_ A_OUT_
B*
B
GND
NC
NC
NC
RXDAT RXDAT
A_IN_B* A_IN_B
GND
GND
NC
NC
NC
TXDATA
TXDATA
_OUT_B
_IN_B*
*
NC
NC
NC
NC
NC
TRIG_S
EL/ME
MENA_I
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
A00
NC
NC
NC
NC
NC
NC
NC
NC
RXDATA RXDATA
_IN_A _OUT_A
A04
A02
NC
NC
NC
A07
A06
A01
NC
NC
NC
A05
A03
NC
NC
NC
NC
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
XCVR_T
HERMA
L_GND
TXDATA XCVR_T XCVR_T XCVR_T
_OUT_A HERMA HERMA HERMA
*
L_GND L_GND L_GND
TXDATA
HERMA HERMA HERMA
_IN_A*
L_GND L_GND L_GND
NC
HERMA HERMA HERMA
L_GND L_GND L_GND
XCVR_T
NC
Tx/Rx-A HERMA +5V_XC
VR
L_GND
Tx/Rx-A Tx/Rx-A +5V_XC
VR
D
E
F
D01
N
SSFLA
G*EXT_
TRIG
MSB/LS
B/DTGR
T*
NC
NC
ZEROW
16/8*/D
TXDATA TXDATA
AIT*/ME
NC
_OUT_B _IN_B
TREQ*
MWR*
ADDR_
POL_S
+3.3/+5 +3.3/+5
LAT/ME CLK_IN EL/DTA
V Logic V Logic
MOE*
CK*
Tx/RxB*
Tx/Rx15
B*
XCVR_T
Tx/RxHERMA
14
B*
L_GND
+5V_XC +5V_XC 13
VR
VR
XCVR_T
HERMA Tx/Rx-B 12
L_GND
Tx/Rx-B Tx/Rx-B 11
NC
NC
NC
10
NC
NC
NC
9
TXINH_ TXINH_I
OUT_B
N_B
NC
NC
NC
NC
NC
NC
NC
NC
+3.3/+5
V Logic
NC
NC
NC
NC
7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
5
NC
NC
NC
NC
NC
NC
NC
NC
4
NC
NC
NC
+3.3/+5
V Logic
NC
NC
NC
NC
NC
NC
3
Tx/RxA*
NC
NC
+3.3/+5
V Logic
NC
NC
NC
NC
NC
NC
NC
2
Tx/RxA*
Tx/RxA*
NC
NC
+3.3/+5
V Logic
NC
NC
NC
NC
NC
NC
NC
1
G
H
J
K
L
M
N
P
R
T
U
V
+5V_RA +5V_RA
M
M
NC
+3.3/+5
8
V Logic
NC
XCVR MISC
1553 MISC
CPU INTERFACE
No Connect
GND
+3.3/+5V Power
Figure 13. Micro-ACE-TE (1.0mm Ball Pitch) ( with +5.0V transceivers) BGA Pin
Assignments
www.ddc-web.com
13
AN/B-49
5/13-0
BGA USER’S GUIDE
A
B
C
D
E
F
G
H
J
18
NC
NC
NC
INT*
D10
D12
D08
D04
D06
17
NC
NC
NC
TRANS/
BUFF*
D11
D07
D03
D05
D02
16
NC
NC
NC
D15
(MSB)
D13
D09
NC
NC
RTAD2
D01
READY
D*
A10
NC
NC
D14
NC
NC
RTAD4
(MSB)
NC
NC
TX_INH_ TX_INH_
A
B
NC
SNGL_E
ND*
NC
TAG_CL
K
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SELEC
T*
A05
NC
GND
GND
GND
GND
NC
MCRST
*
GND
GND
GND
A09
A08
GND
GND
A02
A07
A03
NC
15 IOEN*
14
13
NC
12 STRBD*
A15/CL
11 K_SEL_ RD/WR*
1
10
A12/RT A13/Vc
BOOT*
c
9 +3.3v_L +3.3v_L
OGIC OGIC
K
L
M
T
U
V
RTAD0 RT_AD_ MSTCL
(LSB)
LAT
R*
NC
NC
NC
18
TRIG_S
D00
16/8*/D
+3.3v_L +3.3v_L EL/ME INCMD*
(LSB)
TREQ*
OGIC OGIC MENA_I
NC
NC
NC
17
RTADP RTAD1 RTAD3
N
P
R
NC
NC
NC
NC
NC
NC
16
NC
NC
NC
NC
NC
NC
NC
15
RSTBIT
EN
NC
NC
NC
NC
NC
NC
NC
14
NC
NC
NC
+3.3v_L +3.3v_L
OGIC OGIC
GND
GND
GND
NC
13
NC
NC
NC
NC
+3.3v_L +3.3v_L
OGIC OGIC
GND
GND
GND
NC
12
GND
NC
NC
NC
NC
GND
GND
GND
NC
11
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TXDATA TXINH_
TXDATA
RXDAT RXDATA
8 +3.3v_L +3.3v_L _OUT_A _OUT_A OUT_A
A00
A_IN_A* _IN_A
OGIC OGIC
*
A14/CL
UPADD RXDAT
TXDATA TXDATA TXINH_I
RXDATA
7 K_SEL_ A04
REN/LO A_OUT_ _OUT_A
_IN_A
_IN_A* N_A
0
GIC 1
A*
MSB/LS
MEM/R
A11
6
B/DTGR NC
NC
NC
NC
NC
EG*
T*
5 +3.3V_X +3.3V_X NC
HERMA HERMA HERMA HERMA NC
CVR
CVR
4 +3.3V_X +3.3V_X NC
CVR
CVR
3
NC
NC
NC
XCVR_T
Tx/Rx- Tx/Rx2
NC
NC
NC
Tx/Rx-A Tx/Rx-A HERMA
A*
A*
L_GND
XCVR_T
Tx/Rx- Tx/Rx1
NC
NC
NC
Tx/Rx-A Tx/Rx-A HERMA
A*
A*
L_GND
A
B
C
D
E
F
G
H
+3.3v_L +3.3v_L
OGIC OGIC
NC
NC
ADDR_
RXDAT RXDAT
CLK_IN LAT/ME NC 10
A_IN_B* A_IN_B
MOE*
RXDAT RXDAT
9
NC
NC
NC A_OUT_ A_OUT_ NC
NC
A06
B*
B
TXDATA
SSFLA ZEROW
POL_S
TXDATA
TXINH_
_OUT_B
NC
G*EXT_ AIT*/ME A01 EL/DTA 8
_OUT_B
OUT_B
*
TRIG MWR*
CK*
NC
NC
NC
TXDATA TXDATA TXINH_I
_IN_B _IN_B*
N_B
NC
NC
NC
NC
+3.3v_L +3.3v_L +3.3v_L +3.3v_L 7
OGIC OGIC OGIC OGIC
NC
+3.3v_L +3.3v_L +3.3v_L +3.3v_L 6
OGIC OGIC OGIC OGIC
+3.3V_X +3.3V_X HERMA HERMA HERMA HERMA NC
CVR
CVR L_GND L_GND L_GND L_GND
XCVR_T XCVR_T XCVR_T XCVR_T SLEEPI
+3.3V_X +3.3V_X HERMA HERMA HERMA HERMA
N
CVR
+3.3V_X +3.3V_X HERMA HERMA HERMA HERMA NC
CVR
XCVR_T
Tx/Rx- Tx/Rx+3.3V_X +3.3V_X Tx/Rx-B Tx/Rx-B HERMA
B*
B*
CVR
CVR
L_GND
XCVR_T
Tx/Rx- Tx/Rx+3.3V_X +3.3V_X Tx/Rx-B Tx/Rx-B HERMA
B*
B*
CVR
CVR
L_GND
J
K
L
M
N
P
R
NC
+3.3V_X +3.3V_X 5
CVR
CVR
NC
+3.3V_X +3.3V_X 4
CVR
CVR
NC
NC
NC
3
NC
NC
NC
2
NC
NC
NC
1
T
U
V
XCVR MISC
1553 MISC
CPU INTERFACE
No Connect
GND
+3.3/+5V Power
Figure 14. Micro-ACE-TE (1.0mm Ball Pitch)
(with +3.3V transceivers) BGA Pin Assignments
www.ddc-web.com
14
AN/B-49
5/13-0
BGA USER’S GUIDE
A
18
INT*
17 IOEN*
B
TRANS/
BUFF*
16
+3.3/+5 +3.3/+5
V Logic V Logic
15
TX_INH_ READY
B
D*
14
TX_INH_
STRBD*
A
13
MCRST MEM/R
*
EG*
12 RD/WR*
C
TAG_CL
GND
K
GND
D
E
F
G
H
D14
D12
D8
D2
D0
(LSB)
D15
(MSB)
D11
D7
D3
D5
J
K
L
D6
GND
+3.3/+5
V Logic
D13
GND
+3.3/+5
V Logic
M
N
P
R
D4
D9
RT_AD_
LAT
T
NC
RTADP RTAD3 RTAD1 18
D1
D10
RSTBIT
EN
NC
RTAD4
RTAD0
17
RTAD2
(MSB)
(LSB)
Tx/RxB*
GND
V
Tx/Rx16
B*
XCVR_T
HERMA +5V_XC 15
L_GND
VR
XCVR_T
HERMA +5V_XC 14
L_GND
VR
XCVR_T
HERMA +5V_XC 13
L_GND
VR
SELEC
T*
Tx/Rx-B Tx/Rx-B 12
A15/CL
MSTCL
11 K_SEL_
R*
1
A14/CL
A13/Vc
10
K_SEL_
c
0
9
U
GND
NC
NC
11
NC
NC
10
GND
CLK
9
ZEROW ADDR_
AIT*/ME LAT/ME 8
MWR* MOE*
POL_S
16/8*/D
7
EL/DTA
TREQ*
CK*
MSB/LS TRIG_S
B/DTGR EL/ME 6
T*
MENA_I
8
+3.3/+5 +3.3/+5
V Logic V Logic
7
A12/RT
BOOT*
A11
6
A10
A9
5
A7
A8
NC
NC
5
4
A6
A5
GND
GND
4
3
A4
A3
+5V_RA +5V_RA 3
M
M
2
A2
NC
NC
1
A0
(LSB)
A1
NC
A
B
C
Tx/RxTx/Rx-A HERMA HERMA HERMA
A*
L_GND L_GND L_GND
NC
NC
+3.3/+5
V Logic
Tx/RxA*
NC
NC
+3.3/+5
INCMD*
V Logic
H
J
K
Tx/Rx-A +5V_XC +5V_XC +5V_XC
VR
VR
VR
D
E
F
G
L
NC
M
UPADD
REN/LO
GIC 1
NC
SSFLA
G*EXT_
TRIG
NC
NC
NC
NC
NC
NC
NC
GND
N
P
R
T
U
V
Vdd_Lo
2
w
1
XCVR MISC
1553 MISC
CPU INTERFACE
No Connect
GND
+3.3/+5V Power
Figure 15. Micro-ACE (1.0mm Ball Pitch) BGA Pin Assignments
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4
REFLOW SOLDERING PROCESS
4.1
Solder Reflow Guidlines
The user’s specific equipment and board loading/layout makes it difficult for DDC to
propose a standard reflow solution other than to recommend that the user reference
the reflow profile detailed in IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices.” This reflow profile
is applicable to all of DDCs plastic BGA products in both leaded and lead-free
versions. DDC recommends using Daisy Chain Mechanical Samples (Table 1) to
qualify the PCB assembly processes in lieu of actual devices.
4.2
Package Peak Reflow Temperature
The maximum peak reflow temperature of the plastic BGA case must not exceed +245
°C under any circumstances. This limitation is applicable to all of DDCs plastic BGA
products in both leaded and lead-free versions.
4.3
Underfill
Solder reflow of a BGA device using the previously stated recommendations will
produce good mechanical and thermal properties. In some instances the strength of
the BGA solder bonds can be compromised by external forces. In those cases
underfill (Figure 16) can be used to increase the strength of the BGA bond by 5 to 10
times and improve the thermal performance as well.
Figure 16. BGA Device with Underfill
The underfill is drawn under the BGA by capillary action and the temperature is held
until the product has cured. Fast-curing underfills can be ready in several minutes,
while some can take up to 90 minutes before reaching optimal strength.
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When selecting an underfill, the user should be aware that rework may prove difficult
or impossible depending on the chosen material.
5
MOISTURE SENSITIVITY OF PLASTIC BGAS
5.1
Moisture-Induced Cracking and Popcorning during Solder Reflow
Surface mount reflow processing subjects plastic BGAs to large thermal excursions
and harsh chemicals from solder fluxes and cleaning fluids during assembly. Although
minimized through BGA design elements, additional stresses exist due to differences
between the Thermal Coefficient of Expansion (TCE) of the encapsulant, the Hi TGFR4 substrate and multiple silicon die.
Hard pot epoxy mold compounds used in encapsulating BGAs absorb moisture
(hygroscopic) determined by the storage environment and other factors. This moisture
can vaporize (steam) during the rapid heating inherent in the solder reflow process,
creating high internal pressures. These pressures may be sufficient to cause
delamination, internal / external cracking, and broken/lifted bond wires.
Moisture sensitivity testing, handling procedures, and standards are maintained by
two national organizations. DDC recommends that end users obtain copies of the
documents below (available from www.jedec.org) and incorporate the procedures and
recommendations into their standard process.
IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount
Devices.”
AND
IPC/JEDEC J-STD-033
“Standard for Handling, Packing, Shipping, and Use of Moisture/Reflow Sensitive
Surface Mount Devices.”
5.2
Assigned Package Moisture Sensitivity Level (MSL)
Table 5 depicts the DDC assigned MSL level for various packages. Specific MSL
information and the recommended bake-out procedure are printed on the dry pack
shipping bag in which the components are shipped. The MSL level printed on the dry
pack shipping bag takes precedence over the values listed in Table 5.
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Table 4. Moisture Sensitivity Level
Package Type
Description
Ball Pitch
Series
MSL Rating
324-Ball BGA
18 x 18 Full-Matrix
0.8mm
Total-AceXtreme
MSL-3
312-Ball BGA
24 x 13 Full-Matrix
1.0mm
Total-ACE
MSL-3
324-Ball BGA
18 x 18 Full-Matrix
1.0mm
Micro-ACE-TE
MSL-3
128-Ball BGA
1.0mm
Micro-ACE
MSL-3
5.3
Electrostatic Discharge Sensitivity (ESD)
TABLE 6 depicts the DDC assigned ESD class for various packages. These devices
can be damaged by electrostatic discharges < 250 volts and should be handled
appropriately.
Table 5. Electrostatic Discharge Sensitivity
Package Type
Description
Ball Pitch
Series
ESD Rating
324-Ball BGA
18 x 18 Full-Matrix
0.8mm
Total-ACExtreme
Class 0
312-Ball BGA
24 x 13 Full-Matrix
1.0mm
Total-ACE
Class 0
324-Ball BGA
18 x 18 Full-Matrix
1.0mm
Micro-ACE-TE
Class 0
128-Ball BGA
1.0mm
Micro-ACE
Class 0
DDC's ESD testing, handling procedures, and standards are based on the United
States Military Standards listed below. DDC recommends that end users obtain copies
of the documents below (available from http://global.ihs.com) and incorporate the
procedures and recommendations into their standard process.
MIL-STD-750D
“Test Method Standard for Semiconductor Devices”
AND
MIL-STD-1686C
“Electrostatic Discharge Control Program for Protection of Electrical and Electronic
Parts, Assemblies and Equipment”
6
REWORKING OF PLASTIC BGAS
It is extremely important that proper procedures be followed to ensure successful
reworking of Plastic BGAs. The same caveats regarding bake-out due to the
hygroscopic nature of the hard pot epoxy encapsulation apply during the rework
process as well. The printed circuit board must always be pre-baked before any
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rework operation. It is recommended that the specific instructions provided by the
manufacturer of the rework system be followed.
Specialized equipment and tools allowing for localized plastic BGA removal are
commercially available. Hot gas rework systems with vacuum suction are
recommended as these ensure that the component and the PCB board are not
warped or overheated and that all balls are reflowed.
6.1
BGA Reballing
DDC does not recommend reballing of BGA components due to cost and durability
concerns. A maximum of three reflow cycles are allowed.
6.2
Conformal Coating
DDC plastic (HardPot Epoxy) BGA components are compatible with both Urethane &
Polyurethane conformal coating.
7
BGA PACKAGE LABELS
7.1
Package Marking (Symbolization)
All DDC BGA devices have package marking similar to the example shown in Figures
17 - 19. Marking can be laser inscribed or be in the form of a permanent Mylar label.
Figure 17. Total-AceXtreme Package Markings
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Figure 18. Total-ACE Package Markings
Figure 19. Micro-ACE-TE Package Markings
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Figure 20. Micro-ACE Package Markings
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RM
®
I
FI
REG
U
ST
Outside the U.S. - Call 1-631-567-5700
ERED
DATA DEVICE CORPORATION
REGISTERED TO:
ISO 9001:2008, AS9100C:2009-01
EN9100:2009, JIS Q9100:2009
FILE NO. 10001296 ASH09
The first choice for more than 45 years—DDC
DDC is the world leader in the design and manufacture of high reliability
data interface products, motion control, and solid-state power controllers
for aerospace, defense, and industrial automation.
Inside the U.S. - Call Toll-Free 1-800-DDC-5757
Headquarters and Main Plant
105 Wilbur Place, Bohemia, NY 11716-2426
Tel: (631) 567-5600 Fax: (631) 567-7358
Toll-Free, Customer Service: 1-800-DDC-5757
Web site: www.ddc-web.com
United Kingdom: DDC U.K., LTD
Mill Reef House, 9-14 Cheap Street, Newbury,
Berkshire RG14 5DD, England
Tel: +44 1635 811140 Fax: +44 1635 32264
France: DDC Electronique
10 Rue Carle-Herbert
92400 Courbevoie France
Tel: +33-1-41-16-3424 Fax: +33-1-41-16-3425
Germany: DDC Elektronik GmbH
Triebstrasse 3, D-80993 München, Germany
Tel: +49 (0) 89-15 00 12-11
Fax: +49 (0) 89-15 00 12-22
Japan: DDC Electronics K.K.
Dai-ichi Magami Bldg, 8F, 1-5, Koraku 1-chome,
Bunkyo-ku, Tokyo 112-0004, Japan
Tel: 81-3-3814-7688 Fax: 81-3-3814-7689
Web site: www.ddcjapan.co.jp
Asia: Data Device Corporation - RO Registered in Singapore
Blk-327 Hougang Ave 5 #05-164
Singapore 530327
Tel: +65 6489 4801
The information in this Application Note is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights
are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.
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BGA User`s Guide - Data Device Corporation

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