DVClub Shanghai Presentation

Circuit Design:
Slip Schedule or Automate Debug
Daniel Große
CEO solvertec GmbH
DVClub Shanghai - Friday, 26 September 2014 on
Making Verification Debug More Efficient
ready
IF ?
Image sources:
http://ibmdatamag.com/wp-content/
uploads/2012/02/42-17073473.jpg
http://data3.whicdn.com/images/33933571/original.jpg
= 1 &&
sync = 0
&& addr < 0xFF
&& burst
&& no_reset
% of designs are
behind schedule
3
Agenda
•
•
•
•
Debugging Situations
RTL Debugging Problem
Automating RTL Debugging
Summary
4
Debugging Situations
Debugging
ESL Design
RTL Design
Synthesis
/ECO
Post-silicon
Spec.
Testbench
Testbench/
Formal Property
RTL
RTL
Impl.
Alg. Description
RTL
Gate
Chip
Observation
Execution
Counterex.
/Stimuli
Counterex.
/Mapping
Trace data
Type of bug
Coding issue,
throughput, …
Coding issue,
synchronization, …
(Local)
synthesis issue
Escaped design
bug, electrical
bug
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Debugging Problem
• In the following focus on digital RTL design debugging
• Problem:
If verification fails, where in the implementation is the bug?
?
• Debugging today:


Manual backtracing using waveform viewers and RTL code
Design schematic tools
6
Verification
Testbench
Input
Stimuli
DUT
Response
Check
7
Verification
Testbench
Input
Stimuli
DUT
Response
Check
8
Debugging
Look at
waveform
Find drivers in
RTL code
if (x = ´1´) {
a <= c and b;
else
a <= tmp;
end if;
Determine
active RTL code
if (x = ´1´) {
a <= c and b;
else
a <= tmp;
end if;
Manual Bug Localization
Debug!t
Backtrace &
decide paths
Faulty
• condition?
• values?
• operators?
Candidate
analysis
Fix
Manual Fix
Where to change the code to meet
the expected behavior?
Automated Debugging
9
Debugging Flow using Debug!t
Detect
Localize
Fix
Bug Locations
Correction
values
Explanations
Effect
propagation
Testbench
failing
trace
Input
Stimuli
DUT
Response
Check
+
expected
behavior
Debug!t
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Detect: Expected Behavior of DUT
• Verification failed due to design error in DUT
• Input for Debug!t


Failing trace (e.g. VCD) and
Expected behavior
» Self-checking testbenches

If (x!=23) report “error”;
» Assertions

Failed, signal: x, time: t_now , expected: 23
Assert(x = 23)
» Reference-Model
 is_valid = ‘1’ && x = 23
11
Tool Integration
• Integration via standard interfaces
• Improved integration via TCL making debugit command available


Cadence
Mentor
Failing testcase
Single command extracts
all data and starts Debug!t
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Localize
• Root cause analysis of sources of a design error


Computation of bug locations
Bug location
» Expression in RTL that can be changed to fix the bug
» Contains instance, time, and correction value
• Cut down debugging task to

User decision based on computed set of bug locations:
» bug indeed originates from actual bug location or
» just propagates through it
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Root Cause Analysis
Result 1:
Corrections only possible in
red circuit components
14
Filter out irrelevant code & pinpoint to candidates
Result 2:
Small set of bug locations
… and:
Pinpoint to source code lines &
give explanations for fixing
15
Key Benefit of Debug!t
Dramatic reduction
Manual debugging vs Debug!t
16
Selected Results
Design
Type
Size
(gates)
Reduction to
(time or problem size)
Image processing unit
FPGA
1.2M
8 days  10 min
Arithmetic unit
ASIC
130k
2 hours  10 min
Arithmetic unit
ASIC
390k
0.3%
Gamma encoding
FPGA
420k
0.4%
HW accelerator
ASIC
3.6M
0.5%
Router
FPGA
145k
0.7%
Pixel correction
FPGA
3.4M
4.1%
(problem size measured in lines of code)
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Summary
• Debugging is a challenging problem
• Automation is required to cut down debugging effort
• Debug!t eliminates the design debugging bottleneck
18
Choose the right technology …
Image source: http://img01.lachschon.de/images/160054_Loeschzug_1.jpg
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Visit us at DVCon Europe 2014
Oct 14-15, Munich
Contact
solvertec GmbH
Daniel Große, Co-Founder & CEO
grosse@solvertec.de|+49 421 40 89 84 51