Optimizing PCB Thermal Performance for Cree XLamp LEDs

Transcription

CLD-AP37 Rev 2H
Product design Guide
Optimizing PCB Thermal Performance for Cree® XLamp® LEDs
Table of Contents
Introduction
Introduction...............................................1
This Cree application note outlines a
metalized vias in FR-4 PCBs. For certain
Thermal Management Principles.............2
technique to assist with the development
illumination systems design, thermal
XLamp LED Thermal
of cost-effective thermal management
vias enable the use of FR-4 circuit boards
Characteristics....................................2
for the XT, XP, XB, MX and ML families of
instead of metal core circuit boards. This
PCB Thermal Characteristics.............3
XLamp® LEDs.
can deliver system cost savings in circuit
board and heat sink selection.
Designing Thermal Vias......................4
Open Vias vs. Filled Vias.....................5
One
of
the
most
critical
design
Thermal Performance Simulations..........7
parameters for an LED illumination
This application note serves as a
Surface Thermal Dissipation..............7
system is the system’s ability to draw
practical
Thermal Dissipation with Vias............8
heat away from the LED junction.
transfer
Combined Surface and Via Studies.10
High operating temperatures at the
suggestive, but not definitive, simulation
Summary Results of Thermal
LED
the
and measurement data. Cree advocates
Simulations........................................12
performance
in
this technique as appropriate design
junction
adversely
of
LEDs,
affect
resulting
guideline
based
fundamentals
on
and
heat
includes
Temperature Verification
1
decreased light output and lifetime.
for certain lighting applications and
Measurements........................................13
To properly manage this heat, specific
encourages Cree’s customers to evaluate
Recommended Board Layouts...............15
practices should be followed in the
this option when considering the many
Gerber files.........................................15
design, assembly and operation of LEDs
thermal
FR-4 Boards for XLamp XP and XT
in lighting applications.
available. For additional guidelines on
management
techniques
LED thermal management, refer to the
LED Packages....................................16
FR-4 Boards for XLamp XB LED
This application note outlines a technique
Package.............................................17
for designing a low-cost printed circuit
FR-4 Boards for XLamp MX LED
board (PCB) layout that optimizes the
Package.............................................19
transfer of heat from the LED. The
FR-4 Boards for XLamp ML LED
technique involves the use of FR-4-based
Package.............................................20
PCBs, which cost less than metal core
Chemical Compatibility..........................21
printed circuit boards (MCPCB), but have
References...............................................21
greater thermal resistance. The use of
Thermal Management application note.
metal-lined holes or vias underneath LED
thermal pads is a method to dissipate
heat through an FR-4 PCB and into an
www.cree.com/Xlamp
appropriate heat sink.
Cree XLamp LEDs are designed with
an electrically isolated thermal path.
Cree pioneered this LED feature almost
ten years ago to enable the use of
1 See the Long-Term
application note.
Lumen
Maintenance
Copyright © 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree® and XLamp® are
registered trademarks and the Cree logo is a trademark of Cree, Inc. This document is provided for informational purposes only and is not a warranty
or a specification. For product specifications, please see the data sheets available at www.cree.com. For warranty information, please contact Cree
Sales at sales@cree.com.
Cree, Inc.
4600 Silicon Drive
Durham, NC 27703
USA Tel: +1.919.313.5300
Optimizing PCB Thermal Performance
Thermal Management Principles
Figure 1. Cree XLamp XP LED Package
The technique in this application note is not recommended for Cree LEDs that consume more than 5 W of power, including MC-E, MP-L
and MT-G. For low power applications, this technique can be used for XM-L and XM-L EZW LEDs.
XLamp LED Thermal Characteristics
All XLamp LED packages have an electrically isolated thermal pad. The pad provides an effective channel for heat transfer and optimizes
thermal resistance from the LED chip junction to the thermal pad. The pad is electrically isolated from the anode and cathode of the LED
and can be soldered or attached directly to grounded elements on the board or heat sink system.
Anode
LED chip
Lens
Thermal pad
Cathode
Ceramic substrate
AlNsubstrate
Figure 1: Cree XLamp XP LED package
Heat is conducted from the LED package through the thermal pad and into a PCB that should be mounted to a heat sink to transfer the
conducted heat into the operating environment.2
Tables 1 and 2 list typical thermal resistance values (junction to solder point) for various XLamp series LEDs.
Table 1: Typical thermal resistance values for Cree XLamp white LEDs
Thermal Resistance (ºC/W)
Color
White
(cool, neutral, warm)
ML-B
ML-C
ML-E
MX-3
MX-6
XB-D
XM-L
XM-L
EZW
XM-L
HVW
XP-C
XP-E
XP-G
XT-E
XT-E
HVW
25
13
11
11
5
6.5
2.5
2.5
3.5
12
9
4
5
6.5
Table 2: Typical thermal resistance values for Cree XLamp color LEDs
n/a indicates an LED that Cree does not offer
Color
2
Thermal Resistance (ºC/W)
ML-E
XP-C
XP-E
Royal blue
n/a
12
9
Blue
11
12
9
Green
15
20
15
Amber
n/a
15
10
Red
15
10
10
Red-orange
n/a
10
10
For subsequent discussion and simulation in this document, we assume the PCB is mounted to an infinite heat sink that maintains the back side of the board at 25 ºC.
Copyright © 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree® and XLamp® are registered trademarks and the Cree logo is a trademark of
Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see the data sheets available at www.cree.com. For warranty
information, please contact Cree Sales at sales@cree.com.
2
Figure 2: FR-4 cross-sectional geometry (not to scale)
PCB Thermal Characteristics
FR-4
FR-4 is one of the most commonly used PCB materials and is the National Electrical Manufacturers Association (NEMA) designation for
a flame retardant, fiberglass-reinforced epoxy laminate. A by-product of this construction is that FR-4 has very low thermal conductivity.
Figure 2 below shows a typical cross-sectional geometry for a two-layer FR-4 board.
Heat source
Thermal pad
Top layer Cu
Solder mask
FR4 dielectric
Bottom layer Cu
ENIG
Figure 2: FR-4 cross-sectional geometry (not to scale)
Using the thermal conductivity values in Table 3 below, the total thermal resistance for an FR-4 board can be calculated by adding the
thermal resistances of the layers.
θPCB = θlayer1 + θlayer2 + θlayer3 ... + θlayerN
(1)
For a given layer the thermal resistance is given by the formula:
θ = l / (k x A) (2)
where l is the layer thickness, k is the thermal conductivity, and A is the area normal to the heat source.
For a 1.6-mm thick star board approximately 270 mm2, the calculated through-plane thermal resistance is approximately 30 ºC/W. Bear
in mind that this calculation is one-dimensional and does not account for the size of the heat source, spreading, convection thermal
resistances or boundary conditions. If a smaller heat source size is considered, for example 3.3 mm x 3.3 mm, the resulting onedimensional thermal resistance increases to over 700 ºC/W.
Table 3: Typical thermal conductivities of FR-4 board layers
Layer/Material
Thickness (µm)
SnAgCu solder
75
58
Top layer copper
70
398
FR-4 dielectric
Thermal conductivity (W/mK)
1588
0.2
Bottom layer copper
70
398
Electroless Nickel/Immersion Gold (ENIG)
5
4.2
Metal-Core Printed Circuit Board
A simple one-layer MCPCB is comprised of a solder mask, copper circuit layer, thermally conductive dielectric layer, and metal core base
layer, as shown below in Figure 3. These three layers are laminated and bonded together, providing a path for the heat to dissipate. Often
the metal substrate is aluminum, though steel and copper can also be used.
3
Heat source
Thermal pad
Top layer Cu
Solder mask
Dielectric layer
Al substrate
Figure 3: MCPCB cross-sectional geometry (not to scale)
Using the thermal conductivity values in Table 4 below, the one-dimensional through-plane thermal resistance for a 1.6-mm-thick star
board of approximately 270 mm2 is roughly 0.2 ºC/W. If a smaller heat source size is considered, the resulting thermal resistance is
5.3 ºC/W. In this case, the limiting factor is the PCB dielectric.
Table 4: Typical thermal conductivities of MCPCB layers
Layer/Material
Thickness (µm)
SnAgCu solder
75
58
Top layer copper
70
398
PCB dielectric
100
2.2
Al plate
1588
150
Designing Thermal Vias
An inexpensive way to improve thermal transfer for FR-4 PCBs is to add thermal vias - plated through-holes (PTH) between conductive
layers. Vias are created by drilling holes and copper plating them, in the same way that a PTH or via is used for electrical interconnections
between layers.
Figure 4: FR-4 cross-sectional geometry with thermal vias (not to scale)
4
Application Note: Optimizing PCB Thermal Performance for Cree XLampLEDs
AN_100302-draft8e.docx
Optimizing
PCB Thermal Performance
0.6 mm dia. via with
35 µm plating
Solder mask
0.3 mm dia. via with
35 µm plating
Top layer Cu
FR4 dielectric
Bottom layer Cu
Figure 5. Cross-sectional geometry of small and large thermal vias in FR-4 substrate
Figure 5: Cross-sectional geometry of small and large thermal vias in FR-4 substrate
Adding vias in an appropriate way will improve the thermal resistance of an FR-4 board. The thermal
Adding vias resistance
in an appropriate
way will
thermal resistance
of an
FR-4 board.l The
resistance
of a single
via can be
of a single
viaimprove
can be the
calculated
by the same
formula,
/ (k xthermal
A). Using
the values
in
-3
/ (58
x (0.5 xof0.6
of 0.6inmm
results
in (1.588
x 10 )via
4, a formula,
single solid
diameter
calculated byTable
the same
θ = l via
/ (kwith
x A).aUsing
the values
Table
5, a single
solder-filled
withxa( diameter
0.6xmm results in
-3 2
when
N
vias
are
used,
the
area
increases
by
a
factor
of
N
,
resulting
-3 10 ) )) = 96.8 ºC/W. However,
-3 2
vias
(1.588 x 10 ) / (58 x (� x (0.5 x 0.6 x 10 ) )) = 96.8 ºC/W. However, when N vias are used, the area increases by a factor of Nvias, resulting in:
in:
vias
θvias = l / (Nvias x k x A)
l / (Nvias x k x A)
(3)
(3)
Note that this is applicable only if the heat source is directly normal to the thermal via; otherwise, the resistance increases due to thermal
Keep in mind this is applicable only if the heat source is directly normal to the thermal via; otherwise,
spreading effects.
To calculate
total thermal
for the region
underneath
(or normalthe
to)total
the LED
thermal
pad, the equivalent
the resistance
willthe
increase
due toresistance
thermal spreading
effects.
To calculate
thermal
resistance
the applying
for thefor
region
underneath
to)bethe
LED thermal
pad, the the
equivalent
thermalare
resistance
thermal resistance
the dielectric
layer (or
andnormal
vias must
determined.
For simplicity,
two resistances
treated asfor
parallel
dielectric layer and vias should be determined. For simplicity, the two resistances are treated as
parallel applying this formula:
this formula.
θvias || FR-4 = [ (1/θvias) + (1/θFR-4)-1]-1
= [ (1/ vias) + (1/ FR-4) ]
vias || FR-4
(4)
(4)
2
2
five 0.6-mm-diameter
vias results
an approximate
thermal resistance
Using the values
in Table
5, for ain270 mm
Using
the values
table 4,board
for awith
270mm
board with fivesolder-filled
0.6mm diameter
solidinvias
results in an
thermal
of 12ºC/W,
a 250%
improvement
of 12 ºC/W, aapproximate
60% improvement
overresistance
the initial 30 ºC/W
derived
from the
data in Tableover
3. the initial 30ºC/W derived in
from the data in Table 2.
Table 5: Typical thermal conductivities of FR-4 board layers including thermal vias
Layer/Material
SnAgCu solder
Top-layer copper
FR-4
Filled vias (SnAgCu)
Bottom-layer copper
Layer/Material
SnAgCu solder
Top layer copper
FR-4
Filled vias (SnAgCu)
Bottom layer copper
Solder mask (optional)
Solder mask (optional)
Thickness (um)
75
70
1588
1588
70
25
Thermal
Thickness
(µm)
75
70
1588
1588
70
conductivity (W/mK)
58
58
398
398
0.2
0.2
58
58
398
398
0.2
25
Table 4. Thermal conductivities of FR-4 board layers including thermal vias
0.2
Open Vias vs. Filled Vias
2.3 in aOpen
Vias vs.
Filled than
Viasfilled vias because the area normal to the heat source is reduced per the formula:
Open vias result
higher thermal
resistance
(5) normal to
� x (D x tthermal
– t2)
Open vias will result inA a= higher
resistance compared to filled vias because the area
the heat source is reduced per the formula:
where D is the via diameter and t is the plating thickness.
A=
2
x (D x t – t )
(5)
where D is the via diameter and t is the plating thickness.
2 sales@cree.com.
2
information, please contact Cree Sales at
For a 0.6mm diameter via with 35 m (1 oz.) copper plating, the area (normal to the thermal pad) is
only 0.06mm compared to 0.28mm for a solid via, resulting in a thermal resistance of 441 ºC/W per
5
Application Note: Optimizing PCB Thermal Performance for Cree XLampLEDs AN_100302-draft8e.docx
via compared to 96.8 ºC/W. For the same sized board and number of vias as in the previous example,
the resulting
through-plane
resistance
becomes
~28 ºC/W.
via compared
to 96.8thermal
ºC/W. For
the same
sized board
and number of vias as in the previous example,
via
compared
96.8 ºC/W. For
the same
sized board
and~28
number
of vias as in the previous example,
the
resulting to
through-plane
thermal
resistance
becomes
ºC/W.
the
resulting
through-plane
thermal
resistance
becomes
~28
ºC/W.
However, the ability to create solid (copper) filled vias delivers additional reduced thermal resistance,
For a 0.6-mm diameter via with 35 µm (1 oz.) copper plating, the area normal to the thermal pad is only 0.06 mm2 compared to 0.28 mm2
as compared
to vias
SnAgCu
solder.
However,
the filled
abilitywith
to create
solid
(copper) filled vias delivers additional reduced thermal resistance,
However,
the
ability
to
create
solid
(copper)
filled
vias
deliverstoadditional
resistance,
for a solder-filled via,
resulting
in
a
thermal
resistance
of
64 ºC/W
per via
compared
42 ºC/W ifreduced
filled withthermal
solder or
14 ºC/W if filled
as compared to vias filled with SnAgCu
solder.
as
compared
to
vias
filled
with
SnAgCu
solder.
In
general,
increasing
plating
thickness
during
PCB
production
will
improve
thermal
resistance
of
vias.
completely with copper.
ConsultInwith
your PCB
manufacturer
to determine
if thicker
plating is feasible.
general,
increasing
plating thickness
during
PCB production
will improve thermal resistance of vias.
In
general,
increasing
plating
thickness
during
PCB
production
will improve
thermal resistance of vias.
Consult
your during
PCB manufacturer
determine
thickerresistance
plating
isoffeasible.
In general, increasing
plating with
thickness
PCB productiontoimproves
theifthermal
vias. In the example above, increasing
Consult
PCB filled
manufacturer
to during
determine
if thicker
plating
is feasible.
Non-filled
viaswith
mayyour
become
with solder
reflow.
However,
depending
on a number of
the plating thickness to 70 µm (2 oz.) lowers the thermal resistance to 34 ºC/W per via. Consult your PCB manufacturer to determine if
factors,Non-filled
this may not
reliably. filled
The vias,
if not reliably
not an effective
heaton a number of
viasoccur
may become
with solder
during filled,
reflow.are
However,
depending
Non-filled
viasmay
maynot
become
withThe
solder
during
on a number
of
thicker plating
is feasible.
management
factors,tool.
this
occur filled
reliably.
vias,
if notreflow.
reliablyHowever,
filled, are depending
not an effective
heat
factors,
this
may
not
occur
reliably.
The
vias,
if
not
reliably
filled,
are
not
an
effective
heat
management tool.
management
Non-filled vias
may
become
filledtool.
solder
during reflow.
However,
depending
on production,
a number of factors,
mayis
not
Other
than
creating
awith
solid
via during
the plating
process
in PCB
anotherthis
option
tooccur
fill thereliably and
vias
with
copper
(or
some
other
thermally
conductive
material
such
as
conductive
epoxy)
as
part
of is
the
than creating
solid via during the plating process in PCB production, another option
to fill the
as a result, the vias Other
will conduct
heat less aeffectively.
Other
than
creating
a
solid
via
during
the
plating
process
in
PCB
production,
another
option
is
to fillofthe
PCB fabrication
process.
But
this
adds
an
additional
step
to
fabrication
and
may
increase
the
cost
of
vias with copper (or some other thermally conductive material such as conductive epoxy) as part
the
vias
with
copper (or
some other
thermally
conductive
such as conductive
asthe
part
of the
board.
PCB
fabrication
Butprocess
this
adds
an
additionalmaterial
step
tothe
fabrication
may epoxy)
increase
cost
of such
An option tothe
creating
a solid
via duringprocess.
the plating
in PCB
production
is
to fill
vias with and
a thermally
conductive
material
PCB
fabrication
process. But this adds an additional step to fabrication and may increase the cost of
the
board.
as epoxy asSolder
part of
the
PCB
fabrication
process.
This adds an additional step to fabrication and may increase the cost of the board.
the
board.
voiding in open PTH
vias.
Solder
voiding
in open PTH vias.
Solder voiding in open
PTH
vias
voiding
in openofPTH
vias.vias after reflow, and Figure 6b shows an example of solder
FigureSolder
6a shows
an example
unfilled
voids
underneath
the
device
(shown
in red).
voids
increase
the
thermal
resistance
ofdevice
the of
Figure 6 shows an example
of unfilled
after reflow.
FigureThe
7 vias
shows
anwill
example
of solder
voids
(shown
in red).
Figure 6a
shows vias
an example
of
unfilled
after
reflow,
and
Figure
6bunderneath
shows
an the
example
solder
Figure
6a
shows
an
example
of
unfilled
vias
after
reflow,
and
Figure
6b
shows
an
example
ofofsolder
thermal
interface.
Also,
the
solder
may
overfill
the
hole
leading
to
bumps
on
the
bottom
of
the
board
voids
underneath
the
device
(shown
in
red).
The
voids
will
increase
the
thermal
resistance
the
The voids increase the thermal resistance of the thermal interface. Also, the solder may overfill the hole leading to bumps on the bottom
underneath
the
device
(shown
inboard
red).
The
voids
will
increase
thebe
thermal
resistance
the
whichvoids
can
reduce
contact
area
between
andthe
heat
sink.
Stepstocan
taken
limit theofof
thermal
interface.
Also,
the
solderthe
may
overfill
hole
leading
bumps
on theto
bottom
the
board
of the boardamount
that can
reduce
the
contact
areathe
between
the
board
and
the diameter
heat
sink.
thermal
interface.
Also,
solder
may
overfill
the
hole
leading
to
bumps
on
the
bottom
of
the
of
solder
wicking.
One
way
is
to
maintain
a
via
smaller
than
0.3
mm.
With
smaller
which can reduce contact area between the board and heat sink. Steps can be taken to limit board
the
which
canofreduce
area
board
heat
sink.
Steps
can
be 0.3
taken
toforce
limitof
the
vias, the
surface
tension
of the liquid
solder
the viaand
more
capable
of countering
the
amount
soldercontact
wicking.
Onebetween
way isinside
tothe
maintain
aisvia
diameter
smaller
than
mm.
With
smaller
amount
of
solder
wicking.
One
way
is
to
maintain
a
via
diameter
smaller
than
0.3
mm.
With
smaller
Steps can be
taken
to
limit
the
amount
of
solder
wicking.
One
way
is
to
maintain
a
via
diameter
smaller
than
0.3 mm.
With of
smaller
gravity vias,
on thethe
solder.
If the
via structure
is constructed
following
guidelines
mentioned
above,
surface
tension
of the liquid
solder inside
the viathe
is more
capable
of countering
the force
vias,
the
surface
tension
of
the
liquid
solder
inside
the
via
is
more
capable
of
countering
the
force
of
holding
inside
diameter
toIfaround
0.25
mm
–is0.3
mm,
minimal
solder
wicking
achieved.
The
vias, the surface
tension
of via
thethe
liquid
solder
inside
the
via is
better
able
to counter
the
force
ofguidelines
gravityison
the
solder.
If the
via structure
gravity
on
solder.
the via
structure
constructed
following
the
mentioned
above,
gravity
oninside
the
solder.
If the
structure
isvias
constructed
following
theoverall
guidelines
mentioned
above,
drawback
to this
approach
is
thatvia
smaller
open
will– result
in aminimal
higher
thermal
resistance.
holding
via
diameter
to
around
0.25
mm
0.3
mm,
solder
wicking
is
achieved.
The
is constructed following the guideline above, holding the inside via diameter to around 0.25 mm – 0.3 mm, minimal solder
holding
inside
via diameter
0.25 mm
0.3 mm,
minimal
achieved.
Thewicking is
drawback
to this
approachtoisaround
that smaller
open– vias
will result
in asolder
higherwicking
overallisthermal
resistance.
achieved. The drawback
to this
is thatis
smaller
open vias
result
in awill
higher
overall
resistance.
drawback
to approach
this approach
that smaller
open
vias
result
in a thermal
higher overall
thermal resistance.
Figure 6a. Unfilled vias
Figure
Unfilled
viasvias
Figure6:6a.
Unfilled
Figure 6a. Unfilled vias
Figure 6b. Solder voiding (not to scale)
Figurevoiding
7: Solder
voiding
(not to scale)
Figure 6b. Solder
(not
to scale)
Figure 6b. Solder voiding (not to scale)
Another
for limiting
wicking
involves
using
solder
to solder
restrictfrom
thethe
flow
ofside
solder
Another technique
fortechnique
limiting solder
wickingsolder
involves
using solder
mask
to restrict
themask
flow of
top
of the PCB to the
from the top side of the PCB to the bottom side. One process, called “tenting”, uses solder mask to
Another
technique
limiting
solder
involves
using
solder
mask
to side
restrict
thesolder
flow ofto
solder
prevent
solder
from
eitherfor
the thermal
vias,
depending
on “tenting”,
the
of
the
board
from
the
top side
ofentering
the
PCBor
toexiting
the wicking
bottom
side.
One
process,
called
uses
mask
to
on the side which
of the board
on which
the is
solder
mask
is placed.
Tenting
the
bottom
side
with
solder
mask
to and
cover
and
plugmask
the thermal
from
the
top
side
of
the
PCB
to
the
bottom
side.
One
process,
called
“tenting”,
uses
solder
to to vias
the
solder
mask
placed.
Tenting
the
bottom
side
with
solder
mask
to
cover
plug
the
prevent solder from either entering or exiting the thermal vias, depending on the side of the board
solder
frommask
either
entering
or exiting
thermal
vias,
the
side
of
the
board
to mask
viasflowing
can
prevent
solder
from
flowing
down
into
thethe
via
and
onto
the bottom
ofcover
the
board.
In
can preventthermal
solderprevent
from
down
into
theisvias
and
onto
the
bottom
of
board.
Independing
top-side
viaon
tenting,
small
areas
ofthe
solder
which
the
solder
placed.
Tenting
thethe
bottom
side
with
solder
mask
to
and
plug
which
the
solder
mask
is
placed.
Tenting
the
bottom
side
with
solder
mask
to
cover
and
plug
the
top-side
via tenting,
small
areas
mask
are placed
overthe
thevia
thermal
vias
onfrom
thethe
toptop
side
ofboard.
viason
can
solder
from
down
and
the
bottom
of
the
In
are placed over
the thermal
thermal
vias
theprevent
top
side of
of solder
the PCB
toflowing
prevent
solderinto
from
flowing
into onto
the
vias
side
of the board.
thermal
vias
can
prevent
solder
from
flowing
down
into
the
and
onto
the bottom
of the
the top
board.
PCB to
prevent
solder
from
flowing
into
thesolder
vias from
the
top
sidevia
of
thethe
board.
top-side
via
tenting,
small
areas
of
mask
are
placed
over
thermal
vias on
sideInof the
top-side
tenting,
small
areas
of solder
mask
are
placed
overside
the of
thermal
vias on the top side of the
PCB tovia
prevent
solder
from
flowing
into the
vias
from
the top
the board.
PCB to prevent solder from flowing into the vias from the top side of the board.
Another
technique
limiting
wicking
using
solder
mask
restrict
flow vias,
of solder
bottom side. One process,
called
tenting,for
uses
soldersolder
mask to
preventinvolves
solder from
either
entering
orto
exiting
thethe
thermal
depending
Figure 8: Tented vias with bottom-side solder mask (not to scale)
Figure
7: Tented vias
withas
bottom-side
solderpractical
mask (notand
to scale)
In general Cree advocates creating
copper-filled
vias
being a more
effective
technique,
preferable
solder-filled
vias. copper-filled vias as being a more practical and effective
In general
Creetoadvocates
creating
In general Cree
advocates
creating copper-filled
vias as being a more practical and effective
preferable
to insolder-filled
vias.to change without
Copyright © 2010-2016 Cree, technique,
Inc. All rights reserved.
The information
this document is subject
notice. Cree and XLamp are registered trademarks and the Cree logo is a trademark of
technique,
preferable
to
solder-filled
vias.
®
2010-02-16
2010-02-16
2010-02-16
Cree Company Confidential
®
Page 6 of 17
Page 6 of 17
Page 6 of 17
6
3
Thermal Performance Simulations
Thermal Performance
Simulations
The following section
presents results obtained from computational thermal analysis for a series of
4
PCB configurations .
This section presents results obtained from computational thermal analysis for a series of PCB configurations.3
3.1
Surface Thermal Dissipation
Surface Thermal Dissipation
The first configuration,
in Figureas
9, shown
consists
a star8,FR-4
PCB with
widths
the varying
thermalwidths
pad and
The firstshown
configuration,
in of
Figure
consists
of a varying
star FR-4
PCBofwith
fortwo
theboard thicknesses
thermal
pad
and
two
board
thicknesses
(0.8mm
and
1.6mm);
the
bottom
copper
layer
is
solid
and
(0.8 mm and 1.6 mm); the bottom copper layer is solid and there are no thermal vias.
there are no thermal vias.
Figure 8: Variation in thermal pad width on top side of PCB
Chart 1
Figure 9: Variation in thermal pad width on top side of PCB
The results shown in Chart 1 show for the 1.6mm-thick board increasing the width beyond 12mm
The analysis results
in Chart
1 show that, for
thefor
1.6-mm
thick board,board,
increasing
the thermal pad
width
provides little
provides
little improvement,
while
the 0.8mm-thick
the improvement
tapers
off beyond
beyond 12 mm
a
width
16mm.
improvement and,
forofthe
0.8-mm thick board, improvement diminishes beyond a 16-mm width.
70.00
FR4 No Vias: Top Trace Size- Solder point through board
FR4 No Vias: Top Trace Size- Solder point through board
Thermal Resistance, Solder point through Board (°C/W)
70
60
50
40
30
20
60.00
1.6mm thick FR4 No Vias
0.8mm thick FR4 No1.6mm
Vias thick FR4 No Vias
50.00
0.8mm thick FR4 No Vias
40.00
30.00
20.00
10.00
0.00
0
10
5
10
15
Length/Width of top trace (mm)
20
25
Chart 1: Thermal resistance for FR-4 PCB with no vias with varying thermal pad size
0
0
5
10
15
20
The next configuration is the same except the board is a MCPCB. Data in chart 2 shows for either
board thickness there is little benefit to extending
the thermal pad width beyond 6mm.
25
Chart 1: Thermal resistance for FR-4 PCB with no vias with varying thermal pad size
The next configuration is the same as the first except the board is an MCPCB. Chart 2 shows there is little benefit to extending the thermal
pad width beyond 6 mm for either board thickness.
4
3
Cree used Ansys Design Space, http://www.ansys.com/products/structural-mechanics/products.asp
Cree used Ansys Design Space, www.ansys.com/products/structural-mechanics/products.asp
2010-02-16
Page 7 of 17
7
Chart 2
MCPCB: Top Trace Size- Solder point through board
5.0
1.6mm thick MCPCB
Thermal Resistance, solder point through Board (°C/W)
4.5
0.8mm thick MCPCB
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Figure 9: FR-4 board with 5 and 15 0.7mm diameter vias and 1mm pitch
0.5
0.0
0
5
10
15
20
25
Chart 2: Thermal resistance for MCPCB with varying thermal pad size
Thermal Dissipation with Vias
Chart 3 shows the effects of various filling materials for 0.7-mm diameter vias with 1-mm center-to-center spacing for both 1.6-mm and
0.8-mm board thicknesses, shown in Figure 10. The analysis data indicate solid copper filled vias result in lower thermal resistance and
unfilled vias deliver higher thermal resistance. A via filled with conductive epoxy performs only slightly better than an unfilled via.
Figure 10: FR-4 board with five and fifteen 0.7-mm-diameter vias and 1-mm pitch
8
Solder
12.00
1.6mm thick FR4 PCB, 5 vias
Copper
10.00
8.00
Conductive Epoxy
14.00
Unfilled
Chart 3: Thermal resistance for FR-4 vias filled with materials Optimizing
of differing conductivity
PCB Thermal Performance
6.00
4.00
2.00
0.00
-25
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
Via Thermal Conductivity (W/mK)
Chart 3: Thermal resistance for FR-4 vias filled with materials of differing conductivity
Chart 4
Chart 4 shows the effect of changing the diameter and number of vias. This chart assumes the vias are filled with SnAgCu solder. As
expected, the larger the diameter of the via, the lower the thermal resistance becomes. Increasing the number of vias shows considerable
improvement for smaller via diameters.
Via Size
Thermal Resistance, solder point through board (°C/W)
30
91 Vias, 1.6mm PCB
91 Vias, 0.8mm PCB
47 Vias, 1.6mm PCB
47 Vias, 0.8mm PCB
15 Vias, 1.6mm PCB
15 Vias, 0.8mm PCB
5 Vias, 1.6mm PCB
5 Vias, 0.8mm PCB
25
20
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Via Diameter (mm)
Chart 4: FR-4 PCB with various via diameters and numbers of vias
9
Figure 10: FR-4 board with varying numbers of thermal vias (2, 6, 8, 14, 58, and 102)
The next case considers the effect of varying the number of thermal vias as shown in Figure 11. These vias are solid-plated copper with
a diameter of 0.254 mm (0.010 in.) and center-to-center spacing of 0.635 mm (0.025 in.). The results in Chart 5 indicate that increasing
the number of vias beyond fourteen shows little improvement. (This is the maximum achievable density of the area normal to the LED
thermal pad.)
Chart 5
Figure 11: FR-4 board with varying numbers of thermal vias (2, 6, 8, 14, 58, and 102)
Filled Via Count: Ø10mil, 25.4mil pitch
20
1.6mm thick FR4 PCB
0.8mm thick FR4 PCB
1.6mm MCPCB
0.8mm MCPCB
18
16
14
12
10
8
6
4
2
0
0
20
40
60
# of Filled Copper Vias
80
100
120
Chart 5: Thermal resistance values FR-4 board for varying numbers of copper-filled thermal vias
Combined Surface and Via Studies
The next configuration is an FR-4 PCB with fourteen 0.254-mm diameter copper plated vias with the thermal pad widths shown in Figure
12. The bottom copper layer is solid. The data in Chart 6 show that, beyond a 6-mm width, there is little improvement in thermal resistance.
10
Figure 11: FR-4 PCB with 14 thermal vias and varying top thermal pad widths
(3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm)
Chart 6
Figure 12: FR-4 PCB with 14 thermal vias and varying top thermal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm)
FR4 14 vias: Top Trace Size- Solder point through board
9
1.6mm thick FR4 PCB
8
0.8mm thick FR4 PCB
7
6
5
4
3
2
1
0
0
5
10
Trace Width (mm)
15
20
25
Chart 6: Thermal resistance of FR-4 PCB with 14 vias and varying thermal pad widths
Finally, the previous scenario is repeated with the bottom thermal pad widths shown in Figure 13. The results, shown in Chart 7, indicate
that there is a small difference in thermal resistance that decreases as the width of the bottom pad increases.
11
Figure 12: FR-4 PCB with 14 thermal vias and varying bottom thermal pad widths
(3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm)
Chart 7
Figure 13: FR-4 PCB with 14 thermal vias and varying bottom thermal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm)
FR4 14 vias: Top + Bottom Trace Size- Solder point through board
10
Full Backside & Changing Frontside_ 1.6mm PCB
Full Backside & Changing Frontside_ 0.8mm PCB
Changing Back & Frontside, 1.6mm PCB
Changing Back & Frontside, 10.8mm PCB
9
8
7
6
5
4
3
2
1
0
0
5
10
15
Top + Bottom Trace Width (mm)
20
25
Chart 7: Thermal resistance of FR-4 PCB with 14 vias and varying top and bottom thermal pad widths
Summary Results of Thermal Simulations
1. The results from the various simulations show that the dielectric thickness should be 0.8 mm to achieve the lowest possible thermal
resistance for an FR-4 board.
12
2. Although making the vias as large as possible reduces thermal resistance, the cost of manufacturing the board must also be
considered. Larger unfilled vias introduce the possibility of the vias becoming partially filled during the soldering process. Smaller,
closely spaced vias are a better solution.
3. Finally, adding additional vias and increasing the width of the thermal pad beyond a certain point have diminishing returns because
of thermal spreading resistance.
Based on these conclusions, on page 15 Cree recommends an optimal thermal pad size, via size and spacing that is both thermally
effective and manufacturable.
Temperature Verification Measurements
Because LED junction temperature affects LED lifetime, Cree recommends performing a thermal verification test on the LED-board
assembly under real-life conditions.4
Figure 13: Thermocouple placement
This section illustrates practical LED board thermal measurement using thermocouples, which offers some corroboration for the
simulations on which we base our recommendations.
Figure 14 shows a type-K thermocouple attached to the top copper layer close to the thermal pad. The solder mask (if present) should
be removed to solder the thermocouple to the board. Alternately the thermocouple can be attached using a thermal epoxy or aluminum
tape. If more than one LED is on the board, the lamp with the highest expected temperature should be selected. Another thermocouple
is attached to the back of the heat sink using thermal epoxy. A third thermocouple is used to measure the ambient (air) temperature.5
The thermocouple wires are held in place with Kapton® tape. To calculate the actual heat sink to ambient thermal resistance, divide the
difference between Ths and Ta by the power of the heat source.
Ths1
Tc
Ths2
Figure 14: Thermocouple placement
Table 6 below contains data from five sets of five XLamp XP-E LEDs mounted on star boards. The first four sets are 1.6-mm thick
FR-4 boards with via layouts similar to Figure 12 and Figure 13 with 10-mm wide bottom thermal pads; the last set is 1.6-mm thick
aluminum clad boards. The PCBs were mounted to a heat sink with thermal adhesive.6 Measurements of the forward voltage (Vf) and
4
5
6
Normally the junction temperature cannot be measured directly and must be derived from the temperature measured at a reference point on the top copper layer.
At least 2 mm away from the heat sink and/or illumination source and not in the path of illuminance.
Aavid Thermalloy part number 374424B00035G, with Chomerics THERMATTACH® T411 thermal tape for FR-4; CTS Electronics part number BDN10-5CB/A01for MCPCB
13
case temperature (Tc) were taken at 700 mA (If) at an ambient temperature of 20 ºC (Ta). With these measurements, the power (P), PCB
thermal resistance (θpcb), case to ambient thermal resistance (θca), and heat sink to ambient thermal resistance (θhs-a) can all be calculated
per the following equations.
P = If * Vf
(6)
θpcb = (Tc - Ths) / P (7)
θca = (Tc – Ta) / P
(8)
θpcb = (Ths – Ta) / P (9)
Table 6: PCB temperature measurements
Board
If
(A)
Vf
(V)
Power
(W)
Tc
(°C)
Ths
(°C)
Ta
(°C)
θpcb
(°C/W)
θca
(°C/W)
θhs-a
(°C/W)
1 oz. #1
0.700
3.31
2.32
69.64
45.73
22.0
10.32
20.57
10.25
1 oz. #2
0.700
3.26
2.28
70.29
48.03
22.0
9.75
21.16
11.40
1 oz. #3
0.700
3.21
2.24
65.37
44.02
22.0
9.51
19.33
9.81
1 oz. #4
0.700
3.22
2.25
66.34
47.65
22.0
8.30
19.69
11.39
1 oz. #5
0.700
3.25
2.28
65.77
45.15
22.0
9.06
19.23
10.17
2 oz. #1
0.700
3.32
2.32
71.69
48.19
22.0
10.12
21.41
11.28
2 oz. #2
0.700
3.34
2.34
68.60
45.34
22.0
9.96
19.95
9.99
2 oz. #3
0.700
3.26
2.28
66.95
46.33
22.0
9.04
19.71
10.67
2 oz. #4
0.700
3.34
2.34
66.36
44.37
22.0
9.39
18.95
9.56
2 oz. #5
0.700
3.35
2.35
67.57
45.19
22.0
9.54
19.43
9.89
2 oz. filled #1
0.700
3.36
2.35
67.19
44.39
22.0
9.69
19.20
9.51
2 oz. filled #2
0.700
3.33
2.33
67.48
45.11
22.0
9.59
19.51
9.92
2 oz. filled #3
0.700
3.28
2.30
68.06
44.92
22.0
10.08
20.07
9.99
2 oz. filled #4
0.700
3.29
2.30
66.70
44.86
22.0
9.50
19.44
9.94
2 oz. filled #5
0.700
3.37
2.36
70.03
47.87
22.0
9.39
20.35
10.96
4 oz. #1
0.700
3.31
2.32
64.35
45.80
22.0
7.99
18.25
10.26
4 oz. #2
0.700
3.34
2.33
68.31
48.75
22.0
8.38
19.83
11.46
4 oz. #3
0.700
3.39
2.38
71.87
50.41
22.0
9.03
20.99
11.96
4 oz. #4
0.700
3.26
2.28
66.63
47.87
22.0
8.22
19.54
11.32
4 oz. #5
0.700
3.33
2.33
68.12
48.55
22.0
8.40
19.80
11.40
MCPCB #1
0.700
3.36
2.35
63.20
53.20
20.0
4.25
18.37
14.12
MCPCB #2
0.700
3.04
2.13
57.60
50.90
20.0
3.15
17.67
14.52
MCPCB #3
0.700
3.36
2.35
57.90
50.10
20.0
3.32
16.11
12.80
MCPCB #4
0.700
3.35
2.35
62.00
51.20
20.0
4.61
17.91
13.30
MCPCB #5
0.700
3.37
2.36
60.10
51.30
20.0
3.73
17.00
13.27
Avg. θpcb
(°C/W)
Avg. θca
(°C/W)
Avg.
θhs-a
(°C/W)
9.39
19.99
10.60
9.61
19.89
10.28
9.65
19.71
10.06
8.40
19.68
11.28
3.81
17.41
13.60
14
The results are close to the predicted performance in Chart 2 (which indicates a thermal resistance asymptote of about 3.5 ºC/W for an
MCPCB) and Chart 7 (which shows a fourteen-via 1.6-mm FR-4 board with a thermal resistance of about 8 ºC/W for a 0.254-mm diameter,
2-oz. plated via).7
Recommended Board Layouts
Cree recommends creating areas of 10-mil (0.254-mm) vias arranged on a 25-mil (0.635-mm) rectilinear grid. The reason for this choice
is the combination of cost, performance and manufacturability. According to several PCB manufacturers, 10-mil holes and 25-mil spacing
are reasonable and repeatable production choices when used with a 2-oz. plating solution.
When using multiple LEDs, tighter spacing between emitters results in increased heating. The thermal pads can be connected together
and additional copper can be added, if possible.
The following sections illustrate minimum recommended pad sizes for the XT, XP, XB, MX and ML packages.
Gerber files
For the ML, MX, XB, XP and XT families of LEDs, Cree revised the Gerber files for a star-shaped, single LED circuit board to include via
drilling specifications. The Gerber files are .zip archives posted on Cree’s website in the Design Files area of the product pages for each
of the XT, XP, XB, MX and ML products.8
7
8
In general, thermal measurement of LEDs is challenging and there are chances for error due to the number of variables involved. Thermocouple placement and subsequent
calculations are but two of the concerns. We use these results for their suggestive value rather than their definitive result.
At the Products page, select the LED of interest then select the Documentation tab.
15
Application Note: CLD-AP37 AN_100302^rev1 draft5-20110404 (2).docx rev 1.4
Application Note: CLD-AP37 AN_100302^rev1 draft5-20110404 (2).docx rev 1.4
5.1
FR-4 boards for XLamp XP package
FR-4 boards
forLED
XLamp
XP package
FR-4 Boards5.1
for XLamp
XP and XT
Packages
Dashed line represents optional
Dashedthermal
line represents
optional
10-mm
pad
10-mm thermal pad
Figure 14: Recommended footprint for XLamp XP family of LEDs on FR-4 PCB (top and bottom)
Figure 14: Recommended footprint for XLamp XP family of LEDs on FR-4 PCB (top and bottom)
Figure 15: Recommended footprint for XLamp XP and XT family of LEDs on FR-4 PCB (top and bottom)
2011-04-07
2011-04-07
Page 15 of 18
Page 15 of 18
16
FR-4 Boards for XLamp XB LED Package
XB-D FR4: Minimum Vias (5)
Copyright © 2011, Cree, Inc.
Cree Proprietary & Confidential
pg. 1
XB Back side: Minimum Vias (5)
pg. 2
Figure 16: Minimum footprint for XLamp XB family of LEDs on FR-4 PCB (top and bottom)
17
XB-D FR4: Optional Vias (11)
pg. 3
XB Back side: Optional Vias (11)
pg. 4
Figure 17: Recommended footprint for XLamp XB family of LEDs on FR-4 PCB (top and bottom)
18
Application
Note:
CLD-AP37
AN_100302^rev1
draft5-20110404
(2).docx
rev 1.4
Application
Note:
CLD-AP37
AN_100302^rev1
draft5-20110404
(2).docx
rev 1.4
5.2 5.2
FR-4
boards
MX MX
package
FR-4
boards
for
XLamp
package
FR-4 Boards
for
XLamp
MX for
LEDXLamp
Package
18: Recommended
footprint
XLamp
MXpackage
package
on
PCB
(top(top
and and
bottom)
Figure
15: Recommended
footprint
for XLamp
MX package
on FR-4
PCB
(top
and
bottom)
Figure
15:Figure
Recommended
footprint
for for
XLamp
MX
onFR-4
FR-4
PCB
bottom)
2011-04-07
2011-04-07
Cree Cree
Company
Confidential
Company
Confidential
PagePage
16 of16
18of 18
19
Application
Application Note:
Note: CLD-AP37
CLD-AP37
AN_100302^rev1
AN_100302^rev1 draft5-20110404
draft5-20110404 (2).docx
(2).docx rev
rev 1.4
1.4
5.3
FR-4
for
XLamp
ML
5.3Boards
FR-4
boards
forLED
XLamp
ML package
package
FR-4
forboards
XLamp ML
Package
Figure 19: Recommended
footprint
for XLamp
ML package
FR-4 PCB
PCB
andand
bottom)
Figure
footprint
XLamp
ML
on
(top
bottom)
Figure 16:
16: Recommended
Recommended
footprint for
for
XLamp
ML package
package
ononFR-4
FR-4
PCB(top
(top
and
bottom)
66
Chemical
Chemical compatibility
compatibility
ItIt is
is important
important to
to verify
verify chemical
chemical compatibility
compatibility when
when selecting
selecting the
the interface
interface materials
materials to
to use
use between
between the
the
board
board and
and the
the heat
heat sink,
sink, as
as well
well as
as other
other materials
materials to
to which
which the
the LEDs
LEDs can
can be
be exposed.
exposed. Certain
Certain materials
materials
from
from FR-4
FR-4 board
board fabrication
fabrication and
and assembly
assembly processes,
processes, e.g.,
e.g., adhesives,
adhesives, solder
solder mask
mask and
and flux
flux residue,
residue, can
can
outgas
outgas and
and react
react adversely
adversely with
with the
the materials
materials in
in the
the LED
LED package,
package, especially
especially at
at high
high temperatures
temperatures when
when
aa non-vented
non-vented secondary
secondary optic
optic is
is used.
used. This
This interaction
interaction can
can cause
cause performance
performance degradation
degradation and
and product
product
2011-04-07
2011-04-07
Cree
Cree Company
Company Confidential
Confidential
Page
Page 17
17 of
of 18
18
20
Chemical Compatibility
It is important to verify chemical compatibility when selecting the interface materials to use between the board and the heat sink, as
well as other materials to which the LEDs can be exposed. Certain materials from FR-4 board fabrication and assembly processes,
e.g., adhesives, solder mask and flux residue, can outgas and react adversely with the materials in the LED package, especially at high
temperatures when a non-vented secondary optic is used. This interaction can cause performance degradation and product failure. Each
family or individual LED product has an application note identifying substances known to be harmful to Cree LEDs.10 Consult your PCB
manufacturer to determine which materials it uses.
References
Electronics Cooling, September 1997, Vol.3, No.3, “Calculation Corner: One-dimensional heat flow” Bruce M. Guenin, Ph.D., Associate
Editor
Electronics Cooling, May 1998, Vol.4, No.2, “Calculation Corner: Conduction heat transfer in a printed circuit board” Bruce M. Guenin, Ph.D.,
Associate Editor
Electronics Cooling, August 2004, Volume 10, Number 3, “Calculation Corner: Thermal Vias – A Packaging Engineer’s Best Friend”, Bruce
M. Guenin, Ph.D., Associate Editor
“Thermal and High Current Multilayer Printed Circuit Boards With Thermagon T-lam and Hybrid Boards” January 31, 2001, Thermagon,
Inc., Courtney R. Furnival
“Thermal Considerations for QFN Packaged Integrated Circuits” AN315 rev 1, July 2007, Cirrus Logic, Inc.
10
XT Family LEDs Soldering & Handling
XP Family LEDs Soldering & Handling
XB Family LEDs Soldering & Handling
MX Family LEDs Soldering & Handling
ML Family LEDs Soldering & Handling
21

Optimizing PCB Thermal Performance for Cree XLamp LEDs

Transcription

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