Extraction and Simulation of Complex Silicon Interposer Structures

Extraction and Simulation of Complex Silicon Interposer Structures

Extraction and simulation of complex
silicon interposer structures with
measurement correlation
11/15/2012
Sooyong Kim
Area Technical Manager
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© 2012 ANSYS, Inc.
November 19, 2012
Apache
Design,a asubsidiary
subsidiary of
of ANSYS
Apache
Design,
Project Background
• Interest in tool arose from experience supporting electrical power distribution in 3D
IBM interposer module
– Simple model (two pins) vs. entire interposer
– Difficulties in model extraction (Several tools)
– Large run times/capacity issues even for simple models
– No direct IR drop data across interposer
– No direct dynamic simulations
– Strategic tool for future 3D designs
• Redhawk from Apache team in Ansys for interposer/chip carrier electrical analysis &
3D modules
– IR drop (DC analysis/ EM analysis)
– Dynamic (Transient analysis)
– Power model extraction (SPICE parasitic model, CPM )
– Point to point resistance Check
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Apache Power and Noise Platforms
PowerTheater / PowerArtist
RPM (RTL Power Model)
 Activity, cycle-to-cycle
 Block power
Totem
RedHawk
CMM (Custom Macro Model)
 Hierarchical model
 IP protection
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© 2012 ANSYS, Inc.
November 19, 2012
Sentinel
CPM (Chip Power Model)
 Distributed RLC, current
 Power, signal, EMI, thermal
Apache Design, a subsidiary of ANSYS
Chip/Chip Carrier/Package Software
Tool A
Tool C
Tool B
• Apache software addresses entire module (Tool A)
• Packaging level software (Tool B)
• Chip level software (Tool C)
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Initial Test Cases
• Hendrix (200mm) and Beyonce (300mm) silicon interposer test vehicles
• Same design – different cross section & TSVs
• Four identical quadrants for 4 chips
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Beyonce Design (Top Right) & Pins For Measurements
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1
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© 2012 ANSYS, Inc.
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November 19, 2012
Apache Design, a subsidiary of ANSYS
Beyonce DC resistance measurements*
E
D
A
B
C
interposer position
A
B
C
D
E
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0.737
0.725
0.646
0.710
0.673
Tool used
Tool #
cal date
cal due
Keithley 2700
1076534
2012-04-03
2013-04-03
tested net (ohm)
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2
2.000
0.213
2.028
0.214
2.059
0.221
2.060
0.218
0.227
2.083
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2.079
2.127
2.150
2.150
2.183
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0.786
0.805
0.859
0.815
0.830
* From J. Audet
Tested interposer location
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Redhawk to Measurements Comparison
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Redhawk
(Ohms)
Measured
(Ohms)
Difference
(Ohms)
0.566
0.673
- 0.107
1.879
2.083
- 0.204
0.336
0.227
+0.109
1.976
2.183
- 0.207
0.884
0.830
+0.054
© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Redhawk Dynamic Simulations
PAD current at VDD
• No need for separate tool for static vs. dynamic
• Graph shows effect of having decaps vs no caps on interposer
• Die Power Model ( CPM ) created , open spice format
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Pad voltage at VDD
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Hendrix Small Test Case Details
• Results for dynamic simulation
• Name and size of gds/lef file: hendrix_vdd_grn.gds (28KBytes),
hendrix_3_18_09.def (8.3MBytes)
• Machine run: bucksport (Linux64) in IBM EFK
• Linux OS: Redhat v5.2
• Processor: AMD Opteron 252 - 2 2.6 GHz
• Total physical memory: 10G
• Run time used by Redhawk: 8 mins 0 secs.
• Memory used by Redhawk: 1.324 GBytes
• Diskspace used by Redhawk: 362 Mbytes
• Improvement in model size/run time vs. existing
8 mins vs. 1 week runtime
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Hendrix/Beyonce Large Test Case Details
• Results for dynamic simulation
– (static simulation a bit smaller than this)
• Name and Size of gds file: hendrix_mike.gds (2.48M),
hendrix_3_18_09.def (3G)
• Machine run: ae256 Linux64 in Ansys CA
• Linux OS: Redhat v5.2
• Processor: AMD Opteron 6128HE 4 – 2.0GHz
• Total Physical memory: 256G
• Run time used by Redhawk: 45 hrs 42 mins 20 secs
• Memory used by Redhawk: 48.2G
• Diskspace used by Redhawk: 14G
– Beyonce test case (a bit larger): 69G memory and 68
hrs run time
• Tool can handle large data volumes but large run
times/memory requirements
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© 2012 ANSYS, Inc.
November 19, 2012
Static DC/EM analysis
Dynamic analysis
CPM ( Chip Power
model generation ) in
one shot
Apache Design, a subsidiary of ANSYS
Simplified User Experience
Multi-pane, Multi-canvas Based Power Analysis
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13 © 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Enabling 3D/2.5D Designs
 Shared P/G network and SSN in multiple designs
 Needs simultaneous multi-die simulation for shared noise
Concurrent analysis:
(a) Full-layout visibility of all IC / interposer
(b) hierarchical capacity
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© 2012 ANSYS, Inc.
November 19, 2012
Model based analysis:
(a) Inclusion of CPM for some dies
(b) Interposer modeling
Apache Design, a subsidiary of ANSYS
Model Based CPS Convergence
Global PDN
view
R Metal
Leaf Tx
On die
Decap
SoC Designers
view
in RedHawk
On die
Decap
PCB Designers
view
in Sentinel
R PCB
VRM
On Board
decap
PCB/Pkg RLC,
S parameter
From Sentinel
C4 PG Bump
R Pkg
From RedHawk
L PKG
C Pkg
L Metal
C Metal
CPM
R Pkg
C4 PG Bump
C Metal
R Metal
Leaf Tx
L Metal
C4 PG Bump
L PCB
C Pkg
R PCB
VRM
On Board
decap
Only Common reference point
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
What is CPM?
 Chip on-die Power Grid RLC
Apache
 Transistor current/cap/ESR
 Open SPICE netlist format
 Multi-domain, distributed model
 DC to multi-GHz validity
 Advanced chip excitation modes
 Silicon correlated
Package/Board
Model
System
Houses
ASIC
Vendors
Chip Power
Model
Apache Ecosystem
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
What is CPM?
CHIP DATA
Layout
Library
(Early to Sign-off)
CHIP ANALYSIS
Dynamic
VCD
Static
Dynamic
VectorLess
Chip Power Model
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© 2012 ANSYS, Inc.
November 19, 2012
Modes
Static (Iavg, R)
Frequency domain (RLC)
Time-domain (I(t), RLC)
Apache Design, a subsidiary of ANSYS
CPM Benefits Against Traditional Models
Traditional die model
Apache
Traditional CPM™
Die Model
Chip Parasitics
Chip Current
RedHawk (SoC)
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© 2012 ANSYS, Inc.
Layout
Library
Chip Power Model
 RLC reduction: billions of
parasitics to thousands of Spice
elements
Single Lumped Model
November 19, 2012
 Distributed with full couplings
Apache Design, a subsidiary of ANSYS
Multi-die Analysis Framework
Memory
Logic
Silicon
Interposer
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS
Apache Design Inc. ( Subsidiary of Ansys )
www.apache-da.com
www.ansys.com
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© 2012 ANSYS, Inc.
November 19, 2012
Apache Design, a subsidiary of ANSYS