Agenda - October 17th, 2013 - Park Hilton, Munich

Agenda - October 17th, 2013 - Park Hilton, Munich

2013
- EUROPE -
Agenda - October 17th, 2013 - Park Hilton, Munich, Germany
Registration & Coffee
08:00 - 08:55
08:55 - 09:05
Welcome - Matthias Knoppik, Area Director Central Europe, Mentor Graphics - Room: Ballroom
09:05 - 09:50
Keynote: The Big Squeeze - Wesley Ryder, Worldwide Technical Director, Mentor Graphics - Room: Ballroom
09:50 - 10:20
Keynote: Energy Efficiency Enabled by Innovative Semiconductor Solutions - Arunjai Mittal, Member of the Management Board, Infineon Technologies - Room: Ballroom
Coffee Break
10:20 - 10:50
IC (CALIBRE) Track
IC DESIGN Track
PCB DESIGN Track 1
PCB DESIGN Track 2
FUNCTIONAL VERIFICATION Track 1 FUNCTIONAL VERIFICATION Track 2
Room: Salon van Gogh
Room: Salon Picasso & Dali
Room: Ballroom B+C
Room: Ballroom A
Room: Salon Rumford
10:50 - 11:40
Calibre physical verification platform:
Your design deserves Calibre
confidence
Mentor Graphics
Automotive, increasing embedded IP
and large SOC designs are driving
manufacturing test methodologies
Mentor Graphics
Sketch Router: A Revolutionary New Routing Method
Mentor Graphics
Verification Today, Tomorrow and Beyond Tomorrow
Mentor Graphics
(Salon Rumford)
11:40 - 12:20
Framework for layout constraint
compliance checking
Infineon and Bosch, Germany
Using DFM Techniques in ATPG Pattern
generation
CSR, UK
Design Rule Checks für ein
EMV-sicheres Baugruppen Design
brightONE Embedded Systems, Germany
Get started with the UVM Register
Layer
Doulos, UK
Virtualab: Family of Virtual Device
Solutions
Mentor Graphics
13:20 - 14:00
New approach for voltage-dependent
metal spacing checks
STMicroelectronics, Italy
Creating an MBIST flow with IJTAG
Wolfson Microelectronics plc, UK
Wie viel Theorie verträgt die Praxis? Signal
and Power Integrity Simulation mit
HyperLynx als “Theorie”, High Speed PCB
Design mit Expedition PCB als “Praxis
Harman, Germany
A simple board with a few mezzanine
boards
RUAG Space AB, Sweden
PowerAware simulations using UPF
files for beginners
Sondrel, UK
Introduction of Formal Verification
Methods at Dr. J. Heidenhain
Dr. J. Heidenhain, Germany
14:00 - 14:40
Using Calibre PERC for Circuit
Reliability Verification
TowerJazz, Israel
Use of Olympus in the design of a large
28nm design
Sondrel, UK
Einführung der Expedition Enterprise
Designkette in der Verteidigungselektronik bei Cassidian
Cassidian
Rework or start from scratch?
P-C-D, UK & ARM, UK
A Verification Framework for Fault
Injection using Questa for Automotive
Applications
Infineon, Germany
Formal Verification using „Questa
formal“ at EADS Astrium GmbH – an
experience report
EADS Astrium GmbH, Germany
Analogue and Digital Layout vs.
Schematic using the Hyperlynx Tools
Astrium, UK
Room: Salon Matisse
Lunch
12:20 - 13:20
14:40 - 15:00
Coffee Break
15:00 - 15:40
DFM Scoring and Correction with MAS
and YES
GlobalFoundries, Germany
Advanced System Integration Using
Silicon Interposers
Fraunhofer IIS/EAS
Die perfekte Welle
Signalintegrität für Layouter
Diehl BGT Defence, Germany
A global approach to design high speed
complex digital systems
Link Engineering, Italy
QVIP Randomization Layer for AMBA4
Coverage Closure
ARM, UK
Calibrating Analogue Designs with ECL
Atmel, Norway
15:40 - 16:20
TowerJazz to support Pyxis design
environment using iPDK
TowerJazz, Israel
Using P1687 for IP and pattern reuse
methodology for manufacturing test
Mentor Graphics
Mentor Graphics User Group Meeting:
Neuigkeiten aus den Regionalgruppen
& Erfahrungsaustausch unter Usern
Differential Signal Routing for
PCB Designers
Mentor Graphics
A Metric Driven Verification and
Validation Approach for Smart Power
Devices
Infineon, Austria & TU Vienna
Mixed-signal verification methodology
experience in the automotive
microcontroller project "Aurix"
Epos, Germany
16:20 - 16:30
Closing & Prize Draw & Exhibition - Room: Ballroom
Directly after the Conference: Get together - Restaurant Marco Polo, 15th floor, 16:30 - 21:00