INTERCONNECT APPLICATION NOTE Z-PACK HM-Zd PWB Footprint Optimization for Routing

Transcription

INTERCONNECT APPLICATION NOTE
Z-PACK HM-Zd
PWB Footprint Optimization for Routing
Report # 20GC015-1, Rev. B
July 10, 2003
 Copyright 2003 Tyco Electronics Corporation, Harrisburg, PA
All Rights Reserved
C&D REPORT #20GC015-1, Rev. B : Z-PACK HM-Zd, PWB Footprint Optimization for Routing
Table of Contents
Item
Page #
I.
INTRODUCTION..........................................................................................................1
II.
Z-PACK HM-Zd ............................................................................................................3
III.
CONNECTOR FOOTPRINT.......................................................................................4
A. Dimensions ................................................................................................................4
B. Fabrication Technology .............................................................................................5
1. Pad Size................................................................................................................6
2. Antipad Size.........................................................................................................6
3. Non-functional Pads.............................................................................................11
IV.
SUMMARY ....................................................................................................................12
V.
ADDITIONAL INFORMATION.................................................................................13
A. Z-PACK HM-Zd........................................................................................................13
B. Gigabit Research & General Application Notes ........................................................13
C. Electrical SPICE Models ...........................................................................................13
VI.
CONTACT INFORMATION.......................................................................................13
A. Tyco Electronics ........................................................................................................13
B. Communications Circuits & Design ..........................................................................14
VII.
REVISION HISTORY ..................................................................................................15
The information contained herein and the models used in this analysis are applicable solely to the specified AMP connector. Alternative
connectors may be footprint-compatible, but their electrical performance may vary significantly, due to construction or material characteristics.
Usage of the information, models, or analysis for any other connector is improper, and AMP disclaims any and all liability or potential liability
with respect to such usage.
I.
INTRODUCTION
The transmission of serial gigabit data is helping to drive the development of new industry
standards aimed at increasing aggregate bandwidth. At gigabit speeds the entire system
interconnect needs to be properly considered and designed. Tyco Electronics Corporation (TEC)
has been active in researching the role of the connector in the system interconnect intended to
support gigabit data transmission. In its research TEC has demonstrated that traces in a PWB
environment are capable of handling speeds up to 10 Gb/s. Furthermore, TEC has looked at the
connector / board interface in an effort to understand the discontinuity associated with the
connector. This research allowed TEC to demonstrate a backplane-style interconnect capable of
supporting 5 Gb/s and 10 Gb/s serial links. See Gigabit Research & General Application Notes
on Page 13.
TEC’s research has shown the complexity in developing interconnect topologies capable of
supporting serial gigabit data transmission. Intelligent system architects are employing
techniques to overcome this complexity. There are two main techniques being used. The first
technique compensates for losses associated with the interconnect, using either pre-emphasis at
the transmitter (using either passive or active components) or equalization at the receiver. The
second technique encodes or “conditions” the data in a manner that compensates for the
interconnect. With the introduction of these techniques, the interconnect has progressed from a
passive state to an active state. Figure 1 provides a useful diagram that shows the evolution of
the interconnect.
S
P
E
E
D
V
a
r
i
a
b
l
e
Design Considerations
• Equalization
• Encoding Techniques
• Pre-emphasis
Semiconductors
Board Interface
Other Considerations
• Board Materials
• Trace Length
• Differential Trace Coupling
Connector
F
i
x
e
d
• Frequency Response
• Impedance
DI
• Cross Talk
• Skew
N
• Propagation Delay
• Routing
• Footprint Noise
• Anti-pads
• Trace Width
• Trace Space
Passive
Active
TYPE OF INTERCONNECT
Figure 1 – Evolution of the System Interconnect
Tyco/Electronics
Circuits & Design
PAGE 1
July 10, 2003
Based on the options available to system designers, it is easy to see the difficulty in determining
how “fast” a connector can operate. A connector has specific physical characteristics that
influence the design of the interconnect and specific electrical characteristics that influences the
performance of the interconnect. Nonetheless, the connector is still only part of the overall
system. It is possible to improve the performance of the overall system by simply using better
PWB materials or semiconductor devices that employ advanced signaling techniques.
This paper focuses on providing the designer with guidelines for optimizing the PCB footprint of
the Z-PACK HM-Zd connector. These guidelines have been developed to optimize system
performance.
Tyco/Electronics
Circuits & Design
PAGE 2
July 10, 2003
II.
Z-PACK HM-Zd
Figure 2 – Z-PACK HM-Zd
The Z-PACK HM-Zd connector is a member of the Z-PACK 2mm HM family. It is fully
compatible with 2mm HM Equipment Practice, including all Z-PACK 2mm HM hardware and
accessories. There are currently three basic signal module configurations – a 2 differential pair
per signal column configuration, a 3 differential pair per signal column configuration and a 4
differential pair per signal column configuration. The 2 and 3 pair configurations yield 20 and 30
pairs per 25 mm respectively, and support a 0.8” slot pitch. The 4 pair configuration yields 40
pairs per 25 mm, and supports a 1” slot pitch. In addition to the basic signal modules the breadth
of product line includes high speed cable assemblies, right angle pin headers for coplanar
applications and vertical receptacles for mezzanine applications. Figure 2 shows a system based
on HM-Zd 4 pair modules.
Understanding the use of connectors in real system environments has permitted TEC to develop
a connector that maximizes performance and density. The Z-PACK HM-Zd has been specifically
designed for high-speed differential applications, and can support system speeds up to 6.25
Gigabits per second and beyond. Dedicated L-shaped ground blades reduce connector noise at
the mating interface while eliminating the need to assign “ground” to signal pins, which would
reduce the effective density of the connector. Careful consideration has been given to the design
of the connector to minimize noise created in the connector and in the PCB footprint. For more
information regarding the HM-Zd, please contact TEC via email at hmzd@tycoelectronics.com.
Tyco/Electronics
Circuits & Design
PAGE 3
July 10, 2003
III. CONNECTOR FOOTPRINT
A. DIMENSIONS
Full mechanical dimensioning and tolerances are available for all versions of the HM-Zd
connector. See Section V.A on page 13 for details. The dimensions critical to routing of the
HM-Zd are related to the hole pattern, or “footprint”, of the connector. Figure 3 shows the
dimensions for the HM-Zd receptacle. Figure 4 shows the dimensions for the HM-Zd
header. All dimensions within the footprint are identical for both the backplane (header)
and daughter card (receptacle) components. Both signal and ground pins have identical hole
sizes. Table 1 summarizes critical connector hole dimensions for the circuit board.
Manufacturing dependant dimensions are discussed later in this document.
Figure 3 –Receptacle Dimensions (4 Pair)
Tyco/Electronics
Circuits & Design
PAGE 4
July 10, 2003
Figure 4 – Header Dimensions (4 Pair)
Hole Dimension
Drill Hole Size
Finished Hole Size
Diameter
Mm (in.)
0.70 + 0.025
(0.0276+ 0.001)
0.60 + 0.05
(0.024+ 0.002)
Table 1 – Connector Hole Dimensions
B. FABRICATION TECHNOLOGY
Other important dimensions for board layout are determined by the capabilities of the circuit
board fabricator. Current high-tech PCB industry fabrication technology (i.e. capability)
requires minimum pad sizes ranging from D+10 mils through D+18 mils, where “D” is the
diameter of the drilled hole size (1 mil is 0.0254mm (0.001”)). For the HM-Zd connector
this results in minimum pad sizes ranging from 0.96mm (0.038”) to 1.16mm (0.046”). These
resultant pads are the minimum pad sizes required to maintain 0.05mm (0.002”) of annular
ring for a given PCB manufacturer’s capability. Annular ring is an industry standard
measure of the clearance between the pad edge and worst-case drill edge after
manufacturing. Because the HM-Zd is typically used in high speed or dense applications
where routing issues are most significant, all pad dimensions in this document will assume a
D+12 mil pad size, or 1.02mm (0.040”) pad, unless otherwise specified. The pad diameter
Tyco/Electronics
Circuits & Design
PAGE 5
July 10, 2003
may be optimized for specific project needs, and should be evaluated on a project and
vendor basis. Designing with a D+10 mil technology PCB could mean reduced yields or
breakout, potentially adding cost to the PCB or violating industry specification compliance.
Note: A minimum pad to trace clearance of 0.13mm (0.005”) will also be assumed for
calculating routing dimensions.
1. PAD SIZE
Based upon the D+12 mil fabrication technology assumption, a 1.02mm (0.040”)
diameter pad should be used with all HM-Zd connector pins. For very high-tech PCBs
(D+10 mil) the pad is 0.97mm (0.038”). In some cases the reduced manufacturability of
a D+10 mil technology PCB is required to reduce pad sizes, although potentially
reduced yields or breakout may add cost to the PCB. Where possible the largest
appropriate pad size should be used to provide the PCB manufacturer with the greatest
flexibility, thereby reducing overall system costs.
Thermal reliefs are not required on ground or power pins, because the HM-Zd connector
uses press-fit technology. A direct connection to reference and power planes will offer
the lowest inductance connection to the circuit board.
2. ANTIPAD SIZE
Antipads, or plane clearances (see Figure 5), are required to separate signal holes from
reference voltages to avoid shorting. Choosing the proper size of these clearances is
critical in determining several other design parameters: signal integrity, EMI, voltage
breakdown, and manufacturability. The antipad for the HM-Zd is limited to a minimum
of 1.27mm (0.050”) due to manufacturability to a maximum dimension that is
determined by the differential trace geometry that will be routed through the connector
pinfield. A minimum antipad should be at least 0.25mm (0.010”) in diameter larger than
it associated pad.
Via
Pad
Trace
Plane
Antipad
Figure 5 – Trace, Via, and Antipads in Plane
Tyco/Electronics
Circuits & Design
PAGE 6
July 10, 2003
Determining the proper antipad size depends upon system design goals.
Antipad sizes are minimized:
• To reduce noise by closely shielding adjacent vias with reference planes
• To reduce EMI by minimizing aperture sizes in reference planes
• To maintain a strong reference to ground for single-ended signals and ground
referenced differential signals
Antipad sizes are maximized:
• To maximize voltage breakdown spacing between the pin and the reference plane
• To increase manufacturability by reducing the chance of shorting.
• To reduce reflections in a high speed gigabit serial system by reducing the
capacitive effect of the plated through-hole.
Figure 6 shows the implementation of a differential antipad on a ground plane layer for
the HM-Zd receptacle which would typically reside on a daughtercard. Figure 7 shows
the implementation of a differential antipad on a ground plane layer for the HM-Zd
header which would typically reside on the backplane. The width of the antipad is
limited to 3.48 mm (0.137”) by the adjacent ground pins in the signal column. The
antipad width should be appropriately reduced if vertical routing in the pinfield is
required, in order to provide sufficient ground coverage for signals, or if manufacturing
technology varies from “D+12”. The height, “z”, of the antipad is determined by the
geometry of the differential pair(s) that needs to be routed between two adjacent signal
columns. Note that the antipad sizes are the same for both the header and receptacle.
On reference layers other than ground, an antipad around a ground pin is also required.
Rules related to the isolation of ground from power may drive the design of this antipad.
If there are no such rules, then the same height, “z”, used for a signal pin may be used
for this antipad. If such rules do exist, then the antipad should be developed such that the
desired isolation requirement is met.
It is recommended that differential traces are routed so that they are centered between
signal columns. Figure 8 shows a graph that provides recommendations in Metric units
for the height, “z”, of an antipad when routing a single differential pair between two
signal columns. Figure 9 shows the same graph in English units. Figure 10 shows a
graph that provides recommendations in Metric units for the height, “z”, of an antipad
when routing two differential pairs between two signal columns. Figure 11 shows the
same graph in English units.
Notes:
1. Routing two differential pairs between signal columns will result in crosstalk between
differential pairs. This crosstalk should be factored into the analysis of the system.
2. Recommendations for antipads have been developed to optimize data throughput.
Under nominal conditions for PWB manufacturing, these recommendations will
ensure sufficient ground coverage for trace widths of 15 mils or less.
Tyco/Electronics
Circuits & Design
PAGE 7
July 10, 2003
G
H
HG
FG
E
F
DG
D
C
BG
B
A
B
O
A
R
D
2.5 mm
E
D
G
E
Antipad
Height
“z”
1.5 mm
Antipad Width
3.48 mm (Max.)
1.5 mm
Figure 6 - HM-Zd Receptacle (Daughtercard) Footprint & Antipad Design
A
B
BG
C
D
DG
E
F
FG
G
H
HG
2.5 mm
Antipad
Height
“z”
1.5 mm
Antipad Width
3.48 mm (Max.)
1.5 mm
Figure 7 - HM-Zd Header (Backplane) Footprint & Antipad Design
Tyco/Electronics
Circuits & Design
PAGE 8
July 10, 2003
2.0
"w" = 0.1016 mm
1.9
1.8
"w" = 0.2032 mm
1.7
s
h
"w" =0.1524 mm
w
h
"w" = 0.2540 mm
1.6
"w" = 0.3048 mm
1.5
"w" =0.3556 mm
1.4
"w" = 0.4064 mm
1.3
NOT RECOMMENDED
1.2
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
"s" - Trace Spacing (m m )
Note - Based on a 1.0160 pad
Figure 8 - Recommendations for Antipad Height, “z” (Metric Units)
80
"w " = 4 m ils
78
s
h
76
w
"w " = 6 m ils
74
h
72
"w" = 8 m ils
70
68
"w " = 10 m ils
66
64
62
"w " = 12 m ils
60
58
"w" =14 m ils
56
54
"w" = 16 m ils
52
50
NOT RECOM MENDED
48
0
2
4
N ote - Based on a 40 m il pad
6
8
10
12
14
16
18
20
22
24
26
28
30
"s " - T rac e S pa cin g (m ils )
Figure 9 – Recommendations for Antipad Height, “z” (English Units)
Tyco/Electronics
Circuits & Design
PAGE 9
July 10, 2003
1.8
"w" = 0.1016 mm
h
s
h
Pair 1
s
2w
w
1.7
Pair 2
1.6
"w" = 0.1270 mm
Note - Routing traces in this
manner will result in
crosstalk between differential
pairs. This crosstalk should
be factored into the analysis
of the system design.
1.5
1.4
"w" = 0.1524 mm
1.3
NOT RECOM MENDED
1.2
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
"s" - Trace Spacing (m m )
Note - Based on a 1.0160 pad
Figure 10 - Recommendations for Antipad Height, “z” (Metric Units)
70
"w" = 4 mils
68
s
h
s
2w
w
66
Pair 1
h
Pair 2
"z" - Antipad Height (mils)
64
"w" = 5 mils
62
60
Note - Routing traces in this
m anner will result in
crosstalk between
differential pairs. This
crosstalk should be factored
into the analysis of the
system design.
58
56
"w" = 6 m ils
54
52
50
NO T RECO MM ENDED
48
0
2
Note - Based on a 40 m il pad
4
6
8
10
12
14
"s" - Trace Spacing (m ils)
Figure 11 - Recommendations for Antipad Height, “z” (English Units)
Tyco/Electronics
Circuits & Design
PAGE 10
July 10, 2003
3. ANTIPAD SHAPE
The differential antipad which encompasses both signal vias is shown in Figure 6 and
Figure 7 as octagonal, but may also be oval or rectangular. The selection of shape is
more a determination of CAD ease than electrical performance. If a rectangular antipad
is implemented, avoid routing the signals over or near the corner of the antipad after
exiting the signal via. The proper route-out is perpendicular to the long side of the
rectangle as shown in Figure 12.
Correct
Incorrect
Figure 12 – Rectangular Antipad Corner Avoidance
4. NON-FUNCTIONAL PADS
The removal of non-functional internal pads will improve signal integrity and
manufacturability of the PCB. However, some assembly facilities prefer that pads are
left in order to maintain hole integrity through various soldering processes. For electrical
reasons it is recommended to remove unused pads on internal layers.
5. COUNTERBORING
Counterboring, also referred to as reverse drilling, back drilling, or controlled depth
drilling, is a technique used to reduce the electrical impact of the plated through-hole.
Because the signal only utilizes the portion of the via between the layer connection in the
PWB and the connector surface, a considerable portion of the via is unused by the signal.
By drilling out the remainder of the via, the excess stub is eliminated, leaving only the
portion of the via that is required, similar to a blind via. While this technique provides
electrical advantages and is also compatible with the HM-Zd connector for depths
beyond 1.4 mm (0.055”) from the connector side of the PWB, the board manufacturer
should be consulted when considering counterboring.
Tyco/Electronics
Circuits & Design
PAGE 11
July 10, 2003
IV. SUMMARY
Item
HM-Zd Signal Pin Column Pitch
HM-Zd Signal Pin Row Pitch
Number of Pair per Row
Number of Connector Columns
Suggested Pad Size
Suggested Antipad Size Range
(Single Differential Pair Between Adjacent Columns)
Suggested Antipad Size Range
(Two Differential Pairs Between Adjacent Columns)
Maximum Trace Width (Header & Receptacle)
Maximum Trace Width (Header & Receptacle)
Nominal Finished Hole Sizes
Nominal Drill Hole Sizes
Number of Layers to Route Out 2 Pair Connector
Tyco/Electronics
Circuits & Design
PAGE 12
Value
2.5 mm (0.098”)
1.5 mm (0.059”)
2/3/4
10 typ.
1.02 mm (0.040”)
For Metric Units, see Figure 8, p. 9
For English Units, see Figure 9, p. 9
0.60 mm (0.024”)
0.70 mm (0.0276”)
2
1
4
2
July 10, 2003
V.
ADDITIONAL INFORMATION
A. Z-PACK HM-Zd
More electrical and mechanical information regarding the HM-Zd connector may be
obtained via email to hmzd@tycoelectronics.com.
B. Gigabit Research & General Application Notes
More information regarding Tyco Electronics research into the transmission of electrical
signals at gigabit speeds or general application notes are available for download via the
World Wide Web at www.amp.com/simulation.
C. Electrical SPICE Models
Electrical SPICE models for
modeling@tycoelectronics.com.
the
HM-Zd
connector
may
be
requested
at
VI. CONTACT INFORMATION
A. TYCO ELECTRONICS
Tyco Electronics Corporation is the world's leader in electrical, electronic and fiber-optic
connectors and interconnection systems. Its facilities are located in over 50 countries
serving customers in the automotive, computer, communications, consumer electronics,
industrial and power industries. Tyco Electronics, headquartered in Harrisburg,
Pennsylvania, USA, is the largest passive electronics components supplier in the world,
providing advanced technology products from its AMP, Elcon, Elo Touchsystems, HTS,
M/A-COM, Madison Cable, OEG, Potter & Brumfield, Raychem, Schrack and Simel
brands.
For more information about Tyco Electronics Products, call us today or visit us on the web.
Product Information Center
800-522-6752
717-986-7777
http://www.tycoelectronics.com
Internet
Tyco/Electronics
Circuits & Design
PAGE 13
July 10, 2003
B. CIRCUITS & DESIGN
Circuits & Design (C&D) is part of the Communications, Computer, and Consumer
Electronics Division of Tyco Electronics, which focuses on the telecom, datacom, storage,
and consumer markets. C&D offers the industry interconnection expertise from concept to
production, and helps customers to validate their designs at the concept stage. C&D is
providing a leadership role for the industry in the area of signal integrity by working with
Tyco Electronics customers, industry standard working groups, and semiconductor vendors.
Offering interconnection expertise from concept to production, C&D can help validate your
design and package it for manufacturing. At the front end, our end-to-end computer
simulation and analysis of your system will evaluate the most critical parameters of your
design. Our advanced analysis and modeling techniques can help determine the optimal
device drivers, board design and stackup, and board layout for your design. By identifying
problems such as reflections, ground bounce, crosstalk, jitter, propagation delay, and timing,
C&D can help you reduce costs and verify the performance of your design.
C&D has been instrumental in developing and verifying many of the world’s most popular
bus standards. Here is a brief sampling.
CompactPCI: Our recommendations helped make CompactPCI the rock-solid,
industrial-strength bus that combines high performance with flexibility.
CompactPCI Hot Swap: We provided the critical simulations that allowed
mission-critical hot swapping to be a reality in CompactPCI.
CT: C&D performed the simulations for the H.110 computer telephony
extensions to CompactPCI.
PXI: Our analysis of PXI resulted in several improvements for increased signal
integrity.
CPCI/CT/ATM Backplane: This is a C&D-designed system that combines
CompactPCI, CT, and Cellbus into a high-performance system that meets the
growing needs of communications convergence.
For more information regarding C&D, contact us today.
Internet
Electrical simulation
Electrical models
Tyco/Electronics
Circuits & Design
http://www.amp.com/simulation
simulation@tycoelectronics.com
modeling@tycoelectronics.com
PAGE 14
July 10, 2003
VII. REVISION HISTORY
Revision
Date
A
1/29/01
Initial Release
B
7/10/01
Counterboring, antipad updates, and minor text changes
Tyco/Electronics
Circuits & Design
Change
PAGE 15
July 10, 2003

INTERCONNECT APPLICATION NOTE Z-PACK HM-Zd PWB Footprint Optimization for Routing

Transcription

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