Assignment 7 Solutions Virtual Memory 1 Virtual and Physical Addresses

Assignment 7 Solutions
Virtual Memory
Alice Liang
June 8, 2013
1
Virtual and Physical Addresses
1.1
For each configuration (a-c), state how many bits are needed for each of the following:
• Virtual address
• Physical address
• Virtual page number
• Physical page number
• Offset
a. 32-bit operating system, 4-KB pages, 1 GB of RAM
b. 32-bit operating system, 16-KB pages, 2 GB of RAM
c. 64-bit operating system, 16-KB pages, 16 GB of RAM
Virtual Address = OS address length
Physical Address = log2 (RAM size) bits
Offset = log2 (page size) bits
Virtual Page Number bits = Virtual Address - Offset
Physical Page Number bits = Physical Address - Offset
Config
a
b
c
V.Addr.
32
32
64
P.Addr.
30
31
34
V.Page #
20
18
50
P.Page #
18
17
20
Offset
12
14
14
1.2
What are some advantages of using a larger page size?
- Fewer page faults (if high spatial locality)
- Page table can be smaller
- Fewer TLB misses (the entries in the TLB will span a larger fraction of memory)
1
1.3
- Page faults are more expensive
- Wasted space if pages are under-utilized
2
Using the TLB.
As described in your textbook, virtual memory uses a page table to track the mapping of virtual addresses to
physical addresses. To speed up this translation, modern processors implement a cache of the most recently
used translations, called the translation-lookaside buffer (TLB). This exercise shows how the page table and
TLB must be updated as addresses are accessed.
The following list is a stream of virtual addresses as seen on a system. Assume 4-KB pages and a fourentry fully associative TLB with LRU replacement policy. If pages must be brought in from disk, give them
the next largest unused page number (i.e., starting at 13).
0x0FFF
0x7A28
0x3DAD
0x3A98
0x1C19
0x1000
0x22D0
Initial TLB: (Note: Values are in base-10)
Valid
1
1
1
0
Tag
11
7
3
4
PP #
12
4
6
9
LRU
2
3
4
1
The LRU column works as follows: The older an entry is, the lower its LRU number will be. Each time
an entry is used, its LRU number is set to 4 (since it is now the most-recently used), and the other numbers
are adjusted downward accordingly.
Initial Page Table: (Note: Values are in base-10)
Index
0
1
2
3
4
5
6
7
8
9
10
11
Physical Page
or On Disk
5
Disk
Disk
6
9
11
Disk
4
Disk
Disk
3
12
Valid
1
0
0
1
1
1
0
1
0
0
1
1
2
Solution. Since each page is 4 KB (212 bytes), the lower 12 bits of the address are the page offset and can
be ignored. The page number or tag is the remaining upper 20 bits.
We start by checking all the tags in the TLB for a match. For a correct match, the valid bit must also
be set. If there is a match we have a TLB hit (H), and all we have to do is update the LRU bits.
If there is no match in the TLB, we have to check the page table. Use the page number (tag) as an index
into the page table. If the entry is valid, we have a TLB miss (M). Evict the least recently used entry in the
TLB and replace it with the new translation. Remember to update all of the LRU bits and set the valid bit
as well.
Finally, if the entry in the page table is invalid, our page is on disk and we have a page fault (PF). As
per the instructions, assign it a new page number (starting with 13), and set its valid bit in the page table.
Then you must update the TLB by evicting the LRU entry as before.
The ending tables will look like the following:
Address
0x0FFF
0x7A28
0x3DAD
0x3A98
0x1C19
0x1000
0x22D0
Result
(H, M, PF)
M
H
H
H
PF
H
PF
TLB: (Note: Values are in base-10)
Valid
1
1
1
1
Tag
1
7
3
2
PP #
13
4
6
14
LRU
3
1
2
4
Page Table: (Note: Values are in base-10)
Index
0
1
2
3
4
5
6
7
8
9
10
11
Physical Page
or On Disk
5
13
14
6
9
11
Disk
4
Disk
Disk
3
12
Valid
1
1
1
1
1
1
0
1
0
0
1
1
3