Tip027BB TOPIC: How to Use Freeport Mode to Connect Several S7-200... in a Remote I/O Network VERSION: 4.0

Transcription

INDUSTRIAL AUTOMATION
Tip027BB
TOPIC: How to Use Freeport Mode to Connect Several S7-200 CPUs
in a Remote I/O Network
VERSION: 4.0
DATE: 1/99
***SPECIAL HARDWARE REQUIREMENTS***
Two or more SIMATIC S7-200 CPUs: CPU 212 or CPU 214
One connection cable, 9-pin
If more than two PLCs are used (more than one slave), you will need
a Siemens network bus connector.
***OVERVIEW***
In this example, three SIMATIC S7-200 CPUs are connected. Each one
is a CPU 214. Station 0, called the master, is linked to stations
1 and 2, called the slaves. The master station sends four bytes of
output data to each station in turn. As a result, each station
responds with four bytes of input data. The Freeport communication
mode is used for the data transmission.
Two memory buffers are reserved: one for remote inputs and one for
remote outputs. The output data that is to be transmitted is
captured by moving a double word value from the output buffer to
the Transmit buffer. After transmitting, the master station receives
the response of the slaves and stores the data in the Receive buffer.
This program includes several timed interrupt routines. Each timed
interrupt routine is called by one of the following two interrupt
events: interrupt event 10 and event 11. For example, in this
program, interrupt event 10 calls timed interrupt routines INT0,
INT1, and INT2. At one point in the program, interrupt event 11
calls INT15.
The time interval for a timed interrupt routine that is called by
event number 10 is specified in special memory byte SMB34. The time
interval for the timed interrupt that is called by event number
11 is specified in special memory byte SMB35. In both cases, the
time interval is fixed in increments of 1 ms. The smallest value
permitted for the time interval is 5 ms. The largest value permitted
for the time interval is 255 ms.
In this program, the time interval specified in both SMB34 and
SMB35 is 5 ms.
It is also possible to use the Network Read (NETR) and Network Write
(NETW) instructions to link a CPU 214 to other S7-200 CPUs in the
Point-to-Point Interface (PPI) mode. In the PPI mode, it is possible
to connect TD 200 units and operator panels (OPs) to the network
and still link the stations together.
***PROGRAM STRUCTURE: SLAVE***
The program consists of the following routines:
Main
SBR0
SBR1
INT0
INT1
INT2
INT10
INT11
INT12
INT13
INT14
INT15
Initialize the program.
Enable the Freeport mode and the quiet line timer and receiver,
and set the time-out and delay time.
Disable the Freeport communication mode and
detach the interrupts for receiving, transmitting and
timing.
Enable the reception of input data (quiet line timer).
Stop the timer and the transmitter (Transmit time-out
timer).
Enable the quiet line timer and the quiet line receiver
(message time-out timer).
Enable quiet line timer and quiet line receiver
(transmitter interrupt).
Receive the first character of a message.
Receive the output data.
Receive the frame check sequence (FCS) character.
Enable the quiet line receiver.
Enable the delayed transmitter interrupt.
***PROGRAM DESCRIPTION: SLAVE***
This program enables you to connect two, three, or more
SIMATIC S7-200 CPUs (CPU 214 or CPU 212)
as a communication network.
The universal asynchronous receiver-transmitter (UART) is initialized
as follows:
odd parity
PROLIFIC SYSTEM AND TECHNOLOGY PVT.LTD.
8 bits per character
38,400 baud (CPU 214)
19,200 baud (CPU 212)
If you use only SIMATIC CPU 214 PLCs, the application runs at
38,400 baud.
If you use only SIMATIC CPU 212 PLCs, the application runs
automatically at 19,200 baud.
If you use a combination of SIMATIC CPU 214 and CPU 212 PLCs, you
need to adjust the program slightly: just change the setting of
the value of special memory byte SMB30 from the hexadecimal value
C0 (16#C0) to C4 (16#C4) and from the hexadecimal value C1 (16#C1)
to C5 (16#C5). The application will run at 19,200 baud.
If you use a slower baud rate, you must also change the time-out
value that is loaded into special memory byte SMB34.
***FUNCTION OF THIS PROGRAM:***
Each message is validated by a frame check sequence (FCS) character
that is formed by performing an Exclusive Or operation on the data
bytes in the message. The remote I/O master is station 0 and may
be connected to one, two, or three slave stations. If one slave
station is connected, it must be station 1. If two slaves are
connected, they must be stations 1 and 2. If three slave stations
are connected, they must be stations 1, 2, and 3. The number of
slave stations that are connected must be supplied as a parameter
to the master station in variable memory byte VB0.
For slave stations, the station address is stored in VB0.
If you use a PC/PPI cable with a modem to connect the master and
slave stations, set VB1 = 1; otherwise, set VB1 = 0. This setting
provides a two-character delay between the Receive and Transmit
messages. This delay is required when using the PC/PPI cable.
Each slave station has an input buffer and an output buffer as follows:
Input Buffer
IB0
byte 0
IB1
byte 1
IB2
byte 2
IB3
byte 3
Output Buffer
QB0
byte 0
QB1
byte 1
QB2
byte 2
QB3
byte 3
When the master station transmits a message, the slave station that
is addressed by the master stores the output data in a Receive
buffer and responds to the master's transmission by transmitting
the input data in the Transmit buffer. These buffers are shown
below. VB607 is a garbage location used in the generation of the
Transmit checksum, or Frame Check Sequence (FCS).
Transmit Buffer
VB600 length
VB601 address
VB602 byte 0
VB603 byte 1
VB604 byte 2
VB605 byte 3
VB606 FCS
VB607 xx
Receive Buffer
VB608 byte 0
VB609 byte 1
VB610 byte 2
VB611 byte 3
The message format is as follows:
Address B0
B1
B2
B3
FCS
The S7-200 Programmable Controller System Manual provides you with
more information about the interrupt routines and the Transmit
(XMT) instruction.
***MAIN PROGRAM***˛
Network 1
Enable a Two-Character Delay Time
Load special memory bit SM0.1 to process this network in the first
scan cycle only.
Move the constant 1 into variable memory byte VB1 to enable the
two-character delay that is required by the PC/PPI cable.
SM0.1
1
Network 2
VB1
If the CPU Mode Switch Is in the RUN Position, Start Communication
Load special memory bit SM0.7. (If SM0.7 is on, the mode switch of
the CPU is in the RUN position, enabling you to select the Freeport
communication mode.)
If special memory bit SM0.7 is on,
and special memory bit SM0.1 is on (indicating that this
is the first scan cycle),
call subroutine SBR0 to start communication.
SM0.7
Network 3
SM0.1
0
If the CPU Mode Switch Is Moved to the RUN Position, Start Communication
Load special memory bit SM0.7.
If there is an off-to-on transition (positive or rising edge) at
special memory bit SM0.7 (that is, when the CPU mode switch is
moved to the RUN position),
call SBR0 to start communication.
SM0.7
0
Network 4
If the CPU Mode Switch Is in the TERM Position, Disable Communication
Load special memory bit SM0.7 as a Normally Closed contact
so that power will flow if SM0.7 is not on (that is, if it has a
signal state of 0). If special memory bit SM0.7 is off, the mode
switch of the CPU is in the TERM position.
If the mode switch is in the TERM position,
call SBR1 to disable communication.
SM0.7
Network 5
1
Main Program End
End the main program.
Network 6
Subroutine SBR0
SBR0 initializes the Freeport mode and enables the interrupts for
the quiet line timer and the quiet line receiver.
Start SBR0.
0
Network 7
Enable Freeport Mode, Quiet Line Timer and Receiver, and Set Timers
Load special memory bit SM0.0 to process this network every scan cycle.
Move the hexadecimal value C1 (binary 1100 0001) into
special memory byte SMB30. This bit combination configures
the communication interface for Freeport mode; 38,400 baud;
8 data bits per character; and odd parity.
Enable all interrupt events.
Move the constant 5 into special memory byte SMB34 to set
the time interval to 5 ms for the timed interrupt routines that are
triggered by interrupt event 10. This is the time-out value. (Use the
5-ms value for transmission rates of 38,400 baud and 19,200 baud.
Use a 10-ms value for a transmission rate of 9600 baud.)
Move the constant 5 into special memory byte SMB35 to set the time
interval to 5 ms for the timed interrupt routine that is triggered
by interrupt event 11. This is the two-character delay time, which
has a minimum of 5 ms.
Attach interrupt event 10 to INT0 to enable the 5-ms
quiet line timer and enable the reception of input data.
Attach interrupt event 8 (Port 0: Receive character) to INT14.
When a character is received at Port 0, control is transferred
to INT14 to enable the quiet line receiver.
SM0.0
16#C1
SMB30
5
SMB34
5
SMB35
0
10
14
8
Network 8
End of Subroutine SBR0
End SBR0.
Network 9
Subroutine SBR1
SBR1 disables the Freeport communication mode and detaches the
interrupts for receiving, transmitting, and timing.
Start SBR1.
1
Network 10
Disable Communication
Move the hexadecimal value C0 (binary 1100 0000) into
special memory byte SMB30. This bit combination configures
the communication interface for Point-to-Point Interface (PPI/slave mode)
protocol; 38,400 baud; 8 data bits per character; and odd parity.
(The Freeport mode is disabled.)
Detach interrupt event 8 (Port 0: Receive character) from all
interrupt routines to disable the Receive interrupts.
Detach interrupt event 9 (Port 0: Transmit complete) from all
interrupt routines to disable the Transmit interrupts.
Detach interrupt event 10 (timed interrupt) from all interrupt
routines to stop the timed interrupts.
SM0.0
16#C0
SMB30
8
9
10
Network 11
End of Subroutine SBR1
End SBR1.
Network 12
Interrupt Routine INT0
Start INT0 (the quiet line time-out timer) to enable the reception
of input data.
0
Network 13
Enable Reception of Input Data
to INT11 to enable the reception of input data.
SM0.0
11
8
Network 14
End of Interrupt Routine INT0
End INT0.
Network 15
Start INT1 to detach the timed interrupts that are triggered by
interrupt event 10 and the Transmit interrupts if data is transmitted
or received or if the timer is retriggered.
1
Network 16
Transmit Message Time-Out Timer
Put the CPU into the STOP mode.
SM0.0
10
9
Network 17
End INT1.
Network 18
Start INT2 to interrupt the program if the first character of a
message is received.
2
Network 19
Message Time-Out Timer
quiet line time-out timer.
SM0.0
0
10
14
8
Network 20
End INT2.
Network 21
Start INT10 to interrupt the program if a message is transmitted.
The Transmit interrupts are disabled. The quiet line timer begins
to run and the quiet line receiver is enabled.
10
Network 22
Transmitter Interrupt
quiet line time-out timer.
SM0.0
9
0
10
14
8
Network 23
End INT10.
Network 24
Start INT11 when the first character of a message is received.
The message time-out timer is set. Data can be received. If there
is an error, the quiet line time-out timer and the quiet line
receiver are enabled.
11
Network 25
Receive the First Character of a Message
Load special memory bit SM3.0 as a Normally Closed contact to enable
power flow if there is no parity error at Port 0 of the CPU.
If there is no parity error,
compare the character in SMB2 with the contents of
variable memory byte VB0 (station address of the slave station).
(SMB2 contains each character that is received from Port 0
or Port 1 during Freeport communication. In this example,
the CPU receives the information through Port 0.)
If the number in SMB2 is equal to the station number in VB0,
move the constant 0 into accumulator AC0 to initialize the
checksum register,
move the constant 4 into accumulator AC1 to load the Receive
character count,
set variable memory double word VD638 to function as a pointer to
variable memory byte VB608 (the first byte of the Receive buffer), and
attach interrupt event 10 to INT2 to enable the message time-out timer.
to INT12 to enable the reception of output data.
End INT11 conditionally, that is, if there is no parity error
and the message is intended for this station.
SM3.0
SMB2
VB0
0
AC0
+4
AC1
&VB608
2
10
12
8
VD638
Network 26
Enable the Quiet Line Timer and the Quiet Line Receiver
If the message was not intended for this station or there was a parity error,
load special memory bit SM0.0 to process this network every scan cycle.
Attach interrupt event 10 to INT 0 to enable the 5-ms
quiet line timer and enable the reception of input data.
Attach interrupt event 8 (Port 0: Receive character) to INT14
SM0.0
0
10
14
8
Network 27
End INT11.
Network 28
Start INT12 to interrupt the program if data is received and there
is no error.
The information is stored in a buffer. The frame check sequence
(FCS) can be received by another interrupt. If there is an error,
the quiet line time-out timer and the quiet line receiver are enabled.
12
Network 29
Receive the Output Data
Load special memory bit SM3.0 as a Normally Closed contact
to enable power flow if there is no parity error at Port 0 of the
CPU.
move the contents of special memory byte SMB2 to the location
that is pointed to by VD638 (the Receive buffer).
(The asterisk in front of VD638 indicates that the contents of
this double word is a pointer to another location in memory,
namely to the Receive buffer location).
Increment the value in variable memory double word VD638
to point to the next Receive buffer location.
XOR the corresponding bits of special memory word SMW1 (contains
bits that, if set to 1, indicate errors) with those of accumulator
AC0 and put the result in accumulator AC0. This Exclusive Or Word
operation computes the checksum.
Decrement the value in accumulator AC1 to decrement the Receive
character count.
SM3.0
SMB2
*VD638
VD638
VD638
SMW1
AC0
AC0
AC1
AC1
Network 30
Enable Reception of the FCS
Load special memory bit SM1.0. This bit is turned on (set to 1)
by the execution of certain instructions when the result of the
operation is 0. The Decrement Word (DECW) instruction affects
this bit. If Network 29 indicates that four characters have been
received (that is, if the result of DECW in Network 29 was 0),
special memory bit SM1.0 is turned on (set to 1).
If SM1.0 is on:
attach interrupt event 8 (Port 0: Receive character) to INT13.
to INT13 to enable reception of the FCS.
End INT12 conditionally, that is, if four characters were received.
SM1.0
13
8
Network 31
If a Parity Error Occurs, Enable the Quiet Line Timer and Receiver
Load special memory bit SM3.0. If there is a parity error,
attach interrupt event 10 to INT0 to enable the 5-ms
quiet line timer.
SM3.0
0
10
14
8
Network 32
End INT12.
Network 33
Start INT13 to receive the frame check sequence (FCS) character.
The program does not enable any timed interrupt or any Receive interrupt.
After the FCS is computed, the program enables the transmitter time-out
and transmitter interrupts. If there is an error, the program enables
the quiet line time-out timer and the quiet line receiver.
13
Network 34
Disable the Quiet Line Receiver and the Quiet Line Timer
Detach interrupt event 8 (Port 0: Receive character) from all
interrupt routines to disable the Receive interrupts.
SM0.0
8
10
Network 35
Receive the FCS Character and Save the Output Data
Load special memory bit SM3.0 as a Normally Closed contact to enable
power flow if there is no parity error at Port 0 of the CPU.
compare the character in SMB2 with the contents of accumulator AC0.
If the contents of SMB2 are equal to the FCS,
move the contents of variable memory double word VD608 (the output
data) to output double word QD0 (the output buffer of the slave
station).
Move the constant 6 into variable memory byte VB600 to indicate
the length of the Transmit buffer = 6 bytes.
Move the contents of variable memory byte VB0 (the slave station
address) into variable memory byte VB601 (in the Transmit buffer).
Move the contents of input double word ID0 (the input data of the
slave station) into variable memory double word VD602 (the data
bytes of the Transmit buffer).
XOR the corresponding bits of variable memory word VW602 with those
of VW604 to compute the frame check sequence (FCS) and put the
result in accumulator AC0.
Move the value in accumulator AC0 into variable memory byte VB606.
XOR the corresponding bits of accumulator AC0 and variable memory
word VW606 and put the result into VW606 to save the FCS.
Turn on (set to 1) memory bit M0.0 to enable the Transmit bit.
SM3.0
SMB2
AC0
VD608
QD0
6
VB600
VB0
VB601
ID0
VD602
VW602
VW604
AC0
AC0
VB606
AC0
VW606
VW606
M0.0
Network 36
Enable the Delayed Transmitter Interrupt
Load memory bit M0.0.
If memory bit M0.0 is on (has a signal state of 1),
and the constant 1 is equal to the number in variable memory byte
VB1 (that is, you are using a PC/PPI cable with a modem to connect
the master and slave stations),
attach interrupt event 11 to INT15 to enable the delayed
tranmitter interrupt routine.
End INT13 conditionally, that is, if M0.0 is set
and you are using a PC/PPI cable.
M0.0
1
VB1
15
11
Network 37
Enable Transmitter Timer and Interrupt, Transmit the Data
Load memory bit M0.0.
If memory bit M0.0 is on (has a signal state of 1),
attach interrupt event 10 to INT1 to enable
the 5-ms time-out timer for the transmitter.
Attach interrupt event 9 (Port 0: Transmit complete) to INT10
to enable the transmitter interrupt.
Transmit by means of Port 0 the data buffer (TABLE) that starts
at variable memory byte VB600 (the first byte of the Transmit buffer;
that is, transmit the message).
End INT13 conditionally, that is, if M0.0 is set.
M0.0
1
10
10
9
VB600
0
Network 38
If a Parity Error Occurs, Enable the Quiet Line Timer and Receiver
If there is a parity error,
load special memory bit SM0.0 to process this network every scan cycle.
quiet line timer.
SM0.0
0
10
14
8
Network 39
End INT13.
Network 40
Start INT14 to enable the time-out interrupt.
14
Network 41
Retrigger the 5-ms Quiet Line Time-Out Timer
Attach interrupt event 10 to INT0 to retrigger the 5-ms
quiet line timer.
SM0.0
0
10
Network 42
End INT14.
Network 43
Start INT15 to enable the delayed transmitter interrupt.
This routine provides a delay between the last character
that is received and the first character that is transmitted.
The PC/PPI cable requires a two-character delay time
and some modems also require a delay.
15
Network 44
Delayed Transmitter
Detach interrupt event 11 from all interrupt routines
to disable the transmitter interrupt.
Attach interrupt event 10 to INT1 to enable
the 5-ms time-out timer for the transmitter.
Attach interrupt event 9 (Port 0: Transmit complete) to INT10
to enable the transmitter interrupt.
Transmit by means of Port 0 the data buffer (TABLE) that starts
at variable memory byte VB600 (the first byte of the Transmit buffer;
that is, transmit the message).
SM0.0
11
1
10
10
9
VB600
0
Network 45
End INT15.

Tip027BB TOPIC: How to Use Freeport Mode to Connect Several S7-200... in a Remote I/O Network VERSION: 4.0

Transcription

Similar documents

THE HOOK (AND PATTERN INTERRUPT)

10 Influence Tools – The Pattern Interrupt

corny jokes below! - Monclova Road Baptist Church

Vex Ultrasonic Sensor Interfacing and Programming

Untitled

≥aj 700 air-feed floor model jogger

≥aj 700 air-feed floor model jogger

68HC11 Reset, Stack, JSR, Interrupts

House street Algierska, Saska Kepa district