International Journal of Advent Research in Computer and Electronics (IJARCE)

International Journal of Advent Research in Computer and Electronics (IJARCE)
Vol.1, No.6, October 2014
E-ISSN: 2348-5523
Read Stability Problem of 6T-SRAM and Proposed
Solutions
Gaurav Hemant Patil, Irene Susan Jacob
Electronics and Telecommunication, Mumbai University
Email:gauravh.patil131093@gmail.com,irene.susan08@gmail.com
Abstract- In today’s high performance world,
workstations and servers demand high speed
circuitry, reliable output and optimized chip area
design. SRAMs and DRAMs are the fundamental
building blocks of memory storage devices. 6T
Static Random Access Memory cell has various
problems. Read stability and reverse leakage
current are the two fundamental problems
associated with SRAM. Therefore, 7T and 8T
SRAM cells are used. SRAMs are implemented
using 120 nm technology. Read Stability problem
can be solved by below mentioned techniques. In
7T and 8T SRAM designs, extra transistors are
added in order to provide a discharge path and
solve the problem of read instability. Thus area
increases but reliable output is obtained. Applying
different voltages to Word Line and cell supply
voltage is good option because it neither increases
1.
the area nor power dissipation. However, obtaining
and managing two different supply voltages is
difficult. Increase in width of Driver transistor will
increase the overall area of the chip. It might
introduce some extra time delay. If threshold
voltage of the access transistor is increased then
leakage current will be reduced thus enabling more
number of bit cells in a column. However, memory
fragmentation is also an option but extra hardware
will be required to access each bit cell. Thus,
SRAM is chosen according to the specifications.
High speed, chip area, cost of production, extra
hardware, reliability and stability are the parameter
which should be considered before selecting a
SRAM.
Index Terms-Read stability, SRAM, Leakage
current, threshold voltage, memory fragmentation
INTRODUCTION
One bit SRAM cell is designed by using 6-transistor
structure [2]. The circuit consists of 2 cross-coupled
inverters and two NMOS pass transistors.The cross
coupled inverters consists of two PMOS transistors
are called as Pull up transistors while the two NMOS
transistors are called as Driver transistors. Two
transistors which are connected to the Bit Line and Bit
Line Bar are called as Access Transistors as these
transistors provide access to the bit cell. For read and
write operation ‘word line’ should be high. Thus
access transistors are turned on and internal storage
cell gets connected to the Bit Line(BL) and Bit Line
Bar(BLB). During Hold operation, Word Line is low.
Thus access transistors are off and latched data gets
stored in the memory. Thus one bit data gets stored in
6T SRAM. During write operation, if BL is high then
Q becomes high and simultaneously Q_BAR becomes
low. Thus data on Bit Lines get latched in the
memory. During read operation, Q gets directly
connected to the BL and BLB.
Fig. 2 shows the layout of 6T SRAM cell. In this
figure, Bit Line and Bit Line Bar are complement of
each other. When Word Line is low then SRAM cell
is in HOLD state while when Word Line is high then
it writes or reads.
Fig. 2Layout of 6T SRAM cell
In figure 3, it is observed that Q and Q_BAR latch
the bit values only when Word Line is high. When
Word Line is low, SRAM holds the previous value.
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Fig. 1 Schematic of 6T SRAM cell
International Journal of Advent Research in Computer and Electronics (IJARCE)
Vol.1, No.6, October 2014
E-ISSN: 2348-5523
an open circuit during the read operation. Thus
current will not flow through that path and Vds will
not be generated. Therefore even if Q_BAR voltage
rises above threshold voltage; seventh transistor won’t
conduct and stable output can be obtained. Thus 7T
SRAM eliminates the problem of Read Instability.
Figure 5 shows the schematic of 7T SRAM cell.
Fig. 3 Output of 6T SRAM cell
2. READ STABILITY
Read stability is the main problem faced in the 6T
SRAM cell [3]. If Q is low and Q_BAR is high then
small voltage is produced at the drain terminal of
driver NMOS transistor. This voltage corresponds to
the Vds of that transistor. Very small current is passed
through the driver transistor. This small increase in
the voltage is observed due to the Drain-Source
capacitance of the access transistor. If this increase in
voltage is above the threshold voltage of the NMOS
transistor then it will trigger the cross-coupled
inverter pair and outputs will be interchanged. Thus
stable output can never be assured. Figure 4 highlights
the phenomenon of Read Stability. In fig. 4, v1 is the
output voltage of the SRAM when it is high while v0
is the output voltage of the SRAM when it is low.
Fig.5 Schematic of 7T SRAM
Figure 6 shows the layout of 7T SRAM cell. Two
separate Word Lines are implemented for Read and
Write operation. Due to this arrangement, current will
not flow through driver transistor during read
operation. Thus, Read Instability problem is solved.
Fig. 6 Layout of 7T SRAM cell
Fig. 4Read Stability
In figure 7, output waveforms are shown of 7T cell.
Q_BAR will give the output only when Read Word
Line is high while Q will give the output only when
Write Word Line is high. Proper waveforms can be
obtained by reducing the cell voltage. Extra transistor
will add some resistance in the circuit. Therefore,
output voltage decreases.
3. PROPOSED SOLUTIONS
3.1. Implementing 7T design to construct a bit
cell.
7T SRAM is almost identical to the 6T SRAM
except it has one extra NMOS. It has two separate
word lines. WWL is high when data is latched in the
SRAM. WWL is given to the gate terminal of the
NMOS transistor. RWL is high when data is read
from the SRAM. Thus seventh transistor will act as a
short circuit during write operation while it will act as
Fig. 7Output of 7T SRAM cell
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International Journal of Advent Research in Computer and Electronics (IJARCE)
Vol.1, No.6, October 2014
E-ISSN: 2348-5523
3.2. Implementing 8T SRAM
8T SRAM has separate mechanism for Read
Operation. Read Word Line and Write Word Line are
the two lines used for read and write operation.
When Bit Line is high then output Q will be high and
QB will be low. RBLB line is pre-charged to high
level. Therefore, it follows the Bit Line Bar. The
reason for RBLB in pre-charge is as follows.
Transistors 7 and 8 are connected such that those will
be active only during Read Operation. During write
operation, when BL is high and BLB is low then
during write operation, Q gets the value 1 while QB
gets the value 0. This happens when Write Word
Line is high. Similarly, for read operation, Read
Word Line is high and BL is 0. Thus one transistor is
on while other is off. Therefore, RBLB will have the
value as 1as it is pre-charged. On the other hand,
when RWL is high and BL is 1 then both transistors
are on thus RBLB gets a discharge path. Thus, during
read operation current does not pass through NMOS
Driver transistor and hence 8T SRAM doesn’t have
Stability problem.
cannot be shown in Microwind software. Therefore,
RBLB is set high[1].
Fig. 10 Layout of 8T SRAM cell
3.3. Applying different voltages for Word Line
and VDD of a bit cell
The main cause of Read Instability is the voltage
generated across the driver NMOS transistor.
Therefore, drive strength of the driver transistor
should be greater than the drive strength of access
transistor[6]. Voltage across the access transistor is
Bit Line voltage while the voltage across the driver
transistor is slightly greater than zero. Therefore,
current flowing through the access transistor is much
lower than the current flowing through the driver
transistor. The formula for the drive strength is given
below:
Drive strength of driver(d) >>Drive strength of access
ߤ
ܹ݀
ܹܽ
(ܸ݈݈ܿ݁ − ܸ‫ݐ‬ℎ, ݀)∝ ≫ ߤ
(ܸ݈݈ܿ݁ − ܸ‫ݐ‬ℎ, ܽ)∝
‫݀ܮ‬
‫ܽܮ‬
Fig. 8Schematic of 8T SRAM cell
Figure 9 consists of physical layout of 8 transistors
SRAM. It has two separate transistors which enables
discharge path for RBLB line. It has two separate
lines for Read and Write operations. Thus, current
does not pass through Driver transistor. It passes
through those two extra transistors and solves the
Read Stability problem.
Fig. 9 Layout of 8T SRAM cell
In figure 10, Read Bit Line Bar is set high. In
SRAM both the Bit Lines are pre-charged. Thus,
when it is connected to ground it discharges. Thus, it
acts as a pull up. However, similar phenomenon
Therefore, to avoid Read Instability, VDD of the
cell should be higher than the word line voltage. If the
cell voltage is greater than the word line voltage then
Read Stability problem can be resolved without
compensating for extra area or delay.
3.4. Increasing the width of Driver transistor
Area occupied by the Driver transistor can be
increased. If width of the Driver transistor is increased
then its drive strength will increase[4]. Thus, voltage
developed across the Driver transistor will not be
greater than threshold voltage. However, there is a
disadvantage of increasing the area of Driver
transistor. Though increased transistor width can
withstand more current, length of the connecting paths
will increase proportionally. Thus, area of the chip
will increase and delay should be meticulously
calculated because the increase in current will reduce
the delay but delay will be more due to longer paths.
Thus, Read Stability will be obtained but at the price
of increased area and cost of the chip.
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International Journal of Advent Research in Computer and Electronics (IJARCE)
Vol.1, No.6, October 2014
E-ISSN: 2348-5523
3.5. Increasing threshold voltage of access
transistor
Increasing VTH of the access transistor will
reduce the leakage current of the device. Thus, it will
enable more devices to be connected in a column. If
BL is high and Word line is a low then too small
current flow through the NMOS; that current is called
as Leakage Current[7]. If the SRAM bit cell to be
accessed is storing 1and 0. However, all the other
cells in that particular column are storing 0 and 1.
Then due to leakage current, BL will decrease with
the faster rate than BLB. Thus, Read Stability
problem arises. To overcome these problems, memory
cells are fragmented into smaller memories. Instead of
making an SRAM of 1024*8, two separate 512*8
SRAMs can be designed. However, the disadvantage
of memory fragmentation is, additional hardware is
required to choose memory cells. Therefore, high
threshold voltage of the access transistor will enable
designers to implement 1024*8 SRAM without Read
Stability problem.
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Basics of CMOS Cell Design, Tata McGraw Hill,
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[3] J. M. Rabaey, A. Chandrakasan, B. Nikolic,
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[4] David. A. Hodges and Horace G Jackson,
Analysis and Design of Digital Integrated
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[5] M. Kanda, K. Takahashi, H. Oyamatsu, N.
Nagashima, and M. Kakumu, Highly stable 65
nm node (CMOS5) 0.56_m SRAM cell design
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[6] A. P. Chandrakasan, Low-power CMOS digital
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[7] Bikash Khandal, Bikash Roy, Design and
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2249-6645.
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