Homework 4

Homework 4
CDA 3101: Fall 2014
Due Date: 10/23/2014
11:30 PM
Primary TA: Sebo Kim
You are not allowed to take or give help in completing this assignment. Submit the PDF version of
the submission in e-Learning (Sakai) before the deadline. Please do not submit your handwritten
solution (no scanned PDF). Prepare your solution in Microsoft Word and convert it to PDF (File 
Save As  PDF). Please include the following sentence on top of your submission: “I have neither
given nor received any unauthorized aid on this assignment”.
Total Points: 33 pts
1.
Assume that logic blocks needed to implement a processor’s datapath have the following
latencies:
I-Mem
Add
Mux
ALU
Regs
D-Mem
SignExtend
ShiftLeft-2
200ps
70ps
20ps
90ps
90ps
250ps
15ps
10ps
a) [3 points] What would be the cycle time if you are designing a processor that only fetches
consecutive instructions (see Figure 1)? Show major steps in your computation.
Figure 1: Fetching instructions and incrementing the program counter (same as Figure 4.6 in the textbook)
b) [3 points] Consider a datapath in Figure 2, but for a processor that only has one type of
instruction: unconditional PC-relative branch. What would be the cycle time be for this
datapath? Show major steps in your computation.
Figure 2: MIPS architecture that supports different instruction classes (same as Figure 4.11 in the textbook)
c) [3 points] Now, we need to support only conditional PC-relative branches (see Figure 3).
Assume that the latency for AND gate is 0. What would be the cycle time be for this
datapath? Show major steps in your computation.
Figure 3: MIPS architecture that supports conditional branch (same as Figure 4.21 in the textbook)
2. Assume that the following breakdown shows the total time used by different executed
instructions. For example, the first column indicates that 20% of the total execution time is used
by all ‘add’ instructions in a program.
add
addi
not
beq
lw
sw
20%
20%
0%
25%
25%
10%
a) [3 points] What percentage of time the data memory is used?
b) [3 points] What percentage of time the output of the sign-extend circuit is needed?
3. 10101100011000100000000000010100 is an instruction word given. Assume that data memory
is all zeros and that the processor’s registers have the following values at the beginning of the
cycle in which the above instruction word is fetched:
r0
0
r1
-1
r2
2
r3
-3
r4
-4
r5
10
r6
6
r8
8
r12
2
r31
-16
Figure 4: Modified control and datapath handles jump instruction (same as Figure 4.24 in the textbook)
a) [3 points] What are the outputs of the sign-extend and the jump “Shift left 2” unit (near
the top of Figure 3) for this instruction word?
b) [3 points] What are the values of the ALU control unit’s inputs for this instruction?
c) [3 points] What is the new PC address after this instruction is executed?
d) [3 points] For each Mux, show the values of its data output during the execution of this
instruction with above register values. List the ones that are applicable (can be
determined based on the instruction) in this case. Please keep an entry blank if output of
a mux will not be used by this instruction.
RegDst Mux
ALUSrc Mux
MemtoReg Mux
Branch Mux
Jump Mux
e) [3 points] For the ALU and the two add units, what are their data input values? List the
ones that are applicable (can be determined based on the instruction) in this case.
ALU
Add (PC +4)
Add (Branch)
f) [3 points] What are the values of all inputs for the “Registers” unit? List the ones that
are applicable in this case (can be determined based on the instruction). You can keep it
blank if output of a mux will not be used.
RegWrite
Read register 1 Read register 2 Write register
Write data