Adjustable Front End Overvoltage Protection Controller with

NCP392A
Adjustable Front End
Overvoltage Protection
Controller with Protected
Vbus Output
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The NCP392A is an overvoltage front end protection and be able to
disconnect the systems from its output pin in case wrong input
operating conditions are detected, up to +28 V. Due to this device
using internal NMOS, no external device is necessary, reducing the
system cost and the PCB area of the application board.
Internal OVLO threshold is available, or can be adjusted if external
resistor bridge is used (A version).
At power up (EN pin = low level), the Vout turns on tstart time after
internal timer elapsed.
A LDO, internally connected on IN pin, provided a protected output
voltage even if an over voltage is present on IN pin.
MARKING
DIAGRAM
A
Y
WW
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Over−voltage Protection Up to + 28 V
On−chip Low RDS(on) NMOS Transistors: Typical 34 mW
Over−voltage Lockout (OVLO)
Externally Adjustable OVLO
Protected VBUS Indicator Output VBUS_DET
Internal 15 ms Startup Delay
100 ms Start Up Delay Option (B Version)
Shutdown EN Input
+ 86 V Surge Capability, in Compliance with IEC61000−4−5
Compliance to IEC61000−4−2 (Level 4)
8 kV (Contact)
15 kV (Air)
ESD Ratings:
Machine Model = B (200 V)
Human Body Model = 2 (2 kV)
CSP−12 package 1.3 x 2.0 mm, 0.4 mm Pitch
This is a Pb−Free Device
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN CONNECTION
1
2
3
4
/EN
OUT
OUT
PGND
B
VBUS
_D
OUT
IN
PGND
C
OVLO
IN
IN
PGND
A
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 9 of this data sheet.
Typical Applications
•
•
•
•
•
392AR
AYWW
G
WLCSP 12
FCC SUFFIX
CASE 567JM
Cell Phones
Tablets
Camera Phones
Digital Still Cameras
Personal Digital Applications.
QFN−16
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 3
1
Publication Order Number:
NCP392A/D
NCP392A
B3 IN
0.1 mF
NCP392A
OUT A2
C2 IN
OUT A3
C3 IN
OUT B2
OUTPUT
CHARGER
Lithium Battery
PMIC
C1 OVLO
GND
A4
GND GND
C4
B4
EN
A1
VBUS_D B1
VBUS_DET
/EN
Figure 1. Typical Application Circuit: NCP392A with Adjustable OVLO
FUNCTIONAL BLOCK DIAGRAM
INPUT
OUTPUT
Gate driver
OVLO
GND
selected
Charge
Pump
OVLO
TSD
R1
C1
External OVLO
VREF
Control
logic and
Timer
Internal OVLO
selected
R2
C2
OVLO
SEL
VIN
/EN
LDO
VBUS_DET
Figure 2. Functional Block Diagram: Version A
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2
/EN
NCP392A
PIN FUNCTION DESCRIPTION
1
2
3
4
/EN
OUT
OUT
PGND
B
VBUS
_D
OUT
IN
PGND
C
OVLO
IN
IN
PGND
A
(Top View)
Figure 3. Pinout
Table 1. NCP392 PIN DESCRIPTION
Pin
Pin
Name
Type
A1
EN
I/O
A2,
A3,
B2
OUT
OUTPUT
Output voltage pins.
These pins follow IN pins, with debounce time, when “no fault” are detected.
The outputs are disconnected from the Vin power supply when the input voltage is below UVLO,
above OVLO threshold or internal thermal protection is exceeded.
The three OUT pins must be hardwired together and used for power dissipation.
A4,
B4,
C4
PGND
POWER
Ground. The three GND pins must be hardwired together and connect to the system GND.
B1
VBUS_D
ET
OUTPUT
Vbus detect pin. This pin reflects Vin pin, and be in pass through mode up to regulation level. Upper
this trip, this output regulates IN voltage whatever OVLO event or /EN setting.
B3,
C2,
C3
IN
POWER
Input voltage pins.
These pins are connected to the power supply.
The three IN pins must be hardwired together.
C1
OVLO
INPUT
Description
Enable pin bar.
The device enters in shutdown mode when this pin is tied to a high level. In this case the output is
disconnected from the input.
To allow normal functionality, the EN pin is tied low with internal pull down.
This pin does not have an impact on the VBUS_DET.
External OVLO Adjustment. Connect external resistor bridge to OVLO pin to select a different OVLO
threshold. Connect OVLO pin to GND if not used. In this case internal OVLO will be selected.
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NCP392A
Table 2. MAXIMUM RATINGS
Symbol
Value
Unit
Minimum Voltage (IN, OVLO to GND)
Rating
VminIN
−0.3
V
Minimum Voltage (All others to GND)
Vmin
−0.3
V
VmaxIN
29
V
Maximum Voltage (OVLO to GND)
VmaxOVLO
14
V
Maximum Voltage (OUT to GND)
VmaxOUT
22
V
Maximum Voltage (VBUS_DET to GND)
Maximum Voltage (IN to GND)
VmaxVBUS
10
V
Maximum Voltage (All others to GND)
Vmax
7
V
Maximum DC current
Imax
4.5
A
Peak input current
Ipeak
8
A
Thermal Resistance, Junction−to−Air
RqJA
70
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Junction Operating temperature
TJ
+ 125
°C
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), model = 2 (Note 1)
Machine Model (MM) model = B (Note 2)
Vesd
15 kV air, 8 kV contact
2000 V
200 V
kV
V
V
Moisture Sensitivity
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
2. Machine Model, 200 pF discharged through all pins following specification JESD22/A115
Table 3. ELECTRICAL CHARACTERISTICS Min / Max limits values (−40°C < TA < +85°C and TJ = 125°C) and Vin = +5 V
(Unless otherwise noted). Typical values are TA = +25°C.
Characteristics
Input Voltage Range
Under voltage Lockout
Under voltage Lockout hysteresis
Internal Over voltage Lockout
threshold NCP392AR
Symbols
Conditions
Vin, VOVLO
Vin rising
UVLOhyst
Vin falling
OVLO
Vin rising (Note 3)
OVLO pin tied to GND
25°C
5.9
Vin falling
1.5
OVLOhyst
External OVLO Reference
OVLO_EXT
40
60
5.95
1.221
4
OVLOEXThyst
Vin falling
Unit
28
V
2.8
V
80
mV
6
2.5
%
1.26
V
20
V
2
0.3
V
Vin = 5 V, /EN = GND, –40°C < TJ < 125°C
34
50
mW
Supply Quiescent Current
Idd
No load. /EN = 0.4 V
90
200
mA
Standby Current
Istb
No load. /EN = 1.2 V,
No load on VBUS_DET
150
mA
100
nA
OVLO select leakage
0.2
%
RDSon
Vin versus Vout Resistance
OVLOSEL
Max
V
1.18
External Adjustable OVLO
External OVLO select
Typ
2.8
UVLO
Internal Over voltage Lockout
hysteresis
Over−Voltage Lockout Hysteresis
Min
IOVLO
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Please contact your ON Semiconductor representative for additional OVLO threshold.
Electrical parameters are guaranteed by correlation across the full range of temperature.
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4
NCP392A
Table 3. ELECTRICAL CHARACTERISTICS Min / Max limits values (−40°C < TA < +85°C and TJ = 125°C) and Vin = +5 V
(Unless otherwise noted). Typical values are TA = +25°C.
Characteristics
Symbols
Conditions
Min
VBUSTHRES
Vin > VBUSTHRES
Vin < VBUSTHRES, I load 1 mA
Typ
Max
Unit
6.5
9
V
Vin – 0.2
Vin
V
VBUS_DET (A Version)
VBUS_DET Regulation
VBUS_DET Pass Through
VBUS_DET ron
LDORON
VBUS_DET Current
60
W
1.5
mA
LOGIC
EN Voltage High
Vih
EN Voltage Low
Vil
EN Pull−down
1.2
V
0.4
ENpd
V
100
kW
TIMINGS
tSTART
From Vin > 2.8 V to 10% Vout, /EN low
15
ms
tEN
Vin present, From /EN high to low, 10% Vout
15
ms
Soft start
tRISE
From 10% to 90% of Vout, C load 100 mF,
Rload, 100 W, /EN low
1
ms
VBUS_DET rise time
tVBUS
/EN low, From Vin applied to 90%
VBUS_DET, 4.7 mF load
Turn off time
tOFF
Surge off time
tDIS
tOVLO
Start up Time
Enable time
Disable time
OVLO turn off time
2
ms
100
ns
From EN >1.2 V to 90% Vout. No load
20
ms
Vin rising 2 V/ms
1.5
ms
TSD
140
°C
TSD rearm
115
°C
TSD
Thermal shutdown
Thermal shutdown rearming
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Please contact your ON Semiconductor representative for additional OVLO threshold.
Electrical parameters are guaranteed by correlation across the full range of temperature.
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5
NCP392A
Operation
Over−voltage Lockout (OVLO)
The NCP392A provides over−voltage protection for
positive voltage surge, up to +28 V. An additional clamp,
between IN and GND, protects the part against surge test,
following IEC 61000−4−5 standard. A protected
VBUS_DET output pin provides a secondary supply for the
application biasing.
To protect connected systems on Vout pin from
over−voltage, the device has a built−in over−voltage lock
out (OVLO) circuit. During over−voltage condition, the
output remains disabled until the input voltage is above
OVLO – hysteresis.
Under−voltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in under−voltage lock out (UVLO)
circuit. This circuit has a built−in hysteresis to provide noise
immunity to transient conditions.
VIN
OVLO
UVLO
VBUS DET
VBUSTHRES
90%
VOUT
/EN
tVBUS
tOFF
tSTART
tRISE
tSTART
tRISE
tSOFT
tSOFT
Figure 4. UVLO, OVLO and /EN Functionality
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6
tVBUS
tOFF
NCP392A
INPUT
To select the internal OVLO threshold, the OVLO pin
must be externally tied to GND.
R1
GND
Internal OVLO
selected
OVLO
R2
C2
C1
External OVLO
selected
VREF
SEL
VIN
LDO
VBUS_DET
Figure 6. External Connection to Resistor Bridge of
OVLO
Figure 5. External Connection to GND of OVLO
Example:
OVLO target 12 V.
If OVLO pin is not grounded, and by adding external
bridge resistor on OVLO pin, between IN and GND,
overvoltage protection can be adjusted as following:
NEW_OVLO TH +
OVLO EXT
R1 ) R2
R2
R1 + R2
ǒOVLO
* 1Ǔ + R2 ǒ 12 * 1Ǔ + 8.828
1.221
1.221
(eq. 2)
R2
Taking into account external input bridge doesn’t have
excessive current consumption, and 1% is recommended:
(eq. 1)
R2 arbitrarily fixed at 1.05 MW.
R1 = 9.269 MW (9.31 MW standard value)
Obtained typical OVLO = 12.04 V
C1 and C2 should be selected in such a way that the time
constant R1C1 = R2C2.
With: OVLOEXT = 1.221 V Typical (OVLO External
Reference)
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7
NCP392A
VIN
OVLO
UVLO
TSD
VBUS DET
VBUSTHRES
90%
VOUT
90%
10%
OVLO
/EN
tSTART
tDIS
tVBUS
tRISE
tDIS
tSTART
Figure 7. OVLOEXT, TSD Modes
EN Inputs and Production Mode
Thermal Shutdown Protection
To enable normal operation, the EN pin has to be at low
level. Internal pull down is embedded in the part.
A high level on the pin, disconnects OUT pin from IN pin.
In case of internal overheating, the integrated thermal
Inputs shutdown (TSD) protection allows to open the
internal MOSFET in order to instantaneously decrease the
device temperature.
Embedded hysteresis allows to reengage the MOSFET
when the junction temperature decreases.
If the fault event is still present, the temperature increases
again and engages the thermal shutdown one more time until
fault event disappeared.
Table 4. CONTROL LOGIC MODES
OVP State
NCP392Ax
/EN
OVLO EXT
Low
High
Low
ON Tstart
15 ms
OFF
High
OFF
OFF
PCB Recommendations
To limit internal power dissipation, PCB routing must be
carefully done to improve current capability.
The NCP392A is declined in a CSP package. So power
dissipation can be decreased on each pin connection but
main thermal area must be as large as possible around IN and
OUT pins. Taking into account and respectively, four IN and
OUT pins must be hardwired together on the PCB.
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8
NCP392A
Maximum power dissipation can be calculated with
following formula:
T J * T A + R qJA
(eq. 3)
Pd
TJ: junction temperature
TA: ambient temperature
RqJA: thermal resistance of the junction to air through the
case and board.
Pd: power dissipation = RDS(on) x I2
ESD Tests
The NCP392A fully supports the IEC61000−4−2, level 4
(Input pin, 1 mF mounted on board).
That means, in Air condition, Vin has a ±15 kV ESD
protected input. In Contact condition, Vin has ±8 kV ESD
protected input.
Please refer to the Figure 8 to see the IEC 61000−4−2
electrostatic discharge waveform.
Figure 8. Ipeak = f(t) / IEC61000−4−2
ORDERING INFORMATION
Device
NCP392ARFCCT1G
Marking
Package
Shipping†
392AR
WLCSP
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCP392A
PACKAGE DIMENSIONS
WLCSP12, 1.3x2.0
CASE 567JM
ISSUE A
PIN A1
REFERENCE
0.10 C
2X
ÈÈ
ÈÈ
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
DIE COAT
(OPTIONAL)
A3
D
DIM
A
A1
A2
A3
b
D
E
e
DETAIL A
0.10 C
2X
TOP VIEW
A2
DETAIL A
MILLIMETERS
MIN
MAX
−−−
0.60
0.17
0.23
0.36 REF
0.04 REF
0.24
0.30
1.26
1.31
2.01
2.04
0.40 BSC
A
0.10 C
RECOMMENDED
SOLDERING FOOTPRINT*
0.08 C
SIDE VIEW
NOTE 3
A1
C
SEATING
PLANE
PACKAGE
OUTLINE
A1
e/2
e
12X
b
0.05 C A B
0.03 C
12X
0.40
PITCH
e
C
B
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
A
1
2
3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
4
BOTTOM VIEW
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
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PUBLICATION ORDERING INFORMATION
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10
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP392A/D