Origami Designer™

Product Brief
embedded Programmable Logic
Origami Designer™
Automating the Design and Implementation of Custom Programmable Logic Architecture
Menta® Origami Designer™ is the first complete design environment that allows designers to create
Custom Programmable Logic Architectures (CPLA). Origami Designer dramatically accelerates the design
of programmable accelerators through automated software design tools, RTL and scripts generation
from a single high-level specification. These application-specific programmable logic architectures are
increasingly essential to support the convergence of multiple functionalities all on a single System-onChip (SoC). This makes them ideal for use in a wide variety of applications including networking,
baseband, security, video, audio, control and industrial automation applications.
With the constant drive towards more integrated
devices that perform a variety of functions and support
multiple standards, flexibility and programmability is
becoming the buzzword of today’s design teams. These
teams are tasked with developing products that can
deal with growing performance demands, consume as
little power as possible and can process parallel
functions for real time applications all while meeting
time-to-market pressure. While enabling performance
and low power, in a lot of cases fixed hardware blocks
are inadequate because of their lack of flexibility,
reusability and ability to deal with multiple modes and
standards. For a lot of specific tasks standard,
application-specific and DSP processors have challenges
of their own in terms of meeting the performance and
power consumption requirements.
Figure 1: Origami Designer™ environment
There is where custom programmable logic architectures are saving the day. Their unique ability to offer flexibility
and high performance through software programming while limiting overhead makes them the ultimate trade-off
between flexibility, area and power. CPLA have the added benefit that they provide post-manufacturing flexibility
to reduce the verification effort by decoupling the hardware verification and the functional verification.
Origami Designer gives designers the ability to define, analyze, build and validate the target capacity,
performance, interconnect density and programming method by providing full control over the parameters of the
Menta eFPGA Core® technology. As part of a complete foundry-independent methodology, Origami Designer
enables embedded-FPGA configurability for any SoC or ASIC, on any process technology.
Key Benefits
Rapid design of custom
programmable logic architecture
Unique architecture
optimizations for differentiated
solutions and high-performance
TCL script for batch-mode
processing
Graphical User Interface for
accurate design entry
Foundry independent
methodology
Introduction
Origami Designer creates the eFPGA
Core IP best suited to exactly match
the application needs. Its Graphical
User Interface (GUI) assists the
designer through the definition of
the “tile” (the main building
components of the Menta eFPGA
Core IP technology), and core
parameters such as capacity, size,
aspect ratio and process constraints
(technology, target performance,
target power consumption).
Origami Designer contains all the
tools necessary to build, view,
generate and analyze highperformance custom programmable
logic architectures.
Origami Designer embed the design
software environment (Menta
Origami™)
and enables
the
beginning of application design
development
prior
to
the
availability of silicon, and the very
fast execution and validation of
large amounts of application code.
Based on bottom-up approach,
Origami Designer firstly builds and
Origami Designer
configures “tiles” of the Menta
eFPGA Core IP technology.
Builder
scripts for the silicon flow, and the
Origami DB dedicated to the Menta
Origami
design
software
environment tool.
Scripts are fully compliant with
third-party tools and automate
established flows to generate GDSII
of the architecture. At the end of
this flow, all the necessary
information required to embed the
eFPGA Core IP into the target SoC is
generated.
The Builder wizard helps designers
create and define the “tiles”
parameters,
core
size
and
programmable interconnect.
The “tile” component integrates
block, local and global interconnect.
eLB (embedded Logic Block) is the
block used by default, but
arithmetic operator or custom block
(eCB) and memory (eMB) can be
integrated. For silicon performance,
architecture allows a single type of
block per column.
Viewer
Analyzer
The Analyzer is used to investigate
parameters of the architecture with
the customer application or with a
set of applications (benchmarks).
It also provides a way to visualize
and analyze simulation results and
rapidly compare alternative silicon
implementations of “tiles” or core.
Availability
The Viewer shows full details of the
entire architecture that was
generated by the Builder wizard.
Generator
The Generator creates all the
necessary HDL of the CPLA, EDA
The Menta Origami Designer
environment is now available on
Red Hat Linux X86 64-bit platform.
It comes with an eFPGA Design Kit
including library and core samples
as Starter Kit.
For more information about Menta
products or support services, visit
us on the web at: www.menta.fr or
contact sales@menta.fr.
2
June 2012, Rev. 2
Menta SAS ∙ Cap Omega ∙ CS39521 ∙ Rond-Point Benjamin Franklin ∙ 34960 Montpellier Cedex 2 ∙ France
© 2012 Menta SAS. All rights reserved. eFPGA Creator, eFPGA Core, eFPGA Programmer, Menta and the Menta logo are registered trademarks of
Menta SAS. Origami and Origami Designer are trademarks of Menta SAS. All other trademarks and tradenames are the property of their respective holders.