My CV - Circuits Systems - Imperial College London

My CV - Circuits Systems - Imperial College London

Felix Winterstein
Electrical Engineer, Dipl.-Ing.
Í
Electrical and Electronic Engineering
Imperial College London
London SW7 2BT, United Kingdom
H +49-176-61262087
B f.winterstein12@imperial.ac.uk
http://cas.ee.ic.ac.uk/people/fw1811
Profile
I am a PhD candidate in the Circuits and Systems Group at Imperial College London. My research
concerns digital computation using FPGAs and focuses on high-level synthesis techniques. I am
particularly interested in the optimisation of the memory system for high-level synthesis of programs
using dynamic, pointer-based data structures. My main research focuses on program analyses
leveraging separation logic, a theory for reasoning about the behaviour of programs that currently
finds its main application in modern formal verification tools. I also work as an engineer at the
European Space Agency since 2010. I have professional experience in radar and space communication
systems, ground station engineering, radio frequency electronics and signal processing.
Employment History
06/2012 – Systems Engineer, European Space Agency, Germany.
Present Projects (contractor for Serco Services GmbH / Imperial College London):
{ Supporting the developments of space surveillance radars for ESA’s Space Situational
Awareness Initiative; Specifying performance requirements for a forthcoming operational
surveillance system, participating in design reviews and acceptance testing
{ Development of a new ground station for ESA’s OPS-SAT satellite mission
{ Supporting the CCSDS standardisation of simultaneous bandwidth-efficient telemetry
modulation and ground-space ranging techniques
Research (networking/partnering agreement with Imperial College London):
{ Reconfigurable hardware design for radar signal processing applications
{ Reliable reconfigurable FPGA-based on-board processors
{ Electronic design automation, high-level synthesis
06/2010 – Trainee, European Space Agency, Germany.
05/2012 { Employed through the German Trainee Programme funded by the German Aerospace
Agency / Federal Ministry for Economic Affairs and Energy
{ Developed (in a team of five) a fully functional experimental small-scale phased array
radar from scratch
{ Supported the development of a phased array space surveillance radar for the Space
Situational Awareness Preparatory Programme; Participated in design reviews
03/2009 – Diploma Thesis and Post-Graduate Assistant, Institute for Communication
05/2010 Technologies and Embedded Systems, RWTH Aachen, Germany.
{ Development of an application-specific instruction set processor IC for multiple-input
multiple-output (MIMO) demapping (Sphere Decoding)
{ Thesis entitled “Efficient Memory Architectures for Flexible MIMO Demapping” (thesis
mark: 1.0/4.0, 1.0 being the best achievable mark)
06/2008 – Intern, Infineon Technologies Asia Pacific, Singapore.
12/2008 { Developed a bootstrap loader tool for firmware uploads on Infineon’s 8bit and 32bit
microcontroller families via UART and CAN interfaces
{ Authored four application notes
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09/2000 – Software Developer (part-time), Riemer Communication Systems, Germany.
09/2001 Development of a multimedia control system deployed in the Audi Forum in Germany
Education
2012 – PhD Candidate, Imperial College London, United Kingdom.
Present { Supervisor: Prof. George A. Constantinides
{ Research topics: High-level synthesis targeting FPGAs, memory system optimisations,
program analyses and compilers leveraging separation logic, cache architectures
{ Research partly funded by the European Space Agency through the Networking/Partnering
Initiative
2003 – 2009 German Diploma in Electrical Engineering, RWTH Aachen University, Germany.
{ Level in international classification: ISCED 5A (Master)
{ Principal subjects: Information and communication engineering
{ Final grade: very good, 1.4/4.0 (1.0 being the best achievable mark)
Languages
German Native language
English Full professional proficiency (TOEFL score: 113/120)
French Intermediate
Awards and Grants
2012 ESA Networking/Partnering Initiative - PhD scholarship, European Space Agency,
09/2012 – Present
2012 Distinction awarded at the International Radar Symposium 2012 for the paper “Scalable Front-End Digital Signal Processing for a Phased Array Radar Demonstrator”
2010 German Trainee Programme - Stipend for a traineeship at ESA, German Aerospace
Agency / Federal Ministry for Economic Affairs and Energy, 06/2010 – 05/2012
2009 Texas Instruments Diploma Award for the diploma thesis “Efficient Memory Architectures for Flexible MIMO Demapping”, TI European University Program
2006 Prof. Dr. Koepchen Studienstiftung - Industrial scholarship (RWE AG), 02/2006 –
09/2007
Activities in the Research Community
{ Program committee member for the IEEE International Symposium on Parallel
and Distributed Processing with Applications (ISPA) 2015
{ Reviewer for international conferences in FPGA-related research (FPL, ISCAS)
{ Maintainer of an open source case study: Implementations and comparisons of
K-means clustering algorithms in C++, C++-based high-level synthesis and
VHDL (https://github.com/FelixWinterstein/Vivado-KMeans)
References
References available upon request.
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Publications
Journals
J.1 F. Winterstein, S. Bayliss, G. Constantinides: “Separation Logic for High-Level
Synthesis,” ACM Trans on Reconfigurable Technology and Systems, 2015 (invited).
(submitted)
Conference Proceedings
C.1 F. Winterstein, K. Fleming, H.-J. Yang, S. Bayliss, G. Constantinides: “MATCHUP:
Memory Abstractions for Heap Manipulating Programs,” ACM/SIGDA Int. Symposium on Field-Programmable Gate Arrays (FPGA), 2015. [acceptance rate 26%]
C.2 F. Winterstein: “Simultaneous Transmission of GMSK Telemetry and PN Ranging:
Measurement Report in Support of the Draft CCSDS Recommendations 401(2.4.22A)
and 401(2.4.22B),” Fall Meeting of the Consultative Committee for Space Data
Systems (CCSDS), 2014. [acceptance rate unknown]
C.4 F. Winterstein, S. Bayliss, G. Constantinides: “Separation Logic-Assisted Code
Transformations for Efficient High-Level Synthesis," IEEE International Symposium
on Field-Programmable Custom Computing Machines (FCCM), 2014. (best paper
candidate) [acceptance rate 16%]
C.5 F. Winterstein, S. Bayliss, G. Constantinides: “High-Level Synthesis of Dynamic
Data Structures: A Case Study Using Vivado HLS," International Conference on
Field-Programmable Technology (FPT), 2013. [acceptance rate 21% (46% short)]
C.6 F. Winterstein, S. Bayliss, G. Constantinides: “FPGA-based K-means Clustering
Using Tree-Based Data Structures," International Conference on Field Programmable
Logic and Applications (FPL), 2013. [acceptance rate 23%]
C.7 F. Winterstein, G. Sessler, M. Montagna, M. Mendijur, G. Dauron, P. Besso: “Scalable Front-End Digital Signal Processing for a Phased Array Radar Demonstrator,"
International Radar Symposium (IRS), 2012. (received distinction) [acceptance
rate unknown]
C.8 G. Sessler, M. Martinez, M. Montagna, A. Martin, F. Winterstein, G. Dauron, P.
Besso: “Design and Implementation of a Low Power Mini-Radar Demonstrator,"
European Space Surveillance Conference (ESSC), 2011. [acceptance rate unknown]
Book Chapters
B.1 S. Fleming, D. Thomas, F. Winterstein: “A Power-Aware Adaptive FDIR Framework using Heterogeneous System-on-chip Modules," to appear as a book chapter
in FPGAs and Parallel Architectures for Aerospace Applications, Springer, August
2015, ISBN 978-3-319-14351-4.
Posters
P.3 E. Aguilar Pelaez, S. Bayliss, A. Smith, F. Winterstein, D. Ghica, D. Thomas,
G. Constantinides: “Compiling Higher Order Functional Programs to Composable
Digital Hardware," IEEE International Symposium on Field-Programmable Custom
Computing Machines (FCCM), 2014.
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