Architecture des Systems-on-Chip y p

Architecture des Systems-on-Chip
y
p
—
Introduction
paolo.ienne@epfl.ch
EPFL – I&C – LAP
Who’s
Who
s Who
 Lecturer: Paolo Ienne
 Student Assistants (labs)
 Assistants (labs):
Ana Petkovska
Grace Zgheib
Everybody is reachable at Name.Surname@epfl.ch
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ArchSoC — © Ienne 2015
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52% / year:
Architecture!
processor
performance
~20% / year:
technology
(= transistor speed)
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Sourrce: Hennessyy & Patterson
n, © MK 2011
1
Computer Architecture Rocks!
Content of ArchSoC
Part I: Computer Organization
What is around a processor to make a full computer?
How the p
processor exchanges
g information with the
rest of the world?
Part II: Increasing Performance
What makes a good processor? How real processors
achieve
hi
ever increasing
i
i performances?
f
?
Pa t III:
Part
III M
Multiprocessing
ltip ocessing
What are the challenges of connecting many
processors together? What will change from the
single processor system?
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Textbooks for ArchSoC
 Wakerly, Digital Design (DD), Prentice Hall
 You may have it already from Systèmes Logiques
 Available from LibPoly at a special price
 Ashenden, The VHDL Cookbook (VHDL)
 On the web
THE TEXTBOOK
 Patterson & Hennessy. Computer
Organization
g
& Design
g ((COD))
4th edition, revised printing, MK 2011
 Available from LibPoly at a special price
 The older 2nd, 3rd, and 4th editions are ok, too
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Schedule
Schedule on the web
http://lap.epfl.ch/archsoc/
Courses
ELA1: Wednesdays 11am-1pm
Lab Sessions
INF2/INF3: All Fridays 1-3pm
Additional lab time for personal work
INF2/INF3: All Fridays 3-5pm
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Architecture des Systems-on-Chip
Informatique (SIN) et Systèmes de Communication (SSC)
Printemps 2015
Sem.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Date
Heure
Me 18.02.14 11h - 13h
Thème
Salle
ELA1
Théorie
Presentation + Inputs and Outputs
Ve 20.02.14 13h - 15h INF2/INF3
Me 25.02.14 11h - 13h
ELA1
Travaux Pratiques
FPG4U Tutorial + Nios II Assemby Language + Lab Submission System
Inputs and Outputs + Exceptions
Ve 27.02.14 13h - 15h INF2/INF3
Me 04.03.14
04 03 14 11h - 13h
ELA1
Timer in VHDL Simulated in ModelSim
Exceptions
Ve 06.03.14 13h - 15h INF2/INF3
Me 11.03.14 11h - 13h
ELA1
Timer Interrupt Handler in Simulation
Example of Interrupt Support in a CPU
Ve 13.03.14 13h - 15h INF2/INF3
Me 18.03.14 11h - 13h
ELA1
Interrupt Management for Nios II and Test on FPGA4U
Examples of Interrupts and Exceptions
Ve 20.03.14 13h - 15h INF2/INF3
Me 25.03.14 11h - 13h
ELA1
UART Communication on FPGA4U (I)
Increasing Performance (I) -- Introduction and Basic Pipelining
Ve 27.03.14 13h - 15h INF2/INF3
Me 01.04.14 11h - 13h
ELA1
UART Communication on FPGA4U (II)
Increasing Performance (II) -- Pipelining
Ve 03.04.14 13h - 15h INF2/INF3
Me 15.04.14 11h - 13h
ELA1
No labs (Good Friday)
Increasing Performance (III) -- Dynamic scheduling
Ve 17.04.14 13h - 15h INF2/INF3
Me 22.04.14 11h - 13h
ELA1
Pipelining of an Arithmetic Unit (I)
Increasing Performance (IV) -- Examples of Scheduling
Ve 24.04.14 13h - 15h INF2/INF3
Me 29.04.14
29 04 14 11h - 13h
ELA1
Pipelining of an Arithmetic Unit (II)
Increasing Performance (V) -- Superscalar and VLIW
Ve 01.05.14 13h - 15h INF2/INF3
Me 06.05.14 11h - 13h
ELA1
Pipeline Simulation
Case Studies -- IA-32 and IA-64
Ve 08.05.14 13h - 15h INF2/INF3
Me 13.05.14 11h - 13h
ELA1
Pipelined Processor Design (I)
Multiprocessors (I) -- Cache Coherence
Ve 15.05.14 13h - 15h INF2/INF3
Me 20.05.14 11h - 13h
ELA1
Pipelined Processor Design (II)
Multiprocessors (II) -- Memory Consistency
Ve 22.05.14 13h - 15h INF2/INF3
Me 27.05.14 11h - 13h
ELA1
Ve 29.05.14 13h - 17h INF2/INF3
Pipelined Processor Design (III)
Exercises
Final test
Slides
 Available on the web
http://lap.epfl.ch/archsoc/
 Mostly available now, but there could be late updates—and
they will be clearly indicated on the web
 No paper copy distributed (if you need them, print lab
documents before coming to the lab sessions!)
 Please avoid printing in colour: slides will be readable in B/W
(if not,
not let me know!)
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Board
All labs use the FPGA4U board
 The board is sold for 100 CHF (value ~300 CHF!)
 This gives you the possibility of continuing the labs at home
home—
and of doing many other personal projects, if you so wish
 Pay at the Post Office (not via Internet, please) with the
b ll ti de
bulletin
d versementt, then
th collect
ll t the
th board
b d from
f
the
th HelpDesk
H l D k
(INF117)
…-2011
2012-…
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Introduction to the Labs
 Please all come to the first lab session (at least, if you plan on
doing at least one lab this semester…):
20th February
F b
2015,
2015 1pm-3pm
1
3
 Interactive tutorial to the FPGA4U board and the tools,
complete system setup with TAs available, test of the lab
submission system, etc.
 Essential for not getting lost in silly problems during the following
labs!
 If you plan to use your laptop, install ModelSim and Quartus II
before the first lab (see http://fpga4u.epfl.ch)
http://fpga4u epfl ch)
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Helpdesk and Q&A Forum
 FPGA Helpdesk
 To get your FPGA4U board
Thursdays, 1pm-2pm, INF117
 Q&A Forum
http://moodle.epfl.ch/course/view.php?id=14153
(Help Forum of Moodle, enrolment key ArchSoC_1415)
 Should provide answers to FAQs and a way to get help
efficiently, from both TAs and colleagues
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Final Evaluation and Grading
 Labs (every week):
 Automatic evaluation (info during the first lab)
 Deadline (strict!) for submitting lab solutions is midnight of the day
before the start of the next lab (hence, usually one week or two after
the lab started)
 Individual,
Individual hence no identical submissions allowed
 Different weights for the different labs
 Max 20% bonus (= over the average test grade), proportional to the
f
fraction
i off correct llabs
b
 All labs fully correct to get full bonus (= no absences, etc.)
 Final test (4h):
( )
 29th May 2015, 1pm-5pm
 Room INF2-INF3
 Books,
B k notes,
t
exercises
i
are permitted
itt d
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Exercise Book
 Soon to be available on the web
http://lap.epfl.ch/archsoc/
 Mostly, a collection of old exam questions with full
solutions (for almost all exercises)
 If you want to know how well you are prepared for the
tests, do some exercises from there
 Some of the in-class exercises (3-4 sessions) are also
((modified)) exam questions
q
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On Your Mark!…
Mark! Get Set!
Set!… Go!
Any info missing? Ask now…
now
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