Study of Cracking of Thin Glass Interposers Intended for

Study of Cracking of Thin Glass Interposers Intended for Microelectronic Packaging Substrates
Scott R. McCann1,2, Yoichiro Sato3, Venkatesh Sundaram1,4,
Rao R. Tummala1,4,5, and Suresh K. Sitaraman1,2,*
1
3D Systems Packaging Research Center
Georgia Institute of Technology
Atlanta, GA 30332
2
The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology
3
Asahi Glass Co., Ltd., Tokyo, Japan
4
School of Electrical and Computer Engineering, Georgia Institute of Technology
5
School of Materials Science and Engineering, Georgia Institute of Technology
*contact email: suresh.sitaraman@me.gatech.edu
Abstract
Glass interposers have gained increased attention and
interest in microelectronics industry since 2010. This is
because glass has a tailorable coefficient of thermal expansion
(CTE), high mechanical rigidity, availability in large and thin
panel form, low processing cost, smooth surface for fine line
and space fabrication, and superior electrical properties.
While thin glass panels offer such a plethora of benefits, there
are several processing and reliability challenges that glass
imposes. As a brittle material, glass has low fracture
toughness and is prone to cracking.
In a typical large-area glass panel processing, layers of
dielectric polymers and conducting copper are sequentially
deposited and patterned. Due to these temperature histories
and difference in the CTE among different materials, the
panel is subjected to process-induced residual stresses. When
the panel is subsequently diced into smaller substrates, the
glass could crack. This cracking is due to high residual
stresses as well as dicing defects and possible delamination at
the polymer-glass interface.
This experimental and theoretical work aims to investigate
thin glass cracking and understand the mechanics of such
cracks, focusing on the stresses induced by build-up layers.
As part of this work, glass panels of 150 x 150 mm size and
100 μm thickness were laminated on both sides with ZS-100
polymer of 10 – 22.5 μm thickness and cured. After the
lamination process, 5 – 10 μm thickness of copper is then
deposited through a semi-additive electroless and electrolytic
plating processes. This process of polymer and copper are
repeated to create a total of two metal layers on each side of
the panel. The panel is then diced into 18.4 x 18.4 mm
substrate coupons. Dicing defects are characterized using
optical inspection. Cracking failures are documented. The
unbroken substrates are thermal cycled between -40 and 125
°C.
In parallel to the experimental investigation, numerical
models are created based on the sequential fabrication
process. Copper material properties are obtained from
literature as well as from in-house nanoindentation tests.
Polymer properties are obtained from vendor data, and the
stress-free temperature is obtained through experiments.
Dicing process is simulated by inserting a vertical crack
through the panel, and various dicing defects are introduced in
the singulated substrate.
Energy available for crack
propagation of such defects is determined through fracture
978-1-4799-8609-5/15/$31.00 ©2015 IEEE
mechanics approach, and design guidelines to mitigate glass
fracture during dicing and reliability testing are explored.
Introduction
Glass has gained traction recently as a possible candidate
for microelectronic packaging substrate [1, 2]. This is
because of some of its electrical and mechanical properties as
well as its low cost potential [3]. In comparison to organics
such as FR-4, glass is rigid, has a high glass transition
temperature and tailorable CTE, provides a smooth surface for
fine line lithography [4], and also provides good structural
support. All of these properties lead to lower warpage [5] and
fine pitch I/Os [6] while keeping the package thin. Glass is an
electrical insulator with very low electrical loss and high
resistivity. However, glass has poor thermal conductivity, and
thus, thermal management should be addressed through other
means such as through glass vias [7]. Also, glass is a brittle
material that is prone to cracking.
Sequential deposition and thermal processing of polymer
and copper is carried out on glass panels to create glass
interposers for microeletronic packages. These build up
materials have different CTEs, creating thermo-mechanical
stresses. Once fabricated, glass panels must be separated into
individual interposers through dicing. Such singulation or
dicing could create large enough defects, that when combined
with stresses from redistribution layers (RDL), could lead to
crack propagation ultimately resulting in glass interposer
cracking.
The goal of this work is to investigate why singulated
glass interposers crack during dicing or subsequent thermal
exposure. This paper also discusses options for reducing such
cracks, and explores one such option in detail.
Fabrication, Dicing, and Reliability Testing
Glass interposers are fabricated using clean-room
processes applicable to substrate fabrication. Fabrication
begins with a 150 x 150 mm bare glass panel, which is
cleaned and laminated with a layer of 10 – 22.5 μm polymer,
ZEONIFTM ZS-100. The polymer is cured in a thermal oven
at 180 ºC. Copper traces are deposited through semi-additive
processes, which starts with an electroless copper seed layer,
on top of which dry film photoresist is laminated. The
photoresist is exposed and developed, and copper is then
electroplated. The photoresist is then stripped and the seed
layer is removed through etching, leaving 5 – 10 μm of
copper, which is then annealed. This process is two sided,
creating layers of polymer and copper traces on both sides
1938
2015 Electronic Components & Technology Conference
simultaneously. The processes are repeated to add a second
layer of ZEONIF ZS-100 and copper traces on each side, for a
total of four metal layers, which constitute the RDL. Finally,
a dry film passivation is laminated, exposed, developed, and
cured. Each panel has a six by six array of 18.4 x 18.4 mm
interposers.
Dicing is then used to singulate the glass panel into
individual interposers, producing the structure seen in Figure
1, which shows an expanded schematic of a four metal layer
glass interposer. For this work, dicing is done using blade
dicing, though other options such as score and break, laser
dicing, and laser ablation are available. For more information
on the dicing process and optimization, see Wei’s work [8].
In early test cases, cracking from the diced edge, through the
glass core, occurred immediately after dicing. This is while
samples are still in the dicing tool, attached to the tape.
However, not all fabricated panels exhibit this failure, and the
uncracked panels proceed to reliability testing. Such glass
cracking upon dicing has been reported by Koizumi, who
terms the cracking failure from the free edge “SeWaRe” [9].
Figure 1: Schematic of four metal layer glass interposer.
For samples that did not crack immediately upon dicing,
the surface roughness along the diced edge is measured using
confocal microscopy. Data measured is shown in Figure 2.
The original or “unoptimized” blade shows the maximum
surface roughness. With subsequent improved or “optimized”
dicing conditions, the surface roughness became smaller. The
maximum roughness value measured is treated as the largest
defect or flaw size present in the material. Such locations of
maximum surface roughness are the prime locations for crack
propagation.
Surface Roughness [um]
35
30
25
20
15
10
5
0
Unoptimized Initial Blade Pulsed Laser BKM Blade
Blade (Bare Optimization Dicing
(Disco)
Glass)
(Disco)
(Disco)
Reliability testing includes preconditioning and
temperature cycling testing (TCT). For preconditioning, there
are three steps: bake, moisture soak, and reflow. Bake is done
at 120 °C for 24 hours. For the moisture soak, moisture
sensitivity level 3 (MSL-3) from JEDEC™ Standard 020D.1
(60% RH at 30 ° C for 168 hours) is used [10]. However, the
available humidity chamber was not capable of achieving the
temperature target while maintaining the required humidity
level, so the temperature was kept at about 43 °C, making the
test conditions somewhat more rigorous than normal MSL-3.
Reflow is done three times with a peak temperature of 260 °C.
The time limits given in JESD22-A113F, the JEDEC Standard
on Preconditioning of Non-hermetic Surface Mount Devices
Prior to Reliability Testing [11], are followed. After
preconditioning, temperature cycling of -40 to 125 °C in onehour cycles with fifteen minute ramp times and fifteen minute
dwells was performed, following test condition G in JESD22A104D, the JEDEC Standard on Temperature Cycling [12].
Samples were inspected at the end of processing, after
preconditioning, after 50, 250, 500, and 1000 thermal cycles.
Inspection was done using an optical microscope to inspect
the edges and a C-mode scanning acoustic microscope
(CSAM). From this inspection, crack progress, if any, was
documented and analyzed.
Initial Experimental Data
The first set of samples was fabricated, diced, and
reliability tested, as described in the Fabrication, Dicing, and
Reliability Testing section. Figure 1 shows a schematic of the
glass interposers fabricated and the details are presented in
Table I. These samples had two polymer and two copper
layers on each side of the substrate. Each polymer layer was
22.5 μm thick, and each copper layer was 10 μm thick.
The experimental results after dicing, preconditioning, and
50 temperature cycles are shown in Table II where this first
set of samples is designated with a prefix 1. The samples are
classified by using stop light colors as status indicators.
Green indicates the expected signature after dicing, usually a
pock mark pattern for blade dicing of glass, seen in Figure 3a.
Yellow is worse than green and indicates interface failure;
Figure 3b shows an example of interface failure. In some
cases, interface delamination occurs, as in the figure, while in
other cases, it does not, making it difficult to systematically
measure the amount of interfacial delamination. While CSAM is used, the amount of interfacial delamination is usually
below the resolution of the available tool, making it difficult
to collect meaningful data. Red means cracking of glass and
an example is shown in Figure 3c.
As described in Table II, the samples, 1-A4 and 1-A5, did
not fail after dicing, showed some interfacial delamination
after preconditioning, and the glass substrate cracked after 50
temperature cycles, the first inspection point during TCT. For
the samples to pass the reliability criteria, they need to survive
1000 thermal cycles. To achieve this, numerical models were
developed to help understand the problem and design a
solution, and based on the findings from the numerical
simulations, new samples were built.
Figure 2: Surface roughness of different dicing methods as measured
using confocal microscopy.
1939
Table I: Details for initial samples fabricated for model validation.
Metal Layers
Glass Thickness [μm]
Polymer Thickness [μm]
Copper thickness [μm]
Passivation thickness [μm]
Some researchers often use the glass transition temperature as
the reference temperature in their simulations [13]. It should
be mentioned that this type of matching the curvature (or
warpage) to determine the reference temperature should be
treated with caution, as the modulus, Poisson’s ratio, and CTE
of the polymer and the glass were not directly measured in
this work; rather they were obtained from vendor datasheets.
Similar to the polymer reference temperature, the
reference temperature for annealed copper was obtained using
curvature measurements of a glass substrate with two sides of
polymer and one side of electroless and electroplated copper
followed by annealing at 180 °C. When warpage (or
curvature) measurements were done at room temperature and
compared against simulations, it was seen that a reference
temperature of 108 °C was applicable to copper. This
reference temperature was validated using two different
configurations where one configuration had a 100% copper
plating on top of the polymer layer, while the second
configuration had an 80% patterned copper on top of the
polymer layer. The details of copper layout and the measured
warpage contours are presented in Fig. 4. The reference
temperature details are shown in Table III.
It is seen that copper’s reference temperature of 108 °C is
approximately the average of the electrolytic plating
temperature, 40 °C, and the annealing temperature, 180 °C.
Sample 1
4
100
22.5
10
10
Table II: Experimental results from fabrication, dicing, and
temperature cycling to validate modeling predictions.
Sample
Type Number
1 – A4
1 – A5
After
dicing
After Preconditioning
After 50
cycles
Green
Green
Yellow
Yellow
Red
Red
Figure 4: (a) schematic of one sided sample for curvature
measurement with copper and (b) shadow moiré profile of surface.
Table III: Average Curvature and Reference Temperatures for
Build Up Materials
Material
Figure 3: Optical inspection of glass interposer edge to show
failure classification: (a) expected dicing signature (green), (b)
interface failure and/or minor cracking (orange), and (c) cracking
failure (red).
Stress Measurement through Warpage
As a first step in the simulations, it is necessary to identify
the reference temperature at which the substrate is flat without
any warpage. In this work, such a reference temperature was
obtained by measuring the curvature at room temperature
using a shadow moiré tool and matching the curvature
warpage against simulated value.
Starting with a glass substrate laminated with a laminated
polymer on one side, the average curvature along its two
diagonals was measured to be 2.79 (1/m) using a shadow
moiré tool. Similarly, when simulations were carried out
starting with a glass substrate and a polymer, it was seen that
a reference temperature of 162 °C will produce a curvature of
as 2.79 (1/m) at a room temperature of 27 °C. It should be
pointed out that the glass transition temperature of the
polymer was 162 °C, the same as the reference temperature.
100% 5um Copper
(Annealed)
80% 8um Copper
(Annealed)
ZEONIF ZS-100
Average
Curvature [1/m]
Reference
Temperature [°C]
3.38
108
3.28
2.79
162
Numerical Model Introduction
Using the reference temperatures, in combination with
other measured material properties and material manufacturer
data, finite-element models are created using ANSYSTM to
predict the occurrence of glass cracking failure. Figure 5
shows an example of the 2D plane-strain finite element
model. As seen, glass is the interposer core material, with
copper and polymer as build up materials, and solder resist
passivation on the top and bottom. Table IV shows the
material properties used in the model. The model employs
symmetry at the left hand side. A dicing-induced flaw was
introduced on the free edge on the right, which can be placed
1940
,
and
are the stress and strain tensors,
where
respectively [14]. For a linear, brittle, isotropic material, such
as glass, J is equal to the strain energy release rate, G [15].
The strain energy release rates obtained through the contour
integral approach were cross checked using the Virtual Crack
Closure Technique (VCCT) [16]. For the VCCT, the
predetermined crack path was assumed to be straight forward
into the glass for cracks in the glass.
If the dicing induced defect happens to be at the interface
between polymer and glass, then the propagation of the flaw
or defect should be studied through interfacial fracture
mechanics models. Also, interfacial cracks may continue to
propagate as interfacial cracks or may kink into the glass.
Interface cracks have been shown to kink into brittle materials
[17], the criteria for doing so depends on the ratio of the
critical energy release rate of the interface to the critical
energy release rate of the material [18] and mode mix [19,
20]. Details of interfacial delamination and crack kink models
are discussed in the Cracking Process and Failure Prediction
section.
Figure 5: Finite element model geometry schematic.
Figure 6: (a) Finite element model mesh example and (b)
zoomed in near defect with contour integral.
Table IV: Material properties used in modeling.
Material
Glass
Copper
Polymer
Solder Resist
Modulus [GPa]
77
117
6.9
3
CTE [ppm]
3.3
9.8
23
32 / 95
anywhere along the thickness of the diced edge. This flaw or
defect was assumed to be a perfectly sharp crack and oriented
horizontally.
A typical mesh is shown in Figure 6. The mesh was
refined near the free edge with constant element size near the
crack tip. A contour integral approach was used within the
finite element software to calculate the energy release rate
using J-integral, where J is defined as,
∮
∙
,
(2)
Model to Simulate Dicing
Dicing is usually done in the presence of water. When a
glass interposer is exposed to water or moisture, it could cause
interfacial delamination or glass cracking. During dicing, the
crack propagation is likely due to a lower fracture toughness
of glass in the presence of water. For example, the critical
stress intensity factor of borosilicate glass drops from 0.8
MPa√m in air to about 0.4 MPa√m in the presence of water
[21].
To investigate whether a crack will propagate through the
glass horizontally during dicing operation in water, a second
model was constructed to be compared to the model shown in
Figure 5. The second model had two interposers, with a
partial dicing cut inserted between them and a layer of contact
elements with fixed out of plane displacement below the
model to represent the dicing table, as shown in Figure 7. This
second model is “during dicing” while the first model,
described in the previous section, is “after dicing.” The model
is otherwise identical to the first, with a horizontal defect in
the glass, normal to the free edge created by dicing. Both
models were run without solder resist passivation.
Figure 7: Finite element model geometry for model simulating
dicing.
(1)
where Γ is the counterclockwise curve surrounding the crack
tip, x and y are in in-plane directions (as shown in Figure 6), u
is the displacement vector, ds is the infinitesimal distance
along the path, T are the tractions, and W is the strain-energy
density defined as,
The “during dicing” model had two crack tips. The larger
crack, that is the cut made by the dicing saw, was vertical. If
the vertical crack propagates, the panel is considered diced.
This is the desired outcome of the dicing operation. Creating
a vertical crack in the glass instead of abrading it with a blade
is known to produce a much cleaner surface. The score and
1941
break method, which is commonly used to cut bare glass, does
exactly that, by scoring the surface and then bending or
locally heating the glass until it breaks. The second crack tip
was a defect at the free edge of the glass due to dicing
abrasion and is oriented horizontally into the glass. If this
initial horizontal defect propagates into the glass, the sample
will fail, and this will be an undesired outcome.
“During dicing” model consisted of a 60 μm vertical
dicing cut into the 100 μm thick glass with a 5 μm horizontal
defect from the cut edge of the glass. It was seen that the
energy release rate for crack propagation was 1.204 J/m2.
This number is less than 2% different from the energy release
rate for a horizontal crack in a fully diced glass substrate, as
expected and as shown in Table V. Since the results from the
two models varied by less than two percent, the during dicing
model, which included a larger area, two crack tips, and
contact elements for tape support, was computationally
expensive, and thus, all further analyses were done using the
“after diced” model.
Table V: Comparison of energy release rates from models during
dicing and after dicing.
During dicing
After diced
Gtotal [J/m2]
1.204
1.192
Next, to investigate glass cracking failure during dicing, the
simplified models of fully-diced glass substrates with edge
flaws were run to simulate the dicing conditions. The room
temperature applied as a boundary condition because of the
cooling water. The obtained energy release rates were
compared to the critical energy release rate of borosilicate
glass in water, 1.98 J/m2. The energy release rate as a
function of initial defect size is shown in Figure 8. Multiple
models were constructed with a range of horizontal crack
sizes and the energy release rate available upon polymer
processing, copper annealing, and dicing was examined. An
initial defect size as small as 10 μm may be close enough to
result in glass cracking failure for the 90 μm ZS-100, 40 μm
copper sample. This explains the on-tape failure observed
Figure 8: Energy release rate as a function of initial defect size
during dicing.
prior to this work, which was cut with the original or
unoptimized blade. Also, as seen in Figure 8, if one were to
use 40 um ZS-100 and 20 um copper, it is unlikely that the
substrate will crack during dicing. To address this type of
failure, blade dicing optimization work was done by Frank
Wei and Disco [8].
Cracking Process and Failure Prediction
Now that glass cracking during dicing has been addressed,
glass cracking failure during reliability testing, such as the
failures seen in samples 1-A4 and 1-A5, may be analyzed.
To better understand such glass cracking under thermal
cycling, scanning electron microscopy (SEM) was used on a
sample after failure, shown in Figure 9. Figure 9a shows a
schematic of a glass interposer corner with an interfacial
delamination that kinks into the glass. Figure 9b shows the
glass interposer, zoomed-out, under the SEM, with green and
red boxes indicating regions of interest. Figure 9c shows a
close up on the edge region (green box); Figure 9d shows a
close up on corner region (red box), and Figure 9e shows a
higher zoom on the region from Figure 9d. The polymer is
labeled “ZIF” for ZS-100 in the pictures. In Figure 9c, d, and
e, the bulk of the glass remained on the bottom after
separation, leaving no glass or small amounts of glass on the
top. The crack is seen to propagate at the glass-polymer
interface and kink into the glass, but not into the polymer.
From this observation, there are three different types of failure
which occur subsequently: first, there is glass chipping from
the free edge, created by dicing; second, bare regions of ZS100 are seen, indicating a failure at the glass-polymer
interface; and third, cohesive cracking of the glass.
To investigate the failure during reliability testing,
simulations were run to see if interfacial delamination
between glass and ZS-100 would kink into the glass to result
in glass fracture. Thus, treating the adhesion failure as an
initial crack, the numerical models shown in Figure 5 were
modified to include a kink to the glass, using the notation
shown in Figure 10. Following previous convention [17, 18],
a is the crack length after kinking, ω is the kink angle, and the
interfacial delamination length is much greater than the
kinked crack length. A range of kink angles were run, which
showed less than 10% difference between 10 and 45 degree
crack kinks. A representative kink is chosen to be 10 μm long
and at a 15 degree angle from the glass-polymer. The
interfacial delamination size is varied and the results from
such simulations are shown in Figure 11, in which the total
energy release rate at -40 °C is a function of various
interfacial delamination sizes. The total energy release rate
increases with larger defect sizes, as expected, and the energy
release rate of the 90 μm ZS-100, 40 μm copper structure
reaches the critical energy release rate at about 100 μm
interfacial delamination. The energy release rate of the 40 μm
ZS-100, 20 μm copper structure does not reach the critical
energy release rate. Thus, a thicker build up leads to higher
total energy release rate for any single initial defect size. The
90 μm polymer and 40 μm copper interposer is predicted to
experience cracking failure, while the available energy of the
thinner build up does not reach the critical energy release rate
of glass. As long as the available energy does not reach the
critical energy release rate, glass cracking failure should not
1942
occur. Thus the 40 μm polymer and 20 μm copper sample
should not have cohesive glass cracking. Based on these
results, 40 μm polymer and 20 μm copper was chosen as a
potential solution.
The data in Figure 8 and Figure 11 do not appear entirely
smooth because the model includes variations such as copper
pads and solder resist passivation openings, which lead to
different localized stress patterns for each crack tip location.
Figure 10: Schematic of crack kinking from glass-polymer interface
into glass.
Figure 11: Energy release rate at -40 °C as a function of initial
defect size for glass interposers with different build ups with
interface failure.
Experimental Demonstration of Solution
The models suggest that with thinner polymer and copper
layers, there will be less chances for cracking, and thus, new
samples with polymer layers at 10 μm thick for a total
thickness of 40 μm and copper layers at 5 μm thick for a total
thickness of 20 μm were fabricated, diced, and reliability
tested, as described in the Fabrication, Dicing, and Reliability
Testing section. This thinner structure, called Sample 2, still
follows the schematic in Figure 1 and the details are presented
in Table VI.
The experimental results after dicing,
preconditioning, 50 temperature cycles, and 1000 temperature
cycles for Sample 2 are shown in Table VII. Table VII uses
the same status indicator color scheme as in Table II.
Table VI: Details for samples fabricated for model validation.
Figure 9: SEM of glass interposer after cracking failure: (a)
schematic of interposer surface near edge showing SEM regions, (b)
zoomed-out, (c) edge, (d) corner, and (e) corner zoomed-in.
1943
Metal Layers
Glass Thickness [μm]
Polymer Thickness [μm]
Copper thickness [μm]
Passivation thickness [μm]
Sample 2
4
100
10
5
10
Table VII: Experimental results from fabrication, dicing, and
temperature cycling to validate modeling predictions.
Sample
Type Number
2 – D4
2 – E5
After
dicing
After Preconditioning
After 50
cycles
Green
Green
Yellow
Yellow
Yellow
Yellow
After
1000
cycles
Yellow
Yellow
4.
5.
Similar to the first round of samples, the new samples
showed expected dicing signature after dicing and minor
interface failure after preconditioning. However, at 50
temperature cycles, the new samples, 2-D4 and 2-E5, did not
fail. These samples continued thermal cycling and passed
1000 cycles without major failure. This is the result predicted
by modeling, that the new samples would not fail despite the
interfacial adhesion failure.
Additional samples and other solution methods are being
explored and tested, and the results from those studies will be
reported in a future publication.
Conclusions
In this work, glass cracking failure was studied through
finite-element modeling and experimental work including
reliability testing. Glass cracking failure starts with dicing
induced defects, which may grow due to interface adhesion
failure. Glass cracks cohesively due to the existing defect or
crack size and thermo-mechanical stresses induced by CTE
mismatch. Energy release rate was used to predict the
occurrence of crack propagation, and it was seen that thicker
build up layers would increase the total energy release rate.
Thinner build ups are seen to reduce the energy available for
crack propagation such that glass cracking failure would not
occur, even in the presence of a large initial defect. Based on
this work, glass panels with four polymer layers of 40 μm
total thickness and four copper layers of 20 μm total thickness
have been successfully fabricated, diced, pre-conditioned, and
thermal cycled over 1000 cycles without any major failure or
glass cracking. Additional experiments and simulations are
currently underway to further enhance the robustness of glass
substrates.
Acknowledgments
This work was supported by funding from the Low Cost
Glass Interposers and Packages global industry consortium at
Georgia Tech 3D Systems Packaging Research Center. The
authors would like to thank Mikael Broas, Makoto Kobayashi,
Xian Qin, Dr. Sathyanarayanan Raghavan, Dr. Vanessa Smet,
Yutaka Takagi, Christine Taylor, Jialing Tong, and Laura
Wambera for their valuable help and support.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
References
1.
2.
3.
Y. Sato, S. Sitaraman, V. Sukumaran, B. Chou, J. Min, M.
Ono, et al., "Ultra-Miniaturized and Surface-mountable
Glass-based 3D IPAC Packages for RF Modules," presented
at the ECTC, 2013.
X. Qin, N. Kumbhat, V. Sundaram, and R. Tummala,
"Highly-Reliable Silicon an Glass Interposers-to-Printed
Wiring Board SMT Interconnections: Modeling, Design,
Fabrication, and Reliability," presented at the ECTC, 2012.
V. Sundaram, Y. Sato, T. Seki, Y. Takagi, V. Smet, M.
Kobayashi, et al., "First Demonstration of a Surface
19.
20.
21.
1944
Mountable, Ultra-Thin Glass BGA Package for Smart
Mobile Logic Devices," presented at the ECTC, 2014.
R. Furuya, F. Liu, H. Lu, H. Deng, T. Ando, V. Sundaram,
et al., "2um RDL Wiring Using Dry Film Photoresists and
5um RDL via by Projection Lithography for Demonstration
of Low Cost 2.5D Panel-based Glasss and Organic
Interposers," presented at the ECTC, 2015.
S. R. McCann, V. Sundaram, R. Tummala, and S. K.
Sitaraman, "Flip-Chip on Glass for Low Warpag," in ECTC,
2014.
V. Smet, M. Kobayashi, T. Wang, P. M. Raj, and R.
Tummala, "A New Era in Manufacturable, LowTemperature and Ultra-Fine Pitch Cu Interconnections and
Assembly Without Solders," presented at the ECTC, 2014.
S. Cho, Y. Joshi, V. Sundaram, Y. Sato, and R. Tummala,
"Comparison of Thermal Performance between Glass and
Silicon Interposers," presented at the ECTC, 2013.
F. Wei, "Empirical Investigations on Die Edge Defects
Reductions in Die Singulation Processes for Glass-Panel
Based Interposers for Advanced Packaging," presented at the
ECTC, 2015.
N. Koizumi, "Basic Study of Packaging Structure Using
Glass Material," in GIT, 2013.
J. Standard, "J-STD-020D: Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount
Devices," 2008.
J.
Standard,
"JESD22-A113:
Preconditioning
of
Nonhermetic Surface Mount Devices Prior to Reliability
Testing," 2008.
J. Standard, "JESD22-A104-C temperature cycling," 2005.
J. T. Tzeng, "Predictions and Experimental Verification of
Residual Stresses in Thermoplastic Composite Cylinders,"
presented at the American Society for Composites 8th
Technical Conference, 1997.
J. R. Rice, "A Path Independent Integral and the
Approximate Analysis of Strain Concentration by Notches
and Cracks," J. Applied Mechanics, vol. June, pp. 379-386,
1968.
J. R. Rice, P. C. Paris, and J. G. Merkle, "Some Further
Results of J-Integral Analysis and Estimates," in ASTM STP
536, 1973, pp. 231-245.
E. F. Rybickiand and M. F. Kanninen, "Finite element
calculation of stress intensity factors by modified crack
closure integral," Eng. Frac. Mech., vol. 9, pp. 931-938,
1977.
M.-Y. He and J. W. Hutchinson, "Kinking of a Crack Out of
an Interface," J. Applied Mechanics, vol. 56, pp. 270-278,
1989.
M.-Y. He, A. Bartlett, A. G. Evans, and J. W. Hutchinson,
"Kinking of a Crack Out of an Interface: Role of In-Plane
Stress," J. American Ceramic Society, vol. 74, pp. 767-771,
1991.
A. Agrawal and A. M. Karlsson, "Obtaining Mode Mixity
for a Bimaterial Interface Cracking Using the Virtual Crack
Closure Technique," Int. J. Fracture, vol. 141, pp. 75-98,
2006.
J. Wang and C. Zhang, "Energy Release Rate and Phase
Angle of Delaminatino in Sandwich Beams and Symmetric
Adhesively Bonded Joints," I. J. Solids Structures, vol. 46,
pp. 4409-4418, 2009.
S. M. Wiederhorn and L. H. Bolz, "Stress Corrosion and
Static Fatigue of Glass," J. American Ceramic Society, vol.
53, pp. 543-548, 1970.