Professor Fearing EECS150/Problem Set 6 Solution Fall 2013 1.1

Professor Fearing
EECS150/Problem Set 6 Solution
Fall 2013
1.1. Synchronization pt 1 (10 pts). The AD9980 video decoder on the XUP board sends
luminance information for each pixel Y[7:0], and timing information HSOUT and VSOUT
using a generated data clock DTACK at 49.5 MHz. For 800x600 at 75 Hz, the nominal
DTACK rate is 49.5 MHz. Using the 49.5 MHz clock, 4 consecutive pixels are packed into a
32 bit word YQ[31:0]. This results in YQ(N) = {Y(4N+3),Y(4N+2),Y(4N+1),Y(4N)}.
A FSM (using DTACK as the clock) is used to generate a YRDY signal which lasts for 2
DTACK clock cycles when a new YQ value is ready. YQ should change at 12.375 MHz. For
now assume that HSOUT is asserted for the first pixel of each row, and should be used to
align the input data. The timing diagram below details this operation.
DTACK
HSOUT
Y
YQ
YRDY
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YQ0
Y8
Y9
YQ1
a. Draw a detailed block diagram (to level of registers, muxes, etc.) for the data path which
generates YQ from Y.
Y
8
EN3
EN2
EN1
EN0
EN3
EN3
EN3
32
YQ
All registers are clocked on DTACK.
b. Design a simple FSM which generates a glitch free YQ, and glitch free YRDY and controls
the data path for the Y to YQ conversion.
1
YRDY will be glitch-free if the encoding of this FSM is the output of a single FF. State
= Q2 Q1 Q0 = {I0, I1, S0, S1, S2, S3} = {000, 001, 010, 011, 100, 100} with YRDY = Q1
is an encoding that accomplishes this.
1.2. Synchronization pt 2 (15 pts). The DTACK clock, YQ, YRDY are asynchronous with
respect to the main clock FPGAClk of 100 MHz, which runs the FeatureDetector block.
Consider passing YQ to the FeatureDetector, with control signal YRDY. For every new 32
bit word YQ from the AD9980, a control FSM in the FeatureDetector block should load the
quad pixel into the image processing pipeline. (You can assume a 32 bit input register with
Load enable, clocked at 100 MHz.).
a. How could the FSM generate the Load signal? Draw a state diagram. Explain, with the
aid of a timing diagram, whether or not the following schemes would guarantee proper
inputs (and hence operation) of the FeatureDetector block.
i. YRDY connected directly to FeatureDetector FSM input.
With YRDY connected directly to the FSM input, it is possible with most arbitrary
state encodings that more than one FF could have its setup/hold time violated (or
possibly even become metastable) when YRDY changes. When this happens the state
transition will become inconsistent, and it is not guaranteed the FSM will function as
desired. For this simple case, if the states follow a Gray code transition, e.g. 00 → 01
→ 11, a missed state transition due to the asynchronous clock would result in a delay,
not a bad transition.
ii. YRDY connected to a synchronizing FF, and FF output YRDY Sync connected to
FSM input.
When a synchronizing FF is used to align the asynchronous input YRDY, the possibility of a setup time violation in the FSM next state decoder is eliminated, unless the
synchronizer FF goes metastable. If YRDY Sync is metastable after the rising edge of
the FPGA clock, it can be guaranteed that a valid value for the FSM next state will be
settled by the setup time of the next clock (if fF P GA 1CLOCK > tmeta res + tcomb + tsetup ).
tsetup
tsetup
thold
thold
FPGA CLOCK
YRDY
YRDY Sync
tmeta res
FSM NS
ARM
2
tcomb
VALID
1.3. Synchronization pt 3 (20 pts). Now consider the pixels Y[7:0] at the original rate of
49.5 MHz. Draw a block diagram of a general interface between the AD9980 and the FeatureDetector which would guarantee proper reading of Y[7:0], HSOUT and VSOUT by the
FeatureDetector. (Hint: FIFO.)
VGA
VSOUT
HSOUT
Y
1’b1
DTACK
ASYNC FIFO
DIN
WR_EN
10
DOUT
VALID
RD_EN
100MHz
Feature
Detector
2. SRAM and FIFOs (55 pts). In this problem, you will design 2-port arbiter which can
share reading to and writing from the IS61NLP25636A-200 “ZBT” synchronous SRAM on
the XUP board. This arbiter could enable a simple frame buffer for VGA and DVI interfaces
producing and consuming the frames at different rates. In general, these interfaces have
different clock speeds and refresh rates, so asynchronous FIFOs are used for communication
across clock domains. Assume VGA interface is writing its FIFO at 12.375 MHz, and DVI
is reading/writing its FIFOs at 12.5 MHz. The SRAM is clocked at 100 MHz. Please refer
to the figure below (notice the shift register and tri-state buffer before SRAM DATA). FIFO
signals operate as described for standard read operation for a FIFO with independent clocks
in the section “FIFO Usage and Control” of the Xilinx FIFO Generator v9.1 documentation.
VGA
12.375MHz
Write FIFO
{ADDR,DATA}
DIN
DVI
12.5MHz
DATA
Read Data
FIFO
DOUT
Read Addr
FIFO
ADDR
DIN
RD_EN
VALID
WF_RD_EN
WF_VALID
DOUT
WR_EN
50
OUT_EN
18
ZBT SRAM
DATA
32
RDF_WR_EN
DIN
32
RD_EN
RAF_RD_EN
VALID
DOUT
RAF_VALID
18
READ
SRAM_WE_L
0
1
ADDR_SEL
WRITE_L
ADDR
SRAM
100MHz
a. Complete the datapath above to result in an arbiter which simply alternates serving requests from the read and write FIFOs. The READ signal functions as a trivial FSM
determining which type of operation should be done. If the FIFO for the active operation
does not have valid data, the controller should do nothing (equivalent to an SRAM read
without putting the data in the Read Data FIFO). Your design should drive all bold inputs
above, and use only the bold outputs. You may add simple datapath elements such as
shift registers, gates, and muxes. The controller should drive the SRAM with the “Single
Read/Write Cycle Timing” shown on p. 20 of the SRAM data sheet.
3
READ
ADDR_SEL
RAF_RD_EN
WF_RD_EN
RAF_VALID
RDF_WR_EN
1
0
OUT_EN
SRAM_WE_L
WF_VALID
b. Assume there are 3 read requests and 2 write requests stored in the FIFOs. Draw a timing
diagram showing as many cycles as it takes for these 5 requests to be processed. The
diagram should begin by processing the first read request.
Include 100MHz clock, READ, SRAM WE L, RDF WR EN, WF RD EN, WF VALID,
RAF RD EN, RAF VALID, OUT EN, SRAM DATA, SRAM ADDR, and ADDR SEL in
the diagram.
Please note that the timing diagram below uses the Read with FWFT (First Word Fall
Through) FIFO mode, rather than the standard read mode. (Please see Fig. 5-10 of FIFO
generator, or slide 10 of lecture 14.) The reader will accept either FIFO mode.
CLOCK
READ
ADDR SEL
RAF RD EN
RAF VALID
WF RD EN
WF VALID
SRAM WE L
SRAM ADDR
OUT EN
SRAM DATA
RDF WR EN
RA0
WA0
RA1
WA1
RA2
RD0
WD0
RD1
4
WD1
RD2