ELE 312 Digital Electronics Textbooks

ELE 312
Digital Electronics
Textbooks
• DeMassa and Ciccone, Digital Integrated
Circuits, John Wiley & Sons.
• Taub and Schilling, Digital Integrated
Electronics, McGraw-Hill
1
Contents
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Basic Properties of Digital Integrated Circuits
Diode Digital Circuits
BJT Digital Circuits
– Ebers & Moll equations
– Transistor modelling
– State of transistor in a circuit
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Resistor-Transistor Logic (RTL)
Diode-Transistor Logic (DTL)
Transistor-Transistor Logic (TTL)
Schottky Transistor – Transistor Logic (STTL)
Different TTL Gates
Emitter-Coupled Logic (ECL)
MOS Digital Circuits
NMOS Gates
CMOS Gates
Properties of Digital Integrated
Circuits
2
Most important elements: Inverter and Noninverter
Idealized Inverter and Voltage Transfer Characteristics( VTCs)
3
Propagation Delays
Rise and fall times and turn-on and turn-off times
4
Power dissipation
Logic Element Equivalent Circuit and Fan-out
5
Power - Delay Product:
Speed-power product = (Average Power Diss) x (Propagation Delay)
PD = PDISS(avg) x tP(avg)
Diode Digital Circuits
6
Diodes
Shockleys Eq
I D = IS (e VD /VT − 1)
for Forward Bias
VD ≅ V0 = 0.7 V
7
IV Characteristics
for PN Junction diodes
for MN Schottky diodes
SPICE model
I′D = IS (e VD /VT − 1)
8
Basic Logic Gates: AND
Basic Logic Gates: OR
9
Clamping Diodes
Level shifting diodes
Level Shifting Diode AND Gate
Level Shifting Diode OR Gate
10
BJT Transistors
BJT Fabrication Example
1
Multi-Emitter Fabrication Examples
NPN BJT
2
Ebers-Moll NPN BJT Model
I E = I D ,BE − α R I D ,BC
I C = α F I D ,BE − I D ,BC
IB = IE − IC
I D ,BE = I ES (e VBE / VT − 1)
I D ,BC = I CS (e VBC / VT − 1)
Reciprocity theorem
IS = α F I ES = α R I CS
transport saturation current
BJT Modes of Operation
BE junction
BC junction
Mode
Reverse
Reverse
Cutoff
Forward
Reverse
Forward active (FA)
Forward
Forward
Saturation (SAT)
Reverse
Forward
Reverse active (RA)
(OFF)
3
Reduced models of the operation modes
βF =
(a) Cutoff
αF
1−αF
(b) Forward active
I C = σβ F I B
σ ≤1
βR =
(c) Saturation
αR
1−αR
(d) Reverse active
IV Characteristics
4
Modes of Operation
Examples
βF = 65
IC, IB = ?
Base and emitter voltages = ?
5
TTL Circuit Design
Output-High Pull-up Driver
Output-Low Pull-down Driver
Discharge path and Base-Driving circuitry
6
Power Dissipation Example
Resistor-Transistor Logic
(RTL)
7
Voltage Transfer Characteritics
(VTC)
INVERTER
VIL = VBE ( FA )
VIH = VBE (SAT ) +
VCC − VCE (SAT )
β FR C
RB
NAND
NOR
8
RTL Fan-out
RTL fan-out analysis
9
RTL fan-out analysis
Maximum fan-out?
⎢I ⎥
N = ⎢ OUT ⎥
⎣ I IN ⎦
I OUT =
I IN =
VCC − VOUT
RC
VOUT − VBE (SAT )
RB
VOUT = VIH
VIH = VBE (SAT ) +
VCC − VCE (SAT )
β FR C
RB
10
RTL NONINVERTER
11
AND
OR
12
RTL with Active Pull-up
Fan-out of RTL with Active Pull-up
Determined by the output
high state as QS is cut-off
for low-inputs
Simplified output high state
Simplified input high state
1
Simplified output-high fan-out configuration
I OUT = I EP ≅
⎢I ⎥
N = ⎢ OH ⎥
⎣ I IH ⎦
I IN =
VCC − VCE (SAT ) − VOUT
R CP
VOUT − VBE (SAT )
RB / 2
VOUT (min) = VIH
VIH = VBE (SAT ) +
VCC − VCE (SAT )
β FR C
RB
2
Diode-Transistor Logic
(DTL)
Basic DTL Inverter
Basic DTL NAND Gate
3
Diode Modified DTL Inverter
Transistor Modified DTL Inverter
4
VTC of Transistor Modified DTL Inverter
VOH = VCC
VIL = VBE,O(FA) + VBE,L(FA)
VOL = VCE,O(SAT)
VIH = VBE,O(SAT) + VBE,L(FA)
DTL Fan-out
Determined by the output
low state as DI is off for
high-inputs
5
Cascaded DTL
I B,O = I E ,L − I RD
I OL = I C,O (SAT ) − I RC
⎢I ⎥
N = ⎢ OL ⎥
⎣ I IL ⎦
I RC =
VCC − VCE ,O (SAT )
RC
I C ,O (SAT ) = σβ F I B,O (SAT )
For maximum fan-out σ = 1
I RD =
Path 2
I E ,L ≅
I IL =
VBE ,O (SAT )
RD
VCC − VBE ,L ( FA ) − VD ,L ( ON ) − VBE ,O (SAT )
σR B
VCC − VD ,I ( ON ) − VCE ,O (SAT )
RB
Path 3
Example: Calculate the DTL fan-out for βF = 49 and
σ = 0.85.
Power Dissipation
Example: Calculate the average power dissipation for the
above example?
6
Tansistor-Transistor Logic
(TTL)
Basic TTL Inverter
Basic DTL Inverter (compare)
Basic TTL NAND Gate
7
Actual TTL NAND Gate with Totem Pole Output
VTC of an actual TTL Inverter
VOH = VCC – VBE,P(FA) – VD,L(ON)
VIL = VBE,S(FA) – VCE,I(SAT))
VOL = VCE,O(SAT)
VIH = VBE,O(SAT) + VBE,S(SAT) – VCE,I(SAT)
VOB = VCC – IRCRC – VBE,P(FA) – VD,L(ON)
VIB = VBE,O(FA) + VBE,S(FA) – VCE,I(SAT)
I RC = I RD =
VBE ,O ( FA )
RD
8
States of diodes and BJTs
EOC: Edge of conduction
TTL Fan-out
Determined by the output
low state as QI is cut-off
for high-inputs
9
Cascaded TTL
Path 1
I IL =
VCC − VBE ,I (SAT ) − VCE ,O (SAT )
RB
I E ,S(SAT ) = I B,S + I C,S
I OL = I C,O (SAT ) = σβ F I B,O (SAT )
⎢I ⎥
N = ⎢ OL ⎥
⎣ I IL ⎦
I B,O (SAT ) = I E ,S(SAT ) − I RD
I RD =
I C ,S =
Path 2
VBE ,O (SAT )
RD
For maximum fan-out σ = 1
VCC − VCE ,S(SAT ) − VBE ,O (SAT )
RC
I B,S = I C,I ( RA ) = (1 + β R )I B,I
I B, I =
VCC − VBC,I ( RA ) − VBE ,S(SAT ) − VBE ,O (SAT )
RB
Example (TTL Fan-out)
Example: Calculate the TTL fan-out for βF = 25, σ =
0.85 and βR = 0.1
IRB(OL) = 675 μA
IIL= IRB(OH) = 1 mA
IRC(OL) = 2.5 mA
IOL= 51.9 mA
⎢I ⎥
N = ⎢ OL ⎥ = 51
⎣ I IL ⎦
Example (Power Dissipation)
Example: Calculate the average power dissipation for the
above example?
PCC(avg) = 10.4 mW
10
Open-Collector TTL
Mostly used in data busses where multiple gate outputs
must be ANDed.
• This can be accomplished by using a single pull-up resistor
with open-collector TTL gates
• This type of connection is referred to as wired-AND.
Low Power TTL (LTTL)
Accomplished simply by increasing the resistance values.
However this results in
• Decreased fan-out
• Longer transient-response times
1
LTTL Example
Compare the power dissipation of the LTTL and TTL gates.
IRB(OL) = 67.5 μA
IRB(OH) = 100 μA
PCC(avg) = 919 μW
IRC(OL) = 200 μA
TTL vs LTTL power dissipation ratio = 10.4 / 0.919 = 11.3
High Speed TTL (HTTL)
Accomplished simply by decreasing the resistance values.
However this results in
• Increased power dissipation
2
Schottky Tansistor-Transistor Logic
(STTL)
Schottky Barrier MN diode
Schottky-clamped BJT (Schottky Transistor)
3
Multi-Emitter Fabrication Examples
Modes of Operation for SBJT
1.
2.
3.
4.
OFF
FA
On Hard
Reverse Schottky
4
Example (SBJT)
Example: Draw the VTC graph of the SBJT inverter shown below
STTL NAND Gate
5
STTL NAND Gate (VTC)
VOH = VCC – VBE,P(FA) – VBE,P2(FA)
VIL = VBE,O(FA) + VBE,S(FA)– VCE,I(HARD)
VOL = VCE,O(HARD)
VIH = VBE,O(HARD) + VBE,S(HARD) – VCE,I(HARD)
STTL NAND Gate (Device states)
Device state table
6
STTL Fan-out
Determined by the output
low state as QI is cut-off
for high-inputs
Cascaded STTL
Path 1
I IL =
VCC − VBE ,I ( HARD) − VCE ,O ( HARD)
RB
I E ,S( HARD) = I B,S + I C,S
I OL = I C,O ( HARD) = β F I B,O ( HARD)
I C ,S =
VCC − VCE ,S( HARD) − VBE ,O ( HARD )
RC
⎢I ⎥
N = ⎢ OL ⎥ I B,O ( HARD) = I E ,S( HARD) − I C,D ( HARD) Path 2, 3 I B,S = I C,I ( RS) = ISBD
⎣ I IL ⎦
−V
V
I C ,D ( HARD ) =
BE ,O ( HARD )
R CD
CE , D ( HARD )
ISBD =
VCC − VBC,I ( RS) − VBE ,S( HARD) − VBE ,O ( HARD)
RB
7
Example (TTL Fan-out)
Example: Calculate the STTL maximum fan-out for βF = 49.
IRB(OL) = 1.11 mA
IRC(OL) = 4.11 mA
IRCD(OL) = 1.20 mA
IOL= 197 mA
IIL= IRB(OH) = 1.32 mA
⎢I ⎥
N = ⎢ OL ⎥ = 149
⎣ I IL ⎦
IE,S(OL) = 4.22 mA
IR,O(OL) = 4.02 mA
Example (Power Dissipation)
Example: Calculate the average power dissipation for the
above example?
IE,P(OL) = 0.182 mA
IE,P(OH) = 1.3 mA
PCC(avg) = 20.05 mW
Low Power STTL (LSTTL)
Accomplished by
1. Increasing the resistance value
2. Diode input section
3. Pull-down enhancements
8
Low Power STTL (LSTTL)
LSTTL Example
Compare the power dissipation of the LSTTL and STTL gates.
IRB(OL) = 170 μA
IRB(OH) = 210 μA
PCC(avg) = 2.11 mW
IRC(OL) = 463 μA
STTL vs LSTTL power dissipation ratio = 20.05 / 2.11 = 9.5
9
Advanced Schottky TansistorTransistor Logic
(ASTTL)
Advanced Schottky Transistor
Logic
• Advanced Low-Power Schottky TTL (ALSTTL)
• Fairchild Advanced Schottky TTL (FAST)
• Advanced Schottky TTL (ASTTL)
10
ALSTTL
ALSTTL VTC
VOH = VCC – VBE,P(FA)
VOL = VCE,O(HARD)
VIL = VBE,O(FA) + VEB,IPA(FA)
VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) – VBE,IPA(FA)
11
ALSTTL VTC
FAST
12
FAST VTC
VOH = VCC – VBE,P(FA)
VOL = VCE,O(HARD)
VIL = VBE,O(FA) + VBE,S(FA) + VBE,SB(FA) – VD,IA(ON)
VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) – VD,IA(ON)
ASTTL
13
ASTTL
14
Other TTL Gates
Other TTL Gates
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•
•
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•
AND gates
NOR gates
OR gates
AND-OR-INVERT (AOI) gates
XOR gates
Schmitt Trigger Inverters and NAND gates
Tri-State buffers
1
TTL AND gate
TTL AND gate - VTC
2
TTL NOR gate
TTL NAND gate
Power Dissipation Example
IRB(IL) = 1 mA
IRB(IH) = 675 μA
ICC(LL) = 2 mA
ICC(LH) = 4.175 mA
ICC(HL) = 4.175 mA
ICC(HH) = 3.85 mA
IRC(OL) = 2.5 mA
PCC(avg) = 17.75 mW
TTL OR gate
Example: Noise margins VNMH , VNML?
TTL AND gate
3
Complex Logic TTL Gate Design
1. ANDing of signals
• Multi-emitter input BJT sections
2. ORing of signals
• Multiple input sections (QI and RB)
• Multiple drive splitting BJTs (QS)
3. If non-inverting ORing is desired
• Addional logic inversion circuitry
4. Totem-pole output branch
AND-OR-INVERT (AOI) gate
4
Example
Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF
Example
Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF
5
TTL XOR gate
Hysteresis and Schmitt Trigger Gates
6
Hysteresis
Hysteresis
Base-Emitter coupled Schmitt Trigger Non-inverting circuit
VOHS = VCC
⎛ VCC − VBE (SAT ) VCC − VCE (SAT ) ⎞
VOLS = ⎜⎜
−
⎟⎟R eq + VCE (SAT )
R CS1
R CS2
⎠
⎝
R eq = R CS1 || R CS 2 || R E
⎛ VCC − VBE (SAT ) VCC − VCE (SAT ) ⎞
⎟⎟R eq + VBE ,S1( FA )
VIUS = ⎜⎜
−
R CS1
R CS2
⎠
⎝
VIDS =
VCC + α VBE ,S1(SAT ) − VBE ,S2 ( FA )
α
α=
R CS1
+1
RE
7
Example
Find the VOHS, VOLS, VIUS and VIDS points where RCS1 = 4kΩ, RCS2 = 2.5kΩ, and RES = 1kΩ.
VOHS = 5V
Req = 606Ω
ICS1 = 1.05mA
VOLS = 2V
VIUS = 2.5V
VIDS = 1.66V
ICS1 = 1.92mA
TTL Schmitt Trigger NAND gate
8
Example
Find the VOH, VOL, VIU and VID points where RCS1 = 4kΩ, RCS2 = 2.5kΩ, and RES = 1kΩ.
VOH = 3.6V
VOL = 0.2V
VIUS = 2.5V
VIDS = 1.66V
VIU = 1.8V
VID = 0.96V
TTL Tri-state Buffers
9
TTL Tri-state Buffers
Connecting TTL Tri-state buffers to a Bus
10
11
Emitter-Coupled Logic
(ECL)
Basic ECL Inverter/Non-inverter
(ECL Current Switch)
1
Basic ECL Inverter/Non-inverter VTC
According to inverting output: VINV
VIL = VBB – 0.05 VIH = VBB + 0.05
VOH = VCC
V OL = V CC −
V IH − V BE ( ECL ) + V EE
RE
R CI
( V BE ( SAT ) − V EE )
RE
R
1 + CI
RE
V CC + V BC ( SAT ) +
R CI VS =
Example
Calculate the critical VTC points for the ECL current switch
VCC = 5V, VEE = 0V, VBB = 2.6V, RCI = RCR = RE = 1kΩ,
VBE(ECL) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V
VOH = 5V
VOL = 3.10V
VIL = 2.55V
VIH = 2.65V
VS = 3.2V
VINV (VIN = VS) = 2.6V
2
Basic ECL NOR/OR Gate
3
MECL I NOR/OR Gate
V OH = −
V OL = −
V EE − V BE ( ECL )
R CI + (β F + 1) R DN
R CI − V BE ( ECL )
V IH − V BE ( ECL ) + V EE
RE
R CI − V BE ( ECL )
Example
Find the logical swing, noise margins and noise immunities for the MECL I
circuit above.
βF = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V
VOH = – 0.76V
VOL = – 1.55V
VLS = 0.79V
VIL = – 1.225V
VS = – 0.29V
VIH = – 1.125V
VNMH = 0.365V
VNIH = 0.53V
VNML = 0.325V
VNIL = 0.475V
4
MECL I Fanout
I OH = I E ,BN ( FA ) − I RDN
⎢I ⎥
N = ⎢ OH ⎥
⎣ I IH ⎦
VOH + VEE
R DN
I E ,BN ( FA ) = (β F + 1)I B,BN
− VOH − VBE ,BN ( ECL )
I B,BN =
R CI
I RDN =
I IH =
I RE
βF +1
I RE =
VE + VEE
RE
VE = VOH − VBE ( ECL )
Fan-out Example
Find the maximum fan-out for the MECL I circuit above
βF = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V
Assume load gates reduce VOH by 0.03 volts.
VOH = – 0.79V
IRDN = 2.205 mA
VE = -1.54 V
IB,BN = 148 μA
IRE = 2.95 mA
IE,BN = 7.4 mA
IOH = 5.2 mA
IIH = 59 μA
⎢I ⎥
N = ⎢ OH ⎥ = 87
⎣ I IH ⎦
5
Power Dissipation Example
Find the average power dissipated in the MECL I circuit above
IRE(NOH) = 2.64 mA
IRE(NOL) = 2.98 mA
IRDN(NOH) = 2.22 mA
IRDN(NOL) = 1.825 mA
IRDO(NOH) = 1.825 mA
IRDO(NOL) = 2.22 mA
IEE(NOH) = 6.685 mA
IEE(NOL) = 7.035 mA
PEE(avg) = 35.6 mW
Other ECL Gates
6
DeMorgan’s Theorems
• NOR and OR using ANDs and NANDs
– NOR:
A + B = A⋅B
– OR:
A + B = A⋅B
• NAND and AND using ORs and NORs
– NAND:
A⋅B = A + B
– AND:
A⋅B = A + B
Example
Implement the following logic using only ECL gates
(A + B)(C + D)
Solution:
(A + B)(C + D) ≡ (A + B) + (C + D)
7
Collector Dotting Wired-AND Gates
Complex Logic Gates with Collector Dotting
8
Example
Series Gating – Basic ECL NAND/AND Current Switch
9
Series Gating NAND/AND Gate
Complex Logic Gates with Series Gating
10
Example
ECL XOR/XNOR Gates
11
ECL Decoding Tree
12
MOS Logic
MOS Logic
•
•
NMOS gates
– Fabrication
– Modes of operation
NMOS Inverters and Analysis
– General NMOS Inverter
– Resistor Loaded NMOS Inverter
– E-MOSFET loaded NMOS Inverter
– D-MOSFET loaded NMOS Inverter
1
NMOS (n-channel E-MOSFET) Fabrication Examples
CMOS Fabrication Example
2
IV Characteristics
NMOS modes of operation
(a) Cutoff mode
(c) Saturation mode
(b) Linear mode
(d) body-bias effect
on threshold voltage
3
General NMOS Inverter
Graphical analysis when load is a resistor
4
Load capacitance
Power dissipation
(a) Static power dissipation
PDD = VDD (IDD(OH) + IDD(OL)) / 2
≅ VDD IDD(OL) / 2
PTOTAL = PDD + PD
(b) Transient power dissipation
PD = CL ƒ V2DD
ƒ: frequency at which the gate is switched
5
Resistor Loaded NMOS
Resistor Loaded NMOS Inverter
6
Propagation Delay
Fall time
7
E-MOSFET Loaded NMOS
E-MOSFET Loaded NMOS Inverter
8
D-MOSFET Loaded NMOS
D-MOSFET Loaded NMOS Inverter
9
NMOS Gates
Symbol Shorthands
10
NOR Gate
NOR Gates
11
NAND Gate
⎛ WO ⎞
⎟⎟
k O = ⎜⎜
⎝ LA + LB ⎠
VOL ( NAND) > VOL (Inverter)
OR Gates
12
AND Gates
Example
13
AOI (AND-OR-INVERT) Gates
Examples
14
XOR/XNOR Gates
Hysteresis
15
Schmitt Trigger
Transmission Gate
16
Transmission Gate Array
CMOS Logic
17
CMOS Inverter
CMOS Inverter
18
Symmetric CMOS Inverter
Capacitance Effect on Transition - 1
19
Capacitance Effect on Transition - 2
Electrostatic Discharge (ESD) Protection
20
CMOS Gates
Symbol Shorthands
21
CMOS NAND Gate
CMOS NAND Gates
22
CMOS NOR Gate
CMOS NOR Gates
23
CMOS AND/NAND Gate
CMOS OR/NOR Gate
24
CMOS AOI Gates
CMOS AOI Gates
25
CMOS AND-OR Gate
CMOS OAI Gates
26
CMOS AOI Gates
Example
27
Example
28
XOR Gate
29