Meeting the Design Challenges of nano

1
Meeting the Design Challenges of
nano-CMOS Electronics
Campbell Millar∗ , Scott Roy, David Cummings, Tim Drysdale,
Steve Furber, Doug Edwards, Mark Zwolinski, Andy Tyrrell,
Alan Murray, Steven Pickles, Richard O. Sinnott, David Berry and Asen Asenov
∗ c.millar@elec.gla.ac.uk,
Device Modelling Group, University of Glasgow, www.nanocmos.ac.uk
A BSTRACT
CMOS transistor scaling has driven the phenomenal success of the semiconductor industry, delivering
faster, cheaper, more functional circuits. 40 nm MOSFETs are in mass production at the 90 nm technology
node, and sub-10 nm transistors will be in production
by 2018 (in ultra-thin-body SOI or FinFET form)[1].
However, as devices scale, microscopic variations in
their atomically granular structure give rise to macroscopically measurable variations between devices[2],
[3]. Industry now recognises that such variations represent a major challenge to the scaling and integration of
current and future nano-CMOS transistors and circuits,
and that it will drive revolutionary changes in the
way that future integrated circuits and systems are
designed. This Glasgow led e-Science Pilot Project,
supporting 11 PDRAs and 7 PhD students, combines
the top device, circuit, and system design teams in
the UK, with industry players in device manufacture,
TCAD, analogue & digital fab, and systems design. We
aim to show how e-Science technologies can enable a
revolution in the electronics design process[4].
Traditional IC design (Figure 1) uses a hierarchical
approach that decouples the device, circuit, and systems in order to manage design complexity. Historically (Figure 2) a single device architecture of fixed
size required a single compact model set. However, by
the 25nm node, in addition to multiple VT devices
co-existing on the same chip, bulk devices will be
superseded by fully depleted SOI, ultra thin body
SOI, and various forms of multi-gate devices including
FinFETs.
Atomic scale differences in the structure of devices
made on these scales cause measurable, ineradicable
Figure 1.
Traditional decoupled design hierarchy.
Figure 2.
nodes.
Multiple device architectures for sub 25nm technology
Figure 3. Sub-threshold characteristics for an ensemble of 200,
35nm gate length MOSFETs. Typical device is shown inset, with
granular potential distribution due to the random distribution of
dopants in channel, source and drain.
Standard toolflow for some practical design, (90nm, 45nm?) complete, down past place & route,
so that we have complete cell, device, interconnect information.
Hardware + Software
Future Research
System
ALU
Figure 4. Transfer characteristics of an ensemble of 200 SRAM
cells constructed from 35nm gate length MOSFETs such as those
to the left. Random parameter fluctuations cause device mismatch,
with critical impact on circuit yield.
variations in their macroscopic parameters. They can
no longer be considered nominally identical, and must
be treated as a statistical ensemble. Circuits too (Figure
4) show the statistical spread characteristic of such
‘atomicity’. Therefore, multiple compact model sets
must be available, both for each device architecture
supported on a chip, and statistically within each
architecture. A more useful design methodology, pervasively supporting statistical design, also needs to
be constructed (Figure 5), but in order to be useful
must be cast to a methodology familiar to users. The
project uses e-Science technologies to develop such
a hybrid design methodology. It will be trialled by
academics undertaking research in device, circuit and
system simulation, and will help us to understand and
Subsystem/
system
etc.
ALU
etc.
ALU
Bus
ALU
etc.
Bus
Synapses
ALU
Registers
etc.
Bus
Synapses
Registers
Bus
Registers
Synapses
Synapses
Top level timing ;
and out-of-foundry
yeild, and power
yei
(either calculated from
(ei
toggles or by more
to
detailed analysis)
de
Manchester (Digtal and
Analogue), Glasgow DC,
Edinburgh
Back Annotated RTL-Synopsys
Filters
Logic blk. timing
timi
iming
inte
Blk. interconnect
info.
Cell D
Cell A
Cell F
Cell C
Cell D
Cell B
Logic
Blocks
Cell D
Cell F
Cell A
Cell D
Cell B
Cell D
Cell A
Cell F
Cell A
Cell B
Cell D
Cell C
Cell H
Cell F
Cell A
Cell D
Cell C
Cell E
Cell C
Cell A
Cell G Cell A
Cell F
Cell D
Cell B
Cell D
Cell E
Cell G
Cell E
Cell A
Cell E
Cell B
Cell D
Cell C
Cell A
Cell A
etc.
Bus
Synapses
Registers
Registers
Cell G
Cell E
For each Logic block
cre
create a ‘card index’
of statistically
gen
generated blocks
Manchester, Southampton, York,
Edinburgh, Glasgow Interconnect
Cell G
Cell H
Cell G
Modelsim ??? Possibly VHDL-AMS
Gate/cell
Gate/c
e/cell netlists
tim
Std cell timing
Standard
Cells
A
A
B
B
A
F
B
F
B
B
A
F
A
B
F
A
B
A
A
Transistor
Transi
nsistor netlists
A
F
A
B
B
B
For each Standard Cell York, Southampton, Edinburgh
create a ‘card index’ of Glasgow (Devices), Glasgow (Circuits)
cre
sta
statistically generated
cells
cel
Spice/Randomspice
Aurora
SPICE mod
models
Devices
For each transistor
family create a ‘card
fam
index’ of statistically
ind
generated devices
gen
Technology info.
Techno
Figure 5.
Responsibility
Future Research
Fundamental physics
phy
Glasgow (Devices)
Geronimo
The nanoCMOS variability aware design flow.
forecast the behaviour of next-generation nano-CMOS
based systems.
Using compact models ensembles which characterise variability in a given technology we will characterise sets of standard cells using grid technology
to enable the statistical characterisation of circuits,
via Monte-Carlo methods. Cells will be simulated
using spice, when fully characterised the behaviour and
statistics of the cell library will be modelled using high
level design languages (VHDL-AMS). Once Logic
blocks/subsystems have been described back annotated
RTL will allow designers to asses the impact of device
variability on architectural level designs. It is likely
that variability will have to be combatted on several
levels of the design hierarchy in order to deliver truly
robust and fault tolerant designs.
R EFERENCES
[1] ITRS,
“International
technology
roadmap
for
semiconductors
2005
edition,”
http://www.itrs.net/Links/2005ITRS/Home2005.htm, 2005.
[2] G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov,
“Simulation study of individual and combined sources of intrinsic parameter,” IEEE Transactions on Electron Devices, vol. 53,
no. 12, pp. 3063–3070, 2006.
[3] A. R. Brown, G. Roy, and A. Asenov, “Poly-si-gate-related
variability in decananometer mosfets with conventional architecture,” Electron Devices, IEEE Transactions on, vol. 54, no. 11,
pp. 3056–3063, Nov. 2007.
[4] nanoCMOS
eScience
Pilot
Project,
“http://www.nanocmos.ac.uk.”