MRAM: Device Basics and Emerging Technologies

MRAM: Device Basics and Emerging
Technologies
Matthew R. Pufall
National Institute of Standards and Technology
325 Broadway, Boulder CO 80305-3337
Phone: +1-303-497-5206 FAX: +1-303-497-7364
E-mail: pufall@boulder.nist.gov
Presented at the THIC Meeting at the National Center for Atmospheric Research, 1850 Table Mesa
Drive, Boulder CO 80305-5602
July 19-20, 2005
Pufall, THIC’05: 1
Collaborators:
NIST:
Bill Rippard
Shehzu Kaka
Steve Russek
Tom Silva
Hitachi Global Storage:
Jordan Katine
Freescale:
Fred Mancoff
Nick Rizzo
Pufall, THIC’05: 2
Outline
• What is MRAM? What are its advantages?
• When will we see MRAM?
• How does MRAM work?
• Spintronics basics: Electron spin and Magnetoresistance
• Anatomy of an MRAM bit
• Magnetic Switching
• Engineering Challenges: Consistency and Thermal Stability
• Freescale’s MRAM solution: “Toggle” MRAM
• Big Problems in the Nano-Future: Scaling of bits
• Emerging Solutions to Scaling: Spin Torque Switching
Pufall, THIC’05: 3
What is MRAM?
Magnetic-based Random Access Memory:
Uses small magnetic element to store
{1,0} rather than electric charge
(Some) Other types of RAM:
DRAM
SRAM
FRAM
Flash
Storage Method
Virtues
Charge on capacitor
Multiple transistors
Ferroelectric capacitor
Transistor w/ extra
isolated gate
speed, size, cost
speed, size, no refresh
nonvolatile, speed
nonvolatile, cost, size
…All have advantages/tradeoffs: No “universal” solution
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MRAM advantages:
Nonvolatile
Data don’t need refreshing
• “instant on”, low power
• Data retention >10 yrs
Fast
Read/write symmetric
• 25 ns (10 ns in demo)
• byte writeable
Unlimited cycling
No “fatigue” after >1016 cycles
Viability
Integrated into CMOS process
…If made (very) inexpensive and scalable, a potential
“universal” solution
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When (and where) will we see MRAM?
Freescale: Demos out to vendors
Shipping product end of
2005/early 2006
Uses: Replace battery-backed SRAM
Cell phone/embedded memory
4 Mb chip, 180 nm process
Others: IBM—In development
Toshiba/NEC
Cypress, Honeywell: ?
Pufall, THIC’05: 6
How does MRAM work?
z
Hysteresis Loop
y
M
1
x
My
“1”
Field H
“0”
-1
Ferromagnets have hysteresis:
Information stored in state @H = 0
• Hard disks, tape storage
-1
0
1
Magnetic Field H
Magnetic fields used to change direction (state) of M
Pufall, THIC’05: 7
How do you sense state of M?
Magnetoresistance (MR): Resistance depends on
direction of M
current I
Mfree
Mfixed
Low Resistance
High Resistance
How? Electrons also have magnetic moments: Spin
“Spintronics”
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Magnetization Filters e- Spin:
Electron spins become spin-polarized in direction of M: Spin filter
Magnetization M1
Incident
e-
current
Transmitted spins
Nonparallel spins scatter more: Higher resistance
∆R ~ cos(θM)
Pufall, THIC’05: 9
Sense M by Resistance:
0.6x1.2µm bit at 300mV bias
Current I
Mfixed
11
10.5
RA (kΩ µm2)
Mfree
10
9.5
9
MR=37%
8.5
8
7.5
-10 -7.5 -5 -2.5 0
Magnetic Field H
2.5
5
7.5 10
Field H
State of M determined by electrical measurement:
“Magnetic Tunnel Junction” (MTJ)
Pufall, THIC’05: 10
Anatomy of an MRAM bit
Hard axis field decreases Hc
DigitBLLine
Program Line
Bit Line
Free Ferromagnetic
Layer
Tunnel Barrier
Pinned Ferromagnet
35
Pinning Layer
Bit Line
Line
30
RA = 10 kΩµm2
25
Hhard = 0 Oe
20
MR (%)
15
Hhard
M
10
Hhard = 40 Oe
5
Heasy
0
-75
-50
-25 0
25
Heasy (Oe)
50
75
Pufall, THIC’05: 11
Bit Selection Energetics
E
“0”
Unselected
“1”
Eb
0
½-Selected
Lower barrier
Eb
Heasy ≠ 0
Selected
(a) Heasy = 0
π
θ
Eb
(b) Heasy > 0 or
Hhard > 0
Hhard ≠ 0
(c) Heasy > 0 and
Hhard > 0
Pufall, THIC’05: 12
Bit Addressing Challenges
Programming Probability
MRAM bit
from 256k chip
X
Heasy
Min.
Operating
Fail bits
point
Ihard
Hhard
ibit
Ihard
Iieasy
digit
Data courtesy Freescale
Bits switched/addressed by two fields
Challenge: Bit-to-bit variations make choosing
proper currents difficult/impractical
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Freescale’s Solution: “Toggle” MRAM
Bit Line
BL
Program
Program
Line
Line
2
Ferromagnetic layer
Coupling Layer
Ferromagnetic layer
Free Tri-Layer
Tunnel Barrier
Pinned Ferromagnet
Pinning Layer
Line
Program
Line 1
Coupled tri-layer
programs more
repeatably
Pufall, THIC’05: 14
How does Toggle work? Timing
Anti-parallel-coupled layers respond differently to fields:
HY
HY
HX
Low
Resistance
State
HX
High
Resistance
State
HY
HX
Figure courtesy Freescale
Pufall, THIC’05: 15
What does Toggle do?
• Moves “1/2 select” error horizon:
4Mb, March 6N Toggle Map
H2
IV
I
toggling
Operating
region
No disturb
No disturb
H1
No disturb
toggling
III
II
ibit
No disturb
0% switching region
(no disturbs)
idigit
Also increases bit volume (& thermal stability)
Data courtesy Freescale
Pufall, THIC’05: 16
Freescale 4Mb MRAM Layer structure
Program Path: Dashed green line
Sense Path: Red line (isolated)
Chip process at 180 nm node: Design ported to 90 nm (May ‘05)
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Future Difficulties: Scaling
2003 2004 2005 2006 2007
DRAM ½ pitch (nm)
MPU Physical Gate Length (nm)
100 90
45 37
80
32
70
28
65
25
From ITRS roadmap, 2003
…MRAM must compete with this (aggressive!) scaling
to be viable
Pufall, THIC’05: 18
Scaling Problem: Thermal Stability
As bits get smaller: more susceptible to thermal fluctuations
Energy barrier proportional to
volume, anisotropy: Must increase
anisotropy to keep constant
E
“0”
“1”
Eb
0
π
θ
But, bigger anisotropy—Need
bigger fields to switch bit!
Engineering problem…
Thermal fluctuations: Problem in hard disk media, read heads
General concern in nanoscale devices!
Pufall, THIC’05: 19
Possible Solution: Spin Transfer
Electron spins become spin-polarized in direction of M: M exerts torque
Magnetization M1
Incident
e-
current
Torque
Transmitted spins
Reverse also happens: polarized spins exert torque on M
Pufall, THIC’05: 20
Spin-Transfer-Driven Switching
Sign of torque depends on direction of current: Causes magnetization
motion
Current-driven hysteretic
switching
7.65
7.60
Polarizer
dV/dI (Ω)
Free layer
7.55
7.50
7.45
7.40
7.35
Electron current
-4
-2
0
2
4
Current (mA)
Bistable device: Current through
device drives switching
Pufall, THIC’05: 21
High Speed ST-Switching
Pulse Amplitude
Current (mA)
Switching Probability
30 nm
7.8
6.2
4.9
3.9
3.1
2.5
2.2
2.0
1.8
1.0
0.5
0.0
Katine HGST
100
7.5
1000
10000
Pulse Duration (ps)
µ0H = 66.7 mT
3 .5
7.4
2 .5
-1
(ns )
7.3
2 .0
95
1/τ
dv/dI (Ω)
3 .0
7.2
Q u a s i- s t a t ic
s w it c h in g
c u rre n t
1 .5
1 .0
<300 ps
switching time!
0 .5
0 .0
7.1
-4
-2
0
2
I (mA)
4
-0 .5
0
-1
-2
-3
-4
-5
-6
-7
-8
I (m A )
Pufall, THIC’05: 22
Spin Transfer Advantages
MTJ bit
• Removes X-point field lines—
simpler lithography, two terminal
devices
• Becomes more efficient as
devices shrink: Scalable
Heasy
X
Ihard
Hhard
Spin Transfer: ~1/d2
Fields: ~1/d
d
d
d
Pufall, THIC’05: 23
Spin-Transfer-Driven Oscillators
Electron current
µ0H = 0.9 T
1200
1100
1000
800
8
700
600
500
400
5
300
200
100
0
16.00
applied field H
16.25
Current (mA)
Power (pW)
900
3
16.50
Frequency (GHz)
Monostable device (high fields): Currenttunable, Coherent, microwave
magnetization precession
Pufall, THIC’05: 24
Summary
MRAM is possible “universal” memory solution
• “Spintronic” device: Uses e- charge and spin
• Fast (3-10 ns switching times)
• Nonvolatile (magnetic storage)
• Low power (no refresh)
• Rad-hard (though supporting electronics aren’t!)
Toggle MRAM solves ½-select problem
Problem: Must scale competitively with Si technology
• Nanomagnetic elements sensitive to temperature
• Complicated lithography
Emerging technology solution: Switching with Spinpolarized electron currents
Pufall, THIC’05: 25
Pufall, THIC’05: 26
A Brief History of MRAM
BIWB Core memory, first disk drive, flat film, bubble, plated wire
1984-86 A. V. Pohm and Honeywell
investigating radiation hard memory based fir
BM
I
on anisotropic magnetoresistance (AMR)
84
19
1987 GMR Discovered: Binash, Grunberg et al, PRB B 39, 4828 (1989); Baibich, Fert
et al. PRL 61, 2472 (1988).
1989 NVE formed to develop AMR based MRAM
1990 IBM Spin Valve
(B. Dieny, V Speriosou, S. S. Parkin, B Gurney et al.)
1994 IBM Spin valve MRAM patent (D. D. Tang et al. IBM)
19
I
91
BM
st
fir
1995 Magnetic Tunnel Junctions (MTJ) (Modera et al PRL 74, 3273, 1995)
1996 DARPA MRAM program: Honeywell (PSV), Motorola
(PSV⇒MTJ) IBM (MTJ)
1999 IBM, Motorola MRAM working demos??
19
I
98
BM
du
o
r
t
in
h
ce
st
eM
p
a
t
is
-d
d
ar
t
irs
f
s
R
kM
R
M
G
R
a
he
d
a
he
a
he
d
d
2002 Motorola goes to cladded write lines & tToggle write
2004 Motorola samples 4M MRAM chip
2004/2005 230% TMR in MgO MTJs; Spin transfer switched MRAM
Pufall, THIC’05: 27