Packaging - Enabler for Integration in Mobile Applications

Packaging - Enabler for
Integration in Mobile Applications
Andreas Wolter
Mobile and Communications Group
June 27th, 2013
Content
• Mobile and Communications Group
• Mobile Evolution
• System Integration
– Chip/ Package Co-Design
– Side by Side SiP
– Stacking
o Wirebond, FC-Wirebond
o Package on Package Stacking
o 2.5D Interposer Stacking
o 3D TSV Stacking
• Summary
2
Intel Mobile and Communications Group
Source: http://etherealisation.com/2010/12/mortan-ingemanns-wireless/
 MCG (Mobile and Communications Group) is a business group of Intel Corporation
 MCG develops and markets innovative semiconductor products and solutions for
mobiles, tablets and emerging devices
 MCG products comprise:
• Application Processors
• Mobile platform solutions for all market segments from ultra low cost phones to
advanced smart phones and tablets.  Basebands, Modems, PMU, 2G, 3G, LTE
• Connectivity as Wi-Fi, BT, GPS
3
Trend to Mobile Devices
PCs shipped
2002:
1 bn
2007:
2 bn
Today: ~3.5 bn
PCs installed
1.5 billion installed PCs
today (2 bn in 2015)
Mobile Phones
~6 bn mobile phone
subscriptions worldwide
at the end of 2011
IDC predictions
4
PC = desktop, notebook & server
Device Market Opportunity
>2B
>1.5B
2011
Traditional Phones
Tablets
Connected Devices
2013
In the 2012-16 period, there will be shipments
of:
~9
billion
Phones (of which, 4.6 billion smartphones)
300+
million
‘Cellular’ Tablets
400+
million
M2M modules
1+
billion
USB dongles and other consumer
electronics with cellular connectivity
2016
Smartphones
M2M Modules
~11 Billion Unit Opportunity in 2012-2016
5
Mobile Evolution
1970
1980
1990
2000
2010
Brick Phone
Candy Bar
Feature Phone
Smart Phone
Touch Phone
Candy Bar
• GSM, CDMA,
TDMA, iDEN
• Small size
• SMS service
6
Smart Phone
• GPRS, HSPDA,
Wi-Fi
• Emails driver
• Gadget
Feature Phone
• GPRS, HSCSD
• Data capable
• Camera & MMS
• Mass adoption
Touch Phone
• GPRS, HSPDA,
EVDO, Wi-Fi, LTE
• Sensors, MEMS
• Media Platform
• All about web…
Moore’s Law Scaling
www.itrs.net
can not maintain the pace of progress
In the past:
scaling geometries
enabled
improved
performance,
less power, smaller
size, and lower cost.
Today:
scaling alone does not ensure
improvement of
performance, power,
size and cost.
The primary mechanism
to deliver “More
than Moore” will
come from
integration of
multiple circuit types through
SoC and SiP.
SiP will allow the efficient use
of three dimensions through
innovation in packaging
technology.
7
Mobile Application Package
Trends
 Package down-sizing
 Higher substrate utilization
 Better electrical performance
Wafer Level BGA
Flip Chip BGA
 Down-sizing potential
 Better thermal and electrical
performance
 Cost reduction potential
 Minimum SiP cost adder
Wire Bond BGA
Embedded Die
8
 Performance (f2f)
 Stacking
 Passives embedding
eWLB
(embedded Wafer Level Package)
More than 1 Billion
components sold
9
System Integration
“System integration brings together components into one system and is
ensuring that the components function together as a system”
Important:
 Co-Design
… for the design optimization of the system
module in
eWLB technology:
2 chips side by side,
passives, filters,
PoP on backside
Integration by:
 Side-by-side SiP
 Stacking




Embedded Package Technologies
Package on Package (PoP) stacking
2.5D Interposer Stacking
Die stacking (actives, passives)
 Modules
10
… inherent stacking possibility
… test and burn-in capability and external supply
… half way to stacking
… the hype
… high integration
Chip-Package Co-Design
Design Challenges – we talk about…
Redistribution
ICs
Other embedded
parts
Other ICs/stacks
Other Parts
on PCB
PCB
 Many technologies (& libraries) within one project:
different silicon tech’s – substrate / RDL – PCB – other components
 Multiple length scales
cm  PCB, mm  Substrate, µm  chip, sub-µm  chip devices
 Strong interdependencies between dies, package, testing & application board
 independent optimization at different levels cannot lead to optimum system
 Global design optimization required (chips – package – board/system)
 higher performance, reduced cost, better quality
11
System Integration
Package Technology
www.itrs.net
12
Side-by-Side SiP
• Typically wire bonding or flip-chip bonding technology has been used
• easy to realize in eWLB
• enable pick and place for several die types
• ensure mold filling between dies
• control die shifts, warpage of recon wafer
• Enable higher data transfer rate between
dies on module
• Short interconnect line length targeted
• Bringing dies close together is the key
• Larger package size compared to stacking
Two-die multi-chip eWLB
13
Embedded Die
•
•
•
•
•
Inherent stacking capability as alternative to side by side.
Enabler is basic PCB-technology providing vias and 2 side
metallization.
developed by a wide range of companies for several years
high potential for integration / miniaturization
Challenges:
-- min chip pad pitch = 175µm (typically)
-- supply chain: OSAT + PCB-manufacturer
Example: DC/DC converter:
–
–
–
14
DC/DC converter embedded in substrate
Passive SMD components mounted onto substrate
Size benefit due to face-down mounting of converter
embedded die bottom package
Stacking
Why Stacking?
 Higher electrical Performance
Shorter and less interconnects, lower parasitics,
higher bandwidth
 Smaller Form Factor
Small lateral dimensions, low package height,
higher density
 Heterogeneous integration
Integration of different functional layers (RF,
memory, logic, MEMS, …) based on different
optimized process nodes
 Shorter Time-to-Market
Capability to partitioning, reusable (die-level)
building blocks
 Lower Development, Tooling and Unit Costs
In high volume production
 Die-Level Modularity Reduces Risk
Modularity reduces the risk of failure.
15
Wire bonded stack
TSV stack
Traditional Stacking
Traditional Stacking
PoP
2.5D Interposer
3D-TSV Stack
Flip Chip & Wire Bond
Package on Package
side-by-side integration
vertical integration
Source: SOCcentral


SEM photograph of a 4-die wire-bond
stack-up with direct die-to-die and spacer
16
Stacking of multiple chips into one package
Realization of interconnects typically by flip chip or wire bond
Advantages:
• Reduced package height/ dimensions
• Known processes, high yield
Disadvantages:
• Electrical performance
• Capability for future technology nodes
PoP Stacking
Traditional Stacking
PoP
2.5D Interposer
3D-TSV Stack
Flip Chip & Wire Bond
Package on Package
side-by-side integration
vertical integration
Peripheral BGA balls
interconnecting top and
bottom package
BGA balls connection
to motherboard (desoldered)
Top
package
iPhone's ARM processor (Flip Chip, bottom package) &
DRAM package (Wire Bond, top package)
17

Bottom
package
Stacking of multiple (possibly different kinds of)
packages onto each other
Advantages:
• Both packages can be tested and burned
before assembly
• Interfaces standardized
Disadvantages:
• Dimensions
• Electrical performance
PoP Stacking:
eWLB based TMV PoP
Height reduction is key…
Courtesy of STATSChipPAC
 eWLB standard flow with TMV
connections
 Lowest package profile with but
with only peripheral interconnects
18
Courtesy of STATSChipPAC
PoP Stacking: ePoP
 ePoP: embedded Package on Package
 eWLB flow with two sided redistribution (RDL)
 Multiple possibilities for connection in z-direction:
TMV, TSV, pre-fabricated via bars (PCB, Si)
 area array interconnects on ePoP package backside
 low package height
 Good electrical performance due to short interconnects
 Large package sizes remain a challenge for board level
reliability (without underfill)
19
2.5D Interposer Stacking
Traditional Stacking
PoP
2.5D Interposer
3D-TSV Stack
Flip Chip & Wire Bond
Package on Package
side-by-side integration
vertical integration
2.5D Interposer
BGA Interposer
2.5D silicon Interposer, Cross Section
(Courtesy of ASE)
20
Top Die
 Passive silicon interposer on a BGA laminate
 Side-by-side placement of multiple dies possible
Advantages:
• Si-Interposer technology allows use of very fine pitch
dies and integration of thin-film passives
• Expansion-matching
Trade-Off:
• Cost of Si-interposer with TSVs and multiple RDLs
• Lateral size of multi-chip-package
2.5D Interposer Stacking
Performance driven Example
21
2.5D-Interposer-Stacking: eWLB Alternative
Possible Solution for Low End…
low-k
Approach FC-eWLB:
Flip Chip
2.5D-interposer replacement by
eWLB (for redistributing the extreme
fine pitch to std. Flip-Chip-pitch) and
100µm pitch
SiInterposer
200µm pitch
Substrate
a standard Flip Chip assembly
0.4mm pitch
Avoid
extreme fine 1st level interconnect
si interposer w/ 2-sided RDL, TSVs
Leading to a …
Std. Flip Chip approach with
low-k
 High reliability (FC comparable)
 Lower package height
 Lower cost
 Higher yield
than 2.5D
Interposer
eWLB
Flip Chip
Substrate
 Existing packaging infrastructure (OSATs)
22
200µm pitch
0.4mm pitch
3D TSV-Stacking
Traditional Stacking
PoP
2.5D Interposer
3D-TSV Stack
Flip Chip & Wire Bond
Package on Package
side-by-side integration
vertical integration

Samsung 16Gb NAND stack with TSV
Source: Internet
23
Stacking of multiple chips into each other with shortest
interconnect through the chips (TSV)
Advantages:
• Performance
• Dimensions
Disadvantages:
• Cost
• Maturity
3D TSV-Stacking:
Wide I/O DRAM: A first adoption possibility of TSV…
Source: S. Dumas, Mobile Memory Forum, June 2011
•
•
•
•
24
Wide I/O DRAM offers twice the bandwidth of LPDDR2 for
same power
1200 standardized interconnects to the memory chip
Usage in high performance smartphones first
Likely the first TSV application to come with Logic
3D TSV Stacking
Applications Status, Drivers and Barriers
Application
Driver
Status
Barrier
Image Sensors
Performance, form factor
Production
None
CPUs & memory
Performance
16nm silicon and
beyond
Cost, process, yield,
infrastructure
CPUs & memory
Performance
2014
Cost, process, yield,
infrastructure
FPGAs
Performance
2014
Cost, process, yield,
infrastructure
Wide I/O memory
with Logic
Performance (bandwidth,
lower power consumption)
2012-2013
Cost, process, yield,
KGD, infrastructure
Memory (stacked)
Performance, form factor (z)
(2012)
2013
Cost, process, yield,
assembly
(Source: TechSearch International, Inc., 2011)
 TSV Applications in production with backside vias for Image sensors, MEMS, LED
 3D IC Research and prototypes in memory, wireless applications (Wide I/O), high-speed logic
(processors, FPGAs)
25
Summary
• Packaging is one key to solve the challenges of System Level Integration.
• Side by Side SiPs can be realized as extension of existing technologies.
• Stacking requires new technologies but is the strongest enabler for integration.
• Many stacking technologies are available − Few applications of stacking made
it to commercial success.
• More stacking to come with realization of TSVs when cost, supply chain and
yield issues will be solved
• Until then, other solutions may step in… Fan-Out Wafer Level Packaging is
offering a broad range of possibilities for System Integration and will therefore
be one packaging technology of the future.
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Thank You for Your Attention