MC6809–MC6809E 8-Bit Microprocessor Programming Manual

M6809PM (AD)
MC6809·MC6809E
8·BIT MICROPROCESSOR
PROGRAMMING MANUAL
Original Issue: March 1, 1981
Reprinted: May 1983
©MOTOROLA INC., 1981
TABLE OF CONTENTS
Paragraph No.
Page No.
Title
SECTION 1
GENERAL DESCRIPTION
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.10.1
1.10.1.1
1.10.1.2
1.10.1.3
1.10.1.4
1.10.1.5
1.10.2
1.10.2.1
1.10.2.2
1.10.2.3
1.11
1.11.1
1.11.1.1
1.11.1.2
1.11.1.3
1.11.2
1.11.3
1.11.4
1.11.5
1.11.6
1.11.7
1.11.8
1.11.8.1
1.11.8.2
1.11.8.3
Introduction .............................................................................................................1-1
Features
1-1
Software Features ..................................................................................................1-2
Programming Model ...............................................................................................1-3
Index Registers (X, Y)
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Stack Pointer Registers (U, S) ...............................................................................1.3
Program Counter ( PC) ............................................................................................1-4
Accumulator Registers (A, B, D) ...........................................................................1-4
Direct Page Register (O P) ...................................................................................... 1-4
Condition Code Register (CC) ...............................................................................1-4
Condition Code Bits ...........................................................................................1-5
Half Carry ( H), Bit 5 .........................................................................................1-5
Negative (N), Bit 3 ...........................................................................................1-5
Zero (Z), Bit 2....................................................................................................1.5
Overflow (V), Bit 1 .
. . . . ..
. .. 1-5
Carry (C), Bit 0 .................................................................................................1-5
Interrupt Mask Bits and Stacking Indicator .................................................... 1-5
Fast Interrupt Request Mask (F), Bit 6 .........................................................1-5
Interrupt Request Mask (I), Bit 4 ...................................................................1-5
Entire Flag (E), Bit 7 ........................................................................................1-6
Pin Assignments and Signal Oescription ............................................................ 1-6
MC6809 Clocks ...................................................................................................1-6
Oscillator (EXTAL, XTAL)...............................................................................1-6
Enable (E)............. ,...........................................................................................1-7
Quadrature (Q) ................................................................................................1-7
MC6809E Clocks (E and Q) ................................................................................1-7
Three State Control (TSC) (MC6809E) ..............................................................1-7
Last Instruction Cycle (LIC) (MC6809E) ...........................................................1-7
Address Bus (AO·A15).........................................................................................1-7
Data Bus (00-07) .................................................................................................1-7
ReadlWrite (RIW).................................................................................................1-8
Processor State Indicators (BA, BS) ................................................................1-8
Normal .............................................................................................................1-8
Interrupt or Reset Acknowledge ...................................................................1-8
Sync Acknowledge .........................................................................................1-8
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TABLE OF CONTENTS
(CONTINUED)
Title
Paragraph No.
1.11.8.4
1.11.9
1.11.10
1.11.10.1
1.11.10.2
1.11.10.3
1.11.11
1.11.12
1.11.13
1.11.14
1.11.15
1.11.16
Page No.
Halt/Bus Grant ................................................................................................1·8
Reset (RESET) .....................................................................................................1·9
Interrupts .............................................................................................................1·9
Non·Maskable Interrupt (NMI) ......................................................................1·9
Fast Interrupt Request (FIRQ).......................................................................1·9
Interrupt Request (IRQ)..................................................................................1·9
Memory Ready (MRD Y) (MC6809) .....................................................................1·9
Advanced Valid Memory Address (AVMA) (MC6809E) .................................1·10
Halt (HALT) ........................................................................................................1·10
Direct Memory Access/Bus Request (DMA/BREQ) (MC6809) .....................1·10
Busy (MC6809E) ................................................................................................1·10
Power
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1·11
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SECTION 2
ADDRESSING MODES
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.5.1
2.2.5.2
2.2.5.3
2.2.5.4
2.2.5.5
2.2.5.6
2.2.6
Introduction
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2·1
Addressing Modes ..................................................................................................2·1
Inherent................................................................................................................2·1
Immediate .
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Extended
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Direct
2·2
Indexed
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Constant Offset from Register . ... .
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Accumulator Offset from Register ...............................................................2·3
Autoincrement/Decrement from Register...................................................2·3
Indirection .......................................................................................................2·4
Extended Indirect ...........................................................................................2·4
Program Counter Relative .............................................................................2·4
Branch Relative ..................................................................................................2·4
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SECTION 3
INTERRUPT CAPABILITIES
3.1
3.2
3.3
3.4
3.5
Introduction .............................................................................................................3·1
Non·Maskable Interrupt (NMI) ..............................................................................3·1
Fast Maskable Interrupt Request (FIRQ).............................................................3·2
Normal Maskable Interrupt Request (IRQ) ..........................................................3·2
Software Interrupts (SWI, SWI2, SWI3) ................................................................3·2
iv
TABLE OF CONTENTS
(CONCLUDED)
Paragraph No.
Title
Page No.
SECTION 4
PROGRAMMING
4.1
4.1.1
4.1.2
4.1.2.1
4.1.2.2
4.1.3
4.2
4.2. 1
4.2.1. 1
4.2.1.2
4.2.1.3
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.6.1
4.2.6.2
4.2.6.3
4.2.7
4.3
4.4
Introduction ............................................................................................................. 4-1
Position-Independence ...................................................................................... 4-1
Modular Programming ....................................................................................... 4-1
Local Storage .................................................................................................. 4-1
Global Storage ................................................................................................ 4-2
Reentrancy/Recursion ....................................................................................... 4-2
M6809 Capabilities ................................................................................................. 4-2
Module Construction ......................................................................................... 4-2
Parameters ...................................................................................................... 4-3
Local Storage ..................................................................................................4-3
Global Storage ................................................................................................4-3
Position-Independent Code .............................................................................. 4-4
. Reentrant Programs ........................................................................................... 4-5
Recursive Programs ...........................................................................................4-5
Loops
4-5
Stack Programming ...........................................................................................4-6
M6809 Stacking Operations ..........................................................................4-6
Subroutine Linkage ........................................................................................4-7
Software Stacks .............................................................................................4-8
Real Time Programming ....................................................................................4-8
Program Documentation
4-8
Instruction Set ........................................................................................................4-9
...................................................................................................................
.......................................•...............................................
APPENDIX A
INSTRUCTION SET DETAILS
A.1
A.2
Introduction ............................................................................................................A-1
Notation ..................................................................................................................A-1
Instructions (listed in alphabetical order)...........................................................A-3
APPENDIX B
ASSIST09 MONITOR PROGRAM
8.1
8.2
8.3
8.4
General Description ............................................................................................... 8-1
Implementation Requirements ............................................................................ 8-1
Interrupt Control .................................................................................................... 8-2
Initialization ............................................................................................................ 8-3
v
TABLE OF CONTENTS
(CONTINUED)
Title
Paragraph No.
Page No.
B.5
Input/Output Control ............................................................................................. B-4
B.6
B.7
Command Format ..................................................................................................B-4
Command List ........................................................................................................B-5
B.8
Commands .............................................................................................................. B-5
Breakpoint ...........................................................................................................B-6
Call .......................................................................................................................B-6
Display .................................................................................................................B-7
Encode ................................................................................................................B-7
Go
B-8
.........................................................................................................................
Load ..................................................................................................................... B-8
Memory ...............................................................................................................B-9
Null ....................................................................................................................B-10
Offset ................................................................................................................. B-10
Punch
B-11
Register ............................................................................................................. B-11
.....................................................•...........................................................
Stlevel ................................................................................................................B-12
Trace ..................................................................................................................B-12
B.9
Verify .................................................................................................................B-13
Window .............................................................................................................B-13
Services ................................................................................................................. B-14
BKPT ..................................................................................................................B-15
INCHP................................................................................................................B-15
MONITR.............................................................................................................B-16
OUTCH ..............................................................................................................B-17
OUT2HS.............................................................................................................B-17
OUT4HS.............................................................................................................B-18
PAUSE ...............................................................................................................B-18
PCRLF ...............................................................................................................B-19
PDATA ............................................................................................................... B-19
PDATA1 .............................................................................................................B-20
SPACE ....•..........................................................................................................B-21
VTRSW ..............................................................................................................B-21
B.10
Vector Swap Service ............................................................................................B-22
.ACIA ..................................................................................................................B-23
.AVTBL...............................................................................................................B-23
.BSDTA .............................................................................................................. B-24
.BSOFF ..............................................................................................................B-24
.BSON ................................................................................................................B-25
.CIDTA ...............................................................................................................B-25
.CIOFF ...............................................................................................................B-26
.CION .................................................................................................................B-26
.CMDL1 ..............................................................................................................B-27
.CMDL2 ..............................................................................................................B-28
vi
TABLE OF CONTENTS
(CONTINUED)
Paragraph No.
Page No.
Title
.CODTA
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8-28
.COOFF ............................................................................................................. 8-29
.COON ............................................................................................................... 8-29
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.ECHO ................................................................................................................ 8-30
.FIRQ .................................................................................................................. 8-30·
.HSDATA
.IRQ
.NMI
.PAD
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8-31
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8-32
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8-35
.SWI2.................................................................................................................. 8-35
.SWI3.................................................................................................................. 8-36
8.11
Monitor Listing
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APPENDIX C
MACHINE CODE TO INSTRUCTION CROSS REFERENCE
C.1
Introduction .
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APPENDIX D
PROGRAMMING AID
0.1
Introduction ..... . . . .. .... ...
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APPENDIX E
ASCII CHARACTER SET
E.1
E.2
E.3
E.4
Introduction ............................................................................................................E·1
Character Representation and Code Identification ..........................................E·1
Control Characters ................................................................................................E·2
Graphic Characters ...............................................................................................E·2
vii
TABLE OF CONTENTS
(CONTINUED)
Paragraph No.
Title
Page No.
APPENDIX F
OPCODE MAP
F.1
Introduction
F.2
Opcode Map............................................................................................................ F-1
F-1
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APPENDIX G
PIN ASSIGNMENTS
G.1
Introduction ............................................................................................................ G-1
APPENDIX H
CONVERSION TABLES
H.1
H.2
Introduction ............................................................................................................ H-1
Powers of 2; Powers of 16 ..................................................................................... H-1
H.3
Hexadecimal and Decimal Conversion............................................................... H-2
H.3.1
H.3.2
Converting Hexadecimal to Decimal .............................................................. H-2 .
Converting Decimal to Hexadecimal .............................................................. H-2
LIST OF ILLUSTRATIONS
Figure No.
Title
Page No.
1-1
1-2
1-3
Programming Model ...............................................................................................1-3
Condition Code Register .......................................................................................1-4
Processor Pin Assignments .................................................................................. 1-6
2-1
Post byte Usage for EXGrrFR, PSH/PUllnstructions ........................................2-2
3-1
Interrupt Processing Flowchart ............................................................................3-5
4-1
Stacking Order ........................................................................................................4-7
8-1
Memory Map ........................................................................................................... 8-2
E-1
ASCII Character Set ...............................................................................................E-1
G-1
Pin Assignments .................................................................................................... G-1
viii
LIST OF TABLES
Title
Table No.
Page No.
1 -1
BAlBS Signal Encoding
2-1
Postbyte Usage for Indexed Addressing Modes ................................................2-3
3-1
Interrupt Vector Locations
4-1
4-2
8-Bit Accumulator and Memory Instructions
Instruction Set
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4-9
. 4-1 1
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4-3
16-Bit Accumulator and Memory Instructions
4-4
Index/Stack Pointer Instructions
4-5
4-6
Branch Instructions
Miscellaneous Instructions
A-1
Operation Notation
A-2
Register Notation ...................................................................................................A-2
B-1
B-2
B-3
Command List ........................................................................................................B-5
Services
B-1 4
Vector Table Entries ............................................................................................B-22
C-1
Machine Code to Instruction Cross Reference .................................................. C-2
0-1
Programming Aid ................................................................................................... 0-1
E-1
E-2
Control Characters ................................................................................................ E-2
Graphic Characters .
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E-3
F-1
F-2
Opcode Map
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Indexed Addressing Mode Data
H-1
H-2
Powers of 2; Powers of 16 .....................................................................................H-1
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Hexadecimal and Decimal Conversion Chart ....................................................H-2
ix/x
SECTION 1
GENERAL DESCRIPTION
1.1
INTRODUCTION
This section contains a general description of the Motorola MC6809 and MC6809E
Microprocessor Units (MPU). Pin assignments and a brief description of each input/out­
put signal are also given. The term MPU, processor, or M6809 will be used throughout this
manual to refer to both the MC6809 and MC6809E processors. When a topic relates to
only one of the processors, that specific designator (MC6809 or MC6809E) will be used.
.
1.2
FEATURES
The MC6809 and MC6809E microprocessors are greatly enhanced, upward compatible,
computationally faster extensions of the MC6800 microprocessor.
Enhancements such as additional registers (a Y index register, a U stack pOinter, and a
direct page register) and instructions (such as MUL) simplify software design. Improved
addressing modes have also been implemented.
Upward compatibility is guaranteed as MC6800 assembly language programs may be
assembled using the Motorola MC6809 Macro Assembler. This code, while not as com­
pact as native M6809 code, is, in most cases, 100% functional.
Both address and data are available from the processor earlier in an instruction cycle
than from the MC6800 which simplifies hardware design. Two clock signals, E (the
MC6800 <1>2) and a new quadrature clock Q (which leads E by one-quarter cycle) also
simplify hardware design.
A memory ready (MRDY) input is provided on the MC6809 for working with slow
memories. This input stretches both the processor internal cycle and direct memory ac­
cess bus cycle times but allows internal operations to continue at full speed. A direct
memory access request (DMAIBREQ) input is provided for immediate memory access or
dynamic memory refresh operations; this input halts the internal MC6809 clocks.
Because the processor's registers are dynamic, an internal counter periodically recovers
the bus from direct memory access operations and performs a true processor refresh
cycle to allow unlimited length direct memory access operation. An interrupt
acknowledge signal is available to allow development of vectoring by interrupt device
hardware or detection of operating system calls.
1-1
Three prioritized, vectored, hardware interrupt levels are available: non-maskable, fast,
and normal. The highest and lowest priority interrupts, non-maskable and interrupt re­
quest respectively, are the normal interrupts used in the M6800 family. A new interrupt on
this processor is the fast interrupt request which provides faster service to its interrupt
input by only stacking the program counter and condition code register and then servic­
ing the interrupt.
Modern programming techniques such as position-independent, system independent,
and reentrant programming are readily supported by these processors.
A Memory Management Unit (MMU), the MC6829, allows a M6809 based system to ad­
dress a two megabyte memory space. Note: An arbitrary number of tasks may be sup­
ported - slower - with software.
This advanced family of processors is compatible with all M6800 peripheral parts.
1.3
SOFTWARE FEATURES
Some of the software features of these processors are itemized in the following
paragraphs. Programs developed for the MC6800 can be easily converted for use with the
MC6809 or MC6809E by running the source code through a M6809 Macro Assembler or
any one of the many cross assemblers that are available.
The addressing modes of any microprocessor provide it with the capability to efficiently
address memory to obtain data and instructions. The MC6809 and MC6809E have a ver­
satile set of addressing modes which allow them to function using modern programming
techniques.
The addressing modes and instructions of the MC6809 and MC6809E are upward com­
patible with the MC6800. The old addressing modes have been retained and many new
ones have been added.
A direct page register has been added which allows a 256 byte "direct" page anywhere in
the 64K logical address space. The direct page register is used to hold the most­
significant byte of the address used in direct addreSSing and decrease the time required
for address calculation.
Branch relative addressing to anywhere in the memory map (- 32768 to + 32767) is
available.
Program counter relative addreSSing is also available for data access as well as branch
instructions.
The indexed addreSSing modes have been expanded to include:
0-, 5-, 8-, 16-bit constant offsets,
8- or 16-bit accumulator offsets,
autoincrement/decrement (stack operation).
1-2
In addition, most indexed addressing modes may have an additional level of indirection
added.
Any or all registers may be pushed on to or pulled from either stack with a single instruc­
tion.
A multiply instruction is included which multiplies unsigned binary numbers in ac­
cumulators A and B and places the unsigned result in the 16-bit accumulator D. This un­
signed multiply instruction also allows signed or unsigned multiple precision multiplica­
tion.
1.4
PROGRAMMING MODEL
The programming model (Figure 1-1) for these processors contains five 16-bit and four
8-bit registers that are available to the programmer.
o
15
x - I ndex Register
Y - I ndex Register
U - User Stack Pointer
S - Hardware Stack Poi nter
,
I
Po;",,, Rog;"""
Progra m Cou nter
PC
A
}
Accumu lators
B
D
7
LoI
0
DP
1
...
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7
Direct Page Register
0
I ElF I H I I I N I z I V I C I
Condition Code Register
Figure 1·1. Programming Model
1.5
INDEX REG ISTERS (X, y)
The index registers are used during the indexed addressing modes. The address informa­
tion in an index register is used in the calculation of an effective address. This address
may be used to point directly to data or may be modified by an optional constant or
register offset to produce the effective address.
1.6
STACK POINTER REGISTERS (U, S)
Two stack pOinter registers are available in these processors. They are: a user stack
pOinter register (U) controlled exclusively by the programmer, and a hardware stack
pOinter register (5) which is used automatically by the processor during subroutine calls
1-3
and interrupts, but may also be used by the programmer. Both stack pOinters always
point to the top of the stack.
These registers have the same indexed addressing mode capabilities as the index
registers, and also support push and pull instructions. All four indexable registers (X, Y,
U, S) are referred to as pOinter registers.
1.7
PROGRAM COUNTER (PC)
The program counter register is used by these processors to store the address of the
next instruction to be executed. It may also be used as an index register in certain ad·
dressing modes.
1.8
ACCUMULATOR REGISTERS (A, B, D)
The accumulator registers (A, B) are general·purpose 8·bit registers used for arithmetic
calculations and data manipulation.
Certain instructions concatenate these registers into one 16·bit accumulator with
register A positioned as the most·significant byte. When concatenated, this register is
referred to as accumulator D.
1.9
DIRECT PAG E REGISTER (DP)
This 8-bit register contains the most·significant byte of the address to be used in the
direct addressing mode. The contents of this register are concatenated with the byte
following the direct addressing mode operation code to form the 16·bit effective address.
The direct page register contents appear as bits A15 through A8 of the address. This
register is automatically cleared by a hardware reset to ensure M6800 compatiblity.
1.10
CONDITION CODE REGISTER (CC)
The condition code register contains the condition codes and the interrupt masks as
shown in Figure 1·2.
Carry
....-Overflow
..
----Zero
----- Negative
.......
---
- I RQ Mask
....----.
H alf Carry
'------ FIRQ Mask
----- Entire Flag
Figure 1·2. Condition Code Register
1·4
1.10.1 CONDITION CODE BITS. Five bits in the condition code register are used to in­
dicate the results of instructions that manipulate data. They are: half carry (H), negative
(N), zero (Z), overflow (V), and carry (C). The effect each instruction has on these bits is
given in the detail information for each instruction (see Appendix A).
1.10.1.1 Half Carry (H), Bit 5. This bit is used to indicate that a carry was generated from
bit three in the arithmetic logiC unit as a result of an a-bit addition. This bit is undefined in
all subtract-like instructions. The decimal addition adjust (OAA) instruction uses the
state of this bit to perform the adjust operation.
1.10.1.2 N eg ative (N),
Bit 3. This bit contains the value of the most-significant bit of the
result of the previous data operation.
1.10.1.3 Zero (Z), Bit 2. This bit is used to indicate that the result of the previous opera­
tion was zero.
1.10.1.4 Overflow (V),
Bit 1. This bit is used to indicate that the previous operation caused
a signed arithmetic overflow.
1.10.1.5 Carry(C), Bit O. This bit is used to indicate that a carry or a borrow was generated
from bit seven in the arithmetic logic unit as a result of an a-bit mathematical operation.
1.10.2 INTERRUPT MASK BITS AND STACKING INDICATOR. Two bits (I and F) are used
as mask bits for the interrupt request and the fast interrupt request inputs. When either
or both of these bits are set, their associated input will not be recognized.
One bit (E) is used to indicate how many registers (all, or only the program counter and
condition code) were stacked during the last interrupt.
Mask (F), Bit 6. This bit is used to mask (disable) any fast
Q
interrupt request line (FIR ). This bit is set automatically by a hardware reset or after
recognition of another interrupt. Execution of certain instructions such as SWI will also
inhibit recognition of a FIRQ input.
1.10.2.1 Fast
Interrupt
Request
Ma s k (I), Bit
This bit is used to mask (disable) any interrupt
request input (IRQ). This bit is set automatically by a hardware reset or after recognition
of another interrupt. Execution of certain instructions such as SWI will also inhibit
recognition of an IRQ input.
1.10.2.2Interru�equest
4.
1·5
1.10.2.3 Ent i re Flag (E), Bit 7. This bit is used to indicate how many registers were stack­
ed. When set, all the registers were stacked during the last interrupt stacking operation.
When clear, only the program counter and condition code registers were stacked during
the last interrupt.
The state of the E bit in the stacked condition code register is used by the return from in­
terrupt (RTI) instruction to determine the number of registers to be unstacked.
1.11 PIN ASSIGNMENTS AND SIGNAL DESCRIPTION
Figure 1-3 shows the pin assignments for the processors. The following paragraphs pro­
vide a short description of each of the input and output signals.
MC6809E
MC6809
VSS
H'A'CT
VSS
HALT
NMI
XTAL
NMI
TSC
IRQ
EXTAL
IRQ
37
RESET
36
AVMA
35
Q
LlC
FIRQ
4
RESET
FIRQ
BS
5
MR O Y
BS
BA
6
Q.
VCC
7
E
AO
8
OMA/BREQ
Al
9
R/ W
32
A2
10
DO
31
DO
A3
11
01
30
01
02
29
02
03
28
03
04
04
05
27
26
06
25
06
07
Al5
A6
A7
A8
16
VCC
34
E
AO
33
BUSY
R/W
05
Al0
Al5
Al0
24
23
All
A14
All
22
Al4
Al2
21
A13
A9
A9
07
A12
Figure 1-3. Processor Pin Assignments
1.11.1 MC6809 CLOCKS. The MC6809 has four pins committed to developing the clock
signals needed for internal and system operation. They are: the oscillator pins EXTAL
and XTAL; the standard M6800 enable (E) clock; and a new, quadrature (Q) clock.
1.11.1.1 Oscillator (EXTAL, XTAL). These pins are used to connect the processor's inter­
nal oscillator to an external, parallel-resonant crystal. These pins can also be used for in­
put of an external TTL timing signal by grounding the XTAL pin and applying the input to
the EXTAL pin. The crystal or the external timing source is four times the resulting bus
frequency.
1-6
1.11.1.2 Enable (E). The E clock is similar to the phase 2 (<p2) MC6800 bus timing clock.
The leading edge indicates to memory and peripherals that the data is stable and to
begin write operations. Data movement occurs after the Q clock is high and is latched on
the trailing edge of E. Data is valid from the processor (during a write operation) by the
rising edge of E.
1.11.1.3 Quadrature (Q). The Q clock leads the E clock by approximately one half of the E
clock time. Address information from the processor is valid with the leading edge of the
Q clock. The Q clock is a new signal in these processors and does not have an equivalent
clock within the MC6800 bus timing.
1.11.2 MC6809E CLOCKS (E and Q). The MC6809E has two pins provided for the TIL
clock signal inputs required for internal operation. They are the standard M6800 enable
(E) clock and the quadrature (Q) clock. The Q input must lead the E input.
Addresses will be valid from the processor (on address delay time after the falling edge
of E) and data will be latched from the bus by the falling edge of E. The Q input is fully TIL
compatible. The E input is used to drive the internal MOS circuitry directly and therefore
requires input levels above the normal TIL levels.
1.11.3 THREE STATE CONTROLS (TSC) (MC6809E). This input is used to place the ad­
dress and data lines and the RIW line in the high-impedance state and allows the address
bus to be shared with other bus masters.
1.11.4 LAST INSTRUCTION CYCLE (LIC)(MC6809E). This output goes high during the last
cycle of every instruction and its high-to-Iow transition indicates that the first byte of an
opcode will be latched at the end of the present bus cycl�.
1.11.5 ADDRESS BUS(AO·A15). This 16-bit, unidirectional, three-state bus is used by the
processor to provide address information to the address bus. Address information is
valid on the rising edge of the Q clock. All 16 outputs are in the high-impedance state
when the bus available (BA) signal is high, and for one bus cycle thereafter.
When the processor does not require the address bus for a data transfer, it outputs ad­
dress FFFF16, and read/write (RIW) high. This is a "dummy access" of the least­
significant byte of the reset vector which replaces the valid memory address (VMA) func­
tions of the MC6800. For the MC6809, the memory read signal internal circuitry inhibits
stretching of the clocks during non-access cycles.
1.11.6 DATA BUS (00·07). This 8-bit, bidirectional, three-state bus is the general purpose
data path. All eight outputs are in the high-impedance state when the bus available (BA)
output is high.
1-7
1 .11.7 READIWRITE (RIW). This output indicates the d i rection of data transfer on the data
bus. A low indicates that the processor is writi n g onto the data bus; a high indicates that
the processor is read i n g data from the data bus. The signal at the R/W output is val i d at
the lead i n g edge of the Q clock. The R/W output is in the h igh-i m pedance state when the
bus ava i l able (BA) output is high.
1 .1 1.8 PROCESSOR STATE INDICATORS (BA, BS). The processor uses these two output
l i nes to indicate the p resent processor state. These pins are val id with the leadi n g edge
of the Q c lock.
The bus available (BA) output is used to i ndicate that the buses (address and data) and
the read/write output are in the h i g h-Im pedance state. Thi s signal can be used to i n d i cate
to bus-sharing or d irect memory access systems that the buses are available. When BA
goes low, an additional dead cycle will elapse before the processor regains control of the
buses.
The bus status (BS) output is used in conjunction With the BA output to I ndicate the pre­
sent state of the processor. Table 1 -1 is a listing of the BA and BS outputs and the pro­
cessor states that they Indicate. The fol lowing paragraphs briefly explain each processor
state.
Table 1-1. BAIBS Signal Encoding
M
U
0
0
1
1
0
1
0
1
Pl'OC8IIOr State
Normal (Running)
Interrupt or Reset Acknowledge
Sync Acknowledge
Haiti Bus Grant Acknowledged
1 _1 1 .8.1 Normal. The processor is run n i ng and executing i nstructions.
1 .1 1 .8.2 Interrupt or Reset Acknowledge. This processor state is i nd icated d u ring both
cycles of a hardware vector fetch which occurs when any of the fol l ow i n g i nterrupts have
occurred: RESET, N MI, FIRQ, IRQ, SWI, SWI2, and SWI3.
This output, p l us decod ing of address li nes A3 through A1 provides the user with an
i ndication of which interrupt is bei ng serviced.
1 .11.8.3 Sync Acknowledge. The processor is waiting for an external synchron ization in­
put on an i nterrupt l i ne. See SYN C inst ruction i n Appendix A.
1 .11.8.4 Halt/Bus Grant. The processor is halted or bus control has been g ranted to some
other device.
1-8
1.11 .9 RESET (RESET). This input is used to reset the processor. A low input lasting
longer than one bus cycle will reset the processor.
The reset vector is fetched from locations $FFFE and $FFFF when the processor enters
the reset acknolwedge state as indicated by the BA output being low and the BS output
being high.
During initial power-on, the reset input should be held low until the clock oscillator is ful­
ly operational.
1.1 1 .1 0 INTERRUPT�The processor has three separate interrupt input�s: non­
maskable interrupt (NMI), fast interrupt request (FIRQ), and interrupt request (IRQ). These
interrupt inputs are latched by the falling edge of every Q clock except during cycle steal­
ing operations where only the NMI input is latched. Using this pOint as a reference, a
delay of at least one bus cycle will occur before the interrupt is recognized by the pro­
cessor.
1.1 1 .1 0.1 Non-Maskable Interrupt (NMI). A negative edge on this input requests that a
non-maskable interrupt sequence be generated. This input, as the name indicates, can­
not be masked by software and has the highest priority of the three interrupt inputs. After
a reset has occurred, a NMI input will not be recognized by the processor until the first
program load of the hardware stack pointer. The entire machine state is saved on the
hardware stack during the processing of a non-maskable interrupt. This interrupt is inter­
nally blocked after a hardware reset until the stack pOinter is initialized.
1 .1 1 .1 0.2 Fast Interrupt Request (FIRQ). This input is used to initiate a fast interrupt re­
quest sequence. Initiation depends on the F (fast interrupt request mask) bit in the condi­
tion code register being clear. This bit is set during reset. During the interrupt, only the
contents of the condition code register and the program counter are stacked resulting in
a short amount of time required to service this Interrupt. This interrupt has a higher priori­
ty than the normal interrupt request (IRQ).
1.1 1 .1 0.3 Interrupt Request (IRQ). This input is used to initiate what might be considered
the "normal" interrupt request sequence. Initiation depends on the I (interrupt mask) bit
in the condition code register being clear. This bit is set during reset. The entire machine
state is saved on the hardware stack during processing of an IRQ input. This input has
the lowest priority of the three hardware interrupts.
1 .1 1 .11 MEMORY READ (MRDy) (MC6809). This input allows extension of the E and Q
clocks to allow a longer data access time. A low on this input allows extension of the E
and Q clocks (E high and Q low) in integral multiples of quarter bus cycles (up to 1 0
cycles) to allow interface with slow memory devices.
1-9
M emory ready does not extend the E and Q clocks d u ring non-va l id memory access
cycles and therefore the processor does not slow down for "don't care" bus accesses.
M emory ready may also be used to extend the E and Q clocks when an external device is
using the halt and d i rect memory access/bus request i n p uts.
1.11 .1 2 ADVANCED VALID MEMORY ADDRESS(AVMA)(MC8809E). This output signal in­
d icates that the MC6809E wi l l use the bus In the fol lowing bus cycle. This output is low
when the MC6809E Is in either a halt or sync state.
1.11 .1 3 HALT. This i n put is used to halt the processor. A low i n put halts the processor at
the end of the present instruction execution cycle and the processor remains halted in­
defin itely without loss of data.
When the processor is halted, the BA output is high to indicate that the buses are in the
h i g h-im pedance state and the BS output is also high to indicate that the processor is i n
t h e halt/bus g rant state.
During the halt/bus grant state, the processor will not respond to external real-time re­
q uests such as FIRQ or IRQ. However, a d irect memory accesslbus request input wi l l be
accepted . A non-maskable Interrupt or a reset i n put wi l l be l atched for processing l ater.
The E and Q clocks conti n ue to run during the halt/bus grant state.
1.11.14 DIRECT MEMORY ACCESS/BUS REQUEST (DMAIBREQ) (MC8809). This input is
used to suspend program execution and make the buses available for another use such
as a direct memory access or a dynamic memory refresh.
A low level on this i nput occurring d uring the Q clock high time suspends instruct ion ex­
ecution at the end of the current cycle. The processor ac �nowledges acceptance of this
i n put by setti ng the BA and BS outputs high to sign ify the bus grant state. The requesting
device now has up to 15 bus cycles before the processor retrieves the bus for self-refresh.
!n!!...c � di rect memory access controller w i l l req uest to use the bus by setting the
DMAIBREQ I nput low when E goes high. When the processor acknowledges this i n p ut by
setti ng the BA and BS outputs high, that cycle will be a dead cycle used to transfer bus
mastership to the direct memory access controller. False memory access d u ri ng any
dead cycle should be prevented by externally developing a system DMAVMA signa·1
which Is low in any cycle when the BA output changes.
When the BA output goes low, either as a result of a d irect memory access/bus request or
a processor self-refresh, the d irect memory access device should be removed from the
bus. Another dead cycle w i l l elapse before the processor accesses memory, to al low
transfer of bus mastership without contention.
1.1 1 .1 5 BUSY (MC8809E). This output ind icates that bus re-arbitration should be deferred
and provides the i ndlvisable memory operation required for a "test-and-set" pri m itive.
1-10
This output wi l l be high for the fi rst two cycles of any Read-Modify-Wrlte i n struction, h i g h
d u ring t h e fi rst byte o f a double-byte access, a n d h i g h d u r i n g t h e fi rst byte of any indirect
access or vector-fetch o peration.
1 .1 1 .16 POWER. Two i n puts are used to su pply power to the p rocessor: Vee i s
±
5%, wh i le VSS is g round or 0 volts.
1-1111-12
+ 5.0
SECTION 2
ADDRESSIN G MODES
2.1 INTRODUCTION
This section contains a description of each of the addressing modes available on these
processors.
2.2 ADDRESSING MODES
The addressing modes available on the MC6809 and MC6809E are: Inherent, Immediate,
Extended, Direct, Indexed (with various offsets and autoincrementing/decrementing),
and Branch Relative. Some of these addressing modes require an additional byte after
the opcode to provide additional addressing interpretation. This byte is called a postbyte.
The following paragraphs provide a description of each addressing mode. In these
descriptions the term effective address is used to indicate the address in memory from
which the argument for an instruction is fetched or stored, or fram which instruction pro·
cessing is to proceed.
2.2.1 INHERENT. The information necessary to execute the instruction is contained in
the opcode. Some operations specifying only the index registers or the accumulators,
and no other arguments, are also included in this addressing mode.
Example:
MUL
2.2.2 IMMEDIATE. The operand is contained in one or two bytes immediately following
the opcode. This addressing mode is used to provide constant data values that do not
change during program execution. Both 8- bit and 16-bit operands are used depending on
the size of the argument specified in the opcode.
Example:
LOA #CR
LOB #7
LOA #$FO
LOB #%1110000
LOX #$8004
Another form of immediate addressing uses a postbyte to determine the registers to be
manipulated. The exchange (EXG) and transfer (TFR) instructions use the postbyte as
shown in Figure 2-1(A). The push and pull instructions use the postbyte to designate the
registers to be pushed or pulled as shown in Figure 2-1(8).
2-1
•
b6
b7
I
b4
b5
b3
SOURCE ( R l 1
b2
bl
DESTINAT I O N ( R21
Code-
Register
Code-
Register
0000
000 1
00 1 0
001 1
0 1 00
D (A:BI
X Index
0101
1 000
1001
1010
101 1
Program Counter
Y Index
U Stack Pointer
S Stack Pointer
bO
I
A Accumulator
B Accumulator
Condition Code
Direct Page
All other combinations of bits produce undefined results.
(A) Exchange ( EXG) or Transfer (TFR) Instruction Postbyte
b7
b6
b5
b4
b3
I PC l s/ u I y I X I DP I
b2
B
I
bl
A
bO
I cc I
PC
=
Program Counter
StU
=
Hardware/ User Stack Pointer
=
Y Index Register
y
X
=
DP
=
U Index Register
Direct Page Register
B
=
B Accumulator
A
=
A Accumulator
CC
=
Condition Code Register
(B) Push (PSH) or Pull ( PUll Instruction Postbyte
Figure 2·1. Post byte Usage for EXGrrFR, PSH/PU L Instructions
2.2.3 EXTENDED. The effective address of the argument is contained in the two bytes
fol lowing the opcode. I n structions using the extended addressing mode can reference
arg uments anywhere in the 64K add ressi ng space. Extended addressi ng is generally not
u sed i n position i ndependent programs because it suppl ies an absol ute add ress.
Example:
LOA > CAT
2.2.4 DIRECT. The effective address is developed by concaten ation of the contents of the
d i rect page reg ister with the byte immediately fol lowi n g the opcode. The d i rect page
reg ister contents are the most·significant byte of the address. This allows accessi n g 256
l ocations withi n any one of 256 pages. Therefore, the enti re add ressing range i s avai l able
for access using a single two·byte instruct ion.
Example:
LOA > CAT
2.2.S INDEXED. I n these addressing modes, one of the pOi nter reg i sters (X, V, U, or S), and
someti mes the program counter (PC) is u sed in the calculation of the effective add ress of
the i n struct ion operand. The basic types (and their variations) of i ndexed add ressing
avai lable are shown i n Table 2-1 along with the post byte conf i g u ration used .
2.2.S.1 Constant Offset from Register. The contents of the reg i ster deSignated i n the
post byte are added to a twos com plement offset val ue to form the effective add ress of
2-2
the instruction operand. The contents of the designated register are not affected by this
addition. The offset sizes available are:
No
offset
designated register contains the effective
address
5-bit
16 to + 15
8·bit
128 to + 127
16-bit
32768 to
+
32767
Table 2·1. Postbyte Usage for Indexed Addressing Modes
Variation
Mode Type
Constant Offset from Register
(twos Complement Offset)
Accumulator Offset from Register
(twos Complement Offset)
Auto I ncrement/ Decrement from
Register
Constant Offset from Program
Counter
Extended I ndi rect
Direct
Indirect
No Offset
l R R00 1 00
1 R R 1 0l 00
5-B it Offset
ORRnnnnn
Defaults to 8-bit
8- Bit Offset
l RR01000
l R R l l 000
1 6-Bit Offset
l R R0100l
1 R R l l 00 l
A Accumulator Offset
l R ROOl l 0
l R R 10l l 0
B Accumulator Offset
l R R0010l
1 R R 1 0l 0l
l R R l l0l l
D Accumulator Offset
1 R R010l l
I ncrement by 1
l R ROOOOO
Not Allowed
I ncrement by 2
l R ROOOO l
l R R 1 000 l
Decrement by 1
l R ROOO 1 0
N o t Allowed
Decrement by 2
1 R ROOO l l
l R R 1 00l l
8- Bit Offset
l XXOl l 00
1 XX 1 1 1 00
1 6-Bit Offset
l XXOl l 0 l
l XX l l l 0l
1 6- Bit Address
-
--.........-
1 001 1 1 1 1
The 5·bit offset value is contained in the postbyte. The 8· and 16·bit offset values are con·
tained in the byte or bytes immediately following the postbyte. If the Motorola assembler
is used, it will automatically determine the most efficient offset; thus, the programmer
need not be concerned about the offset size.
Examples:
LOY - 64000, U
LOA ,X
LOB O,Y
LOA 17, PC
LOX 64,000,5 LOA There, PCR
2.2.5.2 Accumulator Offset from Register. The contents of the index or pOinter register
designed in the postbyte are temporarily added to the twos complement offset value con·
tained in an accumulator (A, B, or D) also designated in the postbyte. N either the
designated register nor the accumulator contents are affected by this addition.
Example:
L OA A,X
LOA B,Y
LOA O,U
2.2.5.3 Autoincrement/Decrement from Register. This addressing mode works in a
postincrementing or predecrementing manner. The amount of increment or decrement,
one or two positions, is designated in the postbyte.
2-3
I n the autoincrement mode, the contents of the effective address contai ned i n the
pOi nter reg ister, designated in the postbyte, and then the pOinter regi ster is automatical­
ly incremented ; thus, the pOi nter reg ister is post incremented.
In the autodecrement mode, the poi nter reg ister, designated in the postbyte, is
automatical ly decremented fi rst and then the contents of the new address are used;
thus, the poi nter reg i ster is predecremented.
Exam ples:
Autolncrement
LOA
LOA
LOA
LOA
,X +
,Y +
,5 +
,U +
LOY
LOX
LOX
LOX
,X +
,Y +
,U +
,5 +
Autodecrement
+
+
+
+
LOA
LOA
LOA
LOA
,-X
,-V
,-5
,-U
LOY
LOX
LOX
LOX
,,,,-
-X
-Y
-U
-5
2.2.5.4 Indirection. When using indirect ion, the effect ive address of the base i ndexed ad­
dressing mode is used to fetch two bytes which contai n the final effective address of the
operand. It can be used with al l the i ndexed addressing modes and the program cou nter
rel ative addressing mode.
2.2.5.5 Extended Indirect. The effective address of the arg ument is located at the ad­
dress specified by the two bytes fol low i n g the post byte. The postbyte is used to indicate
i n d i rection .
Example:
LOA [$FOOO]
2.2.5.8 Program Counter Relative. The p rogram counter can also be used as a pOi nter
with either an 8- or 1 6-bit signed constant offset. The offset val ue is added to the program
cou nter to develop an effective address. Part of the post byte is used to indicate whether
the offset is 8 or 16 bits.
2.2.8 BRANCH RELATIVE. This addressing mode is used when branches from the c u rrent
i n struction location to some other locat ion relative to the current program counter are
des i red. If the test condition of the branch instruction is true, then the effective address
is calculated (program counter plus twos complement offset) and the branch is taken. If
the test condition i s false, the processor proceeds to the next in-l i ne instruction. Note
that the prog ram counter is always poi nting to the next instruction when the offset is ad­
ded . Branch relative addressing is always used i n position independent programs for all
contro l transfers.
For short branches, the byte fol lowi n g the branch instruction opcode is treated as an
8-bit signed offset to be used to cal c u l ate the effective add ress of the next i n struction if
the branch i s taken . Th is is cal led a short relative branch and the range is l i m i ted to p l us
1 27 or m i n u s 1 28 bytes from the fol low i n g opcode.
For long branches, the two bytes after the opcode are used to calculate the effective ad­
d ress. Th i s is cal led a long relative branch and the range is p l u s 32,767 or m i n us 32,768
2-4
bytes from the fol lowing opcode or the f u l l 64K address space of memory that the pro­
cessor can add ress at one t i me.
Examples:
Short Branch
Long Branch
BRA PO LE
LBRA CAT
2-5/2-6
SECTION 3
I NTERRUPT CAPABI LITI ES
3.1
INTRODUCTION
The M C6809 and MC6809E microprocessors have six vectored i nterrupts (th ree hardware
and three software). The hardware interrupts are the non-maskable interrupt (N M I), the
fast maskable interru pt req uest (FI RQ), and the normal maskable interru pt req uest (I RQ).
The software I nterrupts consist of SWI , SWI2, and SWI3. When an i nterrupt request is
acknowledged, all the processor registers are pushed onto the hardware stack, except i n
t h e case o f F I RQ where o n l y t h e program counter and t h e condition code register is sav­
ed , and control is transferred to tl!!.! d dress1!!.1he interrupt vector. The p ri o rity of these
i nterrupts is, h i ghest to lowest, N M I , SWI , FI RQ, I RQ, SWI2, and SWI3. Figure 3-1 is a
detai l ed flowchart of i nterru pt processi n g i n these processors. The i nterrupt vector loca­
tions are g iven in Table 3-1 . The vector locations contai n the address for the i nterru pt
routi ne.
Add itional information on the SWI , SWI2, and SWI3 interrupts is g iven in Appendix A. The
hardware i nterrupts, N M I , FI RQ, and I RQ are l i sted al phabetical ly at the end of Appendix
A.
Table 3·1. Interrupt Vector Locations
Vector Location
LS Byte
MS Byte
Interru pt
Description
(RESET)
FFFE
FFFF
FFFC
FFFD
FFFA
FFFB
FFF8
FFF9
FFF6
FFF7
Software I nterrupt 2 ( SWI2)
FFF4
F F F5
Software Interrupt 3 ( SW I3)
FFF2
FFF3
Reserved
FFFO
FFFl
Reset
Non-Maskable I nterrupt
Software Interrupt
(NMi)
�I l
Interrupt Request ( I RQ)
Fast I nterrupt Request
3.2
iFiRQ)
NON-MASKABLE INTERRUPT (NMI)
The non-maskable i nterrupt is edge-sensitive i n the sense that if it is sam p led low one cy­
cle after it has been sampled high, a non-maskable interrupt wi l l be triggered. Because
the non-maskable i nterrupt cannot be masked by execution of the non-maskable i nter­
rupt handler routine, it is possible to accept another non-maskable interru pt before ex­
ecut i ng the first instruct ion of the interru pt routine. A fatal error w i l l exist if a non­
maskable i nterrupt is repeatedly al lowed to occur before completing the retu rn from i n­
terru pt (RTI) instruction of the previous non-maskable interru pt req uest, si nce the stack
3-1
w i l l eventual ly overflow. Th is i nterrupt is especial ly appl icable to gai n i n g i m med iate p ro­
cessor response for powerfa i l , software dynamic memory refresh , or other non-delayable
events.
3.3 FAST MASKABLE INTERRUPT REQUEST (FIRQ)
A low level on the F I RQ i nput with the F (fast i nterrupt req uest mask) bit i n the condit ion
code reg i ster clear triggers this i nterru pt seq uence. The fast i nterru pt req uest provides
fast i nterru pt response by stacking only the prog ram counter and condit ion code
reg i ster. Th i s al lows fast context switching with m i n imal overhead . If any reg i sters are
u sed by the i nterrupt routine then they can be saved by a single push i nstruct ion.
After accepti n g a fast interru pt req uest, the processor clears the E flag, saves the pro­
g ram c2!:!IDer and cond ition code reg ister, and then sets both the I and F bits to mask any
f u rther I RQ and F I RQ i nterrupts. After servicing the ori g i nal interru pt, the user may selec­
t ively clear the I and F bits to al low multi ple-level i nterrupts if so desired .
3.4 NORMAL MASKABLE INTERRUPT REQU EST (IRQ)
A low level on the I RQ input with the I (i nterru pt req uest mask) bit i n the cond ition code
reg i ster clear triggers this i nterru pt seq uence. The normal m askabl e i nterru pt req uest
p rovides a slower hardware response to i nterru pts because it causes the ent i re m ach i ne
state to be stacked . However, this means that i nterrupting software routi nes can use all
p rocessor resou rces without fear of damag ing the i nterrupted routine. A normal i nterru pt
request, havi n g lower priority than the fast i nterrupt request, i s prevented from i nterru p­
t i n g the fast i nterru pt hand ler by the automatic sett i ng of the I bit by the fast i nterrupt re­
q uest handler.
After accepti n g a normal i nterrupt req uest, the p rocessor sets the E flag, saves the ent i re
m achine state, and then sets the I bit to mask any further interrupt req uest i n puts. After
servicing the ori g i nal i nterrupt, the user may clear the I bit to al low m u lt i ple-level normal
i nterrupts.
All interrupt hand l i ng routi nes shou ld retu rn to the formerly executing tasks u s i n g a
ret u rn from i nterrupt (RiT) instruction. Th is i n st ruction recovers the saved mach ine state
f rom the hardware stack and control is retu rned to the i nterru pted program . If t he
recovered E bit is clear, it indicates that a fast i nterrupt req uest occurred and only the
program cou nter address and condition code reg ister are to be recovered.
3.5 SOFTWARE INTERRU PTS (SWI, SWI2, SWI3)
The software i nterru pts cause the processor to go through the normal i nterru pt request
sequence of stacking the complete mac h i ne state even though the i nterru pt i n g sou rce i s
the processor itself. These i nterru pts are com monly used for prog ram debugg i n g a n d for
cal l s to an operating system.
3-2
Normal p rocessing of the SWI i n put sets the I and F bits to p revent either of these i nter­
ru pt req uests from affecting the com pletion of a software i nterrupt req uest. The remain­
ing software interru pt request inp uts (SWI2 and SWI3) do not have the priority of the SWI
i n put and therefore do not mask the two hardware i nterru pt req uest i n puts (FI RQ and
I RQ).
3-3
--,
r- - - - - - ~C6!!
~
O-DPR
I-F,I
l-R/W
Clrimi
LogiC
DlsarmNm
----r---
L
~
___________ _
CWAI
Bus SIal8
Run",n
Interrupt or Reset Acknowledge
ync Acknowledge
Halt Acknowledge
BA I BS
o
o
NOTES: 1. Asserting RESET will result in entering the reset sequence from any point in Ihe flowchart.
2. BUSY is high during first vector fetch cycle (MC6809EI.
Figure 3·1. Interrupt Processing Flowchart
I 0
I 1
o
SECTION 4
P ROG RAM MING
4.1 I NTRODUCTION
These processors are designed to be sou rce-code com patible with the M 6800 to m ake
use of the su bstantial existi n g base of M6BOO software and traini n g . However, this asset
sho u l d not overshadow the capab i l ities bu i lt i nto these processors that allow more
modern prog ram m i ng tec h n i q ues such as position-i ndependence, mod u lar programm­
i n g , and reentrancy/recu rsion to be u sed on a m icroprocessor-based system. A brief
review of these methods is given in the fol l owing paragraphs.
4.1 .1 POSITION I N DEPENDENCE. A program is said to be "posit ion-independent" i f it
wil l run correct ly when the same machine code is positioned arbitrarily in memory. Such
a prog ram is u sef u l i n many d i fferent hardware configurations, and m ight be copied from
a d isk i nto RAM when the operat i ng system first sees a req uest to use a system util ity.
Pos it ion-i ndependent prog rams n ever use absol ute (extended or direct) add ressing: in­
stead, i nherent i m med iate, register, i ndexed and rel ative modes are used . In particu l ar,
there should be no jump (absol ute) or j u m p to subroutine i nstruct ions nor sho u l d ab­
sol ute addresses be used. A position-i ndependent prog ram is al most always preferable
to a position-d ependent program (although position-i ndependent code i s usually 5 to
1 0% slower than normal code).
4.1 .2 MO DULAR P ROG RAMM I N G . M od u lar prog ramm i ng is another indication of q ual ity
code. A mod u l e is a prog ram element which can be easily discon nected from the rest of
the prog ram either for re-use in a new environment or for replacement. A module is usual­
ly a su broutine (although a subroutine i s not necessari ly a mod u le); freq uently, the p ro­
g rammer isol ates reg ister changes i nternal to the module by pushing these reg isters
onto the stack u pon entry, and p u l l i ng them off the stack before the return. I so l at i n g
register changes i n t h e cal led mod u l e , to that mod u l e alone, allows t h e code i n the cal l­
i n g program to be more eas i ly analyzed since it can be assumed that al l registers (except
those spec ifical l y used for parameter transfer are u nchanged by each cal led mod u le.
Th i s l eaves the processor's registers free at each level for loop counts, add ress com­
parisons, etc.
4.1 .2.1 Local Storage. A clean m ethod for al locat i n g "local " storage is req u i red both by
position-i ndependent prog rams as wel l as mod u l ar prog rams. Local or temporary storage
is used to hold va l ues on ly d u ri n g execution of a mod ule (or cal l ed modu les) and is releas­
ed u pon ret u rn . One way to al locate local storage is to decrement the hardware stack
4-1
pOinter(s) by the nu mber of bytes needed. I n terru pts w i ll then leave th i s area intact and i t
c a n b e de-allocated o n exit ing the module. A mod u l e wi ll almost always need more tem­
porary storage than just the M PU regi sters.
4.1.2.2 Global Storage. Even in a modu lar envi ron ment there may be a n eed for "global"
val ues which are accessi ble by many modu l es wit h i n a gi ven system. These provide a
conven ient means for storing val u es from one i nvocat ion to another i nvocat ion of the
same routi n e. Global storage may be created as local storage at some level, and a
pOinter reg ister (usually U) used to pOi nt at this area. Th is register is passed u nchanged
i n al l subrouti n es, and may be used to i ndex i nto the global area.
4.1.3 REENTRANCY/RECURSION. Many programs w i l l eventually i n volve execution in an
i nterrupt-driven envi ronment. If the i nterrupt handlers are com plex, they m ight wel l cal l
the same routine wh ich has just been interrupted. Therefore, to protect present programs
against certai n obsolescence, al l programs should be written to be reentrant. A reentrant
routine allocates d ifferent local variable storage u pon each entry. Th us, a later entry
does not destroy the processing associated wit h an earl ier entry.
The same tec h n i que wh ich was implemented to allow reentrancy also allows recursion .
A recursive routine i s defined as a routine that cal l s itself. A recu rsive routine might be
written to simplify the solution of certai n types of problems, especially those wh ich have
a data structure whose elements may themselves be a structure. For exam ple, a paren­
thet ical equat ion represents a case where the expression i n parenthesis may be con­
sidered to be a val ue wh ich is operated on by the rest of the equation. A programmer
m ight choose to write an expression evaluator passing the parenthetical expression
(which m i g ht also contain parenthetical expressions) i n the call, and receive back the
retu rned value of th e expression wit h i n th e parenthesis.
4.2 M8809 CAPABILITIES
The followi ng paragraphs briefly explain how the MC6809 is used with the programmi ng
tech n i ques mentioned earl ier.
4.2.1 MODULE CONSTRUCTION. A module can be defined as a log ically self-contained
and discrete part of a larger program. A properly constructed mod u l e accepts well defi n ­
e d inputs, carries o u t a set o f processing actions, a n d produces a specified output. The
u se of parameters, local storage, and g lobal storage by a program mod u l e is g iven i n the
followi ng paragraphs. Si nce reg isters wi ll be used i nside the mod u l e (essentially a form
of local storage), the f i rst thing that is usually done at entry to a mod ule is to push (save)
them on to the stack. This can be done with one i n struction (e.g., PSHS Y, X, B, A). After
the body of the mod ule is executed, the saved registers are collected, and a subro ut i n e
retu rn i s performed, at o n e time, by p u l l i ng the program counter from t h e stack (e.g.,
PULS A,B,X,Y,PC).
4-2
4.2.1.1 Parameters. Parameters may be passed to or from modu l es eith er i n reg i sters, if
they will provi de sufficient storage for parameter passage, or on the stack. If parameters
are passed on the stack, they are placed there before call ing the lower level modu l e. The
called modu l e is then written to use local storage i n s i de the -stack as n eeded (e.g., ADDA
offset,S). Notice that the requ i red offset consists of the n u mber of bytes pushed (upon
entry), plus two from the stacked return address, plus the data offset at the t i me of the
call. Th is value may be calculated, by hand, by drawing a "stack pictu re" d i ag ram
representi n g module entry, and assi g n i n g conven i ent mnemonics to these offsets with
the assembler. Returned parameters replace those sent to the routi ne. If more
parameters are to be returned on the stack than would normal ly be sent, space for the i r
return is allocated by t h e call ing rout i n e before t h e act ual call (i f four additional bytes are
to be returned, the caller wou l d execute LEAS -4,S to acqu i re the additional storage).
4.2.1.2 Local Storage. Local storage space is acqu i red from the stack wh i le the present
rout i n e is executing and then returned to the stack prior to exit. The act of push i ng
reg isters which w i l l be used in later calcu l ations essentially saves those regi sters i n tem­
porary local storage. Add itional local storage can easi ly be acqu i red from the stack e.g.,
executing LEAS -2048,S acqu i res a buffer area ru n n i ng from the O,S to 2047,S i nclusive.
Any byte in this area may be accessed d i rectly by any instruction which h as an i ndexed
addresing mode. At the en d of the routi ne, the area acqu ired for local storage is released
(e.g., LEAS 2048,S) prior to the fi nal pull . For c l eaner prog rams, local storage should be
allocated at entry to the module and released at the exit of the module.
4.2.1.3 Global Storage. The area requ i red for global storage is also most effecti vely ac­
qu i red from the stack, probably by the h ighest level routi ne in the standard package.
Although this is local storage to the highest level routine, it becomes "global" by posi­
tion i ng a reg ister to poi nt at this storage, (someti mes referred to as a stack mark) then
establishing the convention that all modu les pass that same pOi nter val u e when cal l i ng
lower level modu les. I n practice, it i s conve n ient to leave this stack mark reg i ster u n ­
changed i n all modules, especially if g lobal accesses are common. The highest level
routi n e in the standard package would execute the fol lowing sequence u pon ent ry (to i n ­
itialize t h e g lobal area):
PSHS
U
h i gh er level mark, i f any
TFR
S,U
n ew stack mark
LEAS
-1 7,U
a l locate global storage
Note that the U register now defines 1 7-bytes of locally allocated (permanent) g lobals
(which are -1 ,U through -17,U) as well as oth er external globals (2,U and above) which
have been passed on the stack by the routi n e which called the standard package. Any
global may be accessed by any modu l e usi n g exact l y the same offset value at any l evel
(e.g., ROL, RAT,U; where RAT EaU -1 1 h as been defi ned). Furthermore, the values stack­
ed prior to i n voki ng the standard package may i nclu de pOi nters to data or I /O peri pherals.
Any i n dexed operat ion may be performed i n dexed i n di rect through those pOi nters, which
means, for example, that the module n eed know noth i n g about the actual hardw are con­
f i gu rat ion, except that (upon ent ry) the pOi nter to an I/O register has been placed at a
gi ven location on the stack.
4-3
4.2.2 POSITION·INDEPENDENT CODE. Position-independent code means that the same
machine lang uage code can be placed anywhere in memory and sti l l function correctly.
The M6809 has a long relative (16-bit offset) branch mode along with the com mon
MC6800 branches, p l u s program-counter rel at ive addressi ng. Program-counter rel ative
addressing u ses the program counter l i ke an i ndexable reg ister, which allows all instruc­
tions that reference memory to also reference data rel ative to the program counter. The
M6809 also h as load effect ive add ress (LEA) i n st ructions which al low the user to pOi nt to
data in a ROM in a position-independent man ner.
An i mportant rule for generat i n g position-independent code is: NEVER USE ABSOLUTE
ADDRESSI NG.
Program-cou nter relative addressing on the M6809 is a form of i ndexed addressing that
uses the prog ram cou nter as the base reg ister for a constant-offset i ndexi ng operation.
However, the M6809 assembler treats the PCR address field differently from that used in
other i ndexed instructions. I n PCR addressing, the assembly t i me location val ue i s sub­
tracted from the (con stant) value of the PCR offset. The resulting distance to the desi red
symbol is the val ue placed i nto the machine language object code. During execution, the
processor adds the value of the run time PC to the d i stance to get a posit ion-independent
absol ute add ress.
The PCR indexed add ressing form can be used to poi nt at any locat ion relati ve to the pro­
g ram regard l ess of position in memory. The peR form of i ndexed addressing al lows ac­
cess to tables with i n the program .s pace in a position-independent manner via use of the
load effective address instruction.
I n a program which is completely position-i nd$pendent, some absol ute locations are
usual ly requi red, particularly for I /O. If the locations of I /O devices are placed on the
stack (as g lobals) by a small set u p rout ine before the standard package Is invoked, all in­
ternal mod ules can do their I /O through that pOi nter (e.g., STA [ACIAD, UD, al lowing the
hardware to be eas i ly changed, i f desi red . Only the Single, smal l , and obvious set u p
rout ine need b e rewritten for each different hardware confi g u rat ion.
Global, permanent, and temporary values need to be eas i ly available in a position­
i ndependent manner. Use the stack for this data s i nce the stacked data is d i rectly ac­
cessible. Stack the absol ute address of I /O devices before cal l ing any standard software
package s i nce the package can use the stacked addresses for I /O in any system.
The LEA instructions al low access to tables, data, or i mmediate val ues i n the text of the
program in a position-i ndependent manner as shown i n the fol lowing example:
MSG1
LEAX
LBSR
MSG1 , PCR
PDATA
FCC
IPRI NT THIS !I
4-4
Here we wish to pOint at a message to be pri nted from the body of the program. By
writing "MSG1 , peR" we s i gnal the assembler to compute the distance between the pre­
sent address (the address of the LBSR) and MSG1 . Th is resu lt is inserted as a constant
i nto the LEA instruction which wi l l be indexed from the program counter value at the t i me
of execution. Now, no matter where the code i s located, when i t is executed the com­
p uter offset from the program cou nter wi ll poi nt at MSG1 . Th is code is position­
i n dependent.
It is common to use space in the hardware stack for temporary storage. Space is made
for temporary variables from O,S through TEMP-1 , S by decrement i n g the stack pOi nter
equal to the len gth of requ i red storage. We could u se:
LEAS
-TEMP,S.
Not only does this facil itate position-i ndependent code but i t is structured and helps
reentrancy and recursion.
A program that can be executed by several d ifferent
users shari n g the same copy of it in memory is called reentrant. Th is is i mportant for i n ­
terrupt driven systems. This method saves considerable memory space, especi a l ly with
l arge i nterrupt routi nes. Stacks are requ i red for reentrant programs, and the M6809 can
su pport up to four stacks by usi n g the X and Y i ndex registers as stack poi nters.
4.2.3 REENTRANT PROGRAMS.
Stacks are simple and convenient mechanisms for generati n g reentrant programs.
Subrouti nes wh ich use stacks for pass i n g parameters and results can be easily made to
be reentrant. Stack accesses use the i ndexed addressing mode for fast, efficient execu ­
tion. Stack addressi n g is qu ick.
Pure code, or code that is not self-modifying, is mandatory to produce reentrant code. No
i nternal i nformation within the code Is subject to modification . Reentrant code never has
i nternal tem porary storage, is sim pler to debug, can be placed i n ROM, and must be i nter­
ruptable.
4.2.4 RECURSIVE PROGRAMS. A recu rsive program is one that can call itself. They are
quite conven ient for parsing mechanisms and certain arithmetic functions such as com­
puting factorials. As with reentrant programmi ng, stacks are very usef u l for this techni­
que.
4.2.5 LOOPS. The usual structured loops (i.e., REPEAT ... UNTIL, WHI LE ... DO, FOR ... , etc.)
are avai lable In assembly language i n exactly the same way a h i gh-level language com­
piler cou ld translate the construct for execution on the target machine. Using a
FOR...NEXT loop as an example, it is possi ble to p ush the loop count, i ncrement value,
and termi nation val ue on the stack as variables local to that loop. On each pass through
the loop, the worki ng register is saved, the loop count picked up, the increment added i n ,
a n d t h e resu lt compared to t h e termi nation value. Based o n t h i s comparison, t h e loop
counter might be u pdated, the worki n g register recovered and the loop resumed, or the
workin g register recovered and the loo p variables de-allocated. Reasonable macros
4-5
cou ld m ake the sou rce form for loop trivial , even i n assembly l an guage. Such m acros
might red uce errors resu lt i n g from the u se of m u lt i ple i n structions sim ply to i m pl ement a
standard control structure.
4.2.6 STACK PROGRAMMING. Many microprocessor applications requ i re data stored as
cont i n g uous pieces of i nformation i n memory. The data may be temporary, that is, sub­
ject to change or it may be permanent. Tem porary data w i l l most li kely be stored in RAM.
Permanent data w i ll most l i kely be stored i n ROM.
It i s i m portant to al low the main program as well as su brouti nes access to this block of
data, especially if arg uments are to be passed from the mai n program to the subrouti nes
and vice versa.
4.2.6.1 M6809 Stacking Operations. Stack pOi nters are markers which poi nt to the stack
and its i nternal contents. Although a l l fou r i ndex reg i sters may be used as stack
regi sters, the S (hardware stack pointer) and the U (user stack pOi nter) are generally
preferred because the push and pull instructions apply to these regi sters. Both are 16-bit
i ndexable registers. The processor uses the S reg i ster automatically d u ring i nterrupts
and subroutine cal ls. The U register is free for any purpose needed. It i s not affected by
i nterrupts or subroutine cal ls i mplemented by the hardware.
Either stack poi nter can be specified as the base address in i ndexed addreSSi ng. One u se
of the i n d i rect addressing mode uses stack poi nters to al low addresses of d ata to be
passed to a subrouti n e on a stack as argu ments to a subrouti n e. The subroutine can now
reference the data with one instruction. Hi gh-level language cal l s that pass argu ments
by reference are now more efficiently coded. Also, each stack push or pull operation in a
program u ses a post byte wh ich specifies any register or set of regi sters to be pushed or
p u lled from either stack. With this option, the overhead associated with subroutine call s
i n both assembl y a n d high-level language program s i s greatly decreased. I n fact, with the
large n u m ber of i n st ructions that use autoincrement and autodecrement, the M6809 can
em u l ate a true stack computer architectu re.
Using the S or U stack poi nter, the order i n which the reg isters are pushed or pu l led i s
shown i n Figure 4-1. Not ice that w e push "onto" the stack towards decreas i n g memory
locations. The program cou nter is pushed fi rst. Then the stack poi nter is decremented
and the "other" stack pOi nter is pushed onto the stack. Decrement i ng and stori ng con­
t i n ues u nt i l all the reg isters requested by the postbyte are pushed onto the stack. The
stack pOi nter pOi nts to the top of the stack after the push ope ration.
The stacki n g order i s specified by the processor. The stacki ng order is identical to the
order used for all hardware and software i nterrupts. The same order is used even if a
subset of the reg i sters i s p ushed.
Without stacks, most modern block-structured h i gh -level languages would be c um ber­
some to i m plement. Subroutine l i n kage is very i m portant in h i g h-level language genera­
tion. Paragraph 4.2.6.2 describes how to use a stack mark pOi nter for this i m portant task.
4-6
Good prog rammi ng pract ice dictates the use of the hardware stack for temporary
storage. To reserve space, decrement the stack poi nter by the amount of storage re­
qu i red with the i n struction LEAS -TEMPS, S. Th i s instruction makes space for tem­
porary variables from 0,5 through TEMPS -1,5.
Memory
=R
·
Stack Pointer
After Stacking
...
}
}
}
}
CC
A
B
DP
-
X.H
-
X.L
-
.Y .H
-
Y. L
U . H or S .H
-
�
U . L or S . L .
-
PC.H
-
PC. L
Stack Pointer
..
Before Stacking
.
·
·
}
}
}
}
Condition Code Register Contents
A Accumu lator Contents
B
�ccumulator Contents
Direct Page Register Contents
X Contents
Y Contents
Other Stack Pointer Contents
P rogram Counter Contents
.
Figure 4·1 . Stacking Order
4.2.6.2 Subroutine Linkage. In the h ighest level routi ne, global variables are someti mes
considered to be local. Therefore, global storage is al located at this poi nt, but access to
these same variables requ ires different offset val ues dependi ng on s u brouti n e dept h .
Because subroutine depth chan ges dynamically, the length may not b e known
beforehan d . Th is problem is solved by ass i g n i ng one pOi nter (U will be u sed i n the fol low­
ing descri ption, but X or Y could also be used) to "mark" a location on the hardware stack
by using the instruct ion TFR S,U. If the prog rammer does this i mmediately prior to
allocating g lobal storage, then all variables will then be available at a constant n egat i ve
offset location from this stack mark. I f the stack i s marked after the g lo bal variables are
4-7
al located, then the g lobal variables are avai lable at a constant positive offset from U .
Reg ister U is then cal led the stack mark pOi nter. Recall that the hardware stack poi nter
m ay be modi fied by hardware i nterrupts. For this reason, i t i s fatal to use data referred to
by a negative offset with respect to the hardware stack pOi nter, S.
If more than two stacks are needed, autoincrement and
autodecrement mode of addressi n g can be used to gen erate addi ti onal software stack
pOi n ters.
4.2.6.3 Software Stacks.
The X, Y, and U i n dex regi sters are qu i te useful i n loops for i ncrementi ng and decremen­
t i ng pu rposes. Th e pOi nter is used for searching tables and also to move data from one
area of memory to another (block moves). Th is auto i ncrement and autodecremen t
feature i s available i n the i ndexed addressi ng mode of the M6809 to fac i l itate such opera­
t ions.
In autoi ncrem ent, the value contained i n the i ndex reg i st er (X or Y, U or S) is used as the
effective address and then the reg ister i s i nc remen ted (post i ncremen ted). I n autodecre­
ment, the i n dex reg i ster is f i rst decremented and then used to obtai n the effecti ve ad­
d ress (predecremented). Postincremen t or predecrement is always performed in this ad­
d ressing mode. Th i s is equ i valent in operation to the push and p u l l from a stack. Th i s
equ i valence allows the X and Y i n d ex reg i sters to be used a s software stack pOi n ters. The
i ndexed addressi ng mode can a l so i mplement an extra level of post i n di rection. Thi s
feature supports parameter and pOi nter operations.
Real t i me programmi ng requ ires special care.
Someti mes a peri pheral or task demands an i mmediate response from the processor,
other t i mes it can wait. Most real t i me app l i cat ions are demanding in t erms of processor
response.
4.2.7 REAL TIME PROGRAMMING.
A common solution is to use the i n terru pt capab i l i ty of the processor in solvi ng real ti me
p roblems. I nterru pts mean just that; they request a break i n the cu rrent sequence of
events to solve an asynch ronous service request. The system designer must consider all
vari at ions of the conditions to be encountered by the system i n c l u ding software i nterac­
t ion w i th i n terrupts. As a resu lt, probl ems d u e to software design are more common in i n ­
terrupt i mplementation code for real t i me programmi ng than most other situations. Soft­
ware timeou ts, h ardware i nterrupts, and program control i n terru pts are typically used i n
solving real t i m e prog ramming problems.
4.3 PROGRAM DOCUMENTATION
Common sense dictates that a wel l docu mented prog ram is mandatory. Comments are
needed to explai n each g roup of i nstructions si nce thei r use i s not always obvious from
l ooking at the code. Program bou n daries and branch i n structions n eed full clarificatio n .
Consider the fol lowing pOi nts when writi n g comments: u p-to-date, acc uracy, com­
pl eteness, conciseness, and u n derstandab i l ity.
4-8
Accu rate docu mentation enables you and others to maintai n and adapt programs for u p­
dat i n g and/or addi tional use with other programs.
The follow i n g program documentation standards are suggested.
A) Each su broutine should have an associated header block contain i n g at least the
followi n g elements:
1 ) A full specification for th is subroutine - includi n g associated data struc­
tures - such that replacement code cou l d be generated from this descri ption
alone.
2) All usage of memory resou rces must be defi ned, i nclu ding:
a) Al l RAM needed from temorary (local) storage used duri ng exec ution of
this subroutine or called subrouti nes.
b) All RAM needed for permanent storage (used to transfer values from one
execution of the subrout i n e to future executions).
c) All RAM accessed as global storage (used to transfer values from or to
h i gher-level subroutines).
d) All possible exit-state conditions, if these are to be used by calli n g
routines t o test occurrences i nternal to t h e subrouti ne.
B) Code i nternal to each subrout ine shou l d h ave sufficient associated li ne com­
ments to help i n u n derstandi ng the code.
C) All code must be non-self-modifying and position-i n dependent.
D) Eac h su broutine which i nclu des a loop m ust be separately documented by a
flowchart or pseudo h i gh-level language algorithm.
E) Any modu le or su broutine should be executable start i n g at the fi rst locat ion and
exit at the last location.
4.4 I N STRUCTION SET
The complete i n struction set for the M6809 is gi ven in Table 4-1.
Table 4·1 . Instruction Set
Description
Instruction
ABX
Add Accumulator B into Index Register X
ADC
Add with Carry into Register
ADD
Add Memory into R egister
AND
logical A N D Memory into Register
ASl
Arithmetic Shift left
ASR
Arithmetic Shift R ight
BCC
Branch on Carry Clear
BCS
Branch on Carry S et
BEQ
Branch on Equal
BGE
Branch on Greater Than or Equal to Zero
BGT
Branch on Greater
BH I
Branch if H igher
BH S
Branch if H igher or S ame
BIT
Bit Test
BlE
Branch if less than or Equal to Zero
4-9
Table 4·1. Instruction Set (Continued)
Instruction
Description
B LO
Branch on Lower
B LS
Branch on Lower or Same
B LT
Branch on Less than Zero
BMI
Branch on Minus
BNE
Branch N ot Equal
BPL
Branch on Plus
BRA
Branch Always
BRN
Branch Never
BSR
Branch t o Subroutine
BVC
Branch on Overflow Clear
BVS
B ranch on Overflow Set
CLR
Clear
CMP
Compare Memory from a Register
COM
Complement
CWAI
Clear CC bit's and Wait for Interrupt
DAA
Decimal Addition Adjust
D EC
Decrement
EOR
Exclusive OR
EXG
Exchange Registers
INC
I ncrement
J MP
J ump
JSR
J ump to Subroutine
LD
Load Register from Memory
LEA
Load Effective Address
LSL
Logical Shift Left
LS R
Logical S hift Right
MU L
Multiply
N EG
Negate
NOP
No Operation
OR
Inclusive OR Memory into Register
PSH
Push Registers
PUL
Pull Registers
ROL
Rotate Left
ROR
Rotate Right
RTI
Return from Interrupt
RTS
Return from Subroutine
SBC
S ubtract with Borrow
S EX
Sign Extend
ST
Store Register into Memory
SUB
Subtract Memory from Register
SWI
Software I nterrupt
SYNC
Synchronize t o External Event
TFR
Transfer Register to Register
TST
Test
4-10
The instruction set can be functional ly divi ded i n to five categories. They are:
8-Bit Accumulator and Memory Instructions
16-Bit Accumulator and Memory I nstructions
I ndex Reg ister/Stack Pointer I nstructions
Branch Instructions
Miscellaneous I nstructions
Tables 4-2 th rough 4-6 are l isti n gs of the M6809 instructions and th eir variations grouped
i nto the five categories l isted.
Table 4·2. 8·Bit Accum ulator and Memory Instructions
Description
Instruction
ADCA, ADCB
Add memory to accumulator with carry
ADDA, A D D B
Add memory t o accumulator
AN DA, A N D B
And memory with accumulator
ASL, A S LA , A S L B
Arithmetic shift of accumulator or memory left
A S R , A S R A , AS R B
Arithmetic shift o f accumulator o r memory right
BITA, BITB
Bit test memory with accumulator
CLR, CLRA, C L R B
Clear accumulator or memory location
CMPA, CMPB
Compare memory from accumulator
COM, COMA, COMB
Complement accumulator or memory location
DAA
Decimal adjust A accumulator
DEC, D ECA, DECB
Decrement accumulator or memory location
EO R A , EO R B
Exclusive o r memory with accumulator
EXG R l , R 2
Exchange R l with R 2 ( R l , R2", A, B, CC, DP)
I N C, I N CA, INCB
I ncrement accumulator or memory location
LOA, LOB
Load accumulator from memory
LSL, LSLA, LSLB
Logical shltt lett accumulator or memory location
LS R , L S R A , L S R B
Logical shift right accumulator o r memory location
MUL
U nsigned multiply ( Ax B-D)
N E G , N EG A , N EG B
Negate accumulator o r memory
ORA, O R B
O r memory with accumulator
ROL, R O LA, R O L B
Rotate accumulator or memory left
ROR, RORA, RORB
Rotate accumulator o r memory right
S BCA, S BCB
Subtract memory from accumulator with borrow
STA, S T B
Store accumulator to memroy
S U BA, S U B B
S ubtract memory from accumulator
TST, TSTA, TSTB
Test accumulator or memory location
TFR R l , R2
Transfer Rl to R2 ( R l , R2",A, B, CC, D P )
NOTE: A, B, C C , or D P may b e pushed t o (pulled from) either stack with P SH S , PS HU
( P U LS , P U LU ) instructions.
4·11
Table 4·3. 16·Bit Accumulator and Memory Instructions
Description
Instruction
ADDD
Add memory t o D accumulator
CMPD
Compare memory from D accumulator
EXG D, R
Exchange D with X, y, S, U, or PC
LDD
Load D accumulator from memory
S EX
Sign Extend B accum ulator into A accumulator
STD
Store D accum ulator to memory
SUBD
Subtract memory from D accumulator ...
TFR D, R
Transfer D to X, Y, S, U, or P C
TFR R , D
Transfer X, Y, S , U, or PC to D
NOTE: D may be pushed (pulled) to either stack with PSHS, PSHU ( P U LS, P U L U )
instructions.
Table 4·4. Index/Stack Pointer Instructions
Instruction
Description
CMPS, CMPU
Compare memory from stack pointer
C M PX, C M P Y
Compare memory from index register
EXG R 1 , R2
Exchange D, x, Y, �, U or PC Wltn D, x, Y, 5, U or PC
LEA S , LEAU
Load effective address into staCk·pointer
LEAX, LEAY
Load effective address into index register
LDS, LDU
Load stack pointer from memory
LDX, LDY
Load index register from memory
PSHS
Push A, B, CC, DP, D, X, Y, U, or P C onto hardware stack
P SH U
Push A, B, CC, D P , D , X, Y , X , or PC onto user stack
P U LS
Pull A, B, CC, DP, D, X, Y, U, or PC from hardware stack
P U LU
Pull A, B, CC, DP, D, X, Y, S, or PC; from hardware stack
STS, STU
Store stack pointer to memory
STX, STY
Store index register to memory
TFR R 1 , R2
Transfer D, X, Y, S, U, or PC to D, X, Y, S, U, or PC
ABX
Add B accumulator to X ( unsigned)
4·1 2
Table 4·5. Branch Instructions
Instruction
I
Description
SIMPLE BRANCHES
B EQ, lBEQ
B ranch if equal
B N E, l B N E
B ranch i f not equal
B M I, l B M I
B ranch i f minus
B Pl,lBPl
B ranch if plus
BCS, lBCS
B ranch if carry set
BCC, lBCC
Branch if carry clear
BVS, lBVS
Branch if overflow set
BVC, lBVC
Branch if overflow clear
BGT, lBGT
B ranch if greater (signed)
SIGNED BRANCHES
BVS, lBVS
B ranch if invalid twos complement result
B G E, l B G E
B ranch i f greater t h a n or equal (signed)
BEQ, l B EQ
B ranch if equal
B N E, l B N E
B ranch i f n o t equal
B lE, lBlE
B ranch if less than or equal (Signed)
BVC, lBVC
B ranch if valid twos complement result
B lT,l B lT
B ranch if less than (Signed)
B H I ,l B H I
B ranch i f higher ( unsigned)
B CC, lBCC
B ranch if higher or same ( unsigned)
B H S,lB H S
B ranch i f higher or same ( unsigned)
UNSIGNED BRANCHES
B EQ, lBEQ
B ranch if equal
B N E, l B N E
B ranch i f n o t equal
B lS, lBlS
B ranch if lower or same ( unsigned)
BCS, lBCS
B ranch if lower ( unsigned)
B lO, lBlO
Branch if lower (unsigned)
B S R, lBSR
B ranch to subroutine
BRA,lBRA
B ranch always
BRN, lBRN
B ranch never
OTHER B RANCHES
Table 4·6. Miscellaneous Instructions
Instruction
ANDCC
Description
A N D condition code register
CWAI
AND condition code register,then wait for interrupt
NOP
N o operation
ORCC
OR condition code register
JMP
Jump
JSR
Jump to subroutine
RTI
Retum from interrupt
RTS
Retum from subroutine
SWI, SWI2, SWI3
Software interrupt (absolute indirect)
SYNC
Synchron ize with interrupt line
4-13/4-14
APPENDIX A
INSTRUCTION SET DETAILS
A.1 INTRODUCTION
This appendix contains detailed information about each instruction in the MC6809 in­
struction set. They are arranged i n an alphabetical order with the mnemonic head ing set
in larger type for easy reference.
A.2 NOTATION
I n the operation description for each instruction, symbols are used to indicate the opera­
tio n . Table A-1 l ists these symbols and their meanings. Abbreviations for the various
registers, bits, and bytes are also used . Table A-2 l ists these abbreviations and their
meani ngs.
Table A·1. Operation Notation
�
Meaning
Is transferred to
A
Boolean A N D
V
Boolean O R
•
Boolean exclusive O R
(Overlinel
Boolean NOT
Concatenation
+
Arithmetic plus
X
Arithmetic multiply
Arithmetic minus
A-1
Table A·2. Register Notation
Abbreviation
Meaning
ACCA or A
Accumulator A
ACCB or B
Accumulator B
ACCA:ACCB or 0
Double accumulator 0
ACCX
Either accumulator A or B
CCR or CC
Condition code register
D P R or DP
Direct page register
EA
Effective add ress
I FF
If and only if
IX or X
I ndex register X
I Y or Y
I ndex register Y
LSN
Least significant nibble
M
Memory location
MI
Memory immediate
MSN
M ost significant nibble
PC
Program counter
R
A register before the operation
R'
A register after the operation
TEMP
Temporary storage location
xxH
Most signifcant byte of any 16-bit register
xxL
Least significant byte of any 1 6-bit register
Sp or S
Hardware Stack pointer
Us or U
User Stack pointer
P
A memory argument with Immediate, Di­
rect,Extended, and Indexed addressing
modes
Q
A read-modify-write argument with Direct,
I ndexed, and Extended addressing modes
( )
The data pointed to by the enclosed
( 1 6-bit address)
dd
�bit branch offset
DODD
16-bit branch offset
I
Immediate value follows
$
Hexadecimal value follows
[ 1
I ndirection
I ndicates indexed addressing
A-2
ABX
Add Accumulator B into Index Register X
ABX
Source Form:
ABX
Operation:
IX' - IX + ACCB
Condition Codes:
Not affected .
Description:
Add the a·bit unsigned val ue in acc u m u l ator B i nto i ndex reg ister X.
Addressing Mode:
I nherent
A·3
ADC
Add with Carry into Register
Source Forms:
ADCA P; ADCB P
Operation:
R' - R + M + C
Condition Codes:
H
N
Z
V
C
-
-
-
-
-
Set
Set
Set
Set
Set
if
if
if
if
if
A DC
a half-carry is generated ; cl eared otherwise.
the result is negat ive; c leared ot herwise.
the result i s zero; c l eared otherwise.
an overflow is generated ; cleared ot herwise.
a carry i s generated ; cleared otherwise.
Description:
Adds the contents of the C (carry) bit and the memory byte i nto an
8-bit acc u m u l ator.
Addressing Modes:
I mmed i ate
Extended
Di rect
Indexed
A-4
A D D (8- Bit)
Add Memory into Register
Source Forms:
ADDA P; ADDB P
Operation:
R' - R + M
Condition Codes:
H
-
N
-
Z
V
C
-
-
-
Set
Set
Set
Set
Set
if
if
if
if
if
AD D (8- Bit)
a half-carry i s generated ; c leared otherwise .
the resu lt i s negative; cleared otherwise.
the resu lt i s zero; cleared otherwise.
an overflow is generated; c leared otherwise.
a carry is generated; cleared otherwise.
Description:
Adds the memory byte i nto an a-bit acc u m u l ator.
Addressing Modes:
I m mediate
Extended
Di rect
I ndexed
A-5
A D D (16-Bit)
Add Memory into Register
Source Forms:
ADDD P
Operation:
R' - R + M : M + 1
AD D (16-Bit)
Condition Codes:
H N Z V C -
Description:
Adds the 1 6·bit memory val ue into the 1 6·bit acc u m u l ator
N ot affected .
Set if the resu lt is negative; cl eared ot herw i se.
Set if the result is zero; cl eared otherwise.
Set if an overflow is generated ; cl eared otherwise.
Set if a carry is generated ; cleared ot herwise.
Addressing Modes: I mmed iate
Extended
D i rect
I ndexed
A·6
AN D
Logical AN D Memory into Regi ster
AN D
Source Form s:
A N DA P; AN DB P
Operation:
R' - RAM
Condition Codes:
H
N Z V C -
Description:
Performs the logical AN D operat ion between t h e contents of an ac·
c u m u l ator and the contents of memory locat ion M and the result i s
stored i n t h e acc u m u l ator.
N ot affected .
Set if the resu lt is negat ive; cleared otherw i se.
Set if the resu lt is zero; c l eared ot herwise.
Always c leared .
N ot affected .
Addressing Modes: I m m ed i ate
Extended
D i rect
I ndexed
A·7
AN D
Logical AND Immediate Memory Into Condition Code Register
AN D
Source Form:
A N DCC #xx
Operation:
A' - AA MI
Condition Codes:
Affected accord ing to the operation.
Description:
Performs a logical AN D between the cond ition code reg ister and the
i m med i ate byte specified in the i n struction and places the result in
the condition code reg ister.
Addressing Mode:
I mmed i ate
A-a
ASL
Arithmetic Shift Left
Source Forms:
AS L Q; AS LA; AS LB
Operation:
c+-I I I I I I I I 1- 0
b7
Condition Codes:
Description:
H
-
N
-
Z
-
V
-
C
-
..
AS L
bO
Undef ined
Set if the result is neg at ive; cleared ot herwise.
Set if the result is zero; c l eared otherw i se.
Loaded with the res u lt of the exc l usive OR of bits s i x and
seven of the ori g i nal o perand .
Loaded with bit seven of the ori g inal operan d .
Sh i fts a l l bits of the operand one place to the l eft. Bit zero is loaded
with a zero. Bit seven is sh i fted into the C (carry) bit.
Addressing Modes: I nherent
Extended
Di rect
I ndexed
A-9
AS R
Source Forms:
Operation:
Arithmetic Shift Right
AS R
ASR Q; ASRA; ASRB
�""""rl----r �
-r- -'Ir---T'I---r-I--'1 -. c
b7
-
bO
Condition Codes:
H
N
Z
V
C
U ndefi ned.
Set if the result is negat ive; c leared otherwise.
Set if the result is zero; c leared otherw i se.
Not affected.
Loaded with bit zero of the ori g i nal operand.
Description:
Shifts al l bits of the operand one pl ace to the right. Bit seven i s held
constant. Bit zero i s shifted i nto the C (carry) bit.
Addressing Modes:
I nherent
Extended
Direct
I ndexed
A·1 0
Bee
Branch o n Carry Clear
Bee
Source Forms:
BCC dd; LBCC DODD
Operation:
TEM P - M I
I F F C = 0 then PC' - PC + TEM P
Condition Codes:
Not affected .
Description:
Tests the state of the C (carry) bit and causes a branch if it is c l ear.
Addressing Mode:
Rel at ive
Comments:
Equ ivalent to B H S dd; LBHS DODD
A-11
B CS
Branch on Carry Set
BCS
DODD
Source Forms:
BCS dd; LBCS
Operation:
TEM P - M I
I F F C=1 then PC' - PC + TEM P
Condition Codes:
Not affected .
Description:
Tests the state of the C (carry) bit and causes a branch if it is set.
Addressing Mode:
Relat ive
Comments:
Eq uivalent to BLO dd; LBLO
A-12
DODD
B EQ
Branch on Equal
B EQ
Source Forms:
B EQ dd; LBEQ DODD
Operation:
T EM P - M I
I F F Z = 1 then PC' - PC + TEM P
Condition Codes:
N ot affected .
Description:
Tests the state of the Z (zero) bit and causes a branch if it is set .
When used after a su btract or compare operation, this i n struction
will branch if the com pared val ues, sig ned or unsig ned, were exact ly
the same.
Addressing Mode:
Relat ive
A·1 3
BG E
Branch on G reater than or Equal to Zero
BG E
Source Forms:
BG E dd; LBG E DODD
Operation:
TEM P - M I
I FF [NeV1 = O then PC' - PC + TEM P
Condition Codes:
Not affected .
Description:
Causes a branch if the N (negat ive) bit and the V (overflow) bit are
either both set or both clear. That is, branch if the sign of a val id
twos com plement resu lt is, or woul d be, positive. When u sed after a
subtract or compare operation on twos com plement val ues, t h i s in­
struction will branch if the reg i ster was g reater than or eq ual to the
memory operand.
Addressing Mode:
Rel at ive
A-1 4
BGT
Branch on Greater
BGT
Source Forms:
BGT dd; LBGT DODD
Operation:
TEM P - M I
I FF Z A [N eV] = O then PC' - PC + TEM P
Condition Codes:
N ot affected .
Description:
Causes a branch if the N (negative) bit and V (ove rflow) bit are either
both set or both clear and the Z (zero) bit is c lear. I n other words,
branch if t he s i g n of a val id twos com p lement result is, or wou l d be,
posit ive and not zero. When used after a subt ract or com pare opera­
tion on twos complement val ues, t h i s i nstruction wi l l branch if the
reg i ster was g reater than the memory operand.
Addressing Mode:
Relat ive
A-15
BHI
Branch if Higher
BHI
Source Forms:
B H I dd; LBH I DODD
Operation:
TEM P - M I
I FF [C v Z] = 0 then PC' - PC + TEMP
Condition Codes:
Not affected .
Description:
Causes a branch if the previous operation caused neither a carry nor
a zero result. When used after a subtract or compare operat ion on
unsigned binary val ues, t h i s instruct ion w i l l branch if the reg ister
was h i gher than the memory operand.
Addressing Mode:
Relative
Comments:
Generally not usef u l after I NC/DEC, LDITST, and TST/CLR/CO M i n­
struct ions.
A-1 6
BHS
Branch if Higher or Same
BHS
Source Forms:
BHS dd ; LBHS DDDD
Operation:
TEM P - M I
I F F C = O then PC' - PC+M I
Condition Codes:
Not affected .
Description:
Tests the state of the C (carry) bit and causes a branch if it is c l ear.
When used after a subt ract or com pare on unsigned binary val ues,
t h i s i n struct ion w i l l branch if the reg i ster was h i gher than or the
same as the memory operand.
Addressing Mode:
Relat ive
Comments:
Th i s is a d u p l icate assembly-lang uage m nemonic for the single
mach i n e i n st ruction BCC. Generally not useful after I NC/DEC,
LD/ST, and TST/CLR/COM instruct ions.
A-1 7
B IT
Bit Test
Source Form:
Bit P
Operation:
TEM P - RAM
Condition Codes:
H
N
Z
V
C
Description:
BIT
- Not affected.
- Set if the resu lt is negat ive; cleared otherwise.
Set if the res u lt is zero; c leared otherwise.
- Always cleared .
- Not affected .
-
Performs the log ical AN D of the contents of accu m u l ator A or B and
the contents of memory location M and mod ifies the cond ition
codes accord i n g ly. The contents of accu m u l ator A or B and memory
locat ion M are not affected .
Addressing Modes: Immed iate
Extended
Di rect
I ndexed
A·1 8
BlE
Branch on Less than or Equal to Zero
BlE
Source Forms:
BlE dd; lBlE DO D D
Operation:
TEM P-M I
I F F Z v [N ED V] = 1 then PC'-PC + TEM P
Condition Codes:
Not affected .
Description:
Causes a branch if the exclusive OR of the N (negative) and V
(overflow) bits is 1 or if the Z (zero) bit is set . That i s , branch i f the
sign of a val id twos com plement result is, or wou ld be, negat ive.
When used after a subtract or com pare operation on twos com p l e­
ment val ues, t h i s i n struct ion wi l l branch if the reg i ster was less than
or equal to the memory operand .
Addressing Mode:
Rel at ive
A-19
BlO
Branch on Lower
BlO
Source Forms:
BLO dd; LBLO DODD
Operation:
TEMP - MI
I FF C=1 then PC'-PC+TEMP
Condition Codes:
Not affected.
Description:
Tests the state of the C (carry) bit and causes a branch if it is set.
When used after a su btract or compare on unsigned bin ary val ues,
this instruction wil l branch if the register was lower than the
memory operand.
Addressing Mode:
Relative
Comments:
This is a du plicate assembly-language mnemon ic for the single
mach ine instruction BCS. General l y not useful after INC/DEC,
LD/ST, and TST/CLR/COM i n structions.
A-20
BLS
Branch on Lower or Same
BLS
Source Forms:
BLS dd; LBLS DOD D
Operation:
TEM P - M I
I FF (C v Z) = 1 then PC' - PC + TEM P
Condition Codes:
Not affected.
Description:
Causes a branch if the previous operat ion caused either a carry or a
zero result. When used after a subtract or compare operat ion on u n­
s i gned binary val ues, t h is i n struction w i l l branch if the reg ister was
lower than or the same as the memory operand.
Addressing Mode:
Relative
Comments:
Generally not useful after I N C/DEC, LD/ST, and TST/CLR/COM i n­
structions.
A-21
Bll
Branch on Less than Zero
Bll
Source Forms:
BLT dd; LBLT DODD
Operation:
TEMP-MI
IFF [NeV]=1 then PC'-PC+TEMP
Condition Codes:
Not affected.
Description:
Causes a branch if either, but not both, of the N (negative) or V
(overflow) bits is set. That i s, branch if the s i g n of a val i d twos com­
plement result Is, or would be, negat ive. When used after a s ubtract
or compare operation on t wos complement b inary values, t h i s i n ­
struction wi l l branch if the reg ister was less t h a n t h e memory
operand.
Addressing Mode:
Relative
A-22
BMI
Branch on Minus
BMI
Source Forms:
BM I dd; LBM I DODD
Operation:
TEM P - M I
I FF N =1 then PC' - PC + TEM P
Condition Codes:
Not affected.
Description:
Tests the state of the N (negative) bit and causes a branch if set.
That is, branch if the sign of the tw os com plem ent result is negative.
Addressing Mode:
Relative
Comments:
When u sed after an operation on signed binary values, this i n struc­
tion w i l l branch if the resu lt is m i n us. It is general ly preferred to use
the LBLT i nstruction after sig ned operations.
A-23
BN E
Branch Not Equal
BNE
Source Forms:
B N E dd; LBN E DODD
Operation:
TEM P - M I
I FF Z = O then PC' - PC + TEM P
Condition Codes:
N ot affected .
Description:
Tests the state of the Z (zero) bit and causes a branch if it is c lear.
When used after a subtract or com pare operation on any binary
val ues, this instruction w i l l branch i f the reg ister is, or would be, not
equal to the memory operand.
Addressing Mode:
Relat ive
A-24
BPL
Branch o n Plus
BP L
Source Forms:
BPL dd; LBPL DODD
Operation:
TEM P - M I
I FF N = 0 then PC' - PC + TEM P
Condition Codes:
Not affected .
Description:
Tests the state of the N (negative) bit and causes a branch if it is
clear. That is, branch if the sign of the twos com p lement result i s
posit ive.
Addressing Mode:
Rel ative
Comments:
When used after an operation on sig ned binary val ues, this i nstruc­
tion wi l l branch if the resu lt (possibly i nval id) is positive. It is general­
ly preferred to use the BGE i n struction after sig ned operations.
A-25
BRA
Branch Always
Source Forms:
BRA dd; LBRA DODD
Operation:
TEM P - M I
PC' - PC + TEM P
Condition Codes:
Not affected .
Description:
Causes an uncond itional branc h .
Addressing Mode:
Relat ive
A·26
B RA
B RN
Branch Never
BRN
Source Forms:
BRN dd; LBRN DODD
Operation:
TEM P - M I
Condition Codes:
N ot affected .
Descript ion:
Does not cause a branch. Th is i n struction is essent ially a no opera­
tion, but has a bit pattern logically rel ated to branch always.
Addressing Mode:
Rel at ive
A-27
BSR
Branch to Subroutine
BSR
Source Forms:
BSR dd; LBSR DODD
Operation:
TEM P - M I
S P' - SP - 1 , (SP) - PCL
S P' - S P - 1 , (S P) - PC H
PC' - PC + TEM P
Condition Codes:
N ot affected .
Description:
The program counter is pushed onto the stack. The prog ram counter
i s then loaded with the sum of the prog ram counter and the offset .
Addressing Mode:
Relat ive
Comments:
A ret urn from subroutine (RTS) i n st ruction i s used to reverse this pro­
cess and m u st be the l ast i n st ruction executed in a subrouti ne.
A-28
Bve
Branch on Overflow Clear
Bve
Source Forms:
BVC dd; LBVC DODD
Operation:
TEM P - M I
I FF V=O then PC' - PC + TEM P
Condition Codes:
N ot affected .
Description:
Tests the state of the V (overflow) bit and causes a branch if it is
clear. That is, branch if the twos complement result was val id. When
used after an operation on twos complement b i nary val ues, t h i s i n­
struct ion wi l l branch if there was no overflow.
Addressing Mode:
Rel at ive
A-29
BVS
Branch on Overflow Set
BVS
Source Forms:
BVS dd; LBVS DODD
Operation:
TEM P - M I
I FF V = 1 then PC' - PC + TEM P
Condition Codes:
N ot affected .
Description:
Tests the state of the V (overflow) bit and causes a branch if it i s set .
That is, branch if the twos complement result was i nval id. When us­
ed after an operation on twos .complement binary val ues, this i n­
struction w i l l branch if there was an overflow.
Addressing Mode:
Relat ive
A-30
CLR
Clear
CLR
Source Form:
CLR a
Operation:
TEM P - M
M - 00 1 6
Condition Codes:
H
N
Z
V
C
Description:
Accu m u l ator A or B or memory location M is loaded with 00000000.
Note that the EA is read during this operation .
-
Not affected.
Always cleared.
Always set.
Always cleared.
Always cleared.
Addressing Modes: I nherent
Extended
Direct
I ndexed
A-31
CMP (8-Bit)
Compare Memory from Register
Source Forms:
C M PA P; CM PB P
Operation:
TEM P - R - �
Condition Codes:
H
N
Z
V
C
-
-
-
-
-
CMP (8-Bit)
U ndefi ned.
Set if the result is negative; cleared otherwise.
Set if the result is zero; cleared otherwise.
Set if an overflow is generated ; cleared otherwise.
Set if a borrow is generated; cleared otherwise.
Description:
Com pares the contents of memory locat ion to the contents of the
specified reg i ster and sets the appropriate condition codes. N either
memory location M nor the specified reg ister is modified . The carry
flag represents a borrow and is set to the i nverse of the resulting
bi nary carry.
Addressing Modes:
I mmed iate
Extended
Di rect
I ndexed
A-32
CMP (1 6- Bit)
Compare Memory from Register
CMP (1 6- Bit)
Source Forms:
C M PD P; CM PX P; CM PY P; CM PU P; CM PS P
Operation:
TEM P - R
Condition Codes:
H
N
Z
V
C
Description:
-
M:M + 1
- Not affected.
- Set if the resu lt is negative; cleared otherwise.
Set if the resu lt is zero; cleared otherw i se.
- Set if an overflow is generated ; cleared otherwise.
- Set if a borrow is generated ; cleared otherwise.
-
Compares the 1 6-bit contents of the concatenated memory locations
M:M + 1 to the contents of the specified reg i ster and sets the ap­
propriate condition codes. N either the memory locations nor the
specified reg ister i s mod ified unless autoincrement or autodecre­
ment are used . The carry flag represents a borrow and is set to the
inverse of the resulting binary carry.
Addressing Modes: I m med iate
Extended
D irect
I ndexed
A-33
CO M
Complement
CO M
Source Forms:
COM Q; COMA; COM B
Operation:
M ' - 0 + f\f
Condition Codes:
H
N
Z
V
C
Description:
Replaces the contents of memory location M or accumulator A or B
with its log ical com plement . When operat i n g on unsig ned val ues,
only BEQ and BN E branches can be expected to behave properly
fol lowing a COM i n st ruction . When operat i n g on twos com plement
val ues, al l signed branches are avai l able.
- Not affected.
- Set if the resu lt is negat ive; cl eared otherwise.
- Set if the res u lt is zero; cl eared otherw ise.
- Atways cleared .
- Always set .
Addressing Modes: I n herent
Extended
D i rect
I ndexed
A·34
CWAI
Clear CC bits and Wait for Interrupt
CWAI
IEl F I H I I I NI I VI C I
Source Form:
CWAI #$XX
Operation:
CCR - CCR A M I (Possibly clear masks)
Set E (ent i re state saved)
SP' - SP - 1 , (SP) - PCL
S P' - SP - 1 , (S P) - PCH
SP' - SP - 1 , (S P) - USL
SP' - SP - 1 , (SP) - USH
S P' - SP - 1 , (SP) - IYL
SP' - SP - 1 , (S P) - IYH
S P' - SP - 1 , (SP) - IXL
SP' - SP - 1 , (S P) - IXH
SP' - SP - 1 , (SP) - DPR
SP' - SP - 1 , (S P) - ACCB
SP' - SP - 1 , (S P) - ACCA
S P' - SP - 1 , (SP) - CCR
Condition Codes:
Affected according to the operation .
Description:
Th i s i nstruction AN Ds an i m med iate byte with the condition code
reg i ster which may c l ear the i nterrupt mask bits I and F, stacks the
ent i re mac h i n e state on the hardware stack and then looks for an i n­
terrupt. When a non-masked i nterrupt occurs, no further mac h i ne
state informat ion need be saved before vectori ng to the i nterrupt
hand l ing routine. Th is i n struction rep l aced the M C6800 CLI WAI se­
q uence, but does not p l ace the buses in a h igh-impedance state. A
Fi"RO' (fast interrupt req uest) may enter its i nterrupt handler with its
ent i re mac h i ne state saved. The RTI (return from i nterrupt) i nst ruc­
tion w i l l automat ical ly ret urn the ent i re machine state after test i n g
the E (ent i re) b i t o f t h e recovered cond it ion code reg i ster.
Addressing Mode:
I m med iate
Comments:
The fol lowi n g i m med iate values w i l l have the fol low i ng results:
F F = enable neither
E F = enable 'iRa
B F = enable FI RQ
AF = enable both
z
A-35
DAA
Decimal Addition Adjust
DAA
Source Form:
DAA
Operation:
ACCA' - ACCA + CF (M SN):CF(LSN)
where CF is a Correct ion Factor, as fol lows: the CF for each n i bble
(BCD) d ig it is determ i ned separately, and is either 6 or o .
Least Significant N ibble
C F(LSN) = 6 I FF 1) C = 1
or 2) LSN > 9
Most Significant N i bble
C F(MSN) = 6 I FF 1) C = 1
or 2) M SN > 9
or 3) M SN > 8 and LSN > 9
Condition Codes:
H
N
Z
V
C
Description:
The seq uence of a single-byte add i nstruction on acc u m u l ator A
(e ither ADDA or ADCA) and a fol lowi ng dec i m a l add ition adj u st i n ­
struction resu lts i n a BCD add ition with an appropriate carry bit.
Both val ues to be added m u st be i n proper BCD form (each n i bble
such that: Os n i bble s 9). M u lt i p l e-precision add ition m ust add the
carry generated by this decimal add ition adj u st i nto the next h i g her
d i g it d u ring the add operation (A DCA) immed i ately prior to the next
dec i m al add it ion adj ust.
Addressing Mode:
I nherent
-
N ot affected .
Set if the result is negative; cl eared otherwise.
Set if the result is zero; c leared otherwise.
U ndefi ned .
Set i f a carry is generated or if the carry bit was set before the
operation; cleared otherwise.
A-36
D EC
Decrement
DEC
Source Forms:
DEC Q; DECA; DECB
Operation:
M' - M - 1
Condition Codes:
H
N
Z
V
C
Description:
Subtract one from the operand. The carry bit is not affected, thus
allowing t h i s instruct ion to be used as a loop counter i n m u lt i ple­
prec ision com putations. When operat i n g on unsig ned val ues, on ly
BEQ and B N E branches can be expected to behave consistently.
When operat i ng on twos com plement val ues, al l sig ned branches
are available.
-
N ot affected .
Set if the resu lt is negat ive; cleared ot herwise.
Set if the result is zero; c leared ot herwise.
Set i f the original operand was 1 0000000; c leared ot herwise.
N ot affected .
Addressing Modes: I n herent
Extended
Di rect
I ndexed
A-37
EO R
Excl usive O R
EO R
Source Forms:
EO RA P; EO RB P
Operation:
R' - R ED M
Condition Codes:
H
N
Z
V
C
Description:
The contents of memory l oc ation M is exc l usive O Red i nto an 8-bit
reg i ster.
-
N ot affected .
Set if the result is negative; cleared otherwise.
Set if the result is zero; c leared otherw i se.
A lways cleared .
N ot affected .
Addressing Modes: I m med iate
Extended
D i rect
I ndexed
A-38
EXG
EXG
Exchange Registers
Source Form:
EXG R1 , R2
Operation:
R1 - R2
Condition Codes:
N ot affected (u n l ess one of the reg i sters is the condition code
reg i ster).
Description:
Exchanges data between two designated reg i sters. Bits 3-0 of the
post byte defi ne one reg ister, wh i l e bits 7-4 d efine the other, as
fo l lows:
OOOO = A:B
0001 = X
001 0 = Y
001 1 = US
01 00 = S P
01 01 = PC
01 1 0 = Undefi ned
01 1 1 = Undefi ned
1 000 = A
1 001 = B
1 0 1 0 = CCR
1 01 1 = DPR
1 1 00 = U ndefi ned
1 1 01 = Undefi ned
1 1 1 0 = Undefi ned
1 1 1 1 = Undefi ned
Only l i ke size reg i sters may be exchanged. (8-bit with 8-bit or 1 6-bit
with 1 6-bit .)
Addressing Mode:
I m med iate
A-39
INC
Increment
I NC
Source Forms:
I N C Q; I N CA; I N CB
Operation:
M'- M + 1
Condition Codes:
H
N
Z
V
C
Description:
Adds to the operand. The carry bit is not affected , thus al low i n g t h i s
i n struction to b e used a s a loop counter in m u lt i ple-precision com­
putat ions. When operating on unsigned val ues, only the BEQ and
BN E branches can be expected to behave consistently. When
operat i ng on twos com plement val ues, al l sig ned branches are cor­
rectly avai lable.
-
N ot affected .
Set if the result is negat ive; cleared otherwise.
Set if the result is zero; c leared otherwise .
Set if the origi nal operand was 01 1 1 1 1 1 1 ; cl eared otherw i se.
N ot affected .
Addressing Modes: I nherent
Extended
Direct
I n dexed
A-40
JMP
J ump
Source Form:
J M P EA
Operation:
PC' - EA
Condition Codes:
N ot affected .
Description:
Prog ram contro l is transferred to the effect ive address.
Addressing Modes: Extended
Di rect
I ndexed
A-41
JMP
JSR
J ump to Subro utine
JSR
Source Form:
JSR EA
Operation:
SP' - SP - 1 , (S P) - PC L
SP' - SP - 1 , (S P) - PC H
PC' - EA
Condition Codes:
Not affected.
Description:
Prog ram control is transferred to the effective add ress after stori ng
the retu rn address on the hardware stack. A RTS i n st ruction sho u l d
b e t h e last executed inst ruct ion o f t h e su brout ine.
Addressing Modes: Extended
Di rect
I ndexed
A·42
L D (8- Bit)
Load Register from M emory
L D (8- Bit)
Source Forms:
LOA P; LOB P
Operation:
R'
Condition Codes:
H
N ot affected .
N - Set if the l oaded data i s negative; cleared ot herwise.
Z
Set if the l oaded data is zero; cl eared otherwise.
V
Always cl eared .
C
N ot affected .
-
M
-
-
-
-
Description:
Loads the contents of memory location M i nto the desig nated
reg i ster.
Addressing Modes: I mmed iate
Extended
Di rect
Indexed
A-43
L D (1 6- Bit)
Load Register from Memory
Source Forms:
LOO P; LOX P: LOY P; LOS P; LOU P
Operation:
R' - M : M + 1
Condition Codes:
H
N
Z
V
C
Description:
L D (1 6-Bit)
N ot affected .
Set if the loaded data is negat ive; c leared otheriwse.
- Set if the loaded data is zero; cl eared otherwise.
- Always cleared .
- N ot affected .
-
Load the contents of the memory locat ion M : M + 1 i nto the
desi gnated 1 6-bit reg i ster.
Addressing Modes: I m med iate
Extended
Di rect
I ndexed
A-44
LEA
L EA
Load Effective Address
Source Forms:
LEAX, LEAY, LEAS, LEAU
Operation:
R' - EA
Condition Codes:
H - N ot affected .
N - N ot affected .
Z - LEAX, LEAY: Set if the resu lt is zero; cl eared otherwise.
LEAS, LEAU: Not affected.
V - N ot affected .
C - N ot affected .
Description:
Cal c u l ates the effect ive add ress f rom the i ndexed addressi ng mode
and pl aces the add ress in an i ndexable reg ister.
LEAX and LEAY affect the Z (zero) bit to al low u se of these reg isters
as counters and for M C6800 I N XIDEX compat i b i l ity.
LEAU and LEAS do not affect the Z bit to al low clean i ng up the stack
w h i l e ret u rn i n g the Z bit as a parameter to a cal l i ng routi ne, and also
for M C6800 I N SID ES com pat i b i l ity.
Addressing Mode:
I ndexed
Comments:
Due to the order i n which effective add resses are calcu lated i nter­
nal ly, the LEAX, X + + and LEAX, X + do not add 2 and 1 (respective­
ly) to the X reg ister; but i n stead leave the X reg ister unchanged . Th is
also appl ies to the Y, U , and S reg isters. For the expected resu lts,
use the faster i nst ruction LEAX 2, X and LEAX 1 , X.
Some exam ples of LEA i nstruction uses are g iven in the fol lowi ng
table.
Instruct ion
LEAX
LEAX
LEAY
LEAY
LEAU
LEAS
LEAS
LEAX
1 0, X
500, X
A, Y
0, Y
- 1 0, U
- 1 0, S
1 0, S
5, S
Operation
X + 10 - X
X + 500 - X
Y+A-Y
Y+D-Y
U - 10 - U
- S - 10 - S
S + 10 - S
S+5-X
A-45
Comment
Adds 5-bit constant 1 0 to X
Adds 1 6-bit constant 500 to X
Add s 8-bit acc u m u l ator to Y
Adds 1 6-bit 0 accumulator to Y
Subt racts 1 0 from U
Used to reserve area on stack
Used to 'clean up' stack
Transfers as wel l as adds
LSL
Source Forms:
Operation:
Logical Shift Left
LSL Q; LSLA; LS LB
c- I I I I I I I I 1- 0
b7
Condition Codes:
H
N
Z
V
C
Description:
LSL
-
-
-
-
-
bO
U ndefi ned .
Set if the res u lt is negative; cleared otherwise.
Set if the res u lt is zero; cl eared otherwise.
Loaded with the resu lt of the exc l usive O R of bits six and
seven of the original operand.
Loaded with bit seven of the origi nal operand .
Sh ifts al l bits of accu m u l ator A or B or memory locat ion M one place
to the left . Bit zero is loaded with a zero. Bit seven of acc u m u l ator A
or B or memory locat ion M is shifted i nto the C (carry) bit.
Add ressing Modes: I n herent
Extended
D i rect
I ndexed
Comments:
Thi s is a d u p l icate assem bly-language mnemonic for the s i n g l e
mach ine i n struction ASL.
A-46
LS R
Source Forms:
Operation:
Logical Shift Right
LS R
LS R Q; LS RA; LSRB
0-+1 I I I I I I I 1- c
b7
bO
Condition Codes:
H - N ot affected .
N - Always cleared .
Z - Set if the result is zero; c leared ot herw i se.
V - N ot affected.
C - Loaded with bit zero of the orig i nal operand .
Description:
Performs a logical shift right on the operand . Sh ifts a zero i nto bit
seven and bit zero i nto the C (carry) bit.
Addressing Modes: I n herent
Extended
D i rect
I ndexed
A·47
MUL
M ultiply
MUL
Source Form:
MUL
Operation:
ACCA':ACCB' - ACCA x ACCB
Condition Codes:
H - N ot
N - N ot
Z - Set
V - N ot
C - Set
Description:
M u lt i p ly the unsigned b i nary n u m bers in the accum u l ators and
place the resu lt in both acc u m u l ators (ACCA contai ns the most­
significant byte of the resu lt). Unsig ned m u lt i ply a l lows m u lt i p l e­
precision operations.
Addressing Mode:
I nherent
Comments:
The C (carry) bit allows rou nding the most-sig nif icant byte t h rough
the seq uence: M U L, ADCA #0.
affected .
affected .
if the res u lt is zero; cleared ot herwise.
affected .
if ACCB bit 7 of resu lt is set; cleared otherwise.
A-48
N EG
Negate
N EG
Source Forms:
N EG Q; N EGA; N EG B
Operation:
M'-0 - M
Condition Codes:
H - U ndefined.
N - Set if the result is negat ive; cleared otherw i se.
Z - Set if the result is zero; c leared otherwise.
V - Set if the orig i nal operand was 1 0000000.
C - Set if a borrow is generated ; cleared ot herwise.
Description:
Rep laces the operand with its twos com plement. The C (carry) bit
represents a borrow and is set to the i nverse of the resulting bin ary
carry. N ote that 80 1 6 i s replaced by itself and only i n this case i s the
V (overflow) bit set . The val ue 00 1 6 is also rep laced by itself, and only
i n t h i s case is the C (carry) bit cleared .
Addressing Modes: I nherent
Extended
Di rect
A-49
NOP
No Operation
NOP
Source Form:
NOP
Operation:
N ot affected .
Condition Codes:
This i nstruct ion causes only the prog ram cou nter to be incremented .
No ot her reg i sters or memory locations are affected .
Addressing Mode:
I nherent
A-50
OR
Inclusive O R Memory into Register
Source Forms:
O RA P; ORB P
Operation:
R'
Condition Codes:
H - N ot affected .
N - Set if the resu lt is negat ive; cleared otherwise.
Z - Set if the result is zero; cl eared otherw ise.
V
Always cleared .
C - N ot affected .
-
OR
Rv M
-
Description:
Performs an i n c l u sive OR operation between the contents of ac­
c u m u l ator A or B and the contents of memory locat ion M and the
resu lt i s stored in accumulator A or B.
Addressing Modes: I mme d iate
Extended
Di rect
I ndexed
A-51
OR
I nclusive OR Memory Immediate i nto Condition Code Register
OR
Source Form:
ORee #XX
Operation:
R' - R v M I
Condition Codes:
Affected according to the operation.
Description:
Performs an inclusive OR operation between the contents of the
cond ition code reg isters and the immed i ate value, and the result is
placed in the cond ition code reg ister. This i n struct ion may be used
to set i nterrupt masks (d i sable i nterrupts) or an y other bit(s).
Addressing Mode:
Immed i ate
A-52
PS·H S
Push Registers on the Hardware Stack
Source Form:
PSH S
PSH S reg ister l i st
PSH S # LABEL
Post byte:
b7
Ipc
Operation:
b6
IU
b5 b4 b3 b2 b1
I Y I X l op I B I A
push order- - - - .
bO
I cc i
I FF b7 of post byte set, then: SP' - SP - 1 ,
SP' - S P - 1 ,
I FF b6 of postbyte set , then: SP' - SP - 1 ,
SP' - SP - 1 ,
I FF b5 of post byte set , then: SP' - SP - 1 ,
SP' - S P - 1 ,
I F F b4 of postbyte set , then: SP' - SP - 1 ,
SP'- SP - 1 ,
I FF b3 of postbyte set, then: SP' - SP - 1 ,
I FF b2 of postbyte set, then: SP' - SP - 1 ,
I FF b 1 of postbyte set, then: SP' - SP - 1 ,
I F F bO of post byte set, then: SP' - SP - 1 ,
(SP) - PCL
(SP) - PCH
(SP) - USL
(SP) - USH
(SP) - IYL
(SP) - IYH
(SP) - I X L
(SP) - I XH
(SP) - DPR
(SP) - ACCB
(SP) - ACCA
(SP) - CCR
Condition Codes:
Not affected .
Description:
Al l , some, or none of the p rocessor reg isters are pushed onto the
hardware stack (with the exception of the hardware stack pOi nter
itself).
Addressing Mode:
I m med iate
Comments:
A single reg i ster may be pl aced on the stack with the cond ition
codes set by doing an autodecrement store onto the stack (example:
STX , - - S).
A·53
PSH U
Source Form:
Push Registers on the User Stack
PSH U reg i ster l i st
PSH U # LABEL
Postbyte:
b7 b6 b5 b4 b3 b2 b1
I PC I U I Y I X I D P I B I A
push order- - - - -�
Operation:
PS H U
bO
I cc I
I FF b7 of postbyte set , then: US' - US - 1 ,
US' - US - 1 ,
I FF b6 of postbyte set , then: US' - US - 1 ,
US' - US - 1 ,
I FF b5 of postbyte set , then: US' - US - 1 ,
US' - US - 1 ,
I FF b4 of post byte set , then: US' - US - 1 ,
US' - US - 1 ,
I FF b3 of postbyte set , then: US' - US - 1 ,
I FF b2 of post byte set, then: US' - US - 1 ,
I FF b1 of postbyte set , then: US' - US - 1 ,
I FF bO of postbyte set , then: US' - US - 1 ,
(US) - PCL
(US) - PCH
(US) - SPL
(US)- SPH
(US) - IYL
(US) - IYH
(US) - IXL
(US) - IXH
(US) - DPR
(US) - ACCB
(US) - ACCA
(US) - CCR
Condition Codes:
N ot affected .
Description:
Al l , some, or none of the p rocessor reg isters are pushed onto the
user stack (with the except ion of the user stack poi nter itself).
Addressing Mode:
I m med iate
Comments:
A s i n gl e reg ister may be p laced on the stack with the condition
codes set by doing an autodecrement store onto the stack (exam ple:
STX , - - U).
A·54
P U LS
Source Form :
P U LS
Pull Registers from the H a rdware Stack
PU lS reg ister l i st
P U lS #lABEl
Postbyte:
b7 be b5 b4 b3 b2 b1 bO
I pc I U I Y I x l op I B I A I cci
... - - - - - - pu l l order
Operation:
then: CCR' - (S P),
then: ACCA' - (S P),
then: ACCB' - (S P),
then: OPR' - (SP),
then: I X H ' - (S P),
I Xl'
- (S P),
I FF b5 of postbyte set , then: IYH ' - (S P),
IYl'
- (SP),
I FF b6 of post byte set , then: USH' - (SP),
USl' - (SP),
I F F b7 of post byte set , then: PCH ' - (S P),
PCl' - (S P),
I FF
I FF
I FF
I FF
I FF
bO
b1
b2
b3
b4
of
of
of
of
of
post byte
postbyte
postbyte
post byte
post byte
set ,
set ,
set ,
set ,
set ,
SP' - S P + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
S P ' - SP + 1
SP' - SP + 1
S P' - SP + 1
SP' - SP + 1
S P' - SP + 1
S P' - SP + 1
SP' - SP + 1
SP' - SP + 1
Condition Codes:
M ay be p u l led from stack; not affected otherwise.
Description:
Al l , some, or none of the processor registers are p ulled from the
h ardware stack (w ith the exception of the h ardware stack poi nter
itself).
Addressing Mode:
I m med i ate
Comments:
A single reg i ster may be p u l l ed from the stack with cond ition codes
set by doing an auto i ncrement load from the stack (exa m ple:
lOX ,S + + ).
A-55
PU LU
Source Form:
Operation:
Pull Registers from the User Stack
PU lU reg ister l i st
PU lU #lASEl
Post byte:
b7 b6 b5 b4 b3 b2 b1
I PC I U I Y I X I OP I S I A
. - - - - - - pu l l order
I FF
I FF
I FF
I FF
I FF
bO
b1
b2
b3
b4
of
of
of
of
of
postbyte
postbyte
post byte
postbyte
postbyte
P U LU
bO
I cci
set ,
set ,
set ,
set,
set ,
then: CCR' - (US), US' - US + 1
then: ACCA' - (US), US' - US + 1
then: ACCS' - (US), US' - US + 1
then: OPR' - (US), US' - US + 1
then: I XH ' - (US), US' - US + 1
I Xl'
- (US), US' - US + 1
I F F b5 of postbyte set , then: IYH' - (US), US' - US + 1
IYl'
- (US), US' - US + 1
I FF b6 of postbyte set , then: SPH' - (US), US' - US + 1
SPl' - (US), US' - US + 1
I FF b7 of postbyte set, then: PCH - (US), US' - US + 1
PCl' - (US), US' - US + 1
Condition Codes:
May be pul led from stack; not affected otherwise.
Description:
Al l , some, or none of the processor reg i sters are p u l l ed from the u ser
stack (with the exception of the user stack pOi nter itself).
Addressing Mode:
I mmediate
Comments:
A single reg i ster may be p u l l ed from the stack with condition codes
set by doing an auto i n c rement load from the stack (exam ple:
lOX ,U + + ).
A-56
RO L
Source Forms:
Operation:
Rotate Left
RO L Q; ROLA; RO LB
"""--"' �....,..-j=r""I ,.
��
b7
Condition Codes:
RO L
'II(�----....
bO
H - N ot affected .
N - Set if the result is negat ive; cleared ot herwise.
Z - Set if the resu lt is zero; cleared otherwise.
V - Loaded with the result of the excl usive O R of bits six and
seven of the orig i nal operand.
C
Loaded with bit seven of the orig i nal operand .
-
Description:
Rotates a l l bits of the operand one place l eft through the C (carry)
bit. Th is is a 9-bit rotation.
Addressing Mode:
I n herent
Extended
Di rect
I ndexed
A-57
RO R
Rotate Right
Source Forms:
ROR Q; RO RA; RORB
Operation:
- I -Y"--'---I�_c_
I �
I -b7
-----�.
RO R
bO
Condition Codes:
H - Not affected .
N - Set i f the result is negat ive; c leared ot herwise.
Z - Set i f the result is zero; c l eared ot herw i se.
V - Not affected .
C - Loaded with bit zero of the previous operand .
Description:
Rotates al l bits of the operand one place right through the C (carry)
bit. Th i s is a 9·bit rotation.
Addressing Modes: I n herent
Extended
Di rect
I ndexed
A·58
RTI
RTI
Return from Interrupt
Source Form:
RTI
Operation:
CCR' - (S P), SP' - SP + 1 , then
I F F CCR bit E is set , then:
ACCA' - (S P),
ACCS' - (SP),
OPR' - (S P),
IXH ' - (S P),
- (SP),
IXL'
IYH ' - (SP),
IYL'
- (S P),
USH' - (S P),
USL' - (S P),
PCH ' - (SP),
PCL' - (S P),
SP' - SP + 1
SP' - S P + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
SP' - SP + 1
I F F CCR bit E i s c lear, then:
PCH ' - (SP), SP' - SP + 1
PCL' - (SP), SP' - SP + 1
Cond ition Codes:
Recovered from the stack.
Description:
The saved mach ine state is recovered from the hardware stack and
contro l i s returned to the i nterru pted prog ram . I f the recovered E (en­
t i re) bit is clear, it i n d icates that only a subset of the machine state
was saved (retu rn address and cond ition co des) and only that subset
is recovered .
Addressing Mode:
I n herent
A-59
RTS
Return from Subroutine
RTS
Source Form:
RTS
Operation:
PCH ' - (SP), SP' - SP + 1
PCl' - (SP), SP' - SP + 1
Condition Codes:
N ot affected .
Description:
Program control is retu rned from the subrout i ne to the cal l i ng pro­
g ram. The return address is pul l ed from the stack.
Add ressing Mode:
I nherent
A-60
SBe
Subtract with Borrow
SBe
Source Forms:
SBCA P; SBCB P
Operation:
R' - R
Condition Codes:
H
N
Z
V
C
Description:
Subtracts the contents of memory locat ion M and the borrow (in the
C (carry) bit) from the contents of the designated a·bit register, and
places the res u lt i n that reg i ster. The C bit represents a borrow and
i s set to the i nverse of the resulting bin ary carry.
-
-
M
-
C
Undefi ned .
Set if t h e resu lt is negative; c l eared otherwise.
Set if the resu lt is zero; c l eared ot herwise.
Set if an overflow is generated; cleared otherwise.
Set if a borrow i s generated ; cl eared oth erwi se .
Addressing Modes: I mm ed i ate
Extended
Di rect
I ndexed
A·61
S EX
Sign Extended
Sou rce Form:
S EX
Operation:
If bit seven of ACCe is set then ACCA' - F F 1 6
e l se ACCA' - 00 1 6
Condition Codes:
H
N
Z
V
C
SEX
- Not affected .
- Set if the result is negat ive; cleared otherwise.
- Set if the resu lt is zero; cleared otherwise.
N ot affected .
- N ot affected .
-
Description:
This i nstruction transforms a twos complement 8-bit value i n ac­
cumulator e i nto a twos com plement 1 6-bit val ue in the 0 ac­
cumulator.
Addressing Mode:
I nherent
A -62
ST (8-Bit)
Store Register· into Memory
ST (8-Bit)
Source Forms:
STA P; STe P
Operation:
M' - R
Condition Codes:
H - Not affected .
N - Set if the resu lt is negat ive; c leared ot herwise.
Z - Set if the result is zero; c leared otherwise.
V - Always cl eared .
C - Not affected .
Description:
Writes the contents of an 8·bit reg ister i nto a memory location .
Addressing Modes: Extended
Di rect
I ndexed
A-63
8T (1 6-Bit)
Store Register Into Memory
8T (1 6-Bi·t )
Source Forms:
STD P; STX P; STY P; STS P; STU P
Operation:
M ':M + 1 ' - R
Condition Codes:
H
N
Z
V
C
Description:
Writes the contents of a 1 6·bit reg ister i nto two consecutive memory
locations.
- Not affected .
- Set if the result is negative; cleared otherwise.
- Set if the resu lt is zero; c leared otherwise.
- Always c l eared .
- Not affected .
Addressing Modes: Extended
Di rect
I ndexed
A-64
SU B (8- Bit)
Su btract Memory from Register
Source Forms:
S U BA P; SUBB P
Operation:
R' - R
Condition Codes:
H
N
Z
V
C
Description:
-
-
-
-
-
-
SU B (8- Bit)
M
U ndefined .
Set if the resu lt is negative; c leared otherwise.
Set if the result is zero; c leared otherwise.
Set if the overflow is generated; c leared otherwise.
Set if a borrow is generated; c leared otherwise.
Subtracts the value i n memory location M from the contents of a
designated 8-bit register. The C (carry) bit represents a borrow and is
set to the inverse of the resu lting b i nary carry.
Addressing Modes: I m m ed iate
Extended
Direct
I ndexed
A-65
S U B (1 6- Bit)
Subtract Memory from Register
S U B (1 6- Bit)
Source Forms:
SUBD P
Operation:
R' - R
Condition Codes:
H - N ot affected .
N - Set if the resu lt is negat ive; cleared otherwise.
Z - Set if the resu lt is zero; cleared otherwise.
V - Set if the overflow is generated ; cleared otherwise.
C - Set if a borrow is generated ; cleared otherw ise.
Description:
Subtracts the val ue in memory location M :M + 1 from the contents of
a designated 1 6-bit reg i ster. The C (carry) bit represents a borrow
and is set to the inverse of the resulting binary carry.
-
M:M + 1
Addressing M odes: I mmed iate
Extended
Di rect
I ndexed
A-66
SWI
Software Interrupt
SWI
Source Form:
SWI
Operation:
Set E (enti re state wi l l be saved)
SP' - SP - 1 , (S P) - PCL
S P' - SP - 1 , (S P) - PCH
S P' - SP - 1 , (SP) - USL
SP' - SP - 1 , (S P) - USH
SP' - S P - 1 , (SP) - IYL
SP' - SP - 1 , (SP) - IYH
SP' - S P .- 1 , (SP) - IXL
SP' - SP - 1 , (SP) - IXH
SP' - SP - 1 , (S P) - D P R
S P' - SP - 1 , (SP) - ACCB
S P' - S P - 1 , (SP) - ACCA
S P' - SP - 1 , (SP) - CCR
Set I, F (mask i nterru pts)
PC' - (FFFA):(FFFB)
Condition Codes:
N ot affected .
Description:
Al l of the processor reg i sters are pushed onto the hardware stack
(with the exception of the h ardware stack poi nter itsel f), and control
is transferred through the software i nterrupt vector. Both the normal
and fast i nterrupts are masked (di sabled).
Addressing Mode:
I nherent
A-67
SWI2
Software Interrupt 2
SWI2
Source Form:
SWI 2
Operation:
Set E (ent i re state saved)
S P' - SP - 1 , (SP) - PCL
S P' - SP - 1 , (S P) - PCH
S P' - S P - 1 , (S P) - USL
S P' - SP - 1 , (S P) - USH
S P' - SP - 1 , (SP( - IYL
S P' - S P - 1 , (SP) - IYH
S P' - SP - 1 , (S P) - IXL
S P' - SP - 1 , (SP) - IXH
S P' - SP - 1 , (SP) - D P R
S P' - S P - 1 , (SP) - ACCB
S P' - SP - 1 , (SP) - ACCA
S P' - SP - 1 , (S P) - CCR
PC' - (FFF4):(FFF5)
Condition Codes:
N ot affected .
Description:
A l l of the processor reg i sters are pushed onto the hardware stack
(with the except ion of the hardware stack pOi n t er itself), and control
i s transferred through the software i nterrupt 2 vector. Th i s i nterrupt
i s avai l able to the end user and must not be u sed i n packaged soft­
ware. Th is interru pt does not mask (d isable) the normal and fast in­
terrupts.
Addressing Mode:
I n herent
A-6 8
SWI 3
Software Interrupt 3
SWI 3
Source Form:
SW I 3
Operation:
Set E (ent i re state wi l l be saved)
SP' - SP - 1 , (SP) - PCl
SP' - SP - 1 , (SP) - PCH
S P' - SP - 1 , (SP) - USl
SP' - SP - 1 , (S P) - USH
S P' - SP - 1 , (SP) - IYl
S P' - SP - 1 , (S P) - IYH
SP' - SP - 1 , (S P) - IXl
S P' - SP - 1 , (S P) - IXH
SP' - S P - 1 , (S P) - DPR
S P' - SP - 1 , (SP) - ACCB
S P' - S P - 1 , (SP) - ACCA
SP' - SP - 1 , (SP) - CCR
PC' - (FFF2):(FFF3)
Condition Codes:
N ot affected .
Description:
Al l of the processor reg i sters are pushed onto the hardware stack
(with the except ion of the hardware stack poi nter itself), and control
i s transferred t h rough the software i nterru pt 3 vector. This i nterru pt
does not mask (d i sable) the normal and fast i nterru pts.
Addressing Mode:
I n h erent
A-69
SYN C
Synchronize to External Event
SYN C
Source Form:
SYNC
Operat ion:
Stop processi ng i n structions
Condition Codes:
N ot affected .
Descri ption:
When a SYNC i nstruct ion is excuted , the processor enters a syn­
chron izi ng state, stops processing instructions, and waits for an in ­
terrupt . When an interrupt occ u rs, the synchron izi ng state i s c leared
and processing cont i n ues. If the i nterrupt is enabled , and it l asts
t h ree cyc les or more, the processor w i l l perform the i nterru pt
routine. i f the i nterrupt is masked or i s shorter t h an three cycles, the
processor s i mply cont i n ues to the next i nstruct ion. Wh i l e in the syn­
chronizing state, the add ress and data buses are in the hig h­
i m pedance state.
This i n struction provides software synchronization with a hardware
process. Consider the fol lowing exam ple for h i g h-speed acq u i s ition
of data:
FAST
SYNC
I nterru pt I
LDA
STA
DECB
BNE
WAIT F O R DATA
DISC
,X +
FAST
DATA FROM DISC A N D CLEAR I NTERRUPT
PUT IN BU FFER
COUNT IT, DON E?
GO AGA I N I F NOT.
The synchron izing state is cleared by any i nterrupt . Of cou rse, enabl­
ed interrupts at this pOint may destroy the d ata transfer and, as
such, shou ld represent only emergency condit ions.
The same con nect ion used for i nterrupt-driven I/O service m ay also
be used for high-speed data transfers by sett i n g the i nterrupt mask
a n d u s i n g the SY N C i n st ruct i o n as t h e above e xa m p l e
demonstrates.
Add ressing Mode:
I n herent
A-70
TFR
Transfer Register to Register
TFR
Source Form:
TFR R1 , R2
Operation:
R1 - R2
Condition Code:
N ot affected unless R2 is the cond ition code reg i ster.
Descri ption:
Transfers data between two designated registers. Bits 7-4 of the
postbyte define the sou rce reg i ster, wh i l e bits 3-0 define the dest i na­
tion reg i ster, as fol lows:
OOOO = A:B
0001 = X
001 0 = Y
001 1 = US
01 00 = S P
01 01 = PC
01 1 0 = U ndefi n ed
01 1 1 = U ndefined
1 000 = A
1 00 1 = B
1 01 0 = CCR
1 01 1 = CPR
1 1 00 = U ndefined
1 1 01 = U ndefined
1 1 1 0 = U n defined
1 1 1 1 = U n defined
O n ly l i ke size reg isters may be t ransferred . (8-bit to 8-bit, or 1 6-bit to
1 6-bit.)
Addressing Mode:
I m med i ate
A-71
TST
Test
TST
Source Forms:
TST Q; TSTA; TSTB
Operation:
TEM P - M
Condition Codes:
H
N
Z
V
C
Description:
Set the N (negat ive) and Z (zero) bits accordi ng to the contents of
memory location M , and c lear the V (overflow) bit. The TST i n st ruc­
t ion provides only m i n i m u m i n formation when testing u n s i g ned
val ues; si nce no unsigned val ue is less than zero, BlO and B lS have
no uti l ity. Wh ile B H I cou l d be used after TST, it provides exactly the
same control as BN E, wh i c h i s preferred. The signed branches are
avai lable.
-
-
0
N ot affected .
Set if the resu lt is n eg ative; cleared otherw i se.
Set if the resu lt is zero; c l eared ot herwise .
Always cleared.
Not affected .
Addressing Modes: I n herent
Extended
Di rect
I ndexed
Comments:
The M C6BOO processor clears the C (carry) bit.
A-72
FI RQ
Fast Interrupt Request (Hardware Interrupt)
FI RQ
Operation:
I F F F bit clear, then: S P' - S P - 1 , (S P) - PCL
S P' - S P - 1 , (S P) - PCH
Clear E (subset state is saved)
S P' - S P - 1 , (S P) - CCR
Set F, I (mask f u rther i nterru pts)
PC' - (FFF6):(FF F7)
Condition Codes:
Not affected .
Description:
A F I RQ (fast i nterru pt req uest) with t h e F (fast i nterru pt req uest
mask) bit clear causes t h i s i nterru pt sequence to occur at the end of
the c u rrent i nstruction. The prog ram cou nter and condit ion code
reg i ster are pushed onto the hardware stack. Program control is
transferred through the fast i nterrupt req uest vector. An RTI (retu rn
from i nterrupt) i n st ruction ret u rns the p rocessor to the ori g i nal task.
It is poss i bl e to enter the fast i nterru pt req uest rout ine with the en­
t i re mach ine state saved if the fast i nterru pt req uest occurs after a
c l ear and wait for i nterru pt i nstruction. A normal i nterru pt req uest
has lower priority than the fast i nterrupt req uest and is prevented
from i nterrupt i ng the fast i nterrupt req uest routi n e by automat ic set­
t i n g of the I (interrupt req uest mask) bit. Th i s m ask bit could then be
reset d u ri n g the i nterrupt rout i ne if priority was not desired. The fast
i nterrupt request al lows o perations on m emory, TST, I N C, DEC, etc.
i n st ruct ions without the overhead of sav i n g the e nt i re mach ine state
on the stack.
Addressing Mode:
I n herent
A-73
I RQ
Interrupt Request (Hardware Interrupt)
I RQ
SP' - S P - 1 , (S P) - PCL
SP' - S P - 1 , (S P) - PCH
SP' - SP - 1 , (S P) - USL
SP' - S P - 1 , (S P) - USH
SP' - SP - 1 , (S P) - IYL
SP' - S P - 1 , (S P) - IYH
SP' - SP - 1 , (S P) - IXL
SP' - S P - 1 , (S P) - IXH
SP' - SP - 1 , (S P) - DPR
SP' - S P - 1 , (S P) - ACCB
SP' - SP - 1 , (SP) - ACCA
Set E (ent ire state saved)
SP' - SP - 1 , (SP) - CCR
Set I (mask further I RQ i nterru pts)
PC' - (FFF8):(F FF9)
Operation:
I FF I bit clear, then:
Condition Codes:
N ot affected .
Description:
If the I (i nterrupt req uest m ask) bit is clear, a low level on the I RQ i n ­
pu t causes this i nterru pt seq uence to occur at the end of the c urrent
i n struction. Control is ret u rned to the i nterru pted prog ram using a
RTI (ret urn from i nterrupt) i n st ruction . A FI RQ (fast i nterrupt req uest)
may i nterru pt a normal I RQ (interrupt req uest) routi n e and be
recogn ized anyt i me after the interru pt vector is take n.
Addressing Mode:
I n herent
A-74
NMI
Non·M askable Interrupt (Hardware Interrupt)
NMI
Ope ration:
SP' - SP - 1 , (S P) - PCl
S P' - S P - 1 , (S P) - PCH
S P' - S P - 1 , (SP) - USl
S P' - S P - 1 , (S P) - USH
SP' - SP - 1 , (SP) - IYl
S P' - S P - 1 , (S P) - IYH
S P' - SP - 1 , (SP) - IXl
S P' - S P - 1 , (S P) - IXH
S P' - S P - 1 , (S P) - OPR
S P' - S P - 1 , (SP) - ACCB
S P' - SP - 1 , (SP) - ACCA
Set E (enti re state save)
S P' - SP - 1 , (SP) - CCR
Set I, F (mask i nterrupts)
PC' - (FF FC):(FFFO)
Condition Codes:
N ot affected .
Description:
A negat ive edge on the N M I (non-maskable i nterru pt) i n put causes
al l of the processor's reg isters (except the hardware stack poi nter)
to be pushed onto the hardware stack, start i n g at the end of the cur­
rent i n struction. Program control is transferred t h rough the N M I vec­
tor. Successive negat ive edges on the N M I i n put wi l l cause s u c­
cessive N M I operations. Non-maskable i nterru pt operat ion can be
i nternal ly blocked by a RESET operation and any non-maskabl e i n ­
terrupt that occ urs wi l l b e latched . If t h i s happens, the non­
maskable i nterru pt operat ion w i l l occu r after the f i rst load i nto the
stack poi nter (lOS; TFR r,s; EXG r,s; etc.) after R ESET.
Add ressing Mode:
I nherent
A- 75
R ESTART
Restart (H ardware Interrupt)
R ESTART
Operation:
CCR' - X1 X1 XXXX
D PR' - 00 1 6
PC' - ( F F F E):(F F F F)
Condition Codes:
Not affected .
Description:
The processor is i n itial ized (req u i red after power-on) to start pro­
g ram exec ution. The start i ng add ress is fetched from the restart vec­
tor.
Addressing Mode:
Extended I n d i rect
A-76
APPEN DIX B
ASSIST09 MON ITOR P ROG RAM
B.1 G ENERAL D ESCR I PTION
The M6809 i s a h igh-performance microprocessor which supports modern programm i ng
techn iques such as position-i ndependent, reentrancy, and mod u l ar programming. For a
software mon itor to take advantage of such capabi l ities demands a more refi ned and
sophist icated user i nterface than that provided by previous mon itors. ASSIST09 is a
monitor which su pports the advanced features that the M 6809 makes possi ble.
ASSI ST09 feat ures i n c l ude the fol lowing:
•
Coded i n a position (address) i ndependent man ner. Wi l l execute anywhere i n the
64K address space.
•
M u ltiple means avai l able for instal l i n g user modificat ions and extensions.
•
F u l l com p l ement of commands for prog ram development i nc l uding breakpoi nt and
trace.
•
Sop h i st icated mon itor cal l s for completely address-i ndependent user prog ram ser­
vices.
•
RAM work area is located relative to the ASSIST09 ROM , not at a fixed address as
with other monitors.
•
Eas i l y adapted to real-time envi ronments.
•
Hooks for user command tables, 110 handlers, and default s pecifications.
•
A com plete user i nterface with services normal ly only seen in f u l l disk operat i n g
systems .
The concise i n st ruction set o f the M6809 al lows al l o f these functions and more t o be
contai ned in only 2048 bytes.
The ASSIST09 monitor is easi ly adapted to run u nder control of a real-time operat ing
system . A s pecial f unction i s avai lable which a l l ows vol untary t i me-slicing, as wel l a s
forced time-sl icing u pon t h e use of several service rout ines b y a user program .
B.2 I M PLEM E NTATION REQ U I REM ENTS
Since ASSIST09 was coded i n an add ress-i ndependent manner, it wi l l properly execute
anywhere in the 64K add ress space of the M 6809. However, an assu m ption must be m ade
reg ard i n g the location of a work area needed to hold miscel l aneous variables and the
default stack location. Th i s work area is cal l ed the page work area and it is addressed
wit h i n ASSIST09 by use of the di rect page reg ister. It is located rel at ive to the start of the
B-1
ASSI ST09 ROM by an offset of - 1 900 hexadec i m a l . Assuming ASSI ST09 resides at the
top of the memory address space for d i rect contro l of the hardware i nterru pt vectors, the
memory map wo u l d appear as shown i n Fig u re B-1 .
FFFF
A S S I S T09
Base R O M
FSOO
A S S I S T09 at Top of
Memory Map
Extension ROM or Other Use
User
Extension R O M
FOOO
Un used 2K
( U n used)
ESOO
PTM / A C I A
EOOO
Work Pagel S tack
Default PTM and ACIA
Locations
Work Page and Default
Stack I DF F F and Down)
Figure B-1 . M emory Map
If F800 i s not the start of the mon itor RO M the add resses wou l d change, but the rel ative
locations would remain the same except for the prog rammable t i mer mod u l e (PTM) and
asynchronous com m u n i cat ions i nterface adapter (ACI A) default addresses which are fix­
ed .
The defau lt con sole i n put/output hand lers access an ACIA located at EOO8. For t race
commands, a PTM with default add ress EOOO is used to force an N M I so that s i n g l e in­
structions may be executed . These default add resses may eas i ly be changed using one
of several methods. The conso l e I/O handlers m ay also be rep laced by user rout i nes. The
PTM is i n it ial ized d uring the M O N ITR service cal l (see Paragraph B.9 SERVICES) to f i reup
the monitor un less its default address has been changed to zero, i n which case no PTM
references w i l l occu r.
B.3 INTE R R U PT CONTROL
U pon reset , a vector table i s created which contai ns, among other things, default i nter­
rupt vector handler appendage add resses. These routi nes may easily be rep l aced by user
appendages with the vector swap service descri bed later. The defau lt act ions taken by
the appendages are as fol lows:
RESET - B u i l d the ASSI ST09 vector tabl e and set up mon itor defaults, then i nvoke
the mon itor start u p rout ine.
SWI - Req uest a service from ASS IST09.
FI RQ - An i mmed i ate RTI is done.
SWI2, SWI3, I RQ, Reserved , N M I - Force a breakpo i nt and enter the command
processor.
B-2
The use of I RQ is recom mended as an abort fu nct ion d u ring prog ram debug g i ng ses­
sions, as breakpoi nts and ot her ASSI ST09 defaults are rei n itial ized u pon RESET. On ly the
primary software i nterru pt i n struct ion (SWI) is used , not the SWI2 or SWI3. Th i s avoids
page fau l t problems which wou l d otherw i se occur with a memory management u n it as
the SWI2 and SWI3 i n st ruct ions do not d i sable i nterru pts.
Cou nter n u m ber one of the PTM is used to cause an N M I i nterru pt for the trace and break­
pOint com m ands. At R ES ET the control reg i ster for t i mer one is i n itial ized for trac i n g pur­
poses. If no trac i n g or breakpointing i s done then the ent i re PTM is available to the user.
Otherwise, only counters two and th ree are avai lable. Although control reg ister two m ust
be used to i n itial ize control reg ister one, ASS I ST09 ret urns contro l reg ister two to the
same val ue i t has after a R ES ET occurs. Therefore, the on ly condition i m posed on a u ser
program is that if the "operate/preset " b it in contro l reg i ster one m ust be tu rned on , $A7
sho u l d be stored, $A6 shou l d be stored if it m ust be t u rned off.
B.4 I NITIALIZAT I O N
During ASSI ST09 exec ution , a vector tabl e i s used to add ress certain service routi nes
and default val ues. Th is table is generated to provide easily changed control information
for user mod ifications. The f i rst byte of t he ASSI ST09 ROM contai ns the start of a
subrout i n e which i n it i al izes the vector table along with sett i ng u p certai n default val u es
before ret u rn i n g to the cal ler.
If the ASSI ST09 RESET vector receives contro l , it does three t h i ngs:
1 . Ass i g n s a default stack i n the work space,
2. Cal ls the aforement ioned su brout ine to i n itial ize the vector table, and
3. Fires up the ASSI ST09 mon itor proper w ith a M O N ITR SWI service req uest .
However, a u ser rout i n e can perform the same fu nctions with a bon us. After cal l i n g the
vector i nt i t i al izat ion subroutine, it may exa m i n e or alter any of the vector table val ues
before start i n g normal ASSIST09 processi ng . Th us, a user routi n e may "bootstrap"
ASSIST09 and alter the defau lt standard val ues.
Another method of i n sert i n g user mod ifications i s to have a user routine reside at an ex­
tension RO M l ocation 2K bel ow the start of the ASSI ST09 ROM . The vector table i n­
itial izat ion routine ment ioned above, looks for a " B RA * " f l ag ($20F E) at this add ress, and
if found cal ls the location fol lowing the flag as a subrout i n e with the U reg i ster poi nting
to the vector table. S i n ce this is done after vector table i n itial ization , any or al l defau lts
may be altered at t h i s t i me. A big advantage to u s i n g t h i s method i s that the mod ifica­
t ions are "automat i c" i n that upon a RESET con�ition t h e changes are made without
overt act ion req u i red such as the execution of a memory change command.
N o special stack is u sed during ASSI ST09 processi n g . Th i s means that the stack pOi nter
m u st be val id at al l i nterru ptable t i mes and sho u l d contai n enough room for the stacki ng
of at least 21 bytes of i nformat ion . The stack i n use d u ring the i n itial M O N ITR service cal l
to start u p ASS I ST09 processing becomes the "official " stack. If any l ater stack val idity
checks occu r, t h i s same stack w i l l be re-based before enteri ng the command han d l er.
B-3
ASS IST09 u ses a work area which is addressed at an offset from the start of the
ASSI ST09 ROM . The offset val ue is - 1 900 hexadecimal . Th is poi nts to the base page us·
ed d u ri n g mon itor execution and contains the vector table as wel l as the start of the
default stack. If the default stack is used and it excee d s 81 bytes i n size, then cont ig uous
RAM m u st exist below this base work page for proper extension of the stack.
85. I NP UT/O UTPUT CONT RO L
O utput generated by use o f t h e ASSIST09 services may b e halted b y pressing a n y key,
causing a ' FREEZE' mode to be entered . The next keyboard entry w i l l release this condi·
tion al low i n g normal output to cont i n ue. Com m ands which generate l arge amou nts of
output m ay be aborted by entering CAN CEL (CONTRO L·X). User programs m ay also
mon itor for CAN CEL along with the ' F REEZE' condition even when not perform i n g con·
sole I/O (PAUSE service).
8.6 CO M M AND FORMAT
There are th ree possible formats for a com m and:
< Com m and > CR
< Command > < Expression 1 > CR
< Comm and > < Expression 1 > < Expression2> CR
The space c h aracter is used as the del i m iter between the command and al l arg u ments.
Two spec ial q u ick commands need no carriage return, "." and "/" . To re-enter a com mand
once a m i stake is made, type the CANCEL (CONTROL·X) key.
Each "expression" above consists of one or more val ues separated by an operator.
Val ues can be hex stri ngs, the l etters " P" , " M " , and "W", or the result of a function. Each
hexadeci m a l st ring is converted i nternally to a 1 6·bit binary n u m ber. The l etter " P"
stands for the current prog ram counter, " M " for the last memory examine/change ad·
d ress, and "W" for the w i ndow value. The w i ndow val ue is set by using the W I N DOW
command.
One function exists and it i s the I N DI RECT fu nction. The character " @ " fol lowi n g a val ue
rep laces that val ue with the 1 6·bit n u m be r o btai ned by using that val ue as an address.
Two operators are al l owed, " + " and " - " which cause add ition and subtract ion. Val ues
are operated on in a left·to·rig ht order.
Exam ples:
480 - h exadecimal 480
W + 3 - val ue of wi ndow p l u s three
P·200 - cu rrent program cou nter m i n u s 200 hexadec i mal
M - W - cu rrent memory pointer m i n u s w i ndow val ue
1 00 @ - value of word addressed by the two bytes at 1 00 hexadeci m al
P + 1 @ - val ue add ressed by the word located one byte u p from the cu rrent prog ram
counter
8·4
B.7 COMMAND LIST
Table B·1 l i sts the commands avai l able i n the ASSI ST09 mon itor.
Table B·1 . Command List
Command Name
Description
Command Entry
B reakpoint
Set,clear,display, or delete breakpoints
B
Call
Cal l program as subroutine
C
D
D isplay
Display memory block in hex and A S C I I
Encode
Return indexed postbyte value
E
Go
Start or resume program execution
G
Load
Load memory from tape
Memory
Examine or alter memory
Memory change or examine last referenced
Memory change or examine
N ull
Set new character and new line padding
N
Offset
Compute branch offsets
0
L
M
/
hex/
P u nch
Punch memory on tape
P
Registers
Display or alter registers
R
Stlevel
Alter stack trace level value
S
Trace
Trace number of instructions
Trace one instruction
T
Verify
Verify tape to memory load
V
Window
Set a window value
W
B.8 CO M M ANDS
Each of the com mands are explai ned on the fo l lowi ng pages. They are arrang ed i n
al phabetical order b y t h e command name used i n t h e command l ist . The command name
appears at each marg i n and i n S l i g htly larger type for easy reference.
B·5
•
B REAKPO I NT
Format:
B R EAKPO I NT
Breakpoi nt
Breakpoint Breakpoint < Add ress >
Breakpoint - < Address >
Operation: Set or change the breakpoint table. The f i rst format d i s p l ays a l l breakpoi nts.
The second c lears the breakpoi nt table. The t h i rd enters an address i nto the
table. The fou rth deletes an address from the table. At reset, all breakpo i nts
are deleted. Only i n structions in RAM m ay be breakpoi nted .
CALL
Format:
CALL
Cal l
Cal l < Address >
Operation: Cal l and execute a user routine as a subrout i ne. The c urrent p rogram cou nter
w i l l be used u n l ess the add ress is specified. The user routi n e shou l d eventual­
ly term inate with a " RTS" i nstruct ion. When this occurs, a breakpoi nt w i l l en­
sue and the prog ram counter wi l l point i nto the mon itor.
B-6
D I S P LAY
DISP LAY
Format:
Display < From >
Display < From > < Length >
Display < From > < To >
Operation: Display contents of memory i n hexadeci mal and ASC I I characters. The se­
cond arg ument, when entered, is taken to be a length if it is less than the f i rst,
otherwise it is the ending address. A default length of 1 6 decimal is assu med
for the fi rst format. The add resses are adj usted to i n c l ude all bytes with i n the
s u rround i n g mod u lo 16 address byte bou ndary. The CANCEL (CO NTROL-X)
key may be entered to abort the d isplay. Care m ust be exercised when the l ast
1 5 bytes of memory are to be d isplayed . The < Length > o pt ion shou ld always
be used in t h i s case to assure proper term i nat ion: D FFEO 40
Exam ples:
D
M
D
EOOO
10
- Display 1 6 bytes s urrou nding the l ast memory
location exam i ned.
FOOO - Display memory from EOOO to FOOO hex.
E N CO D E
EN CO D E
Format:
Encode < I ndexed operand >
Operation: The encode command w i l l return the i ndex i n g i nstruct ion mode postbyte
val ue from the entered assembler-l i ke syntax operand. This is useful when
hand cod i n g i n struct ions. The letter " H " i s used.to i n d icate the n u m ber of hex
d i g its n eeded i n the expression as shown i n the fol lowi n g exam ples:
E ,V
- Ret urn zero offset to V reg i ster postbyte.
E [H H H H , PCR] - Ret urn two byte peR offset using i n d i rection.
E [,S + + 1
- Ret urn autoi ncrement S by two i n d i rect.
E H ,X
- Return 5-bit offset from X.
Note that one " H " specifies a 5-bit offset , and that the result g iven w i l l h ave
zeros in the offset val ue position. Th is comand does not detect all i ncorrect ly
s pec ified syntax or i l l egal i ndex i n g modes.
8-7
GO
GO
Format:
Go
Go < Add ress >
Operation: Execute start i n g from the add ress g iven . The fi rst format w i l l cont i n ue from
the current program cou nter sett i n g . If it is a breakpo i nt no break w i l l be
taken . This al l ows cont i n u ation from a breakpoint. The secon d format wi l l
breakpoint i f the add ress specified i s i n the breakpoi nt l i st.
LOAD
LOAD
Format:
Load
Load < Offset >
Operation: Load a tape f i l e created using the 51 -59 format. The offset option, i f u sed , i s
added to t h e address on t h e tape t o specify t h e act ual load address. Al l off­
sets are positive , but wrap around memory mod u lo 64K. Depend ing on the
eq u i p m ent i nvolved , after the l oad i s complete a few spurious c haracters m ay
sti l l be sent by the i n put device and i nterpreted as com mand characters. If
t h i s happens, a CANCEL (CONTRO L-X) shoul d be entered to cause such
characters to be ig nored . If the load was not successfu l a " 7 " is d isplayed .
8-8
M EM O RY
M EM O RY
Format:
M EM O RY < Add ress > /
< Ad d ress > /
I
Operation: I n it i ate the memory exami ne/change fu nct ion. The second format w i l l not ac­
cept an expression for the add ress, only a hex stri ng. The t h i rd format
defau lts to the address d isplayed during the l ast memory change/exam i ne
fu nction. (The same val u e is obtai ned i n expressions by use of the letter " M ".)
After act ivation, the fol lowing actions may be taken unt i l a carriage ret u rn is
entered:
< Exp r >
Replaces the byte w i t h t h e specified val ue . The value m ay
be an expression.
S PACE
Go to next address and print the byte val ue.
(Comma) Go to next add ress without printing the byte
val ue.
LF
(Li ne feed) Go to next address and print it along with the
byte value on the next l i ne.
(Circumflex or Up arrow) Go the previous address and pri nt
it along with the byte val ue on the next l i ne.
/
Print the current add ress with the byte val u e on the next
l i ne.
CR
(Carriage retu rn) Term inate the com mand.
' < Text > '
Replace succeed i n g bytes with ASCI I characters u nt i l the
second apostrophe i s entered.
I f a change attem pt fai l s (i .e., the locat ion is not vali d RAM) then a q uestion
mark wi l l appear and the next location d i splayed .
8-9
N U LL
N U LL
Format:
N u l l < Specification >
Operation: Set the new l i ne and character pad d i ng count val ues. The expression value i s
treated a s two val ues. The u p per two hex represent t h e character pad count,
and the lower two the new l i ne pad count (triggered by a carriage retu rn). An
expression of less than three hex d i g its wi l l set the character pad count to
zero. The val ues m ust range from zero to 7F hexadec i mal (1 27 deci m al).
Exam ple:
N
N
3
- Set the character cou nt to zero and new l i ne count
to t h ree.
207 - Set character padding cou nt to two and new l i ne
cou nt to seven.
Sett ings for TI Silent 700 term i na l s are:
Baud
Setting
1 00
300
1 200
2400
0
4
31 7
72F
O F FS ET
Format:
O F FS ET
Offset < Offset add r > < To i n st ruct ion >
Operation: Print the one and two byte offsets needed to perform a branch from the f i rst
expression to the i n struction. Th us, offsets for branches as wel l as i ndexed
mode i n struct ions wh ich use offsets may be obtained. If only a fou r byte
val ue is pri nted , then a short branch count can not be done between th.e two
add resses.
Example:
o
P + 2 AOOO - Com pute offsets needed from the c u rrent prog ram cou nter plus two to AOOO.
8-1 0
PUNCH
Format:
PUNCH
Punch < From > < To >
Operation: Punch or record formatted binary object tape i n 51 -59 (M I KBUG ) form at.
REG IST E R
R EG IST E R
Format:
Reg ister
Operation: Print the reg ister set and prom pt for a change. At each prom pt the fol lowi ng
m ay be entered .
SPACE
Ski p to the next reg ister pro mpt
< Expr > S PACE Repl ace with the specified val ue and pro m pt for the next
reg i ster.
< Expr > CR
(carriage retu rn) Replace with the specified val ue and ter­
m i n ate the command.
CR
Term i n ate the com mand.
M I KBUG i s a trademark o f Motorola I nc.
B-1 1
ST LEVEL
Format:
STL EVEL
St l evel
St l evel < Ad dress >
Operation: Set the stack trace l evel for i n h i biting tracing information . As long as the
stack is at or above the stack level address, the trace display wi l l cont i n ue.
H owever, when lower than the address it is i n h i bited . This a l l ows trac i n g of a
routi ne without including al l subrout i ne and lower level cal l s i n the trace i n­
formation. N ote that tracing t h rough a ASSIST09 "SW I " service req uest m ay
also temporarily supress t race output as explai ned i n the descri pt ion of the
t race com mand. The fi rst form at sets the stack trace level to the cu rrent p ro­
g ram stack value.
T RAC E
Format:
T RAC E
Trace < Cou nt >
. (period)
Operation: Trace the specified n u m ber of i nstruct ions. At each trace, the opcode j u st ex­
ecuted w i l l be shown along with the reg ister set. The program counter i n the
reg i ster d i s p l ay pOi nts to the N EXT i n struct ion to be executed. A CAN C E L
(CONTRO L-X) w i l l premat u re l y h a l t t racing. The second format (period) w i l l
cause a s i n g l e trace t o occu r. Breakpoi nts have n o effect d u ring t h e trace.
Selected port ions of a trace m ay be d i sabled using the STLEVEL command.
I nstructions i n ROM and RAM may be traced, whereas breakpoints m ay be
done only in RAM . When tracing t h rough a ASSI ST09 service request, the
t race d isplay wi l l be supressed start i n g two i n structions i nto the mon itor u nt i l
shortly before contro l is retu rned to t h e user program. This is done t o avo id a n
i nord i nate amount o f d isplay i ng because ASSIST09, at t i m es, performs a
sizeable amount of processi n g to provide the req uested services.
B-1 2
V E RI FY
Format:
VERI FY
Verify
Verify < Offset >
Operation: Verify or com pare the contents of memory to the tape f i le. Th is com mand h as
the same format and operation as a LOAD command except the f i l e i s com­
pared to memory. If the verify fai ls for any reason a "?" is d isplayed .
WI N DOW
Format:
WI N DOW
Wi ndow < Value >
Operation: Set t h e w i ndow t o a val ue. Thi s val ue may b e referred to when entering ex­
pressions by use of the l etter "W". The wi ndow may be set to any 1 6-bit val ue.
8-1 3
B.9 SERVICES
The fol lowi ng descri bes services provided by the ASSIST09 mon itor. These servi ces are
i n vo ked by u s i n g the "SWI" instruction fol lowed by a one byte fu nct ion code. Al l services
are designed to al low complete address i ndependence both in i nvocation and operation.
U n l ess spec ified otherwise, a l l reg isters are transparent over the "SW I " cal l . I n the
fol lowing descriptions, the terms " i n put hand ler" and "output hand ler" are used to refer
to appendage rout i nes which may be repl aced by the user. The default rout i nes perform
standard 1/0 through an ACIA for console operations to a term inal . The ASC I I CAN C E L
c o d e can b e entered on most term i nals b y depressing t h e CONTROL and X keys
s i m u ltaneously. A l ist of services is g iven in Table 8-2.
Table B·2. Services
Service
Obtain input character
Description
Entry
Code
INCHP
0
Obtain the input character in reg ister A from the input handler
O utput a character
O UTCH
1
Send the character in the re g ister A to the output handler
Send stri n g
PDATA1
2
Send a strin g of characters to the output handler
Send new line and strin g
P DATA
3
Send a carria g e return . line feed . and strin g of characters to the
output handler
Convert byte to hex
OUT2 H S
4
Display the byte poi nted to by the X reg ister in hex
Convert word to hex
OUT4H S
5
Display the word pointed to by the X reg ister in hex
Output to next line
P C R LF
6
Send a carria g e return and line feed to the output handler
Send space
S PACE
7
Send a blank to the output handler
Fireup A S S I S T09
MONITR
8
Enter the A S S I ST09 monitor
Vector swap
VCTRSW
9
Examine or exchan g e a vector table entry
U ser breakpoint
B R K PT
10
Display reg isters a n d enter the command handler
Prog ram b reak and check
PAU S E
11
Stop p rocessin g and check for a freeze or cancel condition
8-1 4
B R KPT
User Breakpoint
B R KPT
Code:
10
Arguments:
N one
Result:
A d i sabled breakpoint is taken. The reg isters are d i s p l ayed and the com­
m and handler of ASSI ST09 is entered .
Description: Establ i shes u ser breakpoints. Both SWI2 and SWI3 default appendages
cause a breakpoint as wel l , but do not set the I and F m ask bits. However,
s i nce they may both be repl aced by user routi nes the breakpoi nt service
always ensures breakpoint avai labi l ity. These user breakpoi nts h ave
noth ing to do with system breakpoi nts which are hand led differently by the
ASSIST09 mon itor.
Example:
B R KPT
I NCH P
EaU
10
I N PUT COD E FOR B RKPT
SWI
FCB
BRKPT
REaU EST SERV ICE
FU NCTION CODE BYTE
Obtain Input Character
I NCH P
Code:
0
Arguments:
None
Result:
Reg ister A contains a character obtai ned from the i n put handler.
Description: Control is not ret urned unt i l a val i d i n put character is received f ro m the in­
p ut hand ler. The i n put character wil l have its parity bit (bit 7) stri pped and
forced to a zero. Al l N U LL ($00) and RU BOUT ($ 7 F) characters are i g nored
and not returned to the cal ler. The ECH O flag, which m ay be changed by
the vector SWAP service, determ i nes whether or not the i n put character is
echoed to the output hand ler (f u l l d uplex operation). The defau lt at reset is
to echo i n put. When a carriage retu rn ($00) i s received , l i ne feed ($AO) is
automat i cally sent back to the output hand ler.
Example:
I N CH N P
SWI
FCB
Eau o
I N PUT COD E F O R I N CH P
I NCHNP
PERFORM SERV I C E CALL
FU NCTION FOR I N CH N P
A R EG I STER N OW CO NTAI N S N EXT CHARACTER
B-1 5
MO N IT R
Startup ASSISl09
M O N IT R
Code:
8
Arguments:
S - Stack to become the "official " stack
D P - Di rect page defau lt for executed user programs
A = 0 Cal l i nput and output conso l e i n itial ization handlers and g ive the
"ASSI ST09" start u p message
A##O Go d i rectly to the com m and handler
Result:
ASSIST09 is entered and the com and handler g iven control
Description: The pu rpose for this function is to e nter ASSI ST09, either after a system
reset, or when a user program des i res to term inate. Contro l is not ret urned
u n l ess a "GO" or "CALL" com m and is done without altering the p rogram
counter. ASSI ST09 runs on the passed stack, and if a stack error i s
detected during user program exec ution this is t h e stack that is rebased .
The di rect page reg i ster val ue i n use remains the d efault for user program
execution.
The ASSIST09 restart vector routine uses this funct ion to start u p mon itor
processing after cal l i ng the vector build su brout ine as explai n ed in I N·
ITI ALIZATIO N .
I f i n dicated by the A reg ister, the i n put and output i n itial ization handlers
are cal l ed fol lowed by the send i n g of the string "ASSIST09" to the output
handler. The programm able t i mer (PTM) is i n itial ized, if its address i s not
zero, such that reg i ster 1 can be used for causing an N M I d uring t race com·
mands. The command handler is then entered to perform the com m and re·
qu est prompt.
Example:
M O N ITR
EQU
LOO P
CLRA
I N PUT CO D E FO R M O N ITR
8
*
TFR
LEAS
SWI
FCB
BRA
A, D P
STACK, PCR
M O N ITR
LOO P
B-1 6
PREPARE ZERO PAGE REG ISTER AN D
I N ITIALIZATIO N PARAM ETER
S ET DEFAU LT PAG E VALUE
S ETUP DEFAULT STACK VALU E
REQ U EST SERVICE
F U N CTION COD E BYTE
REENTER I F FALLOUT OCCU RS
O UTC H
Output a Character
Code:
1
Arguments:
Reg ister A contains the byte to transmit.
Result:
The character is sent to the output handler
O UTC H
The character is set as fol lows O N LY if a Ll N E FEED was the character to
transmit:
CC = 0 if normal output occu rred.
CC = 1 if CAN CEL was entered d u ring output.
Description: If a FREEZE Occu rs (any i n put character is received) then control i s not
retu rned to the user routi n e u nt i l the condition is released. The F REEZE
cond ition i s checked for only when a l i n efeed is being sent. Padd i n g n u l l
characters (SOO) may be sent fol lowi n g the outputted character depend i ng
on the cu rrent sett ing of the N U LLS command. For DLE (Data Link Escape),
character n u l l s are never sent. Otherwise, carriage retu rns (SOO) receive the
n ew l i ne cou nt of n u l ls, all other characters the character count of n u l ls.
Example:
OUTCH
EQU
1
I N PUT COD E FOR OUTC H
LDA
SWI
FCB
#'0
LOAD CHARACTER "0"
SEN D OUT WITH M O N ITOR COD E
SERVICE CO D E BYTE
O UT2H S
OUTCH
Convert Byte to Hex
O UT2H S
Code:
4
Arguments:
Reg ister X points to a byte to d i s p l ay i n hex.
Result:
The byte is converted to two hex d i g its and sent to the output handler
fol lowed by a blank.
Example:
OUT2HS
EQU 4
I N PUT COD E FOR OUT2HS
LEAX DATA, PCR
SWI
FCB OUT2HS
PO I NT TO ' DATA' TO DECODE
REQU EST S ERV ICE
SERVICE COD E BYTE
B-1 7
O UT4H S
Convert Word to Hex
O UT4H S
Code:
5
Arguments:
Reg ister X pOi nts to a word (two bytes) to d i splay i n hex.
Result:
The word i s converted to four hex d i g its and sent to the output handler
fol lowed by a blan k.
Example:
O UT4HS
PAU S E
EQU 5
I N PUT COD E FOR OUT4HS
LEAX DATA, PCR
SWI
FCB OUT4HS
LOAD ' DATA' ADDRESS TO DECODE
REQU EST ASSIST09 SERVICE
SERVICE COD E BYTE
Program Break and Check
Code:
11
Arguments:
None
Result:
CC = 0 For a normal return.
CC = 1 If a CAN C E L was entered during the i nterim .
PAUS E
Description: The PAUSE service should b e used whenever a s i g n ificant amount o f pro­
cessing i s done by a program without any external i nteraction (such as con­
sole 110). Another use of the PAUS E service is for the monitori ng of FREEZE
or CAN C E L requests from the i nput hand ler. Th i s al lows m ult i-taski n g
operat i n g systems t o receive control and possi bly re-d i spatch ot her pro­
g rams in a ti mesl i ce-l i ke fash ion. Testing for FREEZE and CAN CEL condi­
tions is performed before return. Return may be after other tasks h ave h ad
a chance to execute, or after a F R E EZE condition is l i fted . I n a one task
system , ret u rn is always i mmed i ate u n l ess a FREEZE occu rs.
B·1 8
PC R L F
Output t o N ext Line
PC R L F
Code:
6
Arguments:
None
Result:
A carriage retu rn and l i ne feed are sent to the output hand ler.
C = 1 if normal output occurred.
C = 1 i f CONTROL-X was entered d u ring output.
Description: If a FR E EZE occurs (any i nput character is received), then control is not
ret u rned to the user routi ne u nt i l the cond ition is released . The string is
com pletely sent regard less o f any FREEZE or CAN CEL events occ u rri n g .
Pad d i n g characters may b e sent a s descri bed under t h e OUTCH service.
Example:
PCRLF
P DATA
EQU
6
I N PUT CO D E PCRLF
SWI
FCB
PCRLF
REQ U EST SERVICE
SERVICE CO DE BYTE
Send New Line and String
P DATA
Code:
3
Arguments:
Reg i ster X poi nts to an output stri ng term i n ated with an ASC I I EOT ($04).
Result:
The string is sent to the output handler fol lowi ng a carriage retu rn and l i ne
feed .
CC = 0 if normal output occu rred.
CC = 1 if CONTRO L-X was entered d u ring output.
Description: The output string may contai n em bedded carriage ret urns and l i ne feeds
thus al low i n g several l i nes of d ata to be sent with one function cal l . If a
FR E EZE occurs (any i n put character is received), then control is not ret u rn­
ed to the user routine until the cond ition is released . The stri ng is com p l ete­
ly sent regard less of any FREEZE or CAN CEL events occurri ng. Pad d i n g
ch aracters may b e sent a s descri bed b y the OUTCH fu nction.
B-1 9
Send New Line and String
(Contin ued)
P DATA
Example:
P DATA
PDATA
EQU
3
MSGOUT
FCC
FCB
FCC
FCB
'TH IS IS A M U LTI PLE LI N E M ESSAG E:
$OA, $00
LI N E FEED, CARRIAG E RETU RN
'TH IS IS TH E S ECO N D LI N E.'
STR I N G TERM I N ATO R
$04
I N PUT CODE FO R PDATA
LEAX M SGOUT, PCR LOAD M ESSAG E ADDRESS
REQU EST A SERV I C E
SWI
F C B P DATA
SERVICE CODE BYTE
P DATA1
Send Stri ng
P DATA1
Code:
2
Arguments:
Reg i ster X poi nts to an output string term i n ated with an ASC I I EOT ($04).
Result:
The st ring i s sent to the output hand ler.
CC = 0 if normal output occ urred.
CC = 1 if CONTRO L-X was entered during out put .
Description: The output st ring m ay contai n e m bedded carriage returns and l i ne feeds
thus al lowi ng several l i nes of data to be sent with one function cal l . If a
FREEZE occu rs (any i n put character i s received), then control is not retu rn­
ed to the user routi n e unt i l the condition is released . The stri ng i s com p l ete­
ly sent regard less of any FREEZE or CAN CEL events occurri n g . Pad d i n g
characters may b e sent as described b y t h e OUTCH function.
Example:
I N PUT COD E FOR P DATA1
PDATA
EQU
2
MSG
FCC
FCB
'TH IS IS AN OUTPUT STR I N G '
STR I N G TERM I N ATO R
$04
LEAX M SG , PCR
SWI
FCB PDATA1
B-20
LOAD ' M SG ' STR I N G ADDRESS
REQU EST A SERV I C E
SERVICE COD E BYTE
SPAC E
Single Space O utp ut
Code:
7
Arguments:
N one
Result:
A space is sent to the output hand l er.
SPAC E
Descript ion: Padd ing characters may be sent as descri bed under the OUTCH service.
Example:
SPACE
EQU
SWI
FCB
I N PUT CO DE SPACE
REQU EST ASS IST09 SERV ICE
SERVICE COD E BYTE
7
SPACE
VCT RSW
Vector Swap
Code:
9
Arguments:
Reg ister A contai ns the vector swap i n put code.
Reg i ster X contains zero or a rep l acement val ue.
Result:
Reg ister X contai ns the previous val ue for the vector.
VCT RSW
Description: The vector swap service exam i nes/alters a word entry in the ASSI ST09 vec­
tor table. Th is tabl e contai n s pOi nters and default val ues used d u ri n g
mon itor processing. The entry is repl aced w i t h the value contained i n the X
reg i ster un less it i s zero. The codes ava i l able are l i sted i n Tab l e B·3.
Example:
VCTRSW
. I RQ
EQU
EQU
I N PUT CODE VCTRSW
I RQ APPEN DAG E SWAP FU N CT I O N
CO DE
9
12
LEAX MYIRQ H , PC R LOAD N EW I RQ HAN DLER A D D R ESS
LOAD SU BCOD E FOR V ECTOR SWAP
LOA I. I RQ
SWI
R EQU EST SERVICE
FCB VCTRSW
S ERVICE CO DE BYTE
X N OW HAS TH E PREVIOUS APPEN DAG E ADDRESS
B·21
B.1 0 V ECTO R SWAP SERV I C E
The vector swap service al lows u ser modifications of the vector table to be easily i nstal l­
ed. Each vector hand ler, i n c l u d i n g the one for SWI , perform s a val i d ity check on the stack
before any other processi n g . If the stack is not pOinting to val i d RAM , it is reset to the in­
itial val ue passed to the M O N ITR request which f i red-up ASSIST09 after RESET. Al so, the
cu rrent reg i ster set i s pri nted fol low ing a "?" (q uestion m ark) and then the command
hand l er is entered . A l i st of each entry i n the vector tabl e i s g iven in Table 8-3.
Table B·3. Vector Table Entries
Entry
. AVTB L
Code
Description
0
Returns address of vector table
. C M D Ll
2
Primary command list
. R SVD
4
Reserved M C6809 interru pt vector a ppendage
. SWI3
6
Software interrupt 3 interrupt vector appendage
. SWI2
8
Software interrupt 2 interrupt vector appendage
. FI R O
10
Fast interrupt request vector appendage
. I RO
12
Interrupt request vector appendage
. SWI
14
Software interrupt vector appendage
Non-maskable interrupt vector appendage
.NMI
16
. R ES ET
18
Reset interrupt vector a ppendage
. CION
20
I nput console intiialization routine
. C I DTA
22
I nput data byte from console routine
. CIOFF
24
I nput console shutdown routine
. COON
26
Output console initialization routine
. CO DTA
28
Output/ data byte to console routine
. COOFF
30
Output console shutdown routine
. H S DTA
32
High speed display handler routine
. B SON
34
Punch/ load initialization routine
. B S DTA
36
Punch / l oad handler routine
. B SOFF
38
Punch / l oad shutdown routine
. PAU S E
40
Processing pause routine
. C M D L2
44
S econdary command list
. ACIA
46
Address of ACIA
. PAD
48
Character and new line pad counts
. ECHO
50
Echo flag
. PTM
52
Programmable timer module address
The follow i n g pages describe the p urpose of each entry and the req u i rements which
m u st be met for a user replaceable val ue or routi n e to be successf u l ly substituted .
8-22
.ACIA
Code:
ACIA Address
.ACIA
46
Description: This entry contains the add ress of the ACIA used by the defau lt console in­
put and output device handlers. Standard ASSI ST09 i n itial ization sets this
val ue to hexadec imal E008. If this m ust be altered , then it m ust be done
before the M O N ITR start u p service i s i nvoked , si nce that service cal l s the
.COO N and .CO I N i nput and output device i n itial ization routi nes which i n­
itial ize the ACIA pOi nted to by this vector slot.
.AVT B L
Code:
Return Address of Vector Table
.AVT B L
0
Description: The add ress of the vector table is ret u rned with this code. Th is al lows m ass
changes to the table without i n d ividual cal l s to the vector swap service.
The code val ues are i dentical to the offsets i n the vector table. Th is entry
shou l d n ever be changed , only exam i ned.
8-23
. BS OTA
Code:
P unch/Load H andler Routine
. BS OTA
36
Description: Th i s entry contains the address of a routine which performs p u n c h , load ,
a n d verify operat ions. The . BSON routine is always executed before the
rout i n e is g iven contro l . Th is routine is g iven the same parameter l i st
documented for . BSO N . The default hand ler uses the .CO OTA ro ut i n e to
punch or the .CI OTA rout ine to read data i n S1 /S9 (M I KBUG) format. The
function code byte must be exami ned to determ ine the type req uest bei n g
hand led .
A ret u rn code m ust be given which reflects the f inal processing d i s position :
Z=
or
1 Successfu l com plet ion
Z=0
Unsuccessful com plet ion .
The . BSOFF rout i n e w i l l be cal l ed after this rout ine i s completed .
. BSO F F
Code:
Punch/Load Sh utdown Routine
. BSO F F
38
Description: This entry points to a su broutine which i s des i g n ated to term i n ate d evice
processing for the punch, load , and verify handler . BS OTA. The stack con­
tains a parameter l i st as documented for the . BSO N entry. The d efault
ASSIST09 routine issues OC4 ($1 4 or stop) and OC3 ($1 3 or x-off) fol lowed
by a one second delay to g ive the reader/punch t i m e to stop. Also, an i nter­
nally used fl ag by the I N CH P service rout ine is c leared to reverse the ef­
fect caused by its sett ing in the . BSON handler. See that descri ption for an
exp l anation of the proper use of this f l ag .
B-24
. BSO N
Code:
Punch/Load Initialization Routine
. BSO N
34
Description: T h i s entry poi nts to a su brout ine with the assig ned task of turning on the
device used for punch, load, and verify processi n g . The stack contai ns a
parameter l i st descri bing which funct ion is req uested. The defau lt rout i ne
sends an ASC I I "reader on" or "punch on" code of DC1 ($1 1 ) or DC2 ($1 2)
respectively to the output handler ( .CODTA) . A flag is a lso set which
d i sables test for FREEZE conditions d uri ng I N CH N P processi n g . Th is is
done so characters are not lost by be i n g i nterpreted as FREEZE mode in­
d i c ators. If a user replacement rout i n e a lso uses the I N CH N P service, then
it a l so should set this same byte non-zero and clear it i n the . BSO F F
routi ne. The ASSIST09 source l i sting should b e consu lted for t h e location
of this byte.
The stack is setup as fol l ows:
S + 6 = Code byte, VERI FY ( - 1 ), PU NCH (0) , LOAD (1 )
S + 4 = Start address for punch o n ly
S + 2 = End address for punch, or offset for READ/LOAD
S + 0 = Return address
.CI OTA
Code:
Input Data Byte from Console Routine
.CI OTA
22
Description: This entry determ i nes the console i n put handler appendage. The respon­
s i b i l ity of this routine i s to furnish the req uested next i n put character in the
A reg ister, if avai lable, and ret urn with a cond ition code. The I N CH P ser­
vice routine cal l s this appendage to supply the next ch aracter. Also, a
" F R E EZE" mode routine cal ls at various ti mes to test for a FREEZE condi­
tion or determ ine if the CAN CEL key has been entered . Processi n g for t h i s
appendage m ust abide by t h e follow i n g conventions:
Input:
PC - ASSIST09 work page
S- Return add ress
C = 0, A = i n put character
Output:
C = 1 if no i n put character is yet avai l able
Vol atile Registers: U , B
The hand ler shou ld always pass contro l back i m med i ately even if no
character i s yet available. Th is enables other tasks to do product ive work
w h i l e i n put is unavai lable. The defau lt rout ine reads an ACI A as explai ned
in Parag raph B.2 Implementation Req u i rements.
B-25
.CI O F F
Code:
Input Console Shutdown Routine
.CIO FF
24
Description: Th is entry points to a rout i n e which is cal led to term i nate i n put processing.
It is not cal l ed by ASS IST09 at any time, but is incl uded for consistency.
The defau lt routine merely does an " RTS". The environment is as fol l ows:
Input:
Output:
Volatile Registers:
.CI O N
Code:
None
I n put device term i nated
None
Input Console I nitialization Routine
.CI O N
20
Description: Th i s entry i s cal led to i n itiate the in put device. It is cal led once d u ring the
M O N ITR service which i n itial izes the monitor so the . command processor
m ay obtain commands to p rocess. The defau lt hand ler resets the ACIA
used for standard i nput and output and sets up the fol lowing default condi·
tions: 8-bit word length, no parity checki ng, 2 stop bits, divide·by·1 6 counter
ratio. The effect of an 8·bit word with no parity checking is to accept 7·bit
ASCI I and i g nore the parity bit.
Input:
Output:
Volatile Registers:
.ACIA Memory address of the ACIA
The output device is i n itial ized
A, X
8·26
.CM D L 1
Code:
Primary Comm a nd List
.C M D L 1
2
Description: User suppl ied com mand tables m ay either subst itute or re place the
ASSI ST09 standard tables. The co mmand hand ler scans two l i sts, the
primary table f i rst fo l lowed by the secondary table. The primary table is
poi nted to by this entry and contains, as a defau lt, the ASSIST09 com m and
table. The secondary table defaults to a n u l l l i st . A user may insert their own
table i nto either position. If a user l i st is i nstal led i n the secondary table
position, then the ASSI ST09 l i st wi l l be searched f i rst . The default
ASS I ST09 l i st contains all one character com m and names. Th us, a user
com mand " PRI NT" would be matched if the l etters " PR" are typed , but not
j ust a " P" si nce the system command l ist wou l d match first . A user m ay
rep l ace the primary system l i st if des i red . A command is chosen on a f i rst
match basis com pari ng only the character(s) entered . Th is means that two
or more commands may have the same i n itial characters and that if only
that much i s entered then the fi rst one i n the l i st(s) i s chosen.
Each entry i n the users com mand l i st m ust have the fo l l owing form at :
+0
FCB
+1
FCC
+N
FOB
L
Where " L" is the s ize of the entry i n ­
c l ud i n g t h i s byte
' < stri ng > ' Where " < stri ng > " is the com m and
name
EP - *
Where " EP" represents the sym bo l de­
f i n i ng the start of the command rou­
t i ne
The f i rst byte is an entry length byte and is always three more than the
lengt h of the command stri ng (one for the length itself plus two for the
routi ne offset). The command st ri ng m ust contai n only ASC I I al phan u meric
characters, no spec ial characters. An offset to the start of the com mand
routine i s used i n stead of an absol ute add ress so that position­
i ndependent prog rams may contain command tables. The end of the com­
mand table is a one byte flag . A - 1 ($F F) spec ifies that the secondary table
i s to be searched , or a -2 ($FE) that command l i st search ing is to be ter­
m i n ated. The table represented as the secondary command l i st m u st end
with - 2. The f i rst l i st m ust end with a - 1 if both l i sts are to be searched , or
a - 2 i f o n ly one l i st i s to be used .
A com mand rout ine i s entered with t h e fol l ow i n g reg isters set:
DPR-
ASS IST09 page work area.
S-
A ret urn address to t h e command processor.
Z=
1
Z=0
A carriage return term i nated the command name.
A space del i m iter fol lowed the com m and name.
B-27
.CM D L 1
Primary Command List
(Continued)
.CM D L 1
A com m and ro utine is entered after the del i m iter fol low ing the command
name is typed i n . Th is means that a carriage ret u rn m ay be the d e l i m iter
entered with the i n put device rest i n g on the next l i ne. For this reason the Z
bit i n the condition code is set so the command routi n e m ay determ i ne the
c u rrent position of the i n put device. The com mand routine sho uld ensure
that the console device is left on a new l i ne before returning to the com­
m and h andler.
.CM D L2
Code:
Secondary Command List
.C M D L2
44
Description: T h i s entry poi nts to the second l i st table. The defau lt is a n u l l l i st fol lowed
by a byte of 2. A com plete expl an ation of the use for t h i s entry is provided
under the description of the .CM D L 1 entry.
-
.CO DTA
Code:
Output Data Byte to Console Routine
.CO DTA
28
Description: The responsib i l ity of this handler i s to send the character i n the A reg i ster
to the output device. The default rout ine al so fol lows with paddi ng
characters as explai ned i n the description of the O UTCH service. If the out­
put device is not ready to accept a character, then the " pause" subroutine
should be cal led repeated ly wh i l e this cond ition l asts. The address of the
pause routine i s obtained from the . PAUSE entry i n the vector table. The
character counts for padding are o btai ned from the . PAD entry i n the table.
Al l ASSI ST09 output is done with a cal l to this appendage. Th is incl udes
punch p rocessi n g as wel l . The default routine sends the character to an
ACI A as explai ned i n Paragraph 8.2 I m plementation Req u i rements. The
operat i n g environment i s as fol lows:
A = Character to send
DP = ASSI ST09 work page
. PAD = Character and new l i n e padd ing cou nts
(i n vector table)
. PAUSE = Pause routine (i n vector table)
Character sent to the output d evice
O ut put:
Volatile Registers: None. Al l work reg isters m ust be restored
Input:
8-28
.COO F F
Code:
Output Console Sh utdown Routine
. COO F F
30
Descript ion: This entry addresses the rout ine to term i n ate output device processi n g .
ASSIST09 does not cal l t h i s rout ine. It is incl u ded for com pleteness. The
defau lt routine is an " RTS".
Input:
Output:
Vol at i l e Registers:
.COO N
Code:
D P - ASSI ST09 work page
The output device is term i n ated
None
Output Console Initial ization Routine
.COO N
26
Description: This entry points to a routine to i n itial ize the standard output device. The
defau lt ro ut i ne i n it i a l izes an ACIA and is the very same one descri bed
u nder the .CI O N vector swap def i n ition.
Input:
O utput:
Vol atile Registers:
.ACIA vector entry for the ACIA add ress
The output device is i n it i al ized
A, X
8·29
.
EC H O
Code:
Echo Flag
.
EC H O
50
Description: The fi rst byte of this word is used as a flag for the I N CH P service rout ine
to determ i ne the requ i rement of echoing i n p ut received from the i n put
hand ler. A non-zero value means to echo the i n p ut; zero not to echo. The
ec hoing w i l l take place even if user handlers are substituted for the defau lt
.CI DTA handler as the I N C H P service routine performs the echo .
. FI RQ
Code:
Fast Interrupt Request Vector Appendage
. FI RQ
10
Description: The fast i nterru pt request rout i n e is located via this poi nter. The M C6809
add resses hexadecimal FFF6 to l ocate the hand le r when p rocessi ng a
F I RQ. The stack and mach ine status is as defi ned for the F I RQ i nterrupt
u pon entry to this appendage. It should be noted that t h i s rout i ne is
"j u m ped " to with an i n d i rect jump i n struction which adds eleven cycles to
the i nterru pt time before the handler actual ly receives contro l . The default
handler does an i m med i ate " RT I " which, i n essence, i g nores the i nterrupt.
8-30
. H S DTA
Code:
High Speed Display Handler Routine
. H S DTA
32
Description: This entry is i nvoked as a su broutine by the D ISPLAY command and passed
a parameter l i st contai n i ng the "TO" and " FROM " add resses. The from
val u e is rou nded down to a 1 6 byte add ress boundary. The defau lt routine
displays memory i n both hexadecimal and ASC I I rep resentations, with a
t itle produced on every 1 28 byte boundary. The p urpose for this vector table
entry i s for easy i m plementation of a user rout ine for spec ial pu rpose
hand l i n g of a block of data. (The data cou l d , for exam ple, be sent to a high
speed pri nter for l ater analysis.) The parameters are a l l passed on the
stack. The envi ronment is as fol lows:
Input:
Output:
Volatile Registers:
.I RQ
Code:
S + 4 = Start add ress
S + 2 = Stop address
S + 0 = Return Add ress
D P - ASSIST09 work page
Any p urpose desi red
X, 0
Interrupt Request Vector Appendage
. I RQ
12
Description: A l l i nterrupt req uests are passed to the rout i n e poi nted to by this vector.
H exadeci m a l FFF8 is the M C6809 location w here t h i s i nterrupt vector i s
fetched. The stack a n d processor status i s that defined f o r t h e I RQ i nter­
rupt upon entry to the hand ler. Since the routi ne's address is in the vector
table, an i n d i rect j u m p must be done to i nvoke it. Th is adds eleven cycles to
the i nterrupt ti me before the I RQ handler receives contro l . The default I RQ
handler pri nts the reg isters and enters the ASSIST09 command handler.
8·31
.N M I
Code:
Non·M askable Interrupt Vector Appendage
.N MI
16
Description: Th is entry pOints to the non-maskable interrupt handler to receive control
whenever the processor branches to the address at hexadeci m a l FF FC.
S i nce ASSIST09 uses the N M I i nterru pt d u ring trace and breakpoi nt pro­
cess i n g , such commands sho u l d not be used if a user handler is in control .
Th is is true u n less the user handler has the i ntel l i gence to forward control
to the default handler if the NMl i nterrupt has not been generated d u e to
u ser fac i l ities. The NMT handler g iven control wi l l have an e l even cycle
overhead as its address m u st be fetched from the vector table .
. PA D
Code:
Character and New Line Pad Count
. PAD
48
Description: Th is entry contains the pad count for characters and new l i nes. The f i rst of
the two bytes is the count of n u l l s for other characters, and the second is
the n u m ber of n u l ls (SOO) to send out after any l i ne feed is transmitted . The
ASCI I Escape character (S1 0) never has n u l l s sent fol lowing it. The d efault
.CODTA handler is responsible for transm itting these n u l ls. A user handler
m ay or may not use these counts as req u i red .
The " N U LLS" com mand a lso sets these two bytes with user specified
values.
8-32
. PAUS E
Code:
Processing Pause Routine
. PAU S E
40
Description: I n o rder to support real-t i m e (also known as mult i-taski ng) envi ronments
ASSI ST09 cal ls a dead-time ro ut i ne whenever processing must wait for
some external change of state. An exa mple would be when the OUTCH ser­
vice routine attem pts the sendi n g of a character to the ACIA through the
default .CODTA hand ler and the ACI A status reg isters shows that it can not
yet be accepted. The defau lt dead-t i m e rout ine resides in a reserved fou r
byte area which contains t h e s i n g l e i n struction, " RTS". The . PAUSE vector
entry poi nts to this routine after standard i n itial ization. This poi nter m ay be
changed to point to a user routine w hich d ispatches ot her prog rams so that
the M C6809 may be ut i l ized more efficiently. Another exam ple of use wo u l d
be t o i n c rement a cou nter s o that dead-t i m e cycle counts may be ac­
c u m u l ated for stat i st ical or debug g i ng p urposes. The reason for the fou r
byte reserved area (wh i ch exists i n the ASSI ST09 work page) is so other
code may be overlayed without the need for another space i n the address
map to be assigned. For example, a master mon itor may be usi ng a memory
management unit to assign a com plete 64 K block of memory to ASSI ST09
and the prog rams bei n g executed/tested under ASS I ST09 contro l . The
master mon itor wishes, or course, to be reentered when any "dead t i m e "
occ u rs, s o it overlays the default rou t i n e (" RTS") w i t h i t s o w n "SW I " . S i nce
the m aster mon itor wou l d be "front e nd ing" al l "SWI 's" anyway, it knows
when a "pause" call is being pe rformed and can red i spatch ot her systems
on a t i me-sl ice basis.
Al l reg i sters m ust be transparent across the pause hand l er. Along w ith
selected poi nts i n ASSIST09 user service processi n g , there i s a special ser­
vice cal l specifical ly for user program s to i nvoke the pause rout ine. It m ay
be suggested that i f no servi ces are bei ng req uested for a g iven time period
(say 10 ms) user programs should cal l the . PAUSE service rout ine so that
fai r-task d ispatch i n g can be g uaranteed .
. PTM
Code:
Programm able Timer Module Address
. PT M
53
Description: Th i s entry contains the add ress of the M C6840 program mable timer mod u le
(PT M ). Alterat ion of t h i s slot shoul d occur before the M O N ITR start u p ser­
vice i s cal led as explai ned i n Parag raph 8.4 I n itial izat ion. If no PTM i s
ava i lable, then t h e address s h o u l d b e changed t o a zero s o that no i n­
it ial izat ion attem pt w i l l take p l ace. N ote that i f a zero i s suppl ied, ASSI ST09
B reakpo i nt and Trace com mands should not be issued.
8-33
. RESET
Code:
Reset Interrupt Vector Appendage
. R ESET
18
Description: T h i s entry returns the add ress of the RES ET rout i ne which i nitial izes
ASS IST09. Chang i n g it has no effect , but it is i nc l uded in the vector table i n
c ase a user program w ishes to determi ne where t h e ASS I ST09 restart code
resides. For exam ple, if ASSIST09 resides in the memory map such that it
does not control the MC6809 hardware vectors, a user routine m ay wish to
start it up and thus need to obtai n the standard R ESET vector code ad­
d ress. The ASSI ST09 reset code assigns the default in the work page, cal l s
the vector b u i l d subrout ine, and then starts ASSI ST09 proper w i t h the
M O N ITR service cal l .
. RSV D
Code:
Reserved M C6809 Interrupt Vector Appendage
. RSV D
4
Description: Th i s i s a poi nter to the reserved i nterrupt vector rout ine addressed at hex­
adec imal F F FO. Th is M C6809 hardware vector is not defi ned as yet. The
default rout i n e setup by ASSIST09 w i l l cause a reg ister d i sp l ay and en­
trance to the com m and handler.
.SWI
.SWI
Softare Interrupt Vector Appendage
Code:
14
Description: This vector entry contains the address of the Software I nterru pt routine.
N ormal ly, ASSIST09 hand les these i nterrupts to provide services for user
p rog rams . If a user handler is i n place, however, these fac i l ities cannot be
u sed u n l ess the user routi n e "passes on" such requests to the ASS IST09
default handler. Th is is easy to do, si nce the vector swap fu nct ion passes
back the address of the default handler when the switch is m ade by the
u ser. Th i s "front ending" allows a user routine to exam ine all serivce cal l s ,
or alter/replace/extend them to his requ i rements. Of cou rse, the reg i sters
m u st be t ransparent across the transfer of control from the user to the
standard handler. A "J M P" i n struction branches d i rect ly to the routi ne
poi nted to by this vector entry when a SWI occurs. Therefore, the envi ron­
ment is that as defined for the "SWI " i nterrupt.
.SWI2
Code:
Software Interrupt 2 Vector Appendage
.SWI2
8
Description: Th i s entry contains a poi nter to the SWI2 hand ler entered whenever that in­
struction i s executed . The status of the stack and machine are those defi n­
ed for the SWI2 i nterrupt which has its i nterrupt vector add ress at F F F4
h exadec i m a l . The default handler pri nts the regi sters and enters the
ASSIST09 command handler.
B-35
.SWI3
Code:
Software Interrupt 3 Vector Appendage
.SWI 3
6
Description: Th is entry contai ns a poi nter to the SWI3 handler entered whenever that i n­
struction is executed . The status of the stack and m ach ine are those defin­
ed for the SWI3 i nterurpt which h as its i nterru pt vector add ress located at
hexadecimal F F F2. The default handler prints the reg isters and enters the
ASSIST09 co mmand handler.
8-36
8.1 1 MON ITO R LIST I N G
T h e follow i n g pages contai n a l i st i n g of the ASSI ST09 mon itor.
PAG E
001
AS S I ST0 9 . S A : 0
ASS I S T0 9 - M C 6 8 0 9 MON I TOR
TTL
OPT
00001
00002
AS S I ST 0 9 - M C 6 8 0 9 MON I TOR
ABS , L LE= 8 5 , S , C RE
00004
00005
00006
*************************************
* COPY RIGHT ( C ) M OTO ROLA , I N C . 1 9 7 9 *
***** ********************************
0 00 0 8
0 00 0 9
00010
00011
00012
00013
00014
00015
*** * * * * * * ******************* *********
* TH I S IS THE BAS E AS S I ST 0 9 ROM .
*
IT MAY RUN W I T H OR WITHOUT TH E
*
EXTENS I ON ROM WH I CH
* WHEN PRE S ENT W I L L BE AUTOMAT I CALLY
*
INCORPORAT E D BY THE BLDVTR
*
SUBROUT I N E .
*************************************
00017
0 00 1 8
00019
0 00 2 0
00021
00022
00023
00024
00025
00026
00027
0 00 2 8
00029
0 00 3 0
*********************************************
*
G LOBAL MODU LE EQUAT E S
********************************************
ROMBEG E Q U
$F800
ROM START ASS EMBLY ADDRE S S
RAMOFS EQU
-$ 1 9 0 0
ROM OF F S ET TO RAM WORK PAGE
20 4 8
ROM S I Z E QU
ROM S I Z E
ROM 20F E QU
ROMBEG- ROMS I Z START OF EXTENS ION ROM
$E0 0 8
EQU
AC I A
DEFAULT AC I A ADDRES S
PTM
EQU
$EO OO
DEFAULT PTM ADDRE S S
0
DFTC H P EQ U
DE FAULT CHARACTER PAD COUNT
5
DFTN LP EQU
DE F AU LT NEW L I N E PAD COUNT
,>
PROMPT EQU
P ROMPT CHARACTER
8
NUMBKP EQU
NUMB E R OF BREAK PO I NTS
*********************************************
0 00 3 2
00033
0 00 3 4
0 00 3 5
00036
00037
00038
0 00 3 9
00040
00041
00042
00043
0 00 4 4
0 00 4 5
0 00 4 6
00047
00049
00051
00052
F800
E7 0 0
0800
FOOO
E0 0 8
EO O O
0000
0005
003E
OQ 0 8
A
A
A
A
A
A
A
A
A
A
*********************************************
* M I SC E LANEOUS EQU AT E S
************** ************* ******************
$04
EQU
E N D O F TRANSM I S S I ON
EOT
EQU
BE L L CHARACTER
BELL
$07
$OA
LF
LINE FEED
EQU
$00
CR
EQU
CARR I AGE RETU RN
$10
DLE
DATA L I N K ESCAPE
EQU
$18
CAN C E L ( CTL- X )
EQU
CAN
* p'rM ACC E S S DEF I N I T IONS
PTM+ l
RE AD STATUS REG I STER
PT M ST A EQU
PTM
CONTROL REG I STERS 1 AN D 3
PTMC 1 3 EQU
PTM+ l
CONT ROL REG ISTER 2
PTMC 2
EQU
PTM + 2
P T M T M l BQU
LATCH 1
LATCH 2
PTMTM2 EQU
PTM+ 4
PTM+6
PTMTM3 EQU
LATCH 3
0004
0007
OOOA
0000
0010
0018
A
A
A
A
A
A
EO O l
EO O O
EO O l
E0 0 2
E0 0 4
E0 0 6
A
A
A
A
008C
A SKIP2
1\
A
EQU
$8C
" CM P X # n O PCODE - SK I P S TWO BYTES
*******************************************
AS S I ST0 9 MON ITOR SW I F U N C T I O N S
*
8-37
PAG E
0 00 5 3
00054
00055
00056
0 00 5 7
00058
0 00 5 9
00060
00061
00062
0 00 6 3
0 00 6 4
00065
00066
00067
0 00 6 8
00069
0007 0
00071
00072
0 00 7 3
00074
00075
0 00 7 6
0 00 7 7
00078
0 00 7 9
00080
00081
0 0082
0 00 8 3
00084
00085
0 00 8 6
0 0087
0 00 8 8
00089
0 00 9 0
00091
00092
0 00 9 3
0 00 9 4
00095
00096
00097
0 00 9 8
0 00 9 9
0 0100
00 2
ASS I ST0 9 . SA : 0
AS S I S T0 9 - MC6 8 0 9 MON I TOR
0000
0001
00 0 2
0003
0004
000 5
0006
0007
0008
0009
OOOA
OOOB
OOOB
A
A
A
A
A
A
A
A
A
A
A
A
A
0000
000 2
0004
0006
0008
OOOA
OOOC
OOOE
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
00 24
0026
0028
0 0 2A
0 0 2C
002E
00 3 0
0032
0034
001B
0034
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
* THE FOLLOW I NG EQUA'fES DE F I NE F U NC'nONS PROV I D E D
* B Y THE ASS I S'r0 9 MON ITOR V I A THE SWI INSTRUCT ION .
******************************************
0
I N CHNP EQU
I NPUT CHAR IN A REG - NO PAR I TY
1
OUT PUT CHAR FROM A REG
OUTCH EQU
2
PDATAl EQU
OUTPUT STRI NG
OUTPUT CR/LF THEN STRI NG
PDATA EQU
3
4
OUT 2 H S EQU
OUTPUT TWO HEX AN D S PAC E
OUT4 HS EQU
OUTPUT FOU R HEX AN D S PAC E
5
PCRLF
6
OUT PUT CR/LF
EQU
EQU
7
SPACE
OUTPUT A S PACE
8
MON ITR EQU
ENT E R AS S I ST0 9 MON I TOR
9
VECTOR EXAM I NE/SWITCH
VCTRSW EQU
10
SRKPT E QU
USER PROGRAM BREAK PO I NT
11
TAS K PAU S E F UNCT ION
PAUS E EQU
11
NUMFUN EQU
NU MBER O F AVA I LAB LE FUNCTIONS
* N EXT S U B-CODES FOR ACC E S S I NG THE VECTOR TAB LE .
* THEY ARE EQU IVALENT To O F F S ETS I N THE TAB LE .
* RE LAT IVE POS l 'r I ON I NG MUST BE MA I NTAI N F; D .
0
ADDRE S S OF VECTOR TABLE
. AVTBL EQU
F I RST COMMAND L I ST
2
. C M DLl EQU
4
RE S E RVED HARDWARE VECTOR
. RSVD EQU
5W I 3 ROUT I NE
6
. SW I 3
EQU
8
. SW I 2
SWI 2 ROUT I NE
EQU
10
. F I RQ EQU
F I RQ ROUT I NE
12
EQU
I RQ ROUT I N E
. I RQ
14
. SWI
EQU
SW I ROUT I N E
16
NM I ROUT I N E
.NMI
EQU
18
RE S ET ROUT I NE
. RE S ET EQU
20
EQU
CONSOLE ON
. C ION
22
. C I DTA EQU
CONSOLE INPUT DATA
24
. C IOFF EQU
CONSOLE I N PUT OFF
26
E QU
. COON
CONSOLE OUTPUT O N
28
. C O DTA EQU
CON SOLE OUTPUT DATA
30
CONSOLE OUTPUT O F F
. COOF F EQU
32
H I GH S P E E D PRI NTDATA
. H SDTA EQU
34
EQU
. SSON
PUNCH/LOAD ON
36
. SS DTA EQU
PUNCH/LOAD DATA
38
PUNCH/LOAD OF F
. SSOFF EQU
40
TAS K PAUSE ROUT I N E
. PAUSE EQU
42
EXP RE S S ION ANALY Z E R
. EX PAN EQU
44
SECOND COMMAND LI ST
. CM DL2 EQU
46
AC I A ADDRE S S
. AC I A EQU
CHARACTER PAD AND NEW L I N E PAD
48
EQU
. PAD
50
ECHO/LOAD AN D NULL BKPT F LAG
. ECHO E QU
52
PTM ADDRE S S
EQU
. PTM
N U M B E R OF VECTORS
52/2+1
NUMVTR EQU
H I G H EST VECTOR O F F S E T
52
H I VTR EQU
8-38
PAG E
003
AS S I ST0 9 . S A : 0
0010 2
00103
00104
0010 5
0 0106
00107
0 010S
00109
00110
0 0111
00112
0 0 1 l 3 A EO O O
0 0114
00115
0 0 1 l 6A DFFC
00117
O O l l S A DFFB
00119
0 0 1 2 0 A DFFA
00121
0 0 1 2 2A DF F S
00123
0 0 1 2 4 A DFC 2
00125
0 0 1 2 6 A DF B 2
00127
0 0 1 2 S A DFA2
00129
0 0 l 3 0 A DFAO
00131
0 0 1 3 2A DF 9 E
00133
0 0 1 3 4A D F 9 D
00135
0 0 1 3 6 A DF 9 B
00137
0 0 1 3 SA DF99
00139
0 0 1 4 0 A DF 9 7
00141
0 0 1 4 2A DF 9 5
00143
0 0 1 4 4 A DF 9 3
00145
0 0 1 4 6 A DF 9 1
00147
0 0 1 4 S A DF 9 0
00149
0 0 1 5 0 A DF S F
00151
0 0 1 5 2A DF S E
00153
0 0 1 5 4 A DF 6 6
00155
0 0 1 5 6 A DF 5 1
00157
0015S
DFO O
O O DF
DFFC
DF F B
DFFA
DF F S
DFC 2
DF B 2
DFA2
DFAO
DF9E
DF 9 D
DF 9 B
DF 9 9
DF 9 7
DF 9 5
DF 9 3
DF 9 1
DF 9 0
DF S F
DF S E
DF 6 6
DF 5 1
DF 5 1
AS S I ST0 9 - M C 6 S 0 9 MON ITOR
******************************************
WORK AREA
*
* TH I S WORK AREA IS AS S I G N E D TO THE PAGE ADDRE S S E D BY
* -S l S 0 0 , PCR FROM THE BAS E ADDRE S S OF THE AS S I S T 0 9
* ROM .
THE D I RE CT PAGE RE G I ST E R DURI NG MOST ROUT I NE
* OPERAT I ONS WI LL PO I NT TO TH I S WORK AREA .
THE STACK
* I N I T I ALLY STARTS U N D E R THE RE S E RV E D WORK AREAS AS
* DEF I N E D HERE I N .
******************************************
A WORKPG EQU
ROMB E G + RAMO F S S ETU P D I RECT PAG E ADDRE S S
A
SETDP WORK PG ! > S NOT I F Y AS S E MB LER
ORG
WORKPG+ 2 5 6 READY PAG E DEF I N I T I ONS
* THE FO LLOW I NG THRU BK PTOP MUST RE S I DE I N TH I S ORDE R
* FOR PROPER I N I T I AL I Z AT I ON
*-4
ORG
*
PAUS E ROUT I N E
A PAU S E R EQU
*-1
ORG
BYPASS SWI AS BREAK PO I NT F LAG
*
A SW I B F L EQU
*-1
ORG
BREAK PO I NT COUNT
*
A BK PTCT EQU
*-2
ORG
*
STACK TRAC E LEVEL
A SLEVEL EQU
*-NUMVTR* 2
ORG
*
VECTOR TAB LE
A VECTAB EQU
* - 2 * NU M B K P
ORG
*
A BK PTBL EQU
BREAKPO I NT TABLE
*-2* NUMBKP
ORG
*
BREAK PO I NT OPCODE TAB LE
A BK PTOP EQU
*- 2
ORG
W I N DOW
*
A WI NDOW EQU
*-2
ORG
*
ADDRES S PO I NT E R VALUE
EQU
A ADDR
*-1
ORG
BAS E PAG E VALU E
*
A BAS E PG EQU
*- 2
ORG
B INARY BU I LD AREA
*
A NUMBE R EQU
*-2
ORG
LAST OPCODE TRACE D
*
A LASTOP EQU
*-2
ORG
RE S ET STAC K PO I NT E R
*
A RSTACK EQU
*-2
ORG
COMMAN D RECOVE RY STACK
*
A PSTACK EQU
*-2
ORG
LAST PROG RAM COUNTER
*
A PCNTER EQU
*-2
ORG
*
TRAC E COUNT
A TRAC E C EQU
*-1
ORG
*
TRACE " SW I " N E ST LEVE L COU NT
A SW I C NT EQU
( M I S F LG MUST FOLLOW SW I CN T )
*-1
ORG
LOAD CMD/T H RU BREAK PO I NT F LAG
*
A M I S F LG EQU
*-1
ORG
EXPRESS I ON DE L I M IT E R/WORK BYTE
*
A DEL I M
EQU
*-40
ORG
EXTE NS ION ROM RE S E RVED AREA
*
A RO M2WK EQU
*-21
ORG
TEMPORARY STACK HOLD
A TSTACK EQU
*
START OF I N IT I A L STACK
A STACK
EQU
*
8-39
P AG E
004
AS S I ST0 9 . SA : 0
ASS I ST0 9 - MC6 8 0 9 MON I TOR
00160
0 0161
00162
00163
00164
00165
0 0166
0 01 67A F 8 0 0
******************************************
* DEFAULT THE ROM BEG I N N I NG ADDRES S TO ' ROMBEG '
* AS S I ST0 9 IS POS I T I ON ADDRE S S I N DE P E N DENT , HOWEVE R
* WE AS S EM B LE AS S UM I NG CONTROL OF TH E HARDWARE VECTORS .
* NOTE THAT THE WORK RAM PAG E MUST BE ' RAMOFS '
* F ROM THE ROM BEG I N N I NG ADDRE S S .
* * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * *
0 0169
00170
00171
0 01 7 2
00173
0 01 7 4
00175
00176
00177
0 0178
0 0 1 79
0 0 1 80
00181
************* ****************************************
BLDVTR - BU I L D AS S I ST0 9 VECTOR TAB LE
*
* HARDWARE RE SET CALLS TH I S SUBROUT I N E TO BU I LD TH E
* AS S I ST0 9 VECTOR TABLE . TH I S S U B ROU T I N E RE S I DE S AT
* THE F I RST BYTE OF THE AS S I ST0 9 ROM , AN D CAN BE
* CALLED V I A EXT E RNAL CONTROL CODE FOR RE MOTE
* A S S I ST0 9 EXECUT I ON .
* I NPUT : S- > VAL I D STACK RAM
* OUTPUT : U- >VECTOR TABLE ADDRE S S
DPR- > AS S I ST0 9 WORK AREA PAGE
*
THE VECTOR TAB LE AND DEFAULT S ARE I N I 'r I AL I Z E D
*
* ALL REG I ST E RS VOLAT I LE
*************************************************
0 0 1 8 3A
0 0 1 8 4A
0 0 1 8 5A
0 0 1 86A
0 0 1 87A
0 0 1 88A
0 0 1 89A
0 0 l 90A
0 0 1 9 1A
0 0 1 9 2A
0 0 1 9 3A
0 0 1 94A
0 0 1 9 5A
0 0 1 96A
0 0 1 9 7A
0 0 1 98A
0 0 1 9 9A
0 0200A
0 0 2 0 1A
0 0 2 0 2A
0 0 2 0 3A
0 0 20 4A
0 0 20 5A
0 02 0 6A
0 0 207A
0 0209
0 0210
0 0211
00212
0 0213
F800
F804
Fa06
F808
F aOA
F 80C
F80F
Fall
F813
F815
F817
F819
F81B
F81D
F81F
F821
F823
F825
F826
F828
F 8 2C
F82F
F83l
F833
F835
ROMBEG
ORG
30
IF
IF
97
33
3l
EF
C6
34
IF
E3
ED
6A
26
C6
A6
A7
SA
26
31
8E
AC
26
AD
35
BLDVTR LEAX
8 0 E7 BE
10
TFR
A
TF R
8B
A
STA
A
90
A
LEAU
84
LEAY
8C 3 5
A
STU
81
A
LOB
16
A
PSHS
04
A BLD2
TF R
20
A
ADDD
Al
STD
81
�
DEC
A
E4
BNE
F815
F6
00
LOB
A
A BLD3
LOA
AO
A
STA
80
DE C B
BNE
F821
F9
LEAY
8 0 F 7 D4
A
LDX
20FE
A
CMPX
Al
F835
BNE
02
JSR
A
A4
A B LORTN P U LS
84
ROM ASS EM B LY/DEFAULT ADDRE S S
VECTAB , PCR ADDRE S S VECTOR TABLE
X,D
OBTA I N BAS E PAGE ADDRE S S
A , DP
SETU P DP R
BAS E PG
STORE FOR QU I C K RE F E RENCE
RETURN TABLE TO CALLER
,X
< I N I TVT , PC R LOAD F ROM ADDR
, X++
I N I T VEc'rOR TABLE ADDRE S S
# NU MVTR- 5 NUMB E R RE LOCATABLE VECTORS
STO RE INDEX ON STACK
B
Y,D
PRE PARE ADDRES S RE SOLVE
TO ABSOLUTE ADDRE S S
, Y+ +
I NTO VECTOR TABLE
, X++
,S
COUNT DOWN
BLD2
BRANCH I F MO RE TO I N S E RT
# I NTVE- I NTVS STAT I C VALUE I N I T LE NGTH
, Y+
LOAD NEXT BYTE
STORE I NTO POS I T ION
, X+
COUNT DOWN
LOOP UNT I L DONE
BLD3
ROM 2 0 F , PCR TEs'r POS S I B L E EXTENS I ON ROM
LOAD " B RA * - F LAG PATTE RN
# $ 20FE
, Y+ +
? EXTEN D E D ROM HE RE
BLDRTN
BRAN CH NOT OU R ROM TO RETU RN
CALL EXTENDED ROM I N I T I AL I Z E
,Y
RETURN TO I N I T I AL I Z E R
PC , B
*****************************************************
RE S ET ENTRY PO I NT
*
* HARDWARE RE SET ENTE RS H E RE I F AS S I ST0 9 IS ENAB L E D
* T O REC E I V E TH E MC 6 8 0 9 HARDWARE VECTORS . WE CALL
* THE BLDVTR SUBROUT I N E TO I N I T I AL I Z E THE VECTOR
8-40
PAG E
00 5
00214
00215
00216
0 0 2 1 7A
0 0 2 1 8A
0 0 2 1 9A
0 0220A
0 0 2 2 1A
0 0 2 2 2A
00223A
00225
0 0226
0 0 227
00228
00229
0 0230
00231
00232
0 0 2 3 3A
00234A
0 0 2 3 5A
00236A
0 0237A
0 0238A
00239A
0 02 4 0A
0 0 2 4 1A
0 0 2 4 2A
0 0 2 4 3A
00244A
00245A
0 0246A
0 0 2 4 7A
0 0 2 4 8A
0 0249A
0 0 2 5 0A
0 0 2 5 1A
0 0 2 5 2A
0 0 2 5 3A
00254A
00255
002 56A
00257A
0 0 2 5 8 1\
0 0259A
0 0 2 6 0A
0 0 2 6 1A
0 0 2 6 2A
0 0 2 6 3A
00264
00265
00267
AS S I ST0 9 - M C 6 8 0 9 MON I TOR
AS S I ST0 9 . SA : 0
F837
F83B
F83D
F83E
F840
F841
F842
32
80
4F
IF
3F
20
* TA B L E , S TAC K , AN D TH E N F I RE U P TH E MON I TOR V I A S W I
* CALL .
*******************************************************
8 0 E7 1 6
RE S ET
F800
C3
RESET2
A
8B
08
F9
F844
F846
F848
F84A
F84C
F84E
F850
F852
F854
F856
F858
F85A
F85C
F85E
F860
F862
F864
F866
F868
F86A
F86C
F86E
0158
0292
0290
028E
0 27 0
028A
0045
022B
FFE3
0290
0284
0296
0 28A
0293
0290
039A
02B7
0 2 02
02BF
E7 9 2
0470
012 D
F870
F87 2
F874
F876
F878
F87A
F87B
F87C
E0 0 8
00
0000
EO O O
0000
00
00
39
F8 7D
A
F8 3 D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
LEAS
BSR
C L RA
TFR
SW I
FC B
BRA
STACK , PCR S ET U P I N I T I AL STA C K
B LDV T R
B U I L D V E CTO R TABL E
I S S U E STARTU P MESSAGE
A , DP
DE F AU L'r TO PAGE Z E RO
P ERFO RM MON ITOR F I RE U P
MON I T R
T O E N T E R CO MMAN D P RO C E S S I N G
RE S E T 2
RE ENTER MON ITOR I F ' CONT I NU E '
******************************************************
*
I N I TVT - I N I T I AL VECTOR TABLE
* TH I S TABLE IS RE LOCAT E D TO RAM AN D RE P RE S E NTS TH E
* I lH T I AL STAT E OF THE VECTOR TABLE . ALL ADDRE S S E S
* ARE CONVE R'£E D TO ABSOLU T E FORM . TH I S TABLE STARTS
* W I TH TH E SECON D ENTRY , E N DS WITH STAT I C CON STANT
* I N I T I A L I Z AT I ON DATA WH I C H CARRI E S BEYOND TH E TAB LE .
************************************************
I N I TVT F OB
CM DT B L - * DEF AU LT F I RST COMMAND TAB LE
F OB
RS RVDR- * DEF AULT UNDEF I N E D HARDWARE VECTOR
S W I 3 R- *
DE FAULT SW I 3
F DB
S W I 2 R- *
F OB
DEF AULT SW I 2
F I RQ R- *
F DB
DEFAU LT F I RQ
FDB
I RQ R- *
D E F AUL 'r I RQ ROUT I N E
S W I R- *
FDB
DE F AU LT SWI ROU T I N E
F DB
NM I R- *
DEFAULT NMI ROUT I N E
RE S ET- *
RESTART VECTOR
F OB
C I ON- *
C I D'£A- *
C IOF F- *
COON- *
CODTA- *
COOFF- *
H S DTA- *
B S ON- *
B S D TA- *
BSO F F - *
P A U S E R- *
EX P1 - *
C M DT B 2 - *
F DB
FCB
FOB
FOB
F OB
FCB
FCB
FCB
EQU
AC I A
DE FAU L'£ AC IA
DFTCH P , DFTNLP D E F A U LT NU LL PADDS
0
DE FAULT ECHO
PTM
DEFAU LT PTM
0
I N I T I AL STACK TRAC E LEVEL
I N I T IAL BREAK PO I NT COUNT
0
0
SWI BREAK PO I NT L E V E L
DE FAU LT PAU S E ROUT I NE ( RTS )
$39
* CONSTANTS
A I NTVS
A
A
A
A
A
A
A
A I N TV E
*B
DE F A U LT
DE F A U LT
DE F A U LT
DE FAU LT
DE F A U LT
DE F AU LT
DE F A U LT
DE F AU LT
DE F AULT
D E F AULT
DEFAU LT
DE F AULT
DEFAULT
F OB
F DB
F OB
F OB
F OB
FOB
F OB
F OB
F OB
F OB
FOB
F OB
F OB
C I ON
C I DTA
C IOFF
COON
CODTA
COOF F
HS DTA
BSON
B S DTA
B SOF F
PAUSE ROU T I N E
EXPRE S S ION ANALY Z E R
S E COND COMMAN D TABL E
*
***********************************************
B-41
PAGE
006
AS S I S'r0 9 . SA : 0
ASS I ST 0 9 - MC 6 8 0 9 MON I 'fOR
*
AS S I ST0 9 SW I HANDLER
*
TH E SWI HAN DLER PROV I DE S AL L I NTE RFAC I NG N E C E S SARY
*
FOR A USE R PROG RAM .
A FU NCT ION BYTE IS AS S U M E D TO
*
FOLLOW TH E SWI I N STRUCT ION .
IT IS BOUND CHECK ED
*
AN D TH E P RO P E R ROUT I N E I S G I VEN CONTROL .
TH I S
*
I N VOCAT I O N MAY ALSO BE A BREAK PO I NT I NTE RRU PT .
*
I F SO , TH E BREAK PO I NT HAN DLER I S ENTERE D .
* I NPUT : MAC H I NE STA'rE DEF I N E D FOR SWI
* OUTPUT : VAR I E S ACCORD I NG TO FUNCT ION CALLE D . PC ON
CALLERS STACK I NCREMENTED BY ON E I F VAL I D CALL .
*
* VOLAT I LE REG I ST E RS : SE E F UNCT IONS CALLE D
* S TATE : RUNS D I SAB LED UNLESS FUNCT ION CLEARS I F LAG .
************************************************
00268
0 0269
0 0270
00271
00272
00273
0 0274
0 0275
0 0276
00277
0 02 7 8
0 0279
00280
* SWI F U N CT I ON VECTOR TABLE
Z I NCH-SW IVTB I NCHNP
A SW I VTB F DB
ZOTC H 1 -SWIVTB OUTCH
A
F DB
Z P D'fAl - SW I VTB PDA'fAl
A
F DB
Z P DATA-SWIVTB PDATA
A
F OB
A
Z OT 2 H S- SWIVTB OUT2 H S
F DB
Z OT 4 H S -SWIVTB OUT4 HS
A
F DB
Z PCRLF-SWIVT B PCRLF
A
F DB
Z S PAC E - SWIVTB S PACE
A
FDB
ZMON T R-SWIVTB MON ITR
A
F DB
ZVSWTH-SWIVTB VCTRSW
A
F DB
Z BK PNT- SWI VTB BREAK PO I NT
F DB
A
Z PAUSE-SWIVTB TASK PAUSE
F OB
A
0 0282
0 0 2 8 3A
0 0 2 8 4A
0 0 2 8 5A
0 0 286A
0 0 2 87A
0 0 2 8 8A
0 0 2 8 9A
0 0 2 9 0A
0 0 2 9 1A
0 0 2 9 2A
0 0 2 9 3A
0 0 2 9 4A
F87D
F87F
F88 1
F88 3
F88S
F887
F889
F88B
F88D
F88F
F891
F89 3
0 0 2 9 6A
0 0 2 97A
0 029B
0 0 2 99A
0 0300A
0 0 3 0 1A
0 0 3 0 2A
0 0 3 0 3A
0 0 3 0 4A
0 0 3 0 SA
0 0 3 0 6A
00307A
0 0 3 0 BA
0 0 3 0 9A
00310A
0 0 3 l lA
0 0 3 1 2A
0 0 3 1 3A
0 0 3 1 4A
0 0 3 1 SA
0 0 3 16A
0 0 3 1 7A
0 0 3 l 8A
0 0 3 1 9A
SWI CNT , PCR U P " SWI " LEVEL FOR TRACE
DEC
SW I R
8 D E6 F 7
SETUP PAGE AND VER I FY STAC K
LDDP
LBSR
0 2 2 5 FACl
* C H E C K FOR BREAK PO I N'f TRAP
LDU
A
10 , S
LOAD PROGRAM COUNTER
F89C EE
6A
BACK TO SWI ADDRESS
-l , U
LEAU
A
F89E 33
SF
? TH I S · SW I " BREAK PO I NT
TST
SWI B F L
A
F BAO O D
FB
SW I DNE
BRANCH IF SO TO LET TH ROUGH
BNE
FBBS
F 8 A2 2 6
11
OBTA I N BREAK PO I NT PO I N T E RS
LBSR
C B K LDR
069B FF42
F 8 A4 1 7
OBTA I N POS I T I VE CO UNT
NEGB
F BA7 5 0
COU NT DOWN
DEC B
SWI LP
F B A B SA
BM I
SW I DN E
BRANCH WHEN DONE
F8BS
F 8 A9 2B
OA
CMPU
? WAS TH I S A BREAK PO I NT
A
, Y+ +
F B AB l l A 3 Al
SW I LP
BRANCH I F NOT
BNE
F8
F B AB
F BAE 2 6
SET PROGRAM COU NTER BACK
STU
10 , 5
A
6A
F B BO E F
GO DO BREAK PO I NT
LBRA
Z B K PNT
F 8 B2 1 6
0 2 1 E FAD3
SWI B F L
C LE AR I N CAS E SET
FBBS O F
A SW I DN E C L R
FB
0
PU LU
OBTA I N F UNCT ION BYTE , U P PC
A
F 8 B7 37
06
CMP B
# NUMFUN ? TOO H I GH
A
FBB9 Cl
OB
ERROR
YES , DO BREAK PO I NT
F B BB 1 0 2 2 0 2 0 F FAC E
LBH I
10 , 5
BUMP PROGRAM COUNTER PAST SWI
F B BF E F
STU
A
6A
F UNCTION C O D E T I M ES TWO
AS L B
FBCl SB
LEAU
SWI VTB , PCR OBTAIN VECTOR BRANCH ADDRE S S
F8C2 33
BC B8
B,U
LOA D OF F S ET
LDO
A
F 8 C S EC
CS
D,U
JUMP TO ROUT I N E
F 8 C7 6E
A
JMP
CB
0 0321
00322
00323
0 0 3 24
0194
OlBl
OlCB
01C3
0175
017 3
OlCO
0179
0055
017D
0256
O l Dl
F89S 6A
F899 17
**********************************************
* REG I ST E RS TO FUNCT ION ROUT I NES :
*
DP- ) WORK AREA PAG E
X=AS CALLED FROM US E R
D , Y , U = U N RE L I ABLE
*
8-42
PAGE
007
AS S I s 'r0 9 . S � : 0
�S S I s' r 0 9
-
MC 6 8 0 9
MON I 'rOR
00325
0 0326
*
S=hS F RO M SWI I N'r r; R RU P'r
************************************ *********
00328
0 0329
00330
0 0331
0 0332
0 0333
00334
00335
00336
00337
00338
0 0339
0 0 340
**************************************************
[ S ri I P U N C T I U N 8 )
*
M O N I 'rU i{ E N 'r RY
*
*
F I R E U P 'ru E AS S I ST0 9 MON I 'rU R .
* THE S T A C K WITH I'rs VA L ll E S P O R TI I l� l > I jU� CT PAm:
*
REG I S T E l{ AN D CO N D I 'r I O N CO D E F L AG S A R E U l:> t:: l) AS I ::i .
*
1 ) I N I T I A L I Z 8 CO N l:> U L E I /O
*
2 ) O P T I U N A L L Y P R I N T S I G NON
*
3 ) I N I T I A L I Z E PTM P O R S I NG L � ST � P P I N G
*
4 ) E N T E R COMMAND P ROC E � S O R
* I N P U T : A= O I N l 'r CON S O L E A N D P IU N 'r STAH'ru p �I E S S A G E
A # O OM I 'r CO N SO L E m I 'l' AN D STA RTU P �If'; S S AG E
*
*** ************ ******************************** **
0 0 3 4 2A F 8 C 9
0 0 3 4 3A F8D1
0 0 3 4 5A
0 0 3 4 6A
0 0 3 47A
00348A
0 0349A
0 0350A
0 0 3 5 1A
0 0 3 5 2A
0 0 3 5 3A
0 0 3 54A
0 0 3 5 5A
003 56A
00357A
0 0 3 58A
00359A
0 0360
0 0 3 6 1A
0 0362
00364
0 03 6 5
00366
00367
0 0368
0 0369
0 0370
00371
00372
00373
00374
00375
00376
0 0377
0 0378
F8D2
F8D5
F 8 D7
F 8 D9
F8DD
F8E1
F8E4
F8E5
F8E6
F8E8
F 8 EA
F8EC
F 8EE
F8F1
F8F3
41
04
1 0 DF
60
26
AD
AD
30
3F
9E
27
6F
6F
CC
A7
E7
F8F5 6F
A S I G NO N
A
FCC
/ASS I S'l'0 9/S I G NUN
FCB
Eo'r
EY \:: - C A'rC H E R
RSTACK
SAVE FOR BAO s'rACK RECOVERY
A ZMONTR STS
97
1,S
? I N IT CONSOLE AN D S E N D MSG
TST
A
61
Z MONT2
BRANCH IF NOT
BNE
F8E6
00
[ V ECT A B+ . C I O N , PCR] READY CO N SO L E I N P UT
JS R
9 0 E6 F 9
JSR
[ VECTAB+ . COON , PC R ] READY CO NSOL E OUTPUT
90 E6FB
L F. AX
S I GNON , PCR READY S IGNON EYE- CATCH E R
8C E5
PERFORM
SWI
P RI NT S T R I NG
FCB
PDATA
A
03
A ZMONT2 L O X
VECTAB+ . PTM LOAD PTM ADDRE SS
F6
CMD
BRANCH I F NOT TO U S E A PTM
BEQ
F8F7
00
C LR
A
PTMTMI- PTM , X SET LATCH TO CLEAR RE S ET
02
CLR
PTMTM 1 + 1-PTM , X AN D SET GATE H IG H
A
03
# $ 0 1A6
S E T U P T I M ER 1 MODE
LDO
A
0 1A 6
STA
PTMC 2 -PTM , X S ETUP FOR CONTROL REG I ST E Rl
A
01
PTMC 1 3 - PTM , X SET OUTPUT ENABLE D/
STB
A
84
*
S I NGLE SH O T/ DUAL 8 B I T/ I NTERNAL MODE/OP E RATE
C LR
PTMC 2 -PTM , X SET CR2 RACK TO RE S E T FORM
A
01
* FALL I NTO COMMAN D PROC E S S O R
*** * * * * * * * * * * * * * ************* ******************* ***
COMMAN D HAN DLER
*
BREAK PO I NTS ARE REMOVED AT TH I S T I ME .
*
*
P ROMPT FOR A COM MAN D , AN D STORE ALL CHARA C T E RS
U N T I L A S E PARATOR ON TH E STACK .
*
S EARCH FOR F I RST MATCH I NG COMMAN D SUBSET ,
*
CALL IT OR G IV E 1 1 1 RES PON SE .
*
DU RING COMMAN D SEARC H :
*
B=O F F S ET TO NEXT ENTRY ON X
*
U =SAV E D S
*
U- l = E NTRY S I Z E + 2
*
*
U- 2 =VAL I D NUMBER FLAG ( > = 0 VAL I O ) /COMPARE CNT
U- 3 =CARRIAG E RE 'r U RN F LAG ( O =C R HAS B E E N OON E )
*
U-4=START OF COMMAN D s'rO RE
*
S+O = E N D OF COMMAN D STORE
*
8-43
PAG E
008
AS S I ST 0 9
ASS I S'ro 9 . S A : 0
***********************************************
00379
0 0 3 8 0A
1>1 0 N I 'l'O R
- M C 6 13 0 9
F8F7
0 0 3 8 1A F 8 F 8
0 0 38 2
TU NEW L I N E
F UN C T I O N
PCRLF
* D I SARM TiU': B H C A K PO I 1'�'l' S
C B K I. D R
OBTA I N B R E A K PO Hl 'r PO I NT E RS
F F 4 2 C M D tJ t:: P L B S R
B RAN CH I F' NO'I' ARM E D OR N O N E
C !'t DNOL
BP L
F90A
C 1>1 D
3F
06
0 0 383A
F8F9
17
U646
0 0 3 8 4A
0 0385A
F 8 FC
F 8 FE
2A
OC
0 0 3 8 6A
F 8 F £o'
50
D7
FA
0 0 3 8 7A
0 0 3 88A
F901
F902
F904
S I'l I
A
FeB
A
ST�
MAK E POS I 'r I V t::
NEGB
CM D D D L D E C B
5 11.
2B
06
A6
30
13K P'rCT
F LAG
?
AS
D I S A RM E D
F ! N I S H E: D
H� SO
LOA D O P CODE S T O RE D
STO RE BACK OV E R II S W I
[ , Y+ + )
0 0 3 9 0 A F 9 0 6 A7
B1
C M D DD L
LOOP UNT I L DON E
F901
F7
0 0 3 9 1A 1" 9 0 8 2 0
LOAD U S E RS PROG RAM COUNT E R
10 , S
A CMD N O L LOX
6A
0 0 3 9 2A 1" 9 0 A AE
SAVE FOR EXPRE S S ION ANALY Z E R
PCNT E R
STX
A
93
0 0 3 9 3A F 9 0 C 9 F
# P ROM P T LOAD PROMPT CHARACTER
LOA
3E
A
0 0 3 9 4A F 9 0 E 8 6
SEND TO OUTPUT HANDLER
SWI
0 0 3 9 5A F 9 1 0 3 F
DUTCH
F UNCT ION
FCB
01
A
0 0 3 9 6A F 9 1 1
A
,S
REMEMBER STACK RESTORE ADDRES S
LEAU
E4
0 0 3 97A F912 3 3
REMEMBER STACK FOR ERROR USE
PSTACK
STU
95
A
0 0 3 9 8 A F 9 1 4 OF
PRE PARE Z E RO
CLRA
0 0 3 9 9A F 9 1 6 4 F
PRE PARE Z ERO
CLRB
0 0 4 0 0A F 9 1 7 S F
C LEAR NUMBE R BU I LD AREA
NUM B E R
STD
A
9B
0 0 4 0 1A F 9 1 8 DO
CLEAR M I S CE L . AND SW I CNT F LAGS
M I S F LG
STD
A
8F
0 0 4 0 2A F 9 1 A DO
CLEAR TRACE COUNT
TRAC E C
STD
A
91
0 0 4 0 3 A F 9 1C DO
SET 0 TO TWO
#2
LO AS
A
02
0 0 4 0 4A F 9 1 E C6
P LACE DEFAULTS ONTO STACK
D , CC
PSIi S
07
A
0 0 4 0 5A F 9 20 34
* C H E C K FOR " QU I C K " COMM A N DS .
00406
OBTA I N F I RS T CHARACTER
READ
LBS R
0 4 5 4 F D7 9
0 0407A F922 17
C DOT+ 2 , PCR PRE S ET FOR S I NGLE TRACE
LEAX
0 04 0 8 A F925 30
80 0581
? QU I C K TRACE
CMPA
A
0 04 0 9A F929 81
2E
iI
BRANCH EQUAL FOR TRACE ONE
CMDXQT
BEQ
5A
F987
0 04 1 0 A F 9 2B 27
CMPADP+ 2 , PCR READY MEMORY ENTRY POI NT
LEAX
80 04E9
0 0 4 1 1A F 9 2 D 30
? OPEN LAST USED MEMORY
CMPA
A
0 0 4 1 2A F 9 3 1 8 1
2F
i'l
BRANCH TO DO IT I F SO
CM D XQT
BEQ
F987
52
0 0 4 1 3 A F 9 3 3 27
* P ROCE S S NEXT CHARACT ER
0 04 1 4
? B LANK OR DEL I M ITER
CMPA
A CMD2
t'
0 04 1 5A F 9 3 5 8 1
20
BRANCH YES , WE HAVE IT
CMDGOT
BLS
F94D
14
0 0 4 1 6A F 9 3 7 2 3
BU I LD ONTO STACK
A
PSHS
A
0 0 4 1 7A F 9 3 9 34
02
COUNT TH I S CHARACT E R
-l , U
INC
A
0 0 4 1 8A F93B 6C
SF
? MEMORY COMMAN D
CMPA
A
til
0 0 4 1 9A F 9 3 D 8 1
2F
CMDMEM
BRANCH I F SO
BEQ
F990
0 04 20A F93F 27
4F
TREAT AS H E X VALU E
B L D HXC
LBS R
0 04 21A F941 17
0 4 0 B F D4 F
CMD 3
BRANCH I F ST I LL VAL I D NUMBER
BEQ
F948
02
0 0 4 2 2 A F 9 4 4 27
F LAG AS I NVA L I D NUM B E R
-2 , U
DEC
A
0 04 23A F946 6A
5E
OBTA I N NEXT CH ARACTER
READ
LBS R
0 04 2 4A F 9 4 8 17
0 4 2 E F D7 9 C M D 3
TEST NEXT CHARACTE R
CMD 2
BRA
F935
0 0 4 25A F94B 20
E8
* G O T COMMAN D , NOW S EARC H TABLES
0 04 2 6
SET Z E RO I F CARRI AG E RETU RN
I CR
A CM DGOT SUBA
00
0 0427A F94D 80
SE'fUP F LAG
-3 , u
STA
A
50
0 0 4 2 8A F 9 4 F A7
VECTAB+ . CMDL1 START W I TH F I RST CMD L I ST
LOX
A
C4
0 04 2 9A F 95 1 9 E
LOAD ENTRY LENGTH
,X+
A CMDSCH LOB
80
0 0 430A F953 E6
BRANCH IF NOT L I ST END
CM DS M E
BP L
F967
10
0 0 4 3 1A F 9 5 5 211.
VECTAB+ . C MDL2 NOW TO SECOND CMD L I ST
LOX
A
EE
0 0 4 3 2A F 9 5 7 9 E
? TO CONT I NU E TO DE FAULT L I ST
I NC B
0 04 3 3A F 9 5 9 5 C
BRANCH I F SO
CMDseH
BEQ
F9 5 3
F7
0 0 4 3 4 A F 9 5A 27
PSTACK
RESTORE STACK
A CM DB A D LOS
0 0 4 3 5 A F 9 5 C l O DE 9 5
L E AX
E RRMSG , PCR PO I NT TO E RROR STRING
80 015A
0 04 3 6 A F95F 30
00389A
F 9 0 /\
8M I
C�DNOL
A
1\
I.J)A
STA
B RA
-NUMBK P * 2 , Y
BRAN C H
It
•
8·44
P AG E
009
0 0437A
00438A
0 0 4 3 9A
0 0440
0 0 4 4 1A
0 04 4 2A
0 04 4 3A
0 0 4 4 4A
0 0 4 4 5A
0 0 4 4 6A
0 0447A
0 0448A
0 04 4 9A
0 0450A
0 0 451A
0 0 4 5 2A
0 04 5 3A
0 04 5 4A
0 0 4 5 5A
0 0 4 5 6A
0 0457A
0 0 4 5 8A
0 0 4 5 9A
0 0 4 6 0A
0 0 4 6 1A
0 0 4 6 2A
0 0 4 6 3A
0 0 4 6 4A
0 0 4 6 5A
0 0 4 6 6A
0 0467A
AS S I ST0 9 . SA : 0
F963 3F
F964
F965 20
F967
F968
F96A
F96C
F96D
F96F
F971
F973
F97 5
F977
F978
F97A
F97C
F97E
F980
F98 2
F983
F985
F987
F989
F98B
F98D
F990
F99 2
F994
F997
F999
5A
El
24
3 .11.
20
31
A6
80
A7
5A
A6
Al
26
6A
26
3A
EC
30
60
32
AD
16
60
2B
30
DC
20
ASS I S T 0 9 - M C 6 8 0 9 MON I TOR
02
90
A
F8F7
5F
03
A
F96F
E4
5D
5F
02
5E
F953
A
80
A2
EE
5E
F5
A
A
F96C
A
F977
A
A
A
A
1E
A
8B
50
A
A
C4
A
IE
FF7A F90A
A
5E
C8
F9 5C
A
8 8 AE
A
9B
F987
EC
SWI
FCB
BRA
* S E ARCH NEXT
CM DSME DECR
CMPB
BHS
CMDFLS ABX
B RA
CMDS I Z LEAY
LOA
SUBA
STA
CMDCMP DEC B
LOA
CMPA
SNE
DEC
BNE
ABX
LDD
LEAX
CMDXQT TST
LEAS
JSR
LBRA
CMDMEM TST
BM I
LEAX
LCD
B RA
PDATAI
CMD
ENTRY
S E N D OUT
TO CONSOLE
AN D T R Y AGA I N
TAK E ACCOU NT OF LE NGTH BYTE
? E N T E R E D LON G E R THAN ENTRY
BRANC H I F NOT TOO LO NG
SK I P 'ro NEXT ENTRY
CMDSCH
AN D 'fRY NEXT
-3 , U
PRE PARE TO COMPARE
-l , U
LOA D S I Z E + 2
#2
TO ACTUAL S I Z E E N T E R E D
SAVE S I Z E FOR COUNTDOWN
-2 , U
DOWN ONE BYTE
, X+
NEXT COMMAN D CH ARA C T E R
, -Y
? S AME AS T H AT E N T E R E D
I F NOT
CMDF LS
B RANCH TO F LU S H
COU NT DOWN LENGTH OF ENTRY
-2 , U
CMDCMP
8RAN CH IF MORE TO T E ST
TO NEXT EN'f RY
LOAD O F F S E T
-2 , X
COMPUTE ROUT I N E A DD RES S + 2
D,X
SET CC FOR CARR I AG E RETURN TEST
-3 , U
DELETE STACK WORK AREA
,U
-2 , X
C AL L C O MMAN D
C M DN O L
GO GET NEXT COMMAND
? VAL I D HEX NUMB E R ENTERED
-2 , U
C M D BA D
BRANCH ERRO R I F NOT
<CMEMN-CMPADP , X TO DI F F E RENT ENTRY
N UM B E R
LOAn NUMBE R ENTERE D
CM DXQT
AN D ENT ER MEMORY COMMAN D
-l , U
C M DS I Z
0 0469
0 0470
00471
0 047 2
00473
0 0474
00475
* * COMMAN DS ARE E NT E RE D A S A SUBROUT I N E W I 'fH :
**
DP R- > ASS I ST0 9 DI RECT PAGE �ORK ARE A
**
Z = l CARRI AGE RE'fURN ENTE RED
Z = O NON CARR I AG E RETU RN DE L I M ITER
**
S-NORMAL R ET U RN ADDRE S S
**
* * THE LAB E L n CMDBA D n MAY BE ENTERED TO I S S U E AN
* * A N ERROR F LAG ( * ) .
00477
0 0478
0 0479
00480
00481
0 04 8 2
00483
0 04 8 4
00485
00486
00487
0 0488
0 0489
00490
0 04 9 1
00492
**** **********************************************
ASS I ST0 9 COMMAN D 'fABLES
*
EXTERNAL
* TH E S E ARE THE D E F .e.1J [,1' CO M MA N D TABLE S .
'fAB L E S OF THE SAME FORMAT MAY EXTE N D/ RE PLACE
*
* TH E S E BY US I NG THE VECTOR SWAP FUNCT I ON .
*
* E NTRY FORMAT :
*
+O
TOTAL S I Z E OF E NT RY ( I NC L U D I NG TH I S BYT E )
*
+l
COMM A N D STR I NG
+N
TWO BYTE OF F SE'r TO COM M A N D ( E N T RYA D DR- * )
*
*
* THE 'fAB LES TE RM I NATE WITH A ON E B YT E - l OR - 2 .
* 'l'H E - 1 CONT I N U E S TH E COMMA N D SEARC H W I T H TH E
SECO N D CO MM A N D TAB LE .
*
* THE -2 TERM I NA'r E S COMMA N D S EARCH E::> .
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *� * * * * * * * * * * * * *
•
•
•
•
•
•
•
•
•
B-4 5
PAG E
010
0 0494
0 04 9 5
0 0 4 9 6A F998
FE
0 0498
00499
00500
0 0 5 0 1A
0 0 5 0 2A
0 0 5 0 3A
0 0 5 0 4A
F99C
F99D
F99E
F 9AO
F99C
04
42
0540
04
0 0 5 0 5A
00506A
0 0 5 0 7A
0 0 5 0 8A
00509A
0 0 5 10A
O O S l lA
O O S loil A
0 0 S 1 3A
0 0 S 14A
0 0 S 1 5A
0 0 S 1 6A
F 9A1
F 9 A2
F 9 A4
F 9 A5
F 9 A6
F 9 A8
F9A9
F 9 AA
F 9 AC
F 9 AD
F 9 AE
F 9 BO
43
0417
04
44
0490
04
45
OS9F
04
47
0 3 02
04
00548
00549
* T H I S I S THE DE FAU LT LIST (O'OR THE SECOND COMMAN D
* L I ST ENTHY .
STOP COMMAN D SEARCHES
-2
A CM DT82 FCB
I S 'fH E DE FAULT L I ST FOR THE F I RST COMMAN D
ENTRY .
MON I'fOR COMMAND TABLE
*
A CMDTBL EQU
4
FCB
A
' BREAK PO I NT ' COMMAN D
FCC
A
I BI
* TH I S
*
0 0 S 1 7 A F 9 Bl
0 0 S 1 8A
0 0 S 1 9A
0 0520A
0 0 5 2 1A
0 0 5 2 2A
0 0 5 2 3A
0 0 5 2 4A
0 0525A
0 0526A
0 0527A
0 0 5 2 8A
0 0 5 29A
0 0 5 3 0A
0 0 5 3 1A
0 0 5 3 2A
0 0 5 3 3A
0 05 3 4A
00535A
0 0 5 36A
0 0 5 37A
0 0 538A
0 0539A
00540A
0 0 5 4 1A
0 0 5 4 2A
0 0 5 4 3A
0 0 5 4 4A
0 0 5 4 5A
0 0 5 4 6A
AS S I ST 0 9 - MC6 8 0 9 MON I'fOR
AS s I ST0 9 . sA : 0
F 9 B2
F 9 B4
F 9 &S
F 9 B6
F9B8
F9B9
F 9 BA
F 9 BC
F9BD
F 9 BE
F9CO
F 9C1
F9C2
F9C4
F9C5
F9C6
F9C8
F9C9
F 9 CA
F 9 CC
F9CD
F9CE
F 9DO
F9Dl
F9D2
F 9 D4
F 9 D5
F 9 D6
F 9 D8
4C
0 4 00
04
40
040 0
04
4E
04FD
04
4F
050A
04
50
0 4 AF
04
52
0284
04
53
04F2
04
54
0 4 06
04
56
04CF
04
57
0468
FF
A
A
A
A
A
A
A
A
A
L I ST
F OB
FCB
CSK PT- *
FCC
FOB
IC I
CC A L L - *
4
1 01
FCB
FCC
F OB
FC B
FCC
A
A
A
A
A
F OB
A
FC C
F OB
FCB
FCC
F OB
FCB
FCC
F OB
FC B
FCC
F OB
FCB
FCC
F OB
FCB
FCC
FOB
FCB
FCC
FOB
FCB
FCC
F OB
FCB
FCC
FOB
FCB
FC C
FOB
FCB
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
4
' D I S P LAY '
COMMAN D
C D I S P- *
4
lE I
C E NC DE- *
FCB
4
FC C
F DB
IGI
FCB
' CALL ' COMMAN D
' E N C ODE '
C OMM AN D
' GO ' COMMAN D
CGO- *
4
ILl
' LOAD ' COMMAND
C LOAD- *
4
IMI
' MEMORY ' COMMAN D
INI
' NU LLS ' COMMAN D
101
' OF F S ET ' COMMAN D
IPI
' PUNCH ' COMMAND
IRI
' REG I ST E RS ' COMMAN D
lSI
' STLEVEL ' COMMAND
IT I
' TRACE ' COMMAND
IVI
' VERI FY ' COMMAND
CMEM- *
4
CNU LLs- *
4
COF F S- *
4
CPUNCH - *
4
C REG- *
4
CSTLEV-*
4
CTRAC E - *
4
CVE R- *
4
IWI
' W I NDOW ' COMMAND
CW I N DO- *
EN D , CONT I NU E WITH THE S ECOND
-1
*************************************************
[ SW I F U NCT I ONS 4 AN D 5 )
*
8-46
P AG E
011
ASS I ST0 9 - MC 6 8 0 9 MON I TOR
ASS I ST 0 9 . SA : 0
4 - OUT 2HS - De CODE BYTE TO HEX AN D ADD S PACE
*
5 - OUT 4 H S - DE CODE riORD TO HEX ru� D ADD S P AC E
*
* I NPUT : X-> BYTE O R WORD TO DECODE
* OUTPUT : CHARACT E RS S E NT TO OUTPUT HAN DLER
X - > NEXT BYTE OR WORD
*
**************************************************
0 0550
0 0551
0 0552
0 0553
0 0554
00555
0 0557A
0 0 5 5 8A
0 0 5 59A
0 0 5 6 0A
0 0 5 6 1A
0 0 5 6 2A
Ot0 5 6 3A
0 0 5 6 4A
0 0 5 6 5A
0 0 5 6 6A
0 0567A
0 0568A
F9D9
F 9 DB
F9DD
F 9 DF
F9EO
F9E2
F9E4
F9E6
F9E8
F9E9
F9EB
F9EC
A6
34
C6
3D
80
35
84
8B
19
89
19
6E
80
06
10
0 0 5 7 0A F 9 F O 8 0
0 0 5 7 1A F 9 F 2 8 0
0 0 5 7 2A F 9 F 4 AF
0 0573
E7
E5
64
00575
0 0576
0 0577
00578
0 0 57 9
00580
0 0 5 8 1A F 9 F 6 8 6
0 0 5 8 2A F 9 F 8 2 0
0 0584
0 0585
00586
0 0587
00588
0 0589
00590
0 0 5 9 1A
0 0 5 9 2A
0 0 5 9 3A
0 0 5 9 4A
0 0 5 9 5A
0 05 9 6A
0 05 9 7 A
0 05 9 8A
0 0599A
0 0 6 0 0A
00601
F 9 FA
F 9 FC
F9FE
FAO O
FA0 3
FA0 5
FA0 7
FA0 9
FAO B
FAO D
A6
81
22
10 9 E
EE
EF
AF
27
AF
20
04
06
OF
90
40
90
20
3D
61
34
39
C2
A6
64
7E
2E
A6
2A
A ZOUT 2 H LOA
A
PSHS
A
LOB
MUL
F9E6
BS R
A
PULS
A
ANDA
A ZOUTHX ADDA
OM
-A
ADCA
OM
SEND
JMP
E5EE
F 9 D9 Z OT4 H S
F 9 D9 ZOT2HS
A
* F ALL
,X+
LOAD NEXT BYTE
SAVE - DO NOT REREAD
#16
SH I FT BY 4 B I TS
WITH MULT I P LY
ZOUTIiX
S E N D OUT AS HEX
o
RE STORE BYT E S
#$OF
I SOLATE R I G H T HEX
#$90
PRE PARE A-F ADJ UST
ADJ UST
PRE PARE CHARACTE R B I TS
# $40
ADJ UST
[ VECTAB+ . CODTA , PC R ) S E N D T O OUT HAN D LE R -
o
BSR
ZOUT 2 H
CONVERT F I RS T BYTE
ZOUT 2 H
CONVE RT BYTE T O HEX
4,S
UPDATE USERS X REG I �TER
STX
I NTO SPACE ROUT I N E
B S H.
*************************************************
*
[ SW I F U NC T I ON 7 )
*
S PAC E - S E N D BLANK TO OUTPUT HANDLER
* I NPUT : NONE
* OUT P UT : BLANK SE N D '::0 CONSOLt� lIAN DLER
***************** ********************************
A Z S PACE LOA
LOAD BLANK
#'
FA3 7
BRA
ZOTC H 2
S E N D AN D RETU RN
A
A
FA3 9
A
A
A
A
FA3 9
A
FA3 9
***********************************************
*
[ Sri I FUNCT ION 9 )
SWAP VECTOR TABLE ENTRY
*
* I NPUT : A-VECTOR TABLE CODE ( OF F S ET )
*
X=O OR REP LACEMENT VALUE
* OUTPUT : X = P REVIOUS VALUE
***********************************************
ZVS WTH LOA
1,S
LOAD REQUESTERS A
CMPA
? S U B-CODE TOO H IGH
# H IVTR
BH I
ZOTCH3
IGNORE CALL I F SO
LDY
VECTAB+ . AVTBL LOAD VECTOR TABLE ADDRE S S
LOU
A,Y
U=OLD ENTRY
STU
RETU RN OLD VALUE TO CALLERS X
4 ,S
STX
-2 , S
? X= O
ZOTCH3
BEQ
YES , DO NOT CHANGE ENTRY
STX
A, Y
RE PLAC E ENTRY
RETURN FROM SW I
BRA
ZOTCH 3
*0
8-47
PAG E
012
0 06 0 3
00604
00605
00606
0 0607
00608
0 06 0 9
0 06 1 0
0 0 6 1 1A
0 0 6 1 2A
0 06 1 3A
0 0 6 1 4A
0 0 6 1 5A
0 0 6 1 6A
0 0 6 1 7A
0 0 6 1 8A
0 0 6 1 9A
0 0620A
0 0 6 2 1A
0 0 6 2 2A
0 0 623A
0 06 24A
0 0 6 2 5A
00626A
0 0 6 27
00629
00630
00631
00632
00633
0 06 3 4
00635
00636A
0 0 6 3 7A
0 06 3 8 A
0 0639A
0 0 640A
0 0 6 4 1A
0 0 6 4 2A
AS S I ST 0 9 . SA : 0
FAO F
FAl l
FA1 3
FA1 5
FA1 6
FA1 8
FA1A
FA1 C
FA1 E
FA2 0
FA2 2
FA2 4
FA2 6
FA2 8
FA2A
FA2C
FA2E
FA3 0
FA3 3
FA3 5
FA3 7
FA3 9
FA3B
80
80
24
40
27
81
27
A7
00
26
81
26
86
80
00
26
A6
30
81
27
80
OC
3B
50
SF
FA
F9
7F
F5
61
8F
17
00
04
OA
C2
F4
OB
ASS I ST 0 9 - M C 6 8 0 9 MON I TOR
FA6 E
FAn
FAO F
FAl l
A
FAl l
A
A
FA3 9
A
FA2A
A
F9EC
A
FA3 9
A
61
8C 09
A
OA
OF
FA4 6
F9EC
B3
A
90
00644
00645
0 0646
00647
00648
00649
00650
************************************************
*
[ SW I FUNCT ION 0 ]
*
INCHNP - OBTA I N I N P UT CHAR I N A ( NO PARI TY )
* NULLS AN D RU BOUTS ARE IGNORE D .
* AUTOMAT I C L I N E F E E D I S S E N T U PON HEC I EV I NG A
CARRI AG E RE'l'URN .
*
*
UNLESS �E ARE LOAD I NG F ROM TAPE .
** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
HE LEAS E PROC E S S O R
XQPAUS
Z I NCHP BSR
XQC I DT
CALL I N PUT DATA APP E N DAGE
Z I NCH
aSR
Z I NCHP
LOOP I F NONE AVA I LABLE
BCC
TSTA
? T E ST FOR NU L L
IGNORE NULL
Z I NCH
BEQ
? RU BOUT
# $7F
CMPA
BRANCH YES TO I G NORE
Z I NCH
BEQ
1,S
STORE I NTO CALL E RS A
STA
M I S F LG
? LOAD IN PROG RE S S
TST
ZOTCH3
BRANCH I F SO TO NOT ECHO
BNE
CMPA
#CR
? CARR I AG E RETURN
BNE
Z I N2
NO , TES'l' ECHO BYTE
LOA
# LF
LOAD L I NE F E E D
BSR
SEND
ALWAYS ECHO L I N E F E E D
VEC'l'AB+ . E CHO ? ECHO DES I RE D
TST
Z IN 2
Z OTC H 3
BNE
NO , RETURN
* F AL L TH ROUGH T O OUTCH
************************************************
*
[ S W I FUNCTION 1 ]
*
OUTCH - OUTPUT CHARACT ER F ROM A
*
I N PUT :
NONE
* OUTPUT : I F L I N E F E E D I S TH E OUTPUT CHARACTE R TH E N
C = O NO CTL-X REC I EVED , C= l CTL- X REC I EVED
*
*************** *********************************
ZOTCH 1 LOA
1,S
LOAD CHARACTE R TO S E N D
< Z PCRLS , PC R DEFAU LT FOR L I NE F E E D
LEAX
#LF
? L I NE FEED
CMPA
BEQ
Z P DTLP
B RANCH TO CHECK PAU S E IF SO
SEND
S E N D TO OUTPUT ROUT I N E
ZOTCH 2 BS R
BUMP UP A SWI n T RACE NEST LEVEL
ZOTCH3 I N C
SWICNT
RETURN F ROM n SW I n F UNCT I O N
RT I
**************************************************
[ SW I FUNCTION 6 ]
*
PCRLF - S E N D CR/LF TO CONSOLE HANDLER
*
*
INPUT : NONE
* OUT PUT : C N. AN D LF S E NT TO HANDLER
C = O NO CTL- X , C= l CT L-X REC I EV E D
*
**************************************************
0 0 6 5 2 A FA3C
04
0 0 6 5 4 A FA3 D 3 0
00655
8C FC
A Z P C RLS F C B
EOT
NU L L STRING
Z PCRLF LEAX
Z PC RL S , PC R READY C R , L F ST R I NG
* FALL I NTO CR/LF COD E
8-48
PAG E
013
ASS I �T0 9 . S A : 0
0 0657
0 0658
0 06 59
00660
00661
0 0662
00663
0 0664
0 0665
00666
0 0 6 6 7 A r�A 4 0 8 6
0 0 6 6 8 A FA4 2 8 0
0 0 6 6 9 A FA4 4 8 6
0 0670
ASS I � T0 9 - M C 6 8 0 9 MON I T O R
** * * * * * * * *** *** * * * * * ** * * * * * ** * * * ** * ** * * * ** * * ******
*
[ S W I F U N C T I ON 3 J
on
A8
OA
*
PDATA - OUT P U 'f CR/I. F AND S T � I NG
* I N P UT : X- > S T � I � G
* OUT P U 'l' : C R/ LF AN D ST R I NG � E N 'l' 're O UT P U T CO NSOLE
*
liAlW L E H .
*
C - O NO CT L -X , C - l CT L - X Hi:: C n: V Ell
* NOT E : LINe 1�' E t: D M U S T r'O L f.OW CA!{IU l\G F.: HE T U RN F O R
*
P RO p e l{ P U NCH l)ATA .
*** * * * * * * * * ** * *** *** * * ******** * ** * * * *** * * * ********
A Z P DA'rA LDA
LOA D CAR R I AG E R E 'l' U RN
#CR
BS H
�END IT
F9EC
SEND
LO A n L I N E �' E i': J)
I. nil
# LF
l\
* F A L r. L N'l'O P D AT A l
00672
00673
** ** * *** * ** * * * * * * * * ** * *** * * * * * * * ** * * * ** * * * ** * * * * *
*
[ S W I F U N CT I O N 2 J
00674
00675
00676
0 0677
00678
0 0679
00680
00681
0 0 6 8 2A FA 4 6 8 0
0 0 6 8 3 A FA 4 8 A6
*
PDATAl - OUTPUT �T R I NG T I L L EOT ( $ 0 4 )
*
TK I S ROUT I NE PAUSES IF AN I N PUT BYTE BECOM E S
AVA I LABLE DURI NG OUTPUT TRANSM I S S ION U N T I L A
*
*
SECOND IS REC I EVED .
* I N PUT : X- ) ST R I NG
* OUTPUT : S T R I N G S E NT 're OUTPUT CONSOLE DRI V E R
*
C - O NO CTL- X , C- l CTL- X RE C I EVED
******************* ***************** ******** * * * * *
SEND
S E N D CHARACTE R T O DRI V E R
Z P DTLP S S R
, X+
LOAD NEXT CHA RA C T E R
Z P DTAl LOA
C MP A
# EOT
? EOT
Z P DTLP
LOOP I F NOT
BNE
* FALL I NTO PAU S E CHECK FUNCT ION
0 0 6 8 4 A FA4A 8 1
0 0 6 8 5 A FA 4 C 2 6
00686
00688
0 06 8 9
00690
0 06 9 1
0 0692
0 0693
00694
0 0695
0 06 9 6
0 06 9 7
0 06 9 8
00699
0 0 7 0 0A
0 0 7 0 IA
0 0 7 0 2A
0 07 0 3A
007 04A
FA4 E
FA50
FA 5 2
FA54
FAS6
80
80
IF
E7
20
0 07 0 6
0 0707
0 07 0 8
0 0 7 0 9 A FA S a 8 0
0 0 7 1 0 A FA 5A 2 4
A4
80
04
F8
lE
06
A9
E4
E1
18
05
F9EC
A
A
FA4 6
****************** ******** ******************
*
[ SW I F UN C T I O N 1 2 J
*
PAUSE - RETU RN TO TAS K D I S PATCH I NG AN D CHECK
*
FO R F RE E Z E CON D I T ION OR CTL-X BREAK
*
TH I � FUNCT I ON ENT E RS TH E TAS K PAUSE HANDLER SO
*
OPT I O NALLY OTH E R 6 8 0 9 PROCE S S E S MAY GA I N CONTROL .
*
U PON RETURN , CHECK FOR A ' F REE Z E ' CON D I T I ON
*
W I TH A RE S U LT I NG WA IT LOOP , DR CON D I T I ON CODE
*
RETU RN IF A CONTROL-X IS ENTERED F ROM THE I NPUT
*
HAN D L E R .
* OUTPUT : C= 1 IF CTL-X HAS ENTERE D , C= O OT H E RW I S E
*****•••••••••••••••••••••*•••••••* .**•••*
RE LEASE CONTROL AT EVERY L I N E
XQPAUS
FA6 E ZPAUSE BSR
CKECK F O R FRE E Z E OR ABORT
CHKABT
BSR
FAS 8
A
A
FA3 9
TF R
STB
B RA
CC , B
,5
ZOTCH3
PRE PARE TO REPLACE CC
OVE RLAY OLD ONE O N ST ACK
RETU RN F ROM
" SW I "
• CHKABT - SCAN FOR INPUT PAU S E/ A B O RT DU RI NG OUTPUT
* OUTPUT : C= O OK , C= 1 ABORT ( CTL-X I S S U E D )
• VOLAT I L E : U , X , D
XQC I DT
ATT EMPT I N PUT
FA7 2 CHKABT BSR
FA6 1
BCC
CHKRTN
8-49
BRAN CH NO TO RETU RN
PAG E
014
AS S I ST 0 9 . SA : 0
0 0 7 11A
0 0 7 l 2A
0 0 7 l 3A
0 0 7 l4A
0 0 7 l SA
0 0 7 l 6A
007 l7A
0 0 7 l 8A
0 0 7 l 9A
0 0 7 20A
0 07 21A
FASC
FA S E
FA 6 0
FA6 1
FA6 2
FA6 4
FA6 6
FA6 8
FA6A
FA6C
FA6 D
81
26
53
39
80
80
24
81
27
4F
39
0 07 23
0 0 7 2 4A
0 072SA
0 07 26A
0 0 7 27A
FA6E
FA7 2
FA7 6
FA78
6E
AD
84
39
AS S I ST0 9 - MC 6 8 0 9 MON ITOR
18
02
A
FA6 2
OA
OC
FA
18
F4
FA6 E
FA7 2
FA6 2
A
FA6 0
# CAN
CHKWT
XQPAUS
XQC I DT
CH KWT
# CAN
CHK S E C
? C T L - X F O R ABORT
BRANCH NO TO PAU S E
S E'f CARRY
RETURN TO CALLER WI TH CC SET
PAUS E FOR A MOMENT
? K EY FOR START
LOOP UNT I L REC I EVEO
? ABORT S I GNALE D F ROM WA I T
BRANCH YES
SET C = O FOR NO ABORT
AN D RETURN
* SAVE ME MORY WITH JUMP S
XQPAUS JMP
[ VE CTAB+ . PAUS E , PC R ) TO PAU S E ROU T I N E
90 E S 7 8
XQC I DT J S R
[ V.ECTAB+ . C I DTA , PC R ) T O I NPUT ROUT I NE
90 ES62
A
STR I P PAR ITY
7F
AN DA
#$7F
"
RTS
RETURN TO CALL E R
********************************************
*
NM I DE FAULT IN'fE RRUPT HANDLER
00729
00730
00731
00732
0 07 3 3
00734
0 07 3 5
00736
*
THE NMI HAN DLER I S US E D FOR TRAC I NG I N STRUCT IONS .
*
TRAC E PRI NTOUTS OCCUR ONLY AS LONG AS THE STACK
*
THACE LEV E L I� NOT B R E AC H E D BY FALL I NG BE LOW IT .
*
TRAC I NG CONT I NU E S UNT I L TH E COUNT TU RNS Z E RO O R
*
A CTL-X I S E NTERED F ROM THE I N PUT CONSOLE DEV I C E .
*********************************************
FA 7 D
FA7 F
FA 8 1
FA8 3
FA 8 S
FA87
FA8 9
FA 8 B
FA8D
FA9 0
FA9 1
FA9 2
FA 9 4
�'A 9 8
FA99
FA9A
FA9C
FA 9 E
FAAO
FAA 2
FAM
FAA 6
FAA 8
FAAA
FAAC
FAAE
A MSHOWP F C B
4F
0 0 7 3 8 A FA7 9
0 07 4 0A
0 0 7 4 1A
0 0 7 4 2A
0 0 7 4 3A
0 0 7 4 4A
0 074SA
0 0 7 4 6A
00747A
0 0 7 4 8A
0 0 7 4 9A
007 50A
0 0 7 S 1A
007 S2A
007 S3A
0 07 S4A
0 0 7 S SA
0 07S6A
00757A
0 0 7 S8A
0 0 7 S9A
00760A
0 0 7 6 1A
0 0 7 6 2A
0 07 6 3A
0 0 7 6 4A
0 07 6 SA
CMPA
BNE
C H K S EC COMB
CHKRTN RTS
CH KWT BSR
BSR
BCC
CMPA
BEQ
CLRA
RTS
80
00
26
00
2B
30
9C
25
30
3F
42
FAC 1 NM I R
A
8F
FAB7
34
A
90
29
FABO
A
6C
A
F8
FABO
23
8C £9
02
A
8E
A
09
30
3F
80 ESOI
80
25
06
25
9E
27
30
9F
27
05
17
37
8E
33
91
2F
IF
91
29
AA
25
80
25
A
FAB 3
FADS
A
FAD S
A
FADS
A
A
FADS
FAS 8
FAD S
BSR
TST
BNE
TST
BM I
LEAX
CMPX
B LO
LEAX
SWI
' O , ' P , ' - , EOT OPCODE PREP
LOOP
M I S F LG
N M I CON
SW I CNT
NM I T RC
12 , S
SLEVEL
N M I T RC
LOAD PAGE AND VERI F Y STACK
? T H RU A B R E AK PO I NT
B RANCH I F S O TO CONT I NUE
BCS
LDX
? I N H I B I T " SW I " DU R I NG TRAC E
BRANC H Y E S
OBTA I N US E RS STACK PO I NT E R
? T O TRAC E H E RE
BRAN CH I F 'roo LOW TO D I S PLAY
MSUOWP , PCR LOAD OP PRE P
S E N D TO CON SO L E
P DAT AI
FUNCTION
DE L I M
SAV E CA R RY I H 'r
LASTOP , PC R PO I NT TO LAST OP
S E N D OUT AS H E X
OUT 4 H S
FUNCTION
REG P RS
FOLLOW ME MORY W I T H REG I ST E RS
BRAN C H I F " CANC E L "
Z BKCMD
DE L I M
RE STORE CARRY B I T
Z BKCMD
BRANCH I F " CANCE L "
TRACEC
LOAD TRAC E COUNT
BEQ
LEAX
STX
BEQ
BSR
BCS
ZBKCMD
-1 , X
TRAC EC
ZBKCMD
CH KABT
Z B KCMD
FCB
ROL
LEAX
SW I
FC B
BSR
BCS
ROR
B·50
IF Z E RO TO COMMAN D HAN D L E R
M I N U S ON E
RE I-' RESH
STOP TRAC E WH EN Z E RO
? A BORT THE TRACE
BRANCH YES TO COMMAND HAN DLER
PAG E
015
AS S I ST0 9 . SA : 0
AS S I ST0 9 - M C 6 8 0 9 MON I TOR
0 0 7 6 6 A FAB O 1 6
0 3 F 7 F EAA NMI TRC LBRA
CTRC E 3
NO , TRAC E ANOTH E R I N ST RUCT ION
0 0 7 6 8 A FAB 3 1 7
0 0 7 6 9 A FAB 6 3 9
0 1 B 9 FC6F HEGPRS LBSR
RTS
REG P RT
PRI NT REG I S T E RS AS F ROM COMMAN D
RET U RN TO CAL L E R
00771
0 0 7 7 2A FAB 7 O F
0 0 7 7 3 A FAB 9 1 7
0 0 7 7 4 A FABC 3B
* J U ST
A NMI CON
8F
0 2 E B F DA7
RT I
*
00776
0 0777
0 0778
00779
0 0780
FAC I
FAC 5
FAC 7
FAC 9
FACB
FACE
FADI
FAD2
3F
E6
IF
Al
27
l O DE
30
3F
00794
0 07 9 5
00796
0 0797
0 0798
0 07 9 9 A FAD3 8D
0 0 8 0 0 A FADS 1 6
00802
0 08 0 3
00804
0 0805
0 0806
0 0807
00808
0 0 8 0 9 A FADS 8 D
0 0 8 l 0 A FADA 2 0
00812
0 08 1 3
00814
00815
0 08 1 6
LDDP - SETUP D I RECT PAGE REG I STE R , V E R I FY STACK .
* AN I NVAI. I D STACK CAU S E S A RETURN TO T H E COMMAN D
* HAN D LE R .
* I NPUT : FU LLY STAC K E D REG I ST E RS FROM AN I NTE RRU PT
* OUTPUT : DPR LOADED TO WORK PAGE
0 0 7 8 2A PAB D
0 07 8 4A
0 0 7 8 5A
0 07 8 6A
0 07 8 7A
0 0788A
0 0789A
0 0 7 9 0A
0 0 7 9 1A
00792
E X E C UTE D 'fH RU A BRKPNT .
NOW CONT I NU E NO RMALLY
M I S F LG
C LEAR THHU F LAG
CLR
LBSR
ARM BREAK PO I NTS
A RM B K 2
RT I
AND CONT I NU E U S E RS P ROGRAM
A ERRM SG F C B
' ? , B E LL , $ 2 0 , EOT ERROR RE S PONSE
LOOP
8 D E 4 D8
A
9B
A
63
25
FAF O
A
97
E RROR
SC EC
03
LOB
BAS E PG , PCR LOAD D I RECT PAGE H I GH BYTE
B , DP
S ETU P DI RECT PAGE REG I ST E R
TFR
CMPA
3,S
? I S STACK VAL I D
YES , RETU RN
BEQ
RTS
RSTACK
LDS
RESET TO I N I T I AL STACK PO I N T E R
LEAX
ERRMSG , PC R LOAD ERROR RE PORT
SWI
S E N D OUT BEFORE REG I STERS
ON NEXT L I N E
FCB
A
PDATA
* FALL I N T O BREAK PO I NT HAN DLER
********** ************* ************* *** *** * ***
*
[ SW I FUNCT I ON 1 0 ]
*
BREAK PO I N T PROGRAM FUNCT ION
*
PRI NT REG I ST ERS AN D GO TO COMMAND HAN L E R
******************* ******************** ******t*
DE
FAS 3 Z B K PNT BSR
F E 2 1 F8F9 Z SKCMD LBRA
REG PRS
CMDN E P
PRI NT OUT REG I ST E RS
NOW ENTER COM M AND HAN D L E R
**** **************** **************** *** **** *
*
I RQ , RE S E RVED , SW I 2 AN D SWI 3 INTE RRU PT HANDLERS
*
THE DEF AULT HAN DL I NG I S TO CAUS E A B REAK PO I NT .
******* * * * * * * ** ** * * ** * * * * * * ****** ** ** * ** ** * *
*
SWI 2 ENTRY
A SWI 2 R EQU
*
SWI J ENTRY
A SW I J R
EQU
*
A I RQR
EQU
I RQ ENTRY
FADS
FAD8
FADS
E7
FAC I RSRVDR B S R
FAD3
F7
BRA
LDDP
Z B K PNT
SET BASE PAGE , VAL I DATE STACK
FORCE A BREAK PO I NT
* * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * *
*
*
F I RQ HAN DLER
JUST RETU RN FOR TH E F I RQ INTE RRU PT
********* * **************************** * * **
FABC
A F I RQR
EQU
RT I
8·51
I MME D I ATE RETURN
PAGE
016
AS S I S T0 9 S A : 0
ASS I ST0 9 - MC 6 8 0 9 MON ITOR
.
00818
00819
0 0 8 20
**************************************************
*
DEF AUL'r I /O DRIVERS
**************************************************
0 08 2 2
00823
0 0 8 24
0 0 8 25A
0 08 26A
0 0 8 27A
0 08 28A
0 0 8 29A
0 08 30A
* C I DTA - RETURN CONSOLE I NPUT CHARACT ER
* OUTPUT : C=O I F NO DATA READY , C = l A=CH ARACTER
* U VOLAT I LE
C I D rA LDU
VECTAB+ . A C I A LOAD AC I A ADDRE S S
,U
LOAD STATUS REG I S T E R
L OA
TEST REC I EVER REG I STER F LAG
LS RA
C I RT N
RE T U RN I F NOTH I NG
BCC
1 ,U
LOAD DATA BYTE
L OA
RET U RN TO CALLER
C I RTN
RTS
00832
00833
0 08 3 4
00835
0 0 8 3 6A
00837A
0 08 38A
0 08 3 9A
0 0840A
0 08 4 1A
F A DC
FA DE
FAEO
FAE1
FAE 3
FAE 5
FAE 6
FAE8
FAEA
FAEC
FAE E
FAF O
DE
A6
44
24
A6
39
86
9E
A7
86
A7
39
00843
00844
FO
C4
A
A
02
41
FAE 5
FAE 6
03
FO
84
51
84
FAF O
F AF O
00845
* C ION
* COON
* A ,X
A C I ON
A COON
A
A
A
A
RTS
- INPUT C O N SO LE I N I T I AL I Z AT ION
- OUTPUT CONSOLE I N I T I A L I ZAT ION
VOLAT I LE
*
EOU
LOA
#3
RES E T AC I A CODE
VECTAB+ . A C I A LOAD AC I A ADDRES S
LOX
STORE INTO STATUS REG I S T E R
STA
,X
SET CONTROL
LDA
#$51
STA
,X
REG I STER UP
RTS
RETURN TO CALLER
* THE FOLLOW I NG HAVE NO DUT I ES TO P E RFORM
CONSOLE I N PUT OF F
E OU
RTS
A C IOF F
E OU
CO N SO L E OUTPUT OF F
RTS
A CO O F F
* CODTA - OUTPUT CHARACTE R TO CONSOLE DEV I C E
* I NPUT : A-CHARACT E R TO S E N D
* O UTPUT : CHAR S E N T TO TERM I NAL ri I T H PROPER PADD I NG
* A LL REG I ST E RS TRAN S PARENT
0 08 4 7
0 08 4 8
00849
0 0850
0 0 8 S 2A
0 08 S 3A
0 0 8 S 4A
0 0 8 S SA
0 0 8 S6A
0 08 S7A
0 0 8 S8A
0 0S S 9A
0 0 8 60A
0 0 8 61A
0 0 8 6 2A
0 0 8 6 3A
0 08 6 4A
0 0 8 6 SA
0 08 6 6A
0 0867A
A
'
FAF 1
FAF 3
FAF S
FAF 7
FAF 9
FAF B
FAF D
FAF F
FB O l
FB0 3
FB04
FB06
FB07
FB09
FaOB
FBOD
34
DE
8D
81
27
06
81
26
06
4F
E7
80
6A
2A
35
0 0869A FBOF 17
0 0 8 7 0 A F B 1 2 £6
0 08 7 1A FBl4 CS
47
FO
IB
10
12
F2
00
02
F3
E4
8C
09
E4
FA
C7
A C O DT A
A
Fa1 2
A
FBO D
A
A
FB0 3
A
C O DTP D
A
PSH S
LDU
BSR
CMPA
BEO
LDB
CMPA
BNE
LOB
CLM
STB
FCB
A
F B 1 2 CODTLP BSH
DEC
A
BPL
FB0 7
A COD'rRT PULS
F F S C FA6 E CODTAD LBS R
A CO DTAO L O B
B IT B
A
02
C4
SAVE REG I S 'rERS , WORl( BYTE
U , D , CC
VECTAB+ . AC I A ADDRES S AC I A
CALL OUTPUT CHAR SUBROT I N E
CO DTAO
? DATA L I N E ESCAP E
tDLE
CODTRT
YES , RETU RN
VECTAB+ . PAD DE FAULT TO CHAR PAD COUNT
? CR
#CR
BRANCH NO
CO DTP D
VECTAB+ . P AD+ 1 LOAD NEW L I N E PAD CO UNT
CREAT E NULL
SAVE COUNT
,S
ENT E R LOOP
SKIP2
S E N D NU LL
CO DTAO
? F I N I S ti E D
,S
NO , CONT I NU E WITH MORE
CO DTLP
PC , U , D , CC RE STORE REG I ST E RS AN D RET U RN
XQPAUS
,U
1$02
8·52
TEMPORARY G I V E UP CONTRO L
LOAD AC I A CONTROL REG I ST E R
? TX REG I ST E R CLEAR
PAG E
017
AS S I ST 0 9 - MC 6 8 0 9 MON I TOR
ASS I ST0 9 . SA : 0
0 0 8 7 2 A F B 1 6 27
0 0 8 7 3 A FB 1 8 A7
0 0 8 7 4A FBIA 39
00875
F7
41
00889
00890
0 0 8 9 1A
0 0 8 9 2A
0 0 8 9 3A
0 0 8 9 4A
Q 0 8 9 sA
0 0 8 9 6A
0 08 9 7A
0 0 89 8A
0 0899A
00900A
0 0901A
CO DTAD
1 ,U
RE LE AS E CONTROL IF NOT
STORE I NTO DATA REG I S T E R
RETU RN T O CALLE R
*E
* BSON - TURN ON RE AD/VE R I FY/PUNCH MECHAN I S M
* A IS VOLAT I LE
00877
00878
0 08 8 0A
0 0 8 8 1A
0 0 8 8 2A
0 0 8 8 3A
0 08 8 4A
0 0 8 8 sA
0 0 8 8 6A
0 0887A
BEQ
STA
RTS
FBO F
A
FB I B
FB I D
FBIF
FB21
FB22
FB 2 3
FB 2 4
FB 2 6
86
6D
26
4C
3F
OC
39
11
66
01
A BSON
A
FB22
B S ON 2
01
8F
A
A
LD A
TST
BNE
I NCA
SWI
FCB
INC
RTS
#$11
6,S
BSON 2
OUTC H
M I S F LG
SET RE A D CO DE
? READ OR VE R I F Y
BRAN CH YES
SET TO WRITE
PERFORM OUT PUT
F UNCT ION
SET LOAD IN PROG RE S S F L A G
RETU RN TO CALLE R
B S OF F - T U RN OF F READ/VERI FY/PUNCH ME CHAN I SM
* A , X VOLAT I LE
TO DC4 - ST OP
LDA
# $ 14
BSO F F
S E N D OUT
SW I
F U NC T I O N
OUTCH
FC B
CHANGE TO DC 3 ( X-OF F )
DECA
S E N D OUT
SW I
F U N CT I ON
OUTCH
FCB
C L E AR LOAD I N PROGRE SS F LAG
M I S F LG
DEC
DE LAY 1 SECOND ( 2 M H Z C LOC K )
LDX
#25000
COUNT DOWN
-l , X
BSO F LP LE AX
LOOP T I LL DONE
B SO F LP
B NE
RETURN TO CALLE R
RTS
*
FB27
FB29
F B 2A
FB2B
FB 2C
FB2 D
FB2E
FB 3 0
FB 3 3
FB 3 s
FB 37
86
3F
14
A
01
A
4A
3F
OA
8E
30
26
39
A
01
A
8F
A
61A8
A
IF
FB3 3
FC
*
00903
0 0904
00905
0 0906
00907
0090B
00909
*
*
*
*
*
*
0 0 9 1 1A FB 3 8 B E
0 0 9 1 2A FB3A 6 0
0 0 9 1 3 1\ F B 3 C 2 7
00914
00915
62
66
54
FB9 2
*
LDU
TST
2,S
6 ,S
BS D P U N
BEQ
DU R I NG READ/VER I F Y I
A BS DTA
A
*
*
OO!H6
00917
009 1BA PB3E
0 0 9 l 9A PB4 0
0 0 9 20 A P B 4 l
0 0 9 2 1A FB4 2
0 0 9 2 2 A E' B 4 4
0 0 9 2 3 ,\ E' B 4 &
B S DT A - READ/VER I FY/PUNCH HAN DLER
I N PUT : S + 6 =CODE BYTE , VERI F Y ( - l ) , PUNCH ( O ) , LOAD ( l )
S + 4 = START ADDRE S S
S+ 2 = STOP ADDRE S S
S+O - RETURN ADDRE S S
OUTPUT : Z - 1 NORMAL COMP LET I ON , Z - O I NVAL I D LOAD/VE R
REG I �T E RS A R E VOLAT I L E
*
32
3F
81
26
3F
70
A
IJ� DLL')l
00
53
FA
LEAS
SW I
FCU
A
A aSDLD2 CMPA
8NE
F B4 0
-3 , S
INCHNP
tIS
BS DLOl
SWI
8-53
U-TO ADDRE S S OR OF F S ET
? PUNCH
B RAN CH Y E S
S + 2 -Msn ADDRE S S SAVE BYTE
S + l - SYTE COU NT E R
S+O -CHECKSUM
U HOLDS O F F S ET
ROOM FOR WORK /COU NTER/C H E C K SUM
GET NEXT CH ARACT E R
FUNCT I O N
? START OF S l / S 9
DRAN CH NOT
GE'r N E X T CH ARACT E K
P AG E
018
0 09 24A
0 09 25A
0 0 9 26A
0 0 9 27A
009 28A
0 0 9 29A
009 30A
0 0 9 31A
00932
0 0 9 33A
0 0 9 34A
0 0 9 3 5A
0 0 9 36A
009 37A
00938
0 0 9 39A
00940A
0 0 9 4 1A
0 0 9 4 2A
0 0 9 43A
0 0 9 4 4A
0 0 9 4 5A
0 09 4 6A
ASS I ST0 9 . S A : 0
AS S I ST0 9 - M C 6 8 0 9 MON ITOR
FB47
FB48
FB4A
FB4C
FB4E
FBSO
FBS2
FBS4
81
27
81
26
6F
80
E7
00
39
22
31
F2
E4
21
61
A
A
FB6E
A
FB42
A
FB7S
A
FBS6
FBS8
F B SA
FB SC
FBSE
80
E7
80
A6
31
10
62
19
62
CB
FB7 S
A
FB7 S
A
A
FB60
FB62
FB64
1o� B 6 6
FB6S
Fa6A
FB6C
FB6E
80
27
60
2B
E7
El
27
35
13
OC
69
02
A4
AO
F2
92
0 0 9 4 8 A FB70
0 0 9 4 9 A FB7l
0 09 S 0 A FB73
4C
27
20
F UNCT I ON
? HAVE S9
YES , RETURN GOOD CODE
? HAVE NEW RE CORD
BRANCH IF NOT
C LEAR CH E C K S UM
OBTA I N BY TE COU NT
SAVE FOR DECRE M E N T
F87 S
FB70
A
FB6A
A
A
FB60
A
FCB
INCHNP
CMPA
i' 9
BSDSRT
BEQ
CMPA
i'l
BSDLD2
BNE
,S
CLR
BS R
BYTE
STB
1 ,S
* READ ADDRE S S
BYTE
BS R
STB
2,S
BS R
BYTE
2,S
LOA
LEAY
D,U
* STORE TEXT
BYTE
BS DNXT B S R
BSDEOL
BEQ
9,S
TST
BS DCMP
BM I
,Y
STB
BSDCMP CMPB
, Y+
BS DNXT
BEQ
BS DSRT P U LS
PC , X , A
CD
F9
FB4 0
FB6E
BS DEOL INCA
BEQ
BRA
? VA L I D C H E C K S U M
BRANCH Y E S
RETURN Z = O I NVAL I D
12
10
F B 8 9 BYTE
A
BYTH E X
#16
00
04
EO
89
62
62
63
FB89
A
A
A
A
A
A
BSR
LOB
MU L
BS R
PSHS
ADDA
TFR
ADDA
STA
DEC
BYTRTS RTS
BYTHEX
B
, S+
A,B
2,S
2 ,S
3 ,S
BYTH EX SW I
FCB
LBSR
BEQ
PULS
GET NEXT HEX
I N CH N P
CHARACT E R
CONVERT TO HEX
CNVHEX
BYTRTS
RETURN IF VAL I D H E X
PC , U , Y , X , A RET U RN TO CAL L E R WITH Z = O
00952
NEXT BYTE
BRANC H IF CHECKSUM
? VE R I F Y ON LY
Y E S , ONLY COMPARE
STORE I NTO ME MORY
? VAL I D RAM
Y E S , CONT I NU E RE A D I NG
RETURN W I T H Z SET PRO P E R
* BYTE BU I LDS 8 B IT VALUE F ROM TWO HEX D I G ITS
0 09 S 3A
009S4A
0 09 S SA
00956A
0 0 9 5 7A
009 S8A
0 09 59A
0 0960A
0 0 961A
0 0 9 6 2A
0 0 9 6 3A
FB 7 S
FB77
FB79
FB7A
FB7C
FB7E
FB80
FB82
FB84
FB86
FB88
80
C6
3D
80
34
AS
IF
AB
A7
6A
39
0 0 9 6 5A
0 09 6 6A
0 09 6 7 A
0 0968A
00969A
FB89
FB8A
FB8B
FB 8 E
FB90
3F
00971
0 09 7 2
00973
00974
00975
00976
0 0977A
0 0978A
0 0979A
00980A
BSDLDI
BS DSRT
OBTA I N H I G H VA LUE
SAVE IT
OBTA I N LOW VA LUE
MAK E D=VALUE
Y=ADDRES S+OF F S E'!,
17
27
35
A
00
0 1 04 F D 6 2
F8
FBS8
A
F2
* PUNCH STACK US E :
*
*
*
*
*
F B 9 2 DE
F B 9 4 AE
FB96 34
FB98 CC
F2
64
56
0018
A BS D P U N
A
A
A
LOU
LOX
PSUS
LDD
S + 8 =TO ADDRE S S
S+ 6 = RE T U RN ADDRE SS
S + 4 = S AV E D PAD D I NG VAL U E S
S + 2 F RO M ADDRE S S
S+ I = F RAME COU NT / C H E C K S U M
S + O = BYTE COUNT
VECTAB+ . PAD LOAD PAD D I NG VAL U E S
X= F ROM ADDRE S S
4,S
U,X,D
CREATE STAC K WORK AREA
SET A= O , B = 2 4
i24
8-54
IN
OBTA I N F I RST H E X
PRE P ARE S H I FT
OVE R TO A
OBTA I N S E CO N D HEX
SAVE H I GH HEX
COMB I N E BOTH S I DE S
S E N D BACK I N B
COMP UTE N E W CH E C K S U M
STORE BACK
DECREMENT BYTE COUNT
RET URN TO CALLER
PAGE
019
0 0 9 8 1A
0 0 9 8 2A
0 0 9 8 3A
0 0 9 8 4A
0 0 9 8 5A
0 0986
0 0 9 8 7A
0 0988A
0 0 9 8 9A
0 0 9 9 0A
0 0 9 9 1A
0 0 9 9 2A
0 0 9 9 3A
0 0 9 9 4A
0 0 9 9 5A
0 0996
0 0997A
0 0998A
0 0999A
01000
O lO O lA
0 1 0 0 2A
0 10 0 3A
01004
0 1 0 0 5A
0 1006A
0 10 0 7
0 10 0 8A
0 10 0 9 A
O lO l OA
O lO l lA
0 10 1 2A
0 10 1 3
01014A
0 1 0 1 5A
0 10 1 6A
0 1 0 1 7A
0 1 0 1 8A
0 10 1 9A
0 1020A
0 1 0 21A
O l0 22A
0 10 2 3A
0 1024A
0 10 2 5A
0 10 26 A
0 10 27A
AS S I ST 0 9 - M C 6 8 0 9 MON I TOR
AS S I ST0 9 . SA : 0
07
3F
F2
A
01
04
F2
A
A
A
FB 9 B
FB 9 D
FB9E
FB9F
FBAl
C6
DD
FBA3
F BA 5
FBA7
FBAB
FBAD
FBAF
FBB O
FBB2
FBB 4
68
EC
62
A3
1083 0018
02
25
17
C6
5C
E4
E7
03
CB
61
E7
FBB 6 3 0
FBB 9 3 F
FBBA
A
A
A
FBAF
A
A
A
A
8C 33
03
A
FBBB S F
FBBC 30
FBBE 80
61
27
A
FBE7
FBC O 8 0
FBC 2 8 0
25
23
FBE 7
FBE7
FBC 4
FBC 6
FBC 8
FBCA
F acc
AE
80
6A
26
AF
62
lF
E4
FA
62
A
FBE 7
A
FBC6
A
FBCE
FBCF
FBDl
FBD3
FBD5
F B D7
F B D9
F B DB
F B DE
F B DF
FBEO
FBE2
FBE4
FBE 5
53
E7
30
8D
AE
AC
24
30
3F
A
61
A
61
FBE9
14
A
68
A
62
F BA3
C8
BC 1 1
EC
DD
4F
35
03
64
F2
A
A
A
06
A
VECTAB+ . PAD SETUP 24 CH ARACTER PADS
ST8
S E N D NU LLS OUT
SWI
FUNCT ION
OUTC H
FCB
SETU P NEW L I N E PAD TO 4
LDB
t4
VECTAB+ . P AD SETUP PUNCH PADD I NG
STD
* CALCULAT E S I Z E
LOAD TO
8 ,S
LDD
BS PGO
M I N U S F ROM= LENGTH
2 ,s
SUBD
? MORE TH AN 2 3
# 24
CMP D
NO , OK
BS POK
B LO
FORCE TO 2 3 MAX
#23
LDB
P RE PARE CO U NT E R
I NC B
BS POK
,S
STORE BYTE COU NT
STB
ADJ UST TO F RAME CO U NT
#3
ADDB
SAVE
l ,s
STB
* PUNCH C R , L F , NU LS , S , l
< B S PSTR , PCR LOAD START RE CORD HEADER
LEAX
SEND OUT
SWI
PDATA
F UN C T I O N
FCB
* S E N D F RAME COUNT
I N I T I AL I Z E C H E C K S U M
C LRB
PO I NT TO F R�E COUNT AN D ADDR
LEAX
l,s
S E N D F RA M E CO U NT
BS P U N 2
BSR
* DATA ADDRE S S
S E N D ADDRE S S H I
BS PU N 2
BSR
S E N D ADDRE S S LOW
BS P U N 2
BS R
* PUNCH DATA
LOAD START DATA ADDRE S S
2,s
LDX
S E N D OUT N E X T BYTE
BS P U N 2
BS PMRE B S R
? F I NAL BYTE
,s
DE C
LOOP I F NO'l' DONE
BS PMRE
BNE
U P DATE F ROM ADDRE S S VALU E
2,s
STX
* PUNCH CH E C K S U M
COMPLEMENT
COMB
STORE FOR S E N DOUT
l ,s
STB
PO I NT TO I T
l ,s
LEAX
S E N D OUT AS H E X
BSPUNC
BS R
LOAD TO P ADDRES S
8,s
LDX
? DON E
2,s
CMPX
BRANCH NOT
BS PGO
BH S
< B S PEO F , PCR PRE PARE E N D OF F I LE
LEAX
S E N D OUT STR I NG
SW I
P DATA
FUNCT ION
FCB
RE COVER PAD COUNTS
LDD
4,s
STD
VECTAB+ . P AD RESTORE
SET Z = l FOR OK RET U RN
CLRA
PC , U , X , O RETU RN W I T H OK CO DE
PULS
0 1 0 2 9 A F B E 7 EB
0 1 0 30A FBE9 16
A BS PUN 2 ADDB
84
F D E D F 9 D9 BSPUNC LBRA
0 1 0 3 2A FBEC
0 10 3 3A FBEF
0 10 3 4 A FBF 9
53
53
00
01036
A BS PSTR FCB
A BS PEOF FCC
FC B
A
,X
ZOUT 2 H
ADD TO C H E C K S U M
S E N D OUT A S H E X AN D RETU RN
' S , ' l , EOT CR , LF , N U L L S , S , l
/S 9.0 3 0 0 0 0 FC/EOF STRI N G
C R , L F , EOT
* H S DTA - H I G H S P E E D P R I NT ME MORY
8-55
P AG E
020
AS S I ST 0 9 . SA : 0
ASS I S T0 9 - M C 6 8 0 9 MON I TOR
*
0 10 37
0 10 3 8
01039
0 10 4 0
01042
0 10 4 3A
0 10 4 4 A
0 1 0 4 SA
0 10 4 6A
0 10 4 7 A
0 10 48A
0 1 0 49A
O lO SOA
O l O S lA
0 1 0 S 2A
0 10 S 3A
0 1 0 S4A
O lO S SA
0 10 S6A
0 10 S7A
0 10 S8 A
0 10 S9A
0 10 6 0 A
0 10 6 1A
0 1 0 6 2A
0 10 6 3A
0 10 6 4A
0 10 6 SA
0 10 6 6A
0 10 6 7A
0 10 6 8A
0 1069A
0 1 0 7 0A
O l O 7 lA
O l o nA
0 10 7 3A
0 1 0 7 4A
0 1 0 7 SA
0 10 7 6A
O l 0 77A
0 1078A
0 10 7 9 A
0 10 8 0A
0 1 0 8 1A
0 1 0 8 2A
0 10 8 3A
0 10 84A
0 1 0 8 SA
0. 1 0 8 6 A
0 1087A
0 10 8 8 A
0 1089A
0 1 0 9 0A
0 1 0 9 1A
0 1 0 9 2A
0 10 9 lA
0 1 0 9 4A
*
*
*
FBFC
FBF D
FBF E
FC O O
FC O l
FC 0 2
FC 0 3
FC O S
FC 0 6
FC 0 8
FCO B
FC O C
FC O D
FCOE
FC O F
FC 1 0
FC1 2
FC 1 4
FC 1 5
FC 1 6
FC 1 8
FC1A
FC I B
FCIC
FC I E
FC 2 0
FC 2 1
FC 2 2
FC 2 3
FC 2 S
FC 2 6
FC 2 7
FC29
FC2B
FC 2 D
FC 2 F
FC 3 l
FC l 3
FC 3 S
FC 3 6
FC 3 7
FC 3 8
FC3A
FClC
FC 3 E
FC40
FC4 2
FC 4 3
FC 4 5
FC 4 7
FC 4 8
FC49
3F
C6
3F
SA
26
SF
lF
17
3F
3F
SC
Cl
25
IF
25
30
3F
AE
C6
3F
SA
26
IF
AE
C6
A6
2B
81
24
86
3F
SA
26
AC
24
AF
A6
48
26
20
IF
19
S + 4 = START ADDRE SS
S + 2 = STOP ADDRE S S
S+O = RE T U RN ADDRE S S
X , D V<? L AT I LE
I N PUT :
*
S E N D T I T LE
SW I
H S DT A
PCRLF
A
FCB
06
#6
LOB
A
06
H S B LN K SW I
S PAC E
FCB
07
A
DE C B
HS B LNK
BNE
FCO O
FB
C LR B
B ,A
A HSHTTL TFR
98
ZOUTHX
LBS R
F DDB F 9 E 6
SW I
A
S PAC E
FCB
07
SWI
FCB
S PACE
A
07
10
F2
A
FC0 6
06
2F
64
A
FC47
A
05
64
10
A
A
A
04
A
FB
FC20
INCB
CMPB
B LO
H S U L N E SW I
FCB
BC S
LEAX
# $10
HS HTTL
PCRLF
H S D RTN
4 ,S
SW I
FeB
OUT 4 H S
LDX
4,S
#16
LDB
H S H NXT SWI
07
64
10
80
04
20
02
2E
01
Fl
62
09
64
65
CF
B5
06
A
A
A
FCB
DE C B
OUT 2 H S
BNE
H S H NXT
SW I
FCB
S PACE
LOX
LOB
A H S H C H R LDA
BM I
FCl l
A
CMPA
BH S
FC3 S
A H S H DOT L DA
HSUCOK SWI
FCB
A
DE C B
BNE
FC2 B
A
C PX
FC4 7
A
A
BHS
STX
FC 1 4
8NE
FBFC
LOA
AS LA
BRA
H S DRT N SW I
A
FCB
RTS
4 ,S
#16
, X+
HSH DOT
#'
HSHCOK
#'
•
OUTC H
SEND NEW L I N E
FUN C T I ON
PRE PARE 6 SPAC E S
S E N D BLAN K
FUNCT ION
COUNT DOWN
LOOP IF MO RE
SETU P BYTE COUNT
PRE PARE FOR CONVERT
CONVE RT TO A HEX DIG IT
SEND BLANK
FUNCT ION
SEND ANOT H E R
B LANK
UP ANOTH E R
? PAST
'F'
LOOP U NT I L SO
TO NEXT L I N E
F UNCT ION
RE'rURN I F U S E R ENTERED CTL- X
PO I NT AT ADDRESS TO CONVERT
PRI NT OUT ADDRE S S
F UNCT ION
LOAD ADDRE S S P RO P E R
NEXT S I XT E E N
CONVERT BYTE TO HEX AN D S E N D
F U N CT I ON
COUNT DOWN
LOOP I F NOT S I XTEENTH
SEND BLANK
F UNCT ION
RE LO AD F RO M ADDRE S S
COU NT
NEXT BYTE
TOO LARG E , TO A DOT
? LOWER TH AN A BLANK
NO , BRANCH OK
CONVERT I NVAL I D TO A BLANK
S E N D CHARACT E R
FUNCT ION
? DON E
HSHCHR
2,S
H S DRTN
4 ,S
5,S
HSHLNE
H S DTA
PCRLF
8-56
BRANC H NO
? PAST LAST ADDRE S S
QU I T IF SO
U P DAT E F ROM AD DRE S S
LOAD LOW BYTE ADD RE S S
? TO SECT I O N BOU N DRY
BRANCH I F NOT
BRAN CH IF SO
S E N D NEW L I N E
FUNCT ION
RETURN TO CALLER
PAG E
021
ASS I ST0 9 . S A : 0
AS S I ST0 9 - MC 6 8 0 9 MON I TOR
01095
*F
01097
0 10 9 8
0 10 9 9
***********************************************
A S S I S T 0 9
C O M M A N D S
*
***********************************************
0 1101
0 1 1 0 2 A FC 4 A 8 D
23
0 1 1 0 3 A FC 4 C 4 C
0 1 1 0 4A FC 4 D 8 D
0 1 1 0 5 A FC 4 F 3 9
21
* * * * * * * * * * * * * REG I ST E RS
BSR
FC 6 F CREG
REG P RT
I NCA
BSR
FC7 0
REGCHG
RTS
0 1107
0 1 10 8
0 1109
0 11 1 0
0 1111
01112
0 1113
0 1114
01115
0 1116
0 1117
0 1118
0 1119
01120
0 1121
0 1122
0 1 1 2 3A
0 11 24A
0 1 1 2 5A
0 1126A
0 1127A
0 1128A
0 1129A
0 1130A
0 1 1 3 1A
0 1 1 3 2A
FC 5 0
FC 5 4
FC57
FC5A
FC S D
FC6 0
FC 6 3
FC 6 6
FC6A
FC 6 E
0 1 1 3 4A
0 1 1 3 SA
0 1 l 3 6A
01l37A
01l38A
0 1 1 3 9A
O 1l40A
0 11 4 1A
0 1 l 4 2A
O 1 l 4 3A
O 1 l 4 4A
O 1 l4 SA
O 1l46A
0 1l47A
01l48A
FC 7 0
FC 7 3
FC 7 S
FC 7 8
FC7A
FC 7 B
FC 7 D
FC 7 E
FC 7 F
FC 8 1
FC 8 3
FC 8 4
FC 8 S
FC 8 7
FC 6 F 4 F
30
34
31
EC
40
2F
3F
20
86
3F
30
60
50
41
42
58
59
A
55
53
43
44
00
A
A
A
A
A
A
A
A
A
********************************************
*
REG PRT - PRI NT/CHANGE REG I S T E RS SUBROUT I N E
* WI L L ABORT TO ' C MDBAD ' I F OVERF LOW DETECT E D DUR I NG
* A CHANGE OPERAT I O N .
CHANGE D I S P LAYS REG I STERS WHE N
*
DONE .
* REG I ST E R MASK L I ST CON S I STS OF :
* A ) C HARACTE RS DENOT I NG REG ISTER
B ) Z E RO FOR ONE BYTE , - 1 FOR TWO
*
C ) O F F S ET ON STACK TO REG I S'r E R POS I T I ON
*
* I N P UT : S P + 4 = STACK E D REG I STERS
A= O PRI NT , At O PRI NT AND CHANGE
*
* OUT PUT : ( ON LY POR REG I STER D I S P LAY )
C = l CONTROL-X EN'rERE D , C = O OTH E RW I S E
*
* VOLAT I LE : D , X ( CHANGE )
*
B , X ( D I S P LAY )
*******************************************
' P , ' C , - 1 , 1 9 PC REG
REGMS K F C B
A REG
FCB
' A , 0 , 10
B REG
' B,0 ,11
FCB
' X , - 1 , 1 3 X REG
FCB
FCB
' Y , - 1 , 1 5 Y R� G
FCB
' U , - 1 , 1 7 U RE G
FC B
' 5 , -1 , 1
S REG
FCB
' c , ' C , 0 , 9 C C RE G
' D , ' P , 0 , 1 2 DP REG
FC B
0
FC B
E N D OF L I ST
REG P RT
E8
32
8C
AO
10
A
A
A REG P 1
FC 8 1
01
F7
20
FC 7 S
01
E5
E4
A
A RE G P 2
A
A
A
CLRA
RE G C HG L EAX
08
04
- D I S PLAY AN D CHANGE REG I ST E RS
PRINT REG I STERS
S E T FO R CHANGE FUNCT ION
GO CHANGE , D I S P LAY REG I S'r E RS
RETURN TO COMMAND PROCESSOR
PSHS
LEAY
LD D
TSTA
BLE
SW I
FC B
B RA
LOA
SW I
FCB
LEAX
TST
SETUP
P R I NT ONLY F LAG
READY STACK VALUE
SAV E ON STACK WITH OPT I O N
y , X ,A
REGM S K , PC R LOAD REG I S T E R MAS K
LOAD NEXT CHAR OR < - 0
, Y+
? END OF CH ARACTE RS
BRANCH NOT CH ARAC T E R
RE G P 2
S E N D TO CONSOLE
F U N C T I O N B Y TE
OUTCH
C H E C K NEXT
RE G P 1
READY ' - '
#'S E N D OUT
W I T H OUTCH
OUTCH
X- > REG I ST E R TO P R I NT
B,S
,S
? C H ANGE OPT I O N
4+12 , S
8·57
PAG E
022
AS S l I:iT0 9 . SA : 0
0 1 l 4 9A
0 1 l 50A
0 1 l 5 1A
0 1 l 5 2A
O 1 l 5 3A
0 1 l 54A
O 1 l55A
0 1 l 56A
0 1l 5 7A
0 1 l 5SA
0 1 l 59A
O 1 l 60A
O l l 6 lA
O 1 l 6 2A
FC S 9
FC S B
FC S O
FC S F
FC90
FC 9 l
FC 9 2
FC 9 3
FC 9 4
FC 9 6
FC 9 7
FC 9 9
FC 9 A
FC 9 B
26
60
27
3F
O 1 l 64A
0 1 l65A
O1l66A
O 1l67A
O1l6SA
0 1l69A
0 1l 70A
O l l 7 1A
O l l 7 2A
O 1 l 73A
0 1l 7 4A
0 1 l 7 5A
0 1 l 76A
O ll 77A
01178
0 1 l79A
O l l SOA
O ll SlA
0 1 l 8 2A
0 1 l 8 3A
0 1 1 S 4A
0 11 8SA
FC 9 0
FC 9 F
FCAl
FCA3
FCA 5
FCA7
FCAS
FCA 9
FCAA
FCAB
FCAC
FCAD
FCAF
FCBl
SO
27
Sl
27
E6
SA
50
5S
3F
3F
EC
SO
26
3F
35
12
3F
03
FC 9 0
A
FC 9 2
05
SC
A
A
04
AO
A
A
OF
FC7S
06
B2
A
A
40
10
00
lE
3F
07
SA
26
20
A7
FC B 3
FC B S
F CB 7
F CB 9
FCB B
FCB D
FCBF
DC
60
26
A6
ED
A6
81
0 1 1 8 6 A FCC l 26
ASS I ST0 9 - M C 6 8 0 9 MON I TOR
FB
E3
E4
9B
3F
02
82
84
E4
00
01
FCOF REGCNG BS R
BEQ
FCBl
A
C M PA
FCC 3
BEQ
A
L OB
OE CB
NEGB
AS L B
R E G S K P SWI
A
FCB
DECB
BN E
F C AA
B RA
FC9 4
A RE G N XC ST A
0 1203
0 1204
01205
FC C 3
FCC 7
FCC 9
FCCB
FCC D
FCCE
F C DO
F C D4
F C D6
FC D8
FC DA
F C DB
FC DD
30
C6
35
A7
SA
26
10EE
C6
A6
34
SA
26
20
A
A
FCBB
A
A
A
A
FC 9 4
80 E28A
15
A
A
02
80
A
F9
FCC9
8 8 EC
A
15
A
82
A
A
02
F9
BC
REGC NG
-l , Y
REG P 3
BRANCH YE S
? O N E OR TWO BYT E S
BRAN C H Z E RO M E A N S ON E
P E RF O RM WORD HEX
OUT4 H S
FU N CT I O N
SK I P BYTl-� P R I NT
SKI P2
P E RFORM BYTE HEX
FUNCT ION
OUT2ffS
TO FRONT OF N E X T ENTRY
, Y+
? E N D OF ENT R I E S
LOO P I F MORE
RE G P l
FORC E NEW L I N E
F UNCT ION
PCRLF
PC , y , X , A RESTORE STACK AN D RE TU RN
BLDNNB
REGNXC
t CR
RE GAG N
-l , Y
S PAC E
REG S K P
REG 4
,S
FCD6
FC9 B
I N PUT B I NARY NUMBER
I F CHANGE TH E N JUMP
? NO MORE DE S I RE D
BRANCH NOP E
LOAD S I Z E F LAG
M I N U S ONE
MA K E PO S I T I V E
T I ME S TWO ( = 2 OR = 4 )
PERFORM S PAC E S
F U NCT I O N
LOOP I F MO R E
CONT I NUE W I T H NEXT REG I ST E R
SAV E DE L I M IT E R I N OPT I O N
( ALWAYS >
*
0 1187
0 1188
0 11 89A
0 11 90A
0 1 1 9 lA
0 1 l 9 2A
0 1 1 93A
0 11 94A
0 1 l 9SA
0 11 96A
0 1 1 97A
0 1 1 98A
0 1 1 99A
0 1 200A
0 1 2 0 1A
BU E
TST
BEQ
SWI
FCB
FCB
REGP 3
SW I
FCB
REG 4
LOO
TSTB
BNE
SW I
FCB
REGRTN P U LS
0)
LDD
OBTA I N B I NARY RE S U LT
N UMB E R
TST
? TWO BYT E S WORTH
-l , Y
B NE
RE G TWO
BRAN CH YES
L OA
SETUP FOR TWO
, -X
STORE I N NEW VALUE
REGTWO STD
,X
LOA
RECOV E R D E L I M IT E R
,S
? E N D O F CHANGES
CM PA
tCR
BNE
NO , K E E P O N TRUCK ' N
RE G 4
* MOVE STAC K E D DATA TO NEW STACK I N CASE STACK
* PO I NTER HAS CHAN G E D
TSTAC K , PCR LOA D TEMP AREA
REGAGN LEAX
LOB
LOAD COU NT
# 21
NEXT B Y TE
REGTF l PULS
A
STA
STORE I NT O T E M P
, X+
DECB
COU NT DOWN
BNE
LOO P I F MORE
RE GT F l
LOS
LOAD NEW STACK PO I NTER
... 2 0 , X
LOB
LOAD COUNT AG A I N
#21
REGT F 2 LOA
NEXT T O STO RE
, -X
BACK ONTO N E W S T A C K
PSRS
A
COUNT DOWN
DECB
RE G T F 2
LOO P IF MORE
BNE
GO RE START COMMA N D
RE G RTN
BRA
*********************************************
BLDNUM - B U I LDS B I NARY VAL U E F RO M I N P UT H E X
*
TH E ACT IVE E X P RE S S ION HAN DLER I S U S E D .
*
B·58
PAGE
023
AS S I ST 0 9 . S A : 0
* I NPUT : S=RE T U RN ADDRES S
* OUTPUT : A= DE L I M IT E R WH I CH TE RM I NAT E D VALUE
( I F DELM NOT Z E RO )
*
n NU MB E R " =WORD B INARY RE S U LT
*
Z = 1 I F I N P UT RE C I EVED , Z = O I F NO HEX REC I E VED
*
REG I STERS ARE TRAN S PARENT
*
**********************************************
0 1206
0 1207
01208
0 1209
0 1210
01211
0 1212
01214
0 1215
01216
0 1217
0 1218
0 12 1 9A
0 1220A
Q 1221
0 1 2 2 2A
0 1223A
0 1224A
0 12 2 6
0 1227
01228
0 1229
0 1230
0 1231
0 1 2 3 2A
0 12 3 3A
0 1234A
01235
0 1236A
0 1237A
0 12 3 8
01239A
01240A
0 1 2 4 1A
0 1 2 4 2A
0 1 2 4 3A
0 1244A
0 1245A
0 1246A
0 1247A
0 1248A
0 1249
0 1250A
0 1 2 5 1A
0 1 2 5 2A
01253
0 12 5 4A
0 1 2 5 5A
0 1 2 5 .6 A
0 1257A
0 1258A
01259
0 1 2 6 0A
0 1 2 6 1A
0 1 2 6 2A
0 1 2 6 3A
AS S I ST0 9 - M C 6 8 0 9 MON ITOR
FC DF 4 F
FCEO
8C
FCE1 8 6
FCE 3 9 7
FCE 5 6 E
20
8E
9D
* EXE CUTE S I NGLE O R EXTEN D E D ROM EXPRE S S I O N HAN DLER
*
* THE F LAG " DE L I M n I S US E D AS FOLLOWS :
*
DE L I M = O
N O LEAD I N G B LANK S , N O F O RC E D 'rE RM I N A'rOR
*
DE L I M =CHR ACC EPT LEAD I NG ' CH R ' S , FORC E D TERM I NATOR
NO DYNAM I C DE L I M I T E R
BLDNNB CLRA
A
SKIP2
S K I P NEXT I NSTRUC'r r ClII
FCB
* B U I L D WITH LEAD I NG B LANK S
#'
ALLOW LEAD I N G B LANK S
A BLDNUM LDA
STORE A S DEL I M IT E R
DE L I M
STA
A
[ V ECTAB+ . E XPAN , PC R ] TO EXP ANALY Z E R
JMP
E3 0 3
FC E 9 3 4
FCEB 8 0
FCED 2 7
14
5C
18
A
FD49
F D0 7
FCEF 9 1
FCF 1 2 7
8E
F8
A
FCEB
FCF 3
FCF 5
FCF 7
FC F 9
FC F B
FCF D
FCFF
F OO l
F D0 3
F D0 5
9E
81
27
9E
81
27
9E
81
27
35
9E
40
16
93
50
10
AO
57
OA
94
A
A
FDOF
A
A
FDOF
A
A
FDOF
A
FD07 8D
FD09 27
F DO B 2 0
44
FC
OA
FD4 D
FD07
F D1 7
FDO D
F DO F
FDll
FD13
FD15
AE
9F
OD
27
8D
84
9B
8E
FO
62
A
A
A
F D0 5
F D7 9
FD17
F D1 9
F OIB
F D1 D
9E
81
26
8D
9B
2B
OE
23
A
A
FD2B
F 04 2
* TH I S I S 'rH E DEFAU L'f S I NG L E ROM ANALY Z E R . WE ACC E PT :
1 ) HEX I NP UT
*
2 ) ' M ' F O R LAS 'r MEMORY EXAM I N E ADDRE S S
*
3 ) ' P ' F O R PROG RAM COU NTER ADDRE S S
*
4 ) ' w ' F O R W I N DOW VAL U E
*
5 ) ' @ ' FOR I N D I RECT VALU E
*
X,B
S AVE REG I STERS
PSHS
EXPl
C L E AR NUMBE R , CHECK F I RST CHAR
BLDHX I
EXPDLM B S R
IF HEX DIG IT CONT I NU E BU I L D I NG
EX P2
BEQ
* SK I P B LANK S I F DE S I KE D
DE L I M
? C ORRECT DE L I M IT E R
CMPA
Y E S , I GNORE rr
EXP DLM
BEQ
* TEST FOR M OR P
DEF AU LT FOR ' M '
ADDR
LOX
? r-I E MO RY EXAM I N E ADDR WANTE D
#'M
CMPA
BRANCH I F SO
EXPTDL
BEQ
PCNT E R
DE F AU LT F O R ' P '
LOX
#'P
? LAST PROGRAM COUNT E R WAN T E D
CMPA
BRANCH I F SO
EXPTDL
BEQ
D E F AU LT TO W I N DOW
W I N DOW
LOX
#'W
? W I N DOW WANTEU
CMPA
EXPTDL
BEQ
PC , X , B
RETU RN AN D RESTORE REG I ST E RS
EXPRTN P U LS
* GOT HEX , NOW CONT I N U E BU I L D I NG
COMPUTE NEXT D I G I T
BLDHEX
EXP2
BSR
CONT I NU E I F MORE
EXP2
BEQ
S EARCH FOR +/E X P C DL
BRA
* STORE VALUE AN D CHECK I F N E E D DEL I M I T E R
IN D I RECT ION DE S I RE D
,X
EXPT D I LDX
STORE RE S U LT
NUMBER
EXPTDL STX
DE L I M
? T O FORC E A DE L I M IT E R
TST
RETU RN I F NOT WITH VALUE
E X P RTN
BEQ
OBTA I N NEXT CHARACTE R
READ
BS R
* TEST FOR + OR EX PCDL LOX
NUM B E R
LOAD LAST VALUE
#'+
? ADD OPERATOR
CMPA
EX PCHM
BNE
B RANC H NOT
EXPTRM
BSR
COMPUTE NEXT T E RM
8-59
PAGE
024
0 1 2 6 4A
0 1 2 6 5A
0 1 2 6 6A
0 1 267A
0 1268A
0 1269A
0 1 2 7 0A
0 1 2 7 1A
0 1 2 7 2A
0 1 2 7 3A
0 1 2 7 4A
0 1 2 7 5A
01276A
0 1277A
0 1278A
0 1279A
0 1 2 80A
0 1 2 8 1A
0 1 2 8 2A
0 1283
0 1284
01285
0 12 86A
0 1 2 87A
0 1 288A
0 1290
0 1291
0 1292
0 12 9 3
0 1 2 94
0 1295
0 1296
01297
0 1298
0 1 2 99A
0 1300A
0 13 0 1A
0 1 3 0 2A
0 1 3 0 3A
0 1 3 0 4A
0 13 0 5A
0 1 3 0 6A
0 1307A
0 1 3 0 8A
0 1309A
0 1 3 10A
0 1 3 1 1A
0 1 3 1 2A
01314
0 13 1 5
01316
0 1317
01318
0 1319
ASS I ST0 9 . SA : 0
F DI F
FD21
FD23
FD25
F D2 7
F D29
FD2B
FD2 D
FD2F
FD31
FD33
FD34
F D3 6
FD38
F D3A
F D3 C
FD3D
F D 3E
FD40
34
DC
30
9F
35
20
81
27
81
27
SF
20
80
34
DC
40
50
82
20
F D4 2 8 0
F D 4 4 27
F D4 6 1 6
FD49
F D4 B
F D4 D
F D4 F
FD51
F D5 3
FOSS
F DS 6
F D5 8
FDS9
F DS B
FDSD
F DS E
F D6 0
OF
OF
80
80
26
C6
3D
86
58
09
09
4A
26
20
AS S I ST0 9 - M C 6 8 0 9 MON I TOR
02
9B
8B
9B
02
EC
20
07
40
DA
A
A
A EX PADD
A
A
F01 7
A EXPCHM
FD36
A
FOO D
CF
OA
02
9B
F DO S
F D4 2
A
A
00
El
A
FD23
FCEl
90
F D7 8
32
FC1 3 F 9 5 C
A
9B
9C
2A
11
25
10
A
FD7 9
F D6 2
FD7 8
A
04
A
9C
9B
A
A
F8
14
FD58
F D7 6
A
SAVE DE L I M I T E R
PSHS
LDD
NUMBE R
LOAD N E W T E RM
LEAX
D,X
ADD TO X
NUMB E R
STORE AS NEW RE S U LT
STX
A
RE STO RE DE L I M I 'r E R
PULS
BRA
E X P C DL
NOW T E S T IT
C M PA
#'? S U BTRACT O P E RATOR
BEQ
EXPSUB
BRANC H I F SO
? I N D I RE C T I O N DE S I RE D
CMPA
#'@
BEQ
E X PT D I
BRANC H I F SO
SET DE L I M IT E R RETURN
C LRB
EXPRTN
AN D RET U RN TO CALLE R
BRA
EXPTRM
OBTA I N NEXT T E RM
EXPSUB BSR
A
SAV E DE L I M I T E R
PSHS
NUMB E R
LOAD UP NEXT TERM
LDD
NEGATE A
NEGA
NEGATE B
NEGB
SBCA
#0
CORRECT FO R A
EX PADD
GO ADD TO E X P RE S ION
B RA
* COMPUTE NEXT EX PRES S I ON T E RM
* OUTPUT : X=OLD VALU E
*
' N UMB E R ' =NEXT TE RM
EX PTRM a S R
B LDNUM
OBTAI N N E X T VAL U E
CNVRTS
RETU RN I F VAL I D NUMBER
BEQ
BLDBAD LBRA
CMD�AD
ABO RT COMMAN D I F I NVAL I D
*********************************************
*
BU I L D B I NARY VALU E U S I NG I N PUT CHARACT E RS .
* I N PUT : A=AS C I I HEX VALUE OR DE L I M IT E R
S P + O = RETURN ADDRES S
*
S P+ 2 = 1 6 B I T RE S U LT AREA
*
* OUTPUT : Z = l A= B I NARY VALUE
Z = O I F I NVAL I D H E X CHARAC T E R ( A UNCHANG ED )
*
* VOLAT I LE : 0
****************************************
CLEAR NUMB E R
B L DH X I C LR
NUI-t B E R
NUMBER+ ! CLEAR NU M B E R
CLR
GE'l' I l� P UT CHARACT E R
RE AD
B LDHEX BSR
CO NVERT AN D T E S T CHARACTER
CNVHEX
B L DHXC B S R
RE T U RN IF NOT A NUMBER
CNVRTS
BNE
PRE PARE S H I F'!,
LOB
#16
BY FOUR P LAC E S
MUL
LOA
ROTATE B I NARY I NTO VALU E
#4
BLDS H F AS L B
OBTAI N N E X T � I T
NUM B E R+ l I NTO LOW BYTE
ROL
NUMBER
I NTO H I BYTE
ROL
DECA
COUNT DOW�
BLDSHF
BRANC H I F MORE TO DO
BNE
SET GOOD RET U RN CO DE
CNVOK
B RA
****************************************
* CONVERT ASC I I CHARACT ER TO B I NARY BYTE
* I NP UT : A=AS C I I
* O UTPUT : Z = l A=B I NARY VALUE
Z = O I F I NVAL I D
*
* ALL REG I ST E RS TRAN S PARENT
8-60
PAG E
025
0 1320
0 1321
0 1 3 2 2A
0 1323A
0 1 3 2 4A
0 1 3 2 5A
0 1 3 2 6A
01327A
01328A
0 1 3 2 9A
0 1 3 3 0A
0 1 3 3 1A
0 1 3 3 2A
0 13 3 3A
01335
0 1 3 3 6A
0 1337A
0 1 3 3 8A
0 1 3 3 9A
01340A
01341
AS S I ST0 9 . SA : 0
F D6 2
FD64
F D6 6
F D6 8
F D 6A
FD6C
FD6E
F D7 0
F D7 2
F D7 4
F 07 6
F D7 8
81
25
81
2F
81
25
81
22
80
84
lA
39
F D7 9
F D7 A
F 07 B
F D7 D
F D7 F
3F
81
27
39
01343
0 1 3 4 4 A F D8 0 8 0
0 1 3 4 5 A F 08 2 3 8
01347
0 13 4 8
01349A
0 13 5 0A
0 1 3 5 1A
01352
0 13 5 3
0 1 3 5 4A
0 1 3 5 5A
0 13 5 6 A
01357A
01358A
0 13 5 9A
0 1360A
0 1 3 6 1A
0 1 3 6 2A
0 1 3 6 3A
0 1 3 6 4A
0 1 3 6 5A
01366
013 6 7A
0 1368A
01369A
0 1 3 7 0A
30
12
39
OA
AS S I ST0 9 - M C 6 8 0 9 MON I TOR
A
FD78
A
F D7 4
41
A
46
06
07
OF
04
FD7 8
A
FD7 8
A
A
A
OA
00
18
C7
* GET I N P U T CHAR , ABORT COMMAN D I F CONTROL-X ( C AN C E L )
SW I
READ
GET NEXT CHARAC TER
I NCH N P
A
F U NCT I O N
FCB
? ABORT CO M M A N D
A
I C AN
CM PA
B LDBAD
F046
BRANCH TO AB O RT I F SO
BEQ
RETURN TO CALLER
RTS
*0
01
* * * * * * * * * * * * * * * GO - START PROGRAM EXECUTION
F D8 3 CGO
GOADDR
BU I L D ADDRE S S IF NEEDED
BSR
START EX E C UT I N G
R',I' I
A
F D8 3 3 5
F 08 5 3 4
F D8 7 2 6
30
10
19
F 08 9
F D8 C
F D8 E
F D8 F
F D9 1
F D9 3
F 09 5
F 09 7
F 09 9
F D9 B
0186 FF42
A
6C
17
AE
SA
2B
A6
AC
26
81
26
97
16
30
Al
F7
3F
02
A
F DA2
F DA 7
A
A
F 08 E
A
F D9 0
A
F D9 D O C
FB
8F
F D9 F 1 6
0 1 0 6 F EA 8
F DA2 1 7
F OA5 E D
F OA7 1 7
O O BB
FE60
C9
F 07 8
84
30
A
F OAA 0 0
O 1 3 7 1A F OAC SA
0 1 3 7 2A F OAD 2B
0 1 3 7 3 A F OAF A6
0 1 3 7 4 A F DB l A7
* ( A UNALTERED I F I NVA L I D HEX )
* * * * * * * * * * * * * * * * * * * * * * *- * * * * * * * * * * * * * *
? LOW E R THAN A Z E RO
CNVHE X CMPA
1'0
BRANCH NOT VALUE
CNVRT S
BLO
#'9
? POS S I B LE A-F
CMPA
CNVGOT
BRANCH NO TO ACCEPT
BLE
# 'A
? LESS TH EN TEN
CMPA
CNVRTS
RETURN I F . M I NUS ( I NVAL I D )
BLO
I'F
? NOT TOO LARGE
CM P A
CNVRTS
NO , RETURN TOO LARG E
BH I
DOWN TO B I NARY
S U BA
#7
I$OF
C LEAR H IGH H E X
CN VGOT AN DA
CNVOK ORCC
FORC E Z E RO ON FOR VAL I D H E X
14
RETURN TO CALLER
CNVRTS RTS
A
A
6C
019 8 FF4 2
A
FA
A
* F I N D OPT I ONAL N E W PROGRAM COUNTE R . ALSO A�� TH E
* B REAKPO I NTS .
GOA D DR PULS
RECOVER RET U RN ADDRE S S
Y,X
STORE RETURN BAC K
PSHS
X
I F N O CA RR I AG E RETURN TH E N NEW P C
BNE
GON DF T
* DEFAULT PROGRAM COUNTE R , SO FALL T H RO UG H I F
* I MM E D I ATE BREAKPO I NT .
L BS H
C B K L DR
SEARC H B RE AK PO I N T S
LOAD PROGRAM COUNTER
LOX
12 , S
COUNT DOWN
ARMBLP D E C a
ARM B K 2
BMI
DON E , NON E T O S I NGLE TRACE
L DA
- NU M BK P * 2 , Y P RE - F E T C H OPCODE
CMPX
, Y+ +
? I S TH I S A BREAK PO I NT
AR.'1BLP
BN E
LOOP I F NOT
? SWI 8REAKPO I NT E O
CM P A
t $ 3F
ARMN SW
BNE
NO , S K I P SETT I NG OF PAS S F LAG
SW I BF L
SHOW UP C OMM I NG SWI NOT BRKPNT
S TA
M I S F LG
F LAG TH RU A BREAK PO I NT
ARMNSW INC
DO S I NGL E TRAC E WIO BREAK P O I NTS
LBRA
C DOT
* O BT A I N NEW PROG RAM COUNT E R
OBTA I N NEW PROGRAM CO U NT E R
C D NU M
GO N D F T LBS R
STORE I NTO STACK
12 ,S
STO
C8K LDR
OBTA I N TAB LE
A RM B K 2 LB S R
BK P',I'CT
COMPLEMENT TO SHOW ARM E D
NEG
ARM LOP DE C B
? DON E
CN V RT S
BM I
RE'rU RN WH E N DONE
LDA
LOAD OPCOOE
[ ,Y]
STA
-NUMBK P * 2 , Y STORE I NTO OPCODE TA B LE
8·61
PAGE
026
AS S I ST0 9 . SA : 0 ·
0 1 3 7 5A F DB3 8 6
0 1 3 7 6 A F D B 5 A7
0 1 3 7 7 A F DB 7 2 0
3F
Bl
F3
0 1379
0 1 3 8 0A
0 1 3 8 1A
0 1 3 8 2A
0 1 3 8 3A
0 1 3 8 4A
0 1 3 8 5A
F D8 9
F DB B
F DB D
F DB F
F OC O
FOCl
8D
35
AD
3F
20
C8
7F
Fl
OA
FC
AS S I ST0 9 - MC 6 8 0 9 MON I TOR
A
A
F DAC
F DC 3
F DC 6
F DC 8
F DCA
FDCD
F DCF
F ODO
F DDl
F DD4
17
DO
9E
17
F DD6
F DD 8
0 1 4 0 2 A F DDA
0 1 4 0 3A F DDC
0 1 4 0 4 A F DOE
0 1 4 0 5 A F OE O
0 1 4 0 6 A F DE 2
0 1 4 0 7 A F DE 4
0 1 4 0 8 A F DE 6
81
0 1 4 0 1A
86
3F
17
27
0 0 9A F E 6 0
9E
A
9E
A
F C O C F 9 D9
A
20
A
01
F F O B F C DF
F DE O
OA
26
2C
OE
9F
9E
30
20
01
#$ 3F
[ , Y++ )
ARMLOI?
READY " SW I " O PCODE
STORE AN D MOVE UP TAB LE
AN D CONT I NU E
* * * * * * * * * * * * * * * * * * * CALL - CALL ADDRE S S AS SU B ROUT I N E
F D8 3 CCALL
BS R
GOADDR
FETCH ADDRE S S IF N E E D E D
A
P U LS
U , Y , X , DP , D , CC RE S TORE U S E RS REG I ST E RS
A
JS R
[ , S++ )
CALL US E R S U BROUT I N E
CGOBRK SWI
PE RFORM BREAK PO I NT
A
FCB
BRKPT
FUNCT ION
BRA
F DB F
CGOB RK
LOOP UNT I L U S E R CHANGES PC
0 1387
0 1388
0 1389
0 1 3 9 0A
0 1 3 9 1A
0 1 3 9 2A
0 1 3 9 3A
0 1 3 9 4A
0 1 3 9 5A
0 1 3 9 6A
0 13 97A
0 1 3 9 8A
0 1399
0 1400A
LDA
STA
BRA
A
FDE8
A
A
F OOl
A
F E 2B
* * * * * * * * * * * * * * * *MEMORY - D I S PLAY/CHANGE MEMORY
* CMEMN AND CMPADP ARE D I RECT ENTRY PO I NTS F ROM
* THE COMMAN D HAN D L ER FOR QU I C K COMMAN DS
LBSR
CMEM
C DN U M
OBTA I N ADDRE S S
CMEMN STD
ADDR
STORE DE FAULT
LOX
CM EM2
AD DR
LOAD PO I NT E R
LBS R
ZOUT 2 H
S E N D OUT H E X VALUE OF BYTE
LDA
LOAD DE L I M I T E R
#'SW I
S E N D OUT
FCB
OUTC H
FUNCT I O N
LBS R
OBTAI N NEW BYTE VALUE
CMEM4
BLDNNB
BEQ
CME N U M
BRANCH I F NUMBE R
* COMA - S K I P BYTE
ClI'lPA
? COMMA
ii ,
BNE
CMNOTC
BRANCH NOT
STX
U P DATE PO I NTER
AD D R
L E AX
TO NEXT BYT E
1 ,X
B RA
CMEM 4
AND IUPUT I T
NUMBE R+ l LOAD LOW BYTE VALUE
CMENUM L O B
BSR
MUP DAT
GO OVERLAY MEMORY B YT E
CMPA
? CONT I NU E W I T H NO D I S P LAY
ii ,
CM E M 4
BRANCH Y E S
BEQ
* Q UOT E D ST R I NG
I"
CMNOTC C(l:i PA
? QUOT E D ST R I N G
BN E
BRANC H NO
CMNO T Q
D6
Fl
9C
80
81
2C
A
27
E9
F OO l
0 1 4 1 0 A F DE 8 8 1
27
OC
A
FDF8
8B
27
OC
OBT A I N N E X T CHARACT E R
RE A D
C M E S T R BS R
II I
ClI'l PA
? END OF QUOT E D STRING
YES , QU I T S T R I NG MODE
F DF E
BEQ
CM S P C E
A
TO B FOR SU B ROUT I N E
TF R
A,B
BS R
FE2 B
GO UPDAT E BYTE
MUP DAT
G E T N E X T CH ARACT E R
F DEC
BRA
CM E S T R
* B L AN K - NEXT BYTE
? B LANK FOR NEX T BYTE
A CMNOTQ CMPA
# $ 20
B RANCH NOT
FE0 2
C M NO T B
BNE
U P DAT E PO I NT E R
A
ST X
AD D R
G I VE S P AC E
CMS P C E SW l
F U N CT I O N
A
S P AC E
FC B
B RA
CM E M 2
NOW PROMPT FOR NEXT
F OC S
* L I N E F E E D - NEXT BYTE W I T H ADDRE S S
? L I N E F E E D FOR NEXT BYTE
A CMNOT B CMPA
I LF
BNE
CMNOTL
BRANCH NO
FEO t
LDA
A
G I V E CARR I AG E RETU RN
tCR
47
0 14 0 9
0 1 4 1 1 A F DEA 2 6
0 1 4 1 2 A F DE C 8 0
0 1 4 1 3 A F OE E 8 1
0 1 4 1 4A
0 14 1 5A
0 1416A
0 1 4 1 7A
01418
0 1 4 1 9A
0 14 20A
0 1 4 2 1A
0 1 4 2 2A
0 1 4 2 3A
0 1 4 2 4A
0 1425
F DF O
27
F DF 2 1 F
80
20
89
35
F4
FOF8 8 1
F D FA 2 6
F UFC 9 10"
20
06
9E
F OF E
F UF F
FEOO
3F
20
C6
0 1 4 2 6A FE0 2
0 1 4 2 7 1\ F E 0 4
0 1 4 2 8 1\ F E 0 6
81
26
86
01\
08
00
F DF 4
FDF6
07
FD79
A
8·62
PAGE
0 1 4 2 9A
0 14 3 0A
0 1 4 3 1A
0 1 4 3 2A
0 14 3 3
0 1 4 34A
0 14 3 5A
0 1 4 3 6A
0 1437A
0 14 3 8A
0 14 3 9A
0 1440A
0 1 4 4 lA
0 14 4 2
0 1443A
0 1 4 4 4A
0 1 4 4 5A
027
AS S I ST0 9 . SA : 0
FE0 8 3 F
FE0 9
FEOA 9 F
FEO C 2 0
ASS I ST0 9 - M C 6 8 0 9 MON I TOR
01
9E
OA
A
FE18
5E
OA
lE
9E
A
FEIC
A
A
06
07
AC
A
FE21
F DC 8
FEIC 8 1
FEIE 27
FE2 0 3 9
2F
F6
A
FE1 6
0 1447
0 14 4 8A
0 14 4 9A
0 1 4 5 0A
0 1451A
0 1 4 5 2A
0 1453A
FE 2 1
FE2 3
FE2 5
FE 2 7
FE2 8
FE29
9E
34
30
3F
9E
10
E4
A
A
05
90
A
A
01455
01456A
0 1457A
0 1458A
0 1 4 59A
01460A
0 1 4 6 1A
0 1 4 6 2A
0 1 4 6 3A
0 1 4 6 4A
0 1 4 6 SA
0 14 6 6A
FE2 B
FE 2 D
FE2 F
FE 3 1
FE 3 3
FE 3 5
FE3 6
FE38
FE3A
FE 3 B
FE3C
9E
E7
El
26
9F
39
34
86
3F
FE O E
FEI O
FE1 2
FEl 4
FE1 6
FE1 7
FE1 8
FE1A
81
26
30
9F
3F
80
20
35
35
0 1468
0 1 4 6 9 A FE 3 E 8 0
0 1 4 7 0 A FE4 0 DO
0 1 4 7 1A FE4 2 3 9
01473
0 14 7 4A
0 1 4 7 SA
0 1476A
0 1477A
0 1478A
0 14 7 9A
0 1480A
0 1 4 8 1A
0 1 4 8 2A
FE4 3
FE 4 5
FE4 7
FE 4 9
FE4 B
FE4 D
FE4F
FE S 1
FE 5 3
80
C4
IF
30
25
80
30
34
l0A3
9E
80
IF
03
9E
02
3F
01
82
20
AO
IB
FO
02
2F
04
11
AB
30
62
A
SWI
TO CONSOLE
FCB
OUTCH
HANDLER
STORE NEXT ADDRESS
STX
ADDR
B RA
BRAN CH TO SHOW
CMPADP
* U P ARROW - PREVIOUS BYTE AN D ADDRE S S
CMNOT L CMPA
# '@
? U P ARROW FOR PREV IOUS B YT E
BRAN CH NOT
CMNOTU
BNE
DOWN TO PRE V I O U S BYTE
LEAX
-2 , X
STO RE NEW PO I NT E R
STX
ADDR
CMPADS SW I
FORCE NEW L I N E
FCB
PCRLF
FUNCT ION
CMPP. DP BSR
PRTADR
GO P R I NT I 1'S VALUE
BRA
THEN PROMPT FOR I N PUT
CMEM2
* S LASH - NEXT BYTE W I TH ADDRE S S
CMNOTU CMPA
i'/
? S LAS H FOR CURRENT D I S PLAY
Y E S , S E N D ADDRE S S
BEQ
CMPADS
RE'rURN FROM COMfotAN D
RTS
* P R I NT CURRENT ADDRE S S
ADDR
LOAD PO I NT E R VALU E
SAVE X · ON STACK
X
PSHS
PO I NT TO I T FOR D I S PLAY
,S
LEAX
D I S PLAY PO I NTER I N HEX
SWI
F UNCT ION
OUT 4 H S
FCB
Pc , x
PU LS
RECOVER PO I NT E R AN D RET U RN
A PRTADR LOX
* U P DAT E BYTe
A MU P DAT LOX
A
STB
A
CMPB
BNE
FE36
A
STX
RTS
A MU P BAD PSHS
A
LOA
SWI
A
FCB
A
PULS
ADDR
, X+
-l , X
MUPBA O
ADDR
A
Ii?
OUTCH
PC , A
LOAD NEXT BYTE PO mTER
STO RE AN D I NCRE M E N T X
? S U C C E S F UL L STORE
BRAN C H FOR I ? ' I F NOT
STORE NEW PO I NT E R VALUE
BACK TO CALLE R
SAVE A REG I STER
SHOW I NVAL I D
S E N D OUT
F UNCT ION
RETURN TO CALLER
* * * * * * * * * * * * * * * * * * * * W I N DOW - SET W I N DOW VALUE
C DN U M
FE 6 0 CW I N DO BSR
OBTA I N w I N DOW VALUE
W I N DOW
A
STD
STORE IT I N
RTS
END COMMAND
* * * * * * * * * * * * * * * * * * D I S P LAY - H I GH S P E E D D I S P LAY ME M ORY
CDNUM
F E'rC H ADDRES S
BS H
F E 6 0 CDI S P
#$FO
FORC E '1'0 1 6 BOUN DRY
A
AN DB
D,Y
SAVE I N Y
TF R
A
15 ,y
DE FAULT LENGTH
A
LE AX
C D I S PS
BRANC H I F E N D OF I NPUT
BCS
FE51
C DNU M
OBTA I N COUNT
BSR
FE60
D,Y
LEAX
A
AS S U M E COUNT , COMPUTE E N D ADDR
Y,X
SETUP PARAME T E RS FOR H S DATA
A C D I S PS PSHS
2,s
? WAS IT COU NT
CMPD
A
B-63
PAGE
028
0 1 4 8 3A
0 14 8 4A
0 14 8 SA
0 1486A
AS S I ST0 9 . SA : 0
FES6
FES8
FESA
FESE
23
ED
AD
35
0 1488
0 1489
0 1490
01491
0 1 4 9 2A
0 1 4 9 3A
0 1 4 9 4A
0 14 9 SA
0 14 9 6A
0 1 4 9 7A
0 1498A
0 1499A
FE60
FE6 3
FE 6 S
FE 6 7
FE69
FE6B
FE6D
FE6E
17
26
81
22
81
DC
39
16
0 1501
0 1 S 0 2A
0 1 S 0 3A
0 1 S 0 4A
0 1 S 0 SA
0 1S06A
0 1 S 0 7A
0 1S08A
0 1S 0 9A
0 1S10A
0 1SHA
0 1 S 1 2A
0 I S 1 3A
FEn
FE73
FE7 S
FEn
FE 7 9
FE7B
FE7F
FE83
FE 8 S
FE89
FE8B
FE80
80
IF
80
6F
34
AD
AD
34
AD
35
26
35
0 1515
0 1 S16A FE8F 80
0 1 S 17A FE91
AS S I ST0 9 - MC 6 8 0 9 MON ITOR
FESA
02
A
E4
CDCNT
90 E184
A
EO
F E 7 E FC E I
FE6E
09
A
2F
FE6 E
05
A
OE
A
9B
FAE B F 9 S C
B LS
STD
JSR
PULS
C DCNT
BRAN CH Y E S
,S
STORE H I G H ADDRE S S
[ VECTAB+ . H S DTA , PC R ] CALL PRI NT RO UT I NE
PC , U , Y
CLEAN STACK AN D E N D COMMAND
* OBTA I N NUMBER - ABORT I F NON E
* O N LY DEL I M I T E RS OF C R , BLANK , OR ' I ' ARE AC C E PT E D
* OUTPUT : D=VALU E , C=l IF CARRIAGE RETURN DE LM I T E R ,
*
E L S E C= O
CDNUM
BLDNUM
LBS R
OBT A I N NUM B E R
C DBADN
BNi:'!
BRANCH I F I NVAL I D
? VAL l O DE L I M I T E R
CMPA
i'l
BRANCH I F NOT F O R ERROR
C DBADN
BHI
LEAVE COMPARE FOR CARR I AGE RET
# C R+ l
CMPA
LOAD NUM B E R
NUM B E R
LDD
RETURN W I T H COMPARE
RTS
RETURN TO E RROR MECHAN I SM
CMDBAD
C D BADN LBRA
* * * * * * * * * * * * * * * * * P U NCH - PUNCH MEMORY I N S 1 - S 9 FORMAT
F E 6 0 C PUNCH BSR
ED
CDNUM
OBTA I N START ADDRE S S
A
TFR
D,Y
SAVE I N Y
02
FE60
BSH
CDNU M
OBTA I N E N D ADDRES S
E9
A
, -S
SETU P PU N C H F UNCT ION CO DE
CLR
E2
PSHS
Y,D
A
STORE VAL U E S ON STACK
26
CCALBS J S R
[ VE CTAB+ . B SON , PC R ] I N I T I AL I Z E HANDLER
9 0 E1 6 5
JSR
[ VECTAB+ . BS DTA , PC R ] P E RFORM FUNCT I ON
90 E163
A
PSIIS
CC
SAVE RETURN CODE
01
[ VECTAB+ . B SOFF , PC R ] T U RN O F F HANDLER
JSR
9D E15F
A
P U LS
CC
OBTA I N CON D I T ION CODE SAVED
01
FE6E
BNE
C D BADN
BRANCH IF ERROR
El
A
P U LS
B2
PC , y , X , A RETURN F ROM COMMAND
01
01
* * * * * * * * * * * * * * * * * LOAD - LOAD MEMORY F ROM S 1 - S 9 FORMAT
F E 9 2 C LOAD BS R
C LVOF S
CALL SET U P AN D PAS S CO DE
A
1
FCB
LOAD FUNCT I ON CO DE FOR PAC K ET
Fl
04
03
C6
8C
4F
SF
34
20
A CLVO F S
A
FE 9 B
FE60
A
C LVDFT
4E
DA
A
FE7B
0 1529
0 1 S 3 0 A FEAl 8 0
0 1 S 3 1 A FEA3
EF
FF
* * * * * * * * * * * * * * * * * * V ER I F Y - COMPARE MEMORY WITH F I LE S
C LVO F S
COMPUTE O F F S ET IF ANY
FE9 2 CVER
BSR
A
-1
FCB
VERI F Y FNCTN CO DE FOR PACK ET
0 1 S 1 9A
0 1 S20A
0 1 S 2 1A
0 1 S 2 2A
0 1S 23A
0 1S24A
0 1S 2 SA
0 1 S26A
0 1.S 2 7 A
FE 9 2
FE94
FE9 6
FE9S
FE9A
FE 9 B
FE9C
FE9D
FE9F
33
33
27
80
LEAU
LEAU
BEQ
BSR
FCB
CLRA
CLRB
PSHS
BRA
[ , S++ ]
[ ,U]
C LVDFT
CDNUM
SKIP2
U , DP , D
CCALBS
8-64
LOAD CO D E IN HIGH BYTE OF U
NOT CHAN G I NG CC AND RESTORE S
BRANCH I F CARR I AG E RETURN N E XT
OBTA I N OF F S ET
S K I P DE FAULT OF F S ET
CREATE Z E RO OF F S ET
AS DEFAUL'f
S E'fUP COD E , N U L L ·wORD , OF F S ET
ENTER CALL TO BS ROUT I NES
PAGE
029
0 1533
0 1534
0 1 5 3 5A
0 1536A
0 1537A
0 1 5 3 8A
0 1 539A
0 1 540A
0 1 541A
0 1 54 2A
0 1 5 4 3A
0 1559
0 15 6 0
0 1 5 6 1A
0 1 5 6 2A
0 1 5 6 3A
0 1564
0 1565A
0 1566A
0 1567A
0 1568A
0 1 569A
0 1570A
0 1 5 7 1A
0 1 5 7 2A
0 1 s 7 3A
0 1 s7 4A
0 1 s 7 sA
01576A
0 1577A
0 1 s7 8 A
0 1 s7 9 A
0 1s80A
0 1 s8 1A
0 1 s 8 2A
0 1583
* * * * * * * * * * * * * * * * * * * TRAC E - TRAC E I NSTRU CT IONS
*******************
- S I NGLE ST E P TRAC E
CTRAC E BSR
CDNUM
OBTA I N TRACE COU NT
STORE CO UNT
TRAC EC
STD
LEAS
2,S
RI D COMMAN D RET U �� FROM STACK
COOT
CT RC E 3 LOU
[lO ,S)
LOAD OPCODE TO EX E C UTE
STU
LASTOP
STORE FOR TRAC E INTE RRU PT
LDU
VECTAB+ . PTM LOAD PTM ADDRE S S
LDD
#7 ! <8+1
CYCLES ooWN + C Y C L E S U P
STD
PTMTMI - PTM , U START NM I T I MEOUT
RT I
RETURN FOR ONE I N S T RU CT ION
•
FEA4
FEA6
FEA8
FEAA
FEAD
FEAF
FEBl
FEB4
FEB6
80
DO
32
EE
OF
DE
CC
ED
3B
0 1545
0 1 5 4 6 A FEB7 8 0
0 1 5 4 7 A F E B 9 DO
0 1 5 4 8 A FEBB 3 9
01550
0 1 5 5 1A
0 1 5 5 2A
0 1 5 5 3A
0 15 54A
0 1555A
0 1556A
0 1557A
AS S I ST0 9 - M C 6 8 0 9 MON I TOR
AS S I ST0 9 . SA : 0
F E BC
FEBE
FECO
FEC2
FEC 3
FEC 5
FEC7
27
80
DO
39
30
9F
39
FE60
BA
91
A
A
62
A
Fa OA
99
A
A
F6
A
0701
A
42
A7
F2
OS
AO
Fa
6E
F8
SET NEW L I N E AN D CHAR PADD I NG
* * * * * * * * * * * * * N U L LS
F E 6 0 CNU LLS BSR
CDN U M
OBTA I N NEW L I N E PAD
A
STD
VECTAB+ . PAO RE SET VAL U E S
RTS
END COMMAND
* * * * * * * * * * * * * * * * * * STLEVEL - SET STACK TRAC E LEVEL
FEC3 CST LEV BEQ
STLDFT
TAK E DE F AULT
BSR
CDN U M
OBTA I N NEW STACK LEVEL
FE6 0
A
STD
SLEVEL
STORE NEW E NT RY
RTS
TO COMMAND HAN D L E R
A STLOFT LEAX
14 , S
COMPUTE NMI COMPARE
STX
SLEVEL
AN D STORE I T
A
RTS
END COMMAN D
FEC S 8 0
FECA I F
FECC 8 0
96
01
92
FE60
A
FE60
FECE
F E DO
FED2
F E D4
F E D6
F E DS
F E D9
FE DB
FEDD
F E DE
F E DF
FEEl
FEE3
FEES
FEE6
FEE7
FEES
FEE9
01
30
E4
E4
A
A
30
34
A3
ED
30
10
Al
26
3F
EE
33
EF
3F
3F
35
A
61
A
A
E4
02
FEOF
A
04
E4
SF
84
A
A
A
OS
A
06
96
A
A
A
* * * * * * * * * * * * * * * * * * OF F S ET - COMPUTE SHORT AND LONG
** ****************
B RANC H O F F S ETS
COF F S
BSR
CDNUM
OBTA I N I NSTRUCT I O N ADDRE SS
TF R
D,X
U S E AS F ROM ADDRE S S
BS R
CDNUM
OBTA I N TO ADDRE S S
* D=TO I N STRUCT I O N , X = F RO M I NSTRU CT I O N OF F SET BYT E ( S )
LEAX
1,X
ADJ U S T FOR * + 2 SHORT BRANCH
PSHS
Y,X
STORE WORK WORD AN D VALUE ON S
SUBD
,S
F I N D OF F S ET
STD
,S
SAVE O V ER STACK
LEAX
1 ,5
PO I NT FOR ONE BYTE D I S P LAY
SEX
S I G N EXT E N D LOW BYTE
CMPA
,S
? VAL I D ONE BYTE OF F S E T
BNE
COFNOl
BRANCH I F NOT
SW I
SHOW ONE BYTE O P F S ET
OUT 2 HS
F U NCT ION
FCB
COF NO l LOU
,S
RE LOAD OF F S E T
LEAU
-l , U
CONVERor TO LONG B RANCH OF F S E T
,x
STU
STORE BACK WHE RE X PO I NTS NOW
SW I
SHOW T'1l0 BYTE OF F S ET
OUT 4 H S
FCB
FUNCT ION
SWI
FORCE NEW L I N E
FUNCT ION
PCRLF
FCB
PULS
PC , X , D
RE STORE STACK AN D E N D COMMAN D
*H
8-65
PAGE
030
AS S I ST0 9 . SA : 0
01585
01586
0 1 5 8 7A FEEB
0 1 5 8 8 A FEE D
0 1 5 8 9A FEFO
0 1 5 9 0A F E F 2
0 1 5 9 1A FEN
0 1 5 9 2A FEF 6
0 1 5 9 3A FEF 9
0 1 5 9 4A FEFB
0 1 5 9 5A F E F O
01596
0 1 59 7 A FEFE
0 1 5 9 8A F F O O
0 1 59 9 A FFOl
0 1 6 0 0 A FF 0 3
0 1 6 0 1A F F 0 5
01602
0 16 0 3A F F 0 7
0 1 6 0 4 A FF 0 9
0 1 6 0 5A FFOB
0 1 6 0 6 A FF O C
0 16 0 7 A F F O E
0 1 608A FF10
0 16 0 9 A FF 1 2
0 1 6 1 0 A FF1 4
0 1 6 1 1A F F 1 6
0 1 6 1 2A FF 1 7
0 1 6 1 3A FF1 8
0 1 6 1 4A FF 1 9
0 1 6 1 5 A FF 1 B
0 16 1 6 A FF1C
0 1 6 1 7 A FF 1 D
01618
0 1 6 1 9A F F 1 E
0 1 620A FF20
0 1 6 2 1 A FF 2 2
0 1 6 2 2 A FF 2 4
0 1 6 2 3 A FF 2 6
0 1 6 2 4 A FF 2 8
0 1 6 2 5 A F F 2A
0 1 6 26A FF2C
0 1 6 27A FF 2E
0 1 6 2 8A FF 2 F
0 1 6 2 9A FF 3 1
0 1 6 3 0A FF 3 3
0 1 6 3 1 A FF 3 5
0 1 6 32A FF 3 8
0 1 6 33A FF3A
0 1 6 3 4A F F 3 C
0 1 6 3 5 A FF 3 E
01636
0 1 6 37A FF40
0 1 6 3 8A FF 4 2
0 1 6 3 9A F F 4 6
0 1 6 4 0 A FF 4 8
27
17
27
81
26
17
27
OF
39
80
SA
2B
AC
26
AE
AF
SA
2A
OA
8D
27
30
3F
SA
26
3F
39
80
Cl
27
A6
E7
El
26
A7
SA
2B
AC
26
16
AF
6F
OC
20
9E
31
D6
39
AS S I ST0 9 - M C 6 8 0 9 MON I TOR
* * * * * * * * * * * * * BREAKPO I NT - D I S PLAY/E N T E �/DE LETE/CLEAR
*************
BREAKPO I NTS
F F 1 0 C B K PT BEQ
23
BRANCH D I S P LAY OF J UST ' s '
CBK DS P
ATT EMPT VALUE ENTRY
FDFl F C E l
BLDNUM
LBS R
BRANCH TO ADD I F SO
CBKADD
2C
FF1 E
BEQ
? CORRECT DE L I M ITER
2D
CMPA
#'A
NO , BRANCH FOR ERROR
CBKERR
3F
FF3 5
BNE
ATTEMPT DE LETE VALUE
BLDNUM
FDE8 FCE l
LB S R
GOT ONE , GO DELETE IT
CBK OLE
03
BEQ
FEFE
WAS ' B - ' , SO Z E RO COUNT
BK PTCT
A
FA
CLR
E N D COMMAN D
CBKRTS RTS
* DELETE THE ENTRY
SETU P REG I S 'r E �S AN D VAL U E
CBKSE'r
40
F F 4 0 CBK OLE BSR
? ANY ENTR I E S I N TAB LE
CBKOLP DECB
BRAN CH NO , E RROR
BM I
C B K E RR
32
FF 3 5
? I S TH I S TH E ENTRY
A
Al
CMPX
, Y++
NO , TRY NEXT
CBK DLP
BNE
F9
FFO O
* F OU N D , NOW MOVE OTH E RS UP IN ITS PLACE
A C B K DLM LOX
LOAD NEXT ONE U P
Al
, Y++
A
-4 , Y
STX
MOVE DOWN B Y ONE
3C
? DONE
DE C B
BPL
F9
CBKDLM
NO , CONT I NU E MOVE
FF07
DE CREMENT B REAK PO I NT COUNT
A
BK PTC'l'
DEC
FA
SETUP REG I S T E �S AN D LOAD VALUE
CBKSET
2E
FNO CBK OS P B S R
RETURN IF NONE T O D I S PLY
CBKRT S
FEFD
BEQ
E9
PO I NT TO N E XT ENTRY
A C B K DSL LEAX
Al
, Y++
SW I
D I S PLAY I N HEX
A
F U NCT ION
OUT4 H S
FCB
05
COUNT DOWN
DEC B
LOOP I F MORE TO DO
BNE
CBKDSL
FF14
F9
SK I P TO NEW L I N E
SW I
FUNCT ION
PCRLF
A
FCB
06
RT S
RETU RN TO END COMMAN D
* ADD NEW ENTRY
SETUP REG I ST E RS
CBKSET
F F 4 0 CBKADD BSR
20
? A LREADY FULL
A
CMPB
#NUMBKP
08
BRAN CH ERRO R I F SO
C B K E RR
BEQ
FF3 5
11
LOAD BYTE TO TRAP
LDA
,X
A
84
TRY TO CHANGE
,X
ST B
A
84
? C HANGAB LE RAM
CMPB
,X
A
84
BRANCH EORROR IF NOT
CBK ERR
BNE
09
FF 3 5
RE STORE BYTE
STA
,X
A
84
COUNT DOWN
CBKADL DE C B
BRANCH IF DON E 'ra ADD IT
CBKADT
BM I
07
FF38
? ENTRY ALREADY HERE
CMPX
A
, Y+ +
Al
LOOP I F NOT
C BKADL
BNE
F9
FF2E
RETURN TO ERROR PRODUCE
CM OBAD
F A 2 4 F 9 5 C CBKERR LBRA
ADD TH I S ENTRY
,Y
A CBKADT STX
A4
-NUMBK P * 2 + 1 , Y C LEAR OPT I ONAL BYTE
C LR
A
31
ADD ONE TO COU NT
BK PTCT
FA
INC
A
CBKDSP
AND NOW D i S PL�Y ALL OF ' EM
BRA
DO
FF10
* SETUP REG I ST E RS FOR SCAN
LOA D VALUE DE S I �E D
NU M B E R
A CBKSET LDX
9B
BK PTBL , PCR LOAD START OF TAB LE
8 D E0 6 C
C B K LDR LEAY
A
FA
BK PTCT
LDB
LOAD ENTRY COUNT
RTS
RETURN
8-66
PAGE
031
01642
0 16 4 3A
0 1 6 4 4A
0 16 4 SA
0 1646A
0 1 6 4 7A
0 1 6 48A
0 1 6 4 9A
0 1 6 S0A
0 16S1A
0 1 6 S2A
016S3A
0 1 6 S4A
0 1 6 S SA
0 1 6 S6A
0 1 6 S7A
0 1 6 S8 A
0 16 S9A
0 1 6 60A
0 1 6 6 1A
0 1 6 6 2A
0 1663A
0 1 6 6 4A
0 1 6 6 SA
0 1 6 6 6A
0 1667A
0 1668A
0 1669A
0 1 670A
0 1 6 7 1A
0 1 6 7 2A
0 1 6 7 3A
0 1 674A
0 1 675A
0 1 67 6A
0 1677A
0 1678A
0 1679A
0 1680A
AS S I ST 0 9 . SA : 0
· · · · · · · · · · · · · · · · · ENCODE
FF49
FF4B
FF4C
FF 4 F
FFSO
FF S l
FF S 3
FF S S
FF S7
FF S !:!
FF SA
FFSB
FF S D
FFSF
FF61
FF63
FF6S
FF67
FF 6 9
�' F 6 B
FF6E
FF70
FF72
FF74
FF 7 6
FF 7 8
FF 7A
FF7C
FF7E
FF80
FF 8 2
FF84
FF86
FF 8 8
FF89
FF8A
FF8B
FF8C
6F
SF
30
3F
81
26
86
A7
3F
81
27
60
2B
Al
26
EB
20
30
IF
84
AA
A7
C4
60
27
El
26
E6
EA
E7
30
3F
E2
00
SB
06
10
E4
00
00
OC
84
02
81
F8
IF
98
60
E4
E4
9F
84
B9
81
F8
IF
E4
E4
E4
LE AX
35
STA
C E NG E T SW I
A
FC B
A CEN 2
C M PA
FF6B
BEQ
A C E N L P l TS'f
FF 3 S
BM I
A
CMPA
BNE
FFSF
A
A
A
A
A
CE N Dl
A
A CENLP2
FF 3 5
A
FF78
A
A
A
A
A
06
84
A
A
1084
1288
1486
168B
1881
lAS 3
8380
00
BNE
LOA
A
04
FFB 7
FFBB
SW I
FC B
CM P A
A
A
FFSB
A
3F
41
48
20
55
50
FF
FFC 3
FFC?
FFCB
FFCF
FFD3
CLRB
F F S !:!
EE
8C 4 9
FF8E
FF 9 6
FF 9 E
FFA6
FFAE
FFB6
FFBF
A CENCDE CLR
8C 3 F
01682
0 1683A
0 1 6 8 4A
0 1 685A
0 1686A
0 1687A
0 1 6 8 8A
0 1689
0 1690
0 1 6 9 1A
0 1 6 9 2A
0 1 6 9 3A
0 1694A
0 1 6 9 5A
0 1696A
0 1697A
0 1698A
ASS I ST0 9 - MC 6 8 0 9 MON I 'fOR
ADDB
BRA
LEAX
TFH
ANDA
ORA
STA
AN DB
TST
BEQ
CM P B
BNE
LOB
ORB
STB
LEAX
SW I
FCB
SW I
FC B
PULS
* TABLE ONE
A CONVl
FCB
A
A
A
A
A
A
A
A
A
A
A
A
A
, -5
ENCODE A POSTBYTE
DE FAULT TO NOT I N D I RECT
Z E RO PO STBYTE VA L U E
< C O N V1 , P C R START TAB L E S E ARC H
OBTA I N
I NCHNP
#' I
CEN2
#$10
,s
I N CH N P
#CR
C E N Dl
F I RS T C H ARACT E R
FUNCT ION
? I N D I RE C 'r H E HE
BRANCH I F" No'r
SET I N D I R E C T B I T ON
SAVE FOR LAT F H
O BTA I N N E X T C H A RA C T E R
F U N CT I O N
? END O F E N T RY
BRANCH
YES
,X
? E N D OF TAB LE
C B K E RR
BRANCH ERROR I F SO
, X ++
CE N L P l
-l , X
C E N GE 'f
? TH I S TH E CH ARACT E H
BRANCH I F NOT
ADD 'flU S VALUE
GET N E XT I N P U T
< CONV2 , PC R PO I NT AT T AB L E 2
SAVE COpy I N A
B ,A
I SO LATE HEG I ST E R MAS K
#$60
ADD I N I N D I RE CT ION B IT
,S
,S
SAVE BACK AS POSTBYTE SKELETON
CLEAR REG I ST E R B ITS
#$9F
? E N D OF TAB LE
,X
CBKERR
BHANCH E RROR I F SO
? S AME VALUE
, X ++
CENLP2
LOOP I F NOT
-l , X
LOAD RE S U LT VAL U E
ADD TO BAS E S K E L ETON
,S
SAVE POSTBYT E O N STACK
,S
PO I NT TO I T
,S
S E N D OUT AS HEX
F U N C T I ON
OUT 2HS
TO NEXT L I NE
PC R L F
F UNCT ION
PC , B
END OF COMMAN D
DE F I N E S VAL I D I N PUT I N SEQUENCE
' A, $04 , ' B , $05 , ' D, $ 06 , ' H , $01
FCB
' H , $Ol , ' H , $Ol , ' H , $OO , ' , , $OO
' - , $0 9 , ' - , $01 , ' 5 , $7 0 , ' Y , $ 30
FCB
' U , $ 50 , ' X , $10 , ' + , $0 7 , ' + , $01
FCB
' P , $8 0 , ' C , $OO , ' R , $DO , ' ) , $0 0
FCB
$FF
E N D O F TABLE
FCB
*CO N V2 U S E S ABOVE CO NVERS ION TO SET POSTBYTE
B I T S K E L ETON .
*
H ,R
$1084 , $1100 R,
F OB
CONV 2
HHHH , R
$ 1 2 8 8 , $ 1 3 8 9 HH , R
F OB
B,R
$1486 , $1585 A,R
F DB
, R+
$1688 , $ 17 80 O, R
F OB
, -R
$ 1 8 8 1 , $ 1 9 8 2 , R++
F OB
$ 1A 8 3 , $ 8 2 8 C , --R
HH , P C R
F OB
[ H HH H )
$ 8 3 8 D , $ 0 3 9 F HHHH , PCR
F OB
E N D OF TABLE
0
FCB
B-67
PAGE
032
0 1700
0 1701
0 1702
0 1 703A
0 1704A
0 1 705A
0 1706A
0 1 7 0 7A
0 1708A
0 1 7 0 9A
01711
0 1712
0 1713
01714
0 1715
0 1 7 1 6A
0 1 7 1 7A
0 1 7 1 8A
0 1 7 1 9A
0 17 20A
0 1 7 2 1A
0 1 7 2 2A
0 1 7 23A
0 1 7 2 4A
AS S I ST 0 9 . SA : 0
F F D4
F F D8
F F DC
FFEO
FFE4
FFE8
FFEC
6E
6E
6E
6E
6E
6E
6E
FFF O
FFF O
FFF 2
FFF 4
FFF 6
FF F 8
FFFA
FFFC
FFFE
90
90
90
90
90
90
90
AS S I ST0 9 - MC 6 8 0 9 MON I TOR
****************************************************
DE FAULT I NTERRUPT TRANS F E RS
*
*
****************************************************
[VECTAB+ . RSVD , PC R ) RE S E RVED VECTOR
RSRVD JMP
[ VECTAB+ . SW I 3 , PC R ) SWI 3 VECTOR
JMP
SW I 3
[ VECTAB+ . SW I 2 , PCR) SWI 2 VECTOR
JMP
SW I 2
[ V ECTAB+ . F I RQ , PCR) F I RQ VECTOR
JMP
F I RQ
[ V ECTAB+ . I RQ , PCR) I RQ VECTOR
JMP
I RQ
[ VECTAB+ . SW I , PCR] S W I VECTOR
JMP
Sill I
[ VECTAB+ . NM I , PCR ] NM I VECTOR
JMP
NMI
DF EE
DFEC
DFEA
DF E S
DF E 6
DF E4
DFE2
F F D4
F F DS
F F DC
FFEO
FFE4
FFES
FFEC
FS37
A
A
A
A
A
A
A
A
01726
A
FS37
TOTAL ERRORS 0 0 0 0 0 - - 0 0 0 0 0
TOTAL WARN I N G S 0 0 0 0 0 --0 0 0 0 0
002E
0 000
0024
0 0 26
0022
0016
001S
0014
0002
0 0 2C
001C
0 0 lE:
001A
0032
002A
0 0 0 1\
0020
O OOC
0010
0 030
002S
0034
. AC I A
AVTBL
BS DTA
. BSO F F
. S SON
. C I l)'f1\
. C IOFF
. C ION
•
•
. CM D L 1
. CMDL2
. C O DTA
. COO F F
. COOt�
. EC H O
. E X P AN
. F l �o.
. lt S DTA
. UQ
.NMI
. P AD
. P AU S E
• P'l'M
* * * ***************************************************
ASS I S'f0 9 HA�DWARE VECTOR TABLE
*
*
TH I S TABLE I S U S E D IF TH E AS S I ST 0 9 ROM ADDRE S S E S
*
T H E MC 6 S 0 9 HARDWARE VECTORS .
*** ***************************************************
ROMBEG+ROMS I Z - 1 6 SETU P HARDWARE VECTORS
ORG
RS RVD
RES E RVED S LOT
F OB
F OB
SW I 3
SOFTWARE I NT E RRUPT 3
F OB
SWI 2
SOFTWARE I NT E RRUPT 2
F OB
F I RQ
FAST I NT E RRU PT REQUEST
INTE RRUPT REQUEST
I RQ
F OB
F OB
Sill I
SOFTWARE I NT E RRU PT
NON-MAS KAB LE I NTERRUPT
NMI
FOB
RESET
RE START
F OB
END
RE SET
00095*00S25 00837 00S53
00072*00594
00090*01508
00091*01510
000S9*01507
00083*00725
00084*
00082*00348
00073*00429
000 9 4 * 0 0 4 3 2
0 0 0 S G * 0 0 5 6 t1
00087*
000S5*00349
00097*00625
00093*01224
00077*01706
0 00 8 8 * 0 1 4 8 5
0 0 0 7 1:1 * 0 1 7 0 7
000SO*01709
00096* 00S57 00860 00977 00981 009a5 01025 01547
000 9 2* 0 0 7 2 4
00098*00353 01540
B·68
PAGE
033
AS S I ST 0 9 . SA : 0
0 0 1 2 . RESET
0 0 0 4 . RSVD
O O O E . SW I
0 0 0 8 . SW I 2
0 0 0 6 . SW I 3
E 0 0 8 AC IA
DF9E ADDR
F DA7 ARMBK 2
F D8 E
F OAC
F 09 0
OF90
0007
OFB2
OFFA
O FA 2
F81s
F821
ARM B L P
ARM LOP
ARMNSW
BAS E PG
BELL
BK PTBL
BK PTCT
BK P'rO p
BL02
BL03
B LOBAD
B LOH E X
BLOHXC
B LOH X I
BLON N B
F 04 6
F 04 D
F D4 F
F 04 9
F C Olo'
F C E I BLONUM
F83s
F Os 8
F800
O OOA
FB6A
FB70
FB40
FB42
FB60
FB92
FB6E
FB38
FB27
FB33
FBIB
FB22
F BE F
F BA 3
F BC 6
F BAF
F BE C
FBE7
FBE9
FB75
FB89
F B8 8
0018
FFlE
FF2E
FF38
F E F !::
FF07
FFOO
F Fl 4
BLORTN
BLDSHF
BLDVTR
BRKPT
BS OCMP
BS OEOL
BS DLD I
BS DLD 2
BS DNXT
BSDPUN
BSDSRT
B S DTA
B SO F F
BSO F LP
BSON
BSON 2
BS PEOF
BS PGO
BS PMRE
BS POK
BS PSTR
BS PUN 2
BS PUN C
BYTE
BYTH E X
BYTRT S
CAN
CBKADD
CBKA.DL
CBK A DT
CBKDLE
CBK DLM
CBKDLP
CBKDSL
ASS I ST0 9 - MC 6 8 0 9 MON ITOR
00081*
00074*01703
00079*01708
00076*01705
00075*01704
00024*00256
00133*01239 01391 01392
00773 01357 01369*
01356*01360
01371 *01 377
01362 01364*
00 1 3 5 * 0 0 1 8 6 0 0 7 8 4
00 0 3 6 * 0 0 7 8 2
00127*01638
00121*00386 01370 01594
00129*
001 9 2 * 0 0 1 9 6
00198*00201
012 8 8 * 0 1 3 3 9
01250 01301*
00421 0 1 3 0 2*
01233 01299*
01164 01219*01397
01222*01286 01492 01588
00205 00207*
01307*01311
00183*00 218
00066*0 1384
00942 00944*
00940 00948*
00919*00922 00949
00921*00928
00939*00945
00913 00977*
00926 00946*00950
00250 00911*
00251 00891*
00899 *00900
00249 00880*
00882 00884*
01021 01033*
00987*01020
01009*01011
00990 00992*
0 0 9 9 7 0 1 0 3 2*
01003 01005 01006 01009
01017 01030*
00930 00933 00935 00939
00953 00956 00965*
009 6 3 * 0 0 9 6 8
00040 * 0 0 7 1 1 0 0 7 1 8 01338
01589 01619*
01627*01630
01628 01632*
01593 01597*
01603*01606
01598*01601
01610*01614
01402 01421 01431 01437 01448 01456 01460
01607 01634 01639
01 592
0 1 0 29 *
00953*
8-69
PAGE
034
ASS I ST0 9 . SA : 0
FFI0
FF35
FF42
F EEB
F EF D
FF40
FE7B
F DB 9
F E6 E
F E5A
FE4 3
FE51
FE60
CBKDSP
CBK E RR
CBKLDR
CBKPT
CBK RTS
CBK S ET
CCA LBS
CCALL
C DBADN
C DCNT
C DI S P
C OI S PS
C DN U M
F EA8
F F 5B
FF49
F F 6B
F F 59
FF5F
FF78
F D8 0
F DBF
FA58
FA61
FA60
FA62
F A De
F AF O
F AE 6
F AE 5
FE8F
F E9 B
FE92
F8F7
F935
F948
F 95C
F 977
F901
F 96C
F94D
F 990
F8F9
F 9 0A
F953
F96F
F 96 7
F99B
F 99C
F987
F DC3
F DC 8
F DO l
F DC6
F DEO
F DEC
FE02
C OOT
CEN 2
C E N C DE
CEN D l
e ENG ET
CEN L P l
CENLP2
CGO
CGO BRK
CHKABT
CHKRTN
CHKSEC
CH KWT
C I DTA
C IO F F
C ION
C I RTN
C LOAD
C LVDFT
C LVOF S
CMD
CM D 2
CMD3
CMOBAD
CMDCMP
CMDDDL
CMD F LS
CMDGOT
CMDMEM
CMDN E P
CM DNOL
CM DSC H
CM DS I Z
CMOSME
CMDT B 2
CMOT B L
CMDXQT
CMEM
CMEM2
CMEM4
CMEMN
CMENUM
CM E ST R
CMNOTB
ASS I ST0 9 - M C 6 8 0 9 MON I TOR
01587 01608*01635
01591 01599 01621 01625 01631*01657 01669
00303 00383 01354 01369 01638*
0 0 50 3 0 1 5 8 7 *
01595*01609
01597 01608 0 1 6 19 01637*
01507*01527
00506 01380*
01493 01495 01499*01512
01483 01485*
00509 01474*
01478 01481*
01367 01390 01469 01474 01479 01492*01502 01504 01522 01535 01546
01552 01561 01563
00408 0136 5 01537*
01649 01654*
00512 016 4 3 *
0 1 6 5 5 016 6 2*
01652*01661
01656*01659
01668*01671
00515 01344*
01383*01385
007 0 1 0070 9 * 0 0 7 6 4
00710 00714*
00713*00719
007 1 2 00715*00717
00243 00825*
00244 00844*
0024 2 00835*
00828 00830*
00518 01516*
01 5 2 1 0 1 5 2 4 *
01516 01519*01530
00 3 5 4 0 0 3 8 0 * 0 0 4 39
00415*00425
00422 00424*
0 0 4 3 5 * 0 0 4 6 4 0 1 28 8 0 1 4 9 9 0 1 6 3 1
00450 * 0 0 4 5 5
00387*00391
00444*00453
00416 00427*
00420 00463*
00383*00800
00384 00388 00392*00462
00430*00434 00445
00443 00446*
00431 00441*
00254 00 4 9 6 *
00233 00500*
00410 00413 00459*00467
00521 01390*
01392*01424 01441
0139 7 * 0 1 4 0 4 0 1 4 0 8
00465 01391*
01398 01405*
014 1 2 * 0 1 4 1 7
01420 01426*
B·70
PAGE
035
F OE 8
FEOE
F OF 8
FE1C
F E1 8
F E1 6
F OFE
F EB 7
F 07 4
F 06 2
F 07 6
F 07 8
F AF I
FBOF
F B1 2
F B07
FB03
FBOO
F EC 8
F E OF
FF8E
FFB7
F AF O
F AE 6
FE71
0000
F C 4A
F EBC
F EA4
F EAA
F EAl
FE3E
DF8E
0 00 0
0005
0010
0004
F AB D
F AC E
F CE 9
F D0 7
FD23
F 01 7
F D2 B
F CE S
F D0 5
F 03 6
F OO D
F OO F
F D4 2
FFEO
F ABC
F 08 3
F DA2
0034
FCOO
FC47
F BFC
ASS I ST 0 9 . SA : 0
ASS I ST0 9 - M C 6 8 0 9 MON I TOR
CMNOTC 0 1 4 0 1 0 1 4 1 0 *
CMNOTL 0 1 4 2 7 0 1 4 3 4 *
CMNOTQ 0 1 4 1 1 0 1 4 1 9 *
CMNOTU 0 1 4 3 5 0 1 4 4 3 *
CMPAOP 0 0 4 1 1 0 0 4 6 5 0 1 4 3 2 0 1 4 4 0 *
CMPADS 0 1 4 3 8 * 0 1 4 4 4
CM SPCE 0 1 4 1 4 0 1 4 2 2 *
CNULLS 0 0 5 2 4 0 1 5 4 6 *
CNVGOT 0 1 3 2 5 0 1 3 3 1 *
CNVHEX 0 0 9 6 7 0 1 3 0 2 0 1 3 2 2 *
0 1 3 1 2 0 1 3 3 2*
C NVOK
C NVRTS 0 1 2 8 7 0 1 3 0 3 0 1 3 2 3 0 1 3 2 7 0 1 3 2 9
COOTA 0 0 2 4 6 0 0 8 5 2 *
COOTAO 0 0 8 6 9 * 0 0 8 7 2
COOTAO 0 0 8 5 4 0 0 8 6 4 0 0 8 7 0 *
COOTLP 0 0 8 6 4 * 0 0 8 6 6
COOT P O 0 0 8 5 9 0 0 8 6 1 *
COOTRT 0 0 8 5 6 0 0 8 6 7 *
00527 01561*
COFFS
COFNOI 0 1 5 7 2 0 1 5 7 5 *
01645 01683*
CONVI
01662 01691*
CONV2
00247 008 45*
COO F F
00 2 4 5 0 0 8 3 6 *
COON
CPUNCH 0 0 5 3 0 0 1 5 0 2 *
00038*00427 00621 00667 00858
CR
00533 01102*
CRE G
CSTLEV 0 0 5 3 6 0 1 5 5 1 *
CTRACE 0 0 5 3 9 0 1 5 3 5 *
CTRC E 3 0 0 7 6 6 0 1 5 3 8 *
00 5 4 2 0 1 5 3 0 *
CVE R
CWI N OO 0 0 5 4 5 0 1 4 6 9 *
00153*00751 00757 01223 01236
DE L I M
DFTCH P 0 0 0 2 6 * 0 0 2 5 7
OFTNLP 0 0 0 2 7 * 0 0 2 5 7
00039*00855
OLE
EOT
000 3 5 * 0 0 3 4 3 00652 00684 00738
ERRMSG 0 0 4 3 6 0 0 7 8 2 * 0 0 7 8 9
ERROR 0 0 3 1 4 0 0 7 8 9 *
EXPI
00253 01232*
01234 01250*01251
EX P 2
EX PADO 0 1 2 6 6 * 0 1 2 8 2
EX P C DL 0 1 2 5 2 0 1 2 6 0 * 0 1 2 6 9
EXPCHM 0 1 2 6 2 0 1 2 7 0 *
EXPDL� 0 1 2 3 3 * 0 1 2 3 7
EXP RTN 0 1 2 4 8 * 0 1 2 5 7 0 1 2 7 5
EXPSUS 0 1 2 7 1 0 1 2 7 6 *
EXPTOI 0 1 2 5 4 * 0 1 2 7 3
EXPTDL 0 1 2 4 1 0 1 2 4 4 0 1 2 4 7 0 1 2 5 5 *
EXPTRM 0 1 2 6 3 0 1 2 7 6 0 1 2 8 6 *
F I RQ
01706 *01720
F I RQR 0 0 2 3 7 0 0 8 1 6 *
GOADDR 0 1 3 4 4 0 1 3 4 9 * 0 1 3 8 0
GONDFT 0 1 3 5 1 0 1 3 6 7 *
H I VT R 0 0 1 0 0 * 0 0 5 9 2
HSSLN K 0 1 0 4 6 * 0 1 0 4 9
HSDRTN 0 1 0 6 2 0 1 0 8 6 0 1 0 9 2 *
HS OTA 0 0 2 4 8 0 1 0 4 3 * 0 1 0 9 1
8-71
01333*01372
01034 01166 01185 01428 01496 01654
01256
00782 01032 01034
PAGE
036
PC2 a
FC3 5
FC3 3
rC1 4
tC20
FC0 6
0000
r844
r870
F870
FFE4
AS S I S T 0 9 . S A a O
AS S I ST0 9
-
HS H C H R
HSH COK
HSU ooT
HSH �NE
01076*01084
01079 0108 1 *
01077 Ol0 8 0 *
01060*01090
HSH NXT 0 1 0 6 8 * 0 1 0 7 1
HS HTT� 0 1 0 5 1 * 0 1 0 5 9
INCHN P 0 0 0 5 6 * 0 0 9 2 0 0 0 9 2 4
I N ITVT 0 0 1 8 8 0 0 2 3 3 *
00197 00264*
INTVE
I NTVS 0 0 1 9 7 0 0 2 5 6 *
01707*0172l
I RQ
00966
Ol 337
00238 00808*
001 39*00752 0 1 5 39
00297 00740 00784*00809
000 3 7 * 0 0 6 2 3 00638 00669 0 1 0 3 4
00151 * 0 0 4 0 2 0 0 6 1 9 0074l 00 7 7 2
000 6 4 * 0 0 2 2 2
007 3 8 * 0 0 7 4 8
01459 014 6 2*
MU P DAT 0 1 4 0 6 0 1 4 1 6 0 1 4 5 6 *
01709*01723
NM I
FAB 7 NM I CON 0 0 7 4 2 0 0 7 7 2 *
00240 00740*
F A7 0 NM I R
F A D8
OF99
FAC 1
O OOA
OF8F
0 00 8
FA79
F E3 6
FE2B
F F EC
M C 6 8 0 9 MON ITUR
I RQR
�ASTOP
�OOP
�F
MISF�
MON I T R
M S HOWP
MUPBAO
F AB O NM I 'rRC 0 0 7 4 4 0 0 7 4 7 0 0 7 6 6 *
DF 9 B NUMB E R 0 0 1 3 7 * 0 0 4 0 1 0 0 4 6 6 0 1 1 7 9
01308 01309 01405 01497
0 0 0 8 NUMBKP 0 0 0 2 9 * 0 0 1 2 6 0 0 1 2 8 0 0 3 8 9
O O O B NUMF UN 0 0 0 6 8 * 0 0 3 1 3
0 0 1 B NUMVTR 0 0 0 9 9 * 0 0 1 2 4 0 0 1 9 0
0 0 0 4 OUT2 HS 0 0 0 6 0 * 0 1 0 6 9 0 1 1 5 6 0 1 5 7 4
0 0 0 5 OUT 4 H S 0 0 0 6 1 * 0 0 7 5 4 0 1 0 6 5 0 1 1 5 3
0 0 0 1 OUTCH
00057* 0 0 3 9 6 00885 00893
01465
O O O B PAU S E
00 0 6 7 *
OFFC PAU S E R 00 1 1 7 * 0 0 2 5 2
O F 9 3 PCNTER 0 0 1 4 5 * 0 0 3 9 3 0 1 2 4 2
00062*00381 01044 01061
0 0 0 6 PCRLF
00 0 5 9 * 0 0 3 5 2 0 0 7 9 1 0 0 9 9 9
0 0 0 3 POATA
0 0 0 2 POATA1 0 0 0 5 8 * 0 0 4 3 8 0 0 7 5 0
0 0 3 E PROMPT 00 0 2 8 * 0 0 3 9 4
F E 2 1 P RTA DR 0 1 4 4 0 0 1 4 4 8 *
OF 9 5 PSTACK 0 0 1 4 3 * 0 0 3 9 8 0 0 4 3 5
000 2 5 * 0 0 0 4 2 0 0 0 4 3 0 0 0 4 4
E O O O PTM
00359 00 3 6 1 0 1 5 4 2
E O O O PTMC 1 3 0 0 0 4 3 * 0 0 3 5 9
E 0 0 1 PTMC2
00044 * 0 0 3 5 8 00361
E 0 0 1 PTMSTA 0 0 0 4 2 *
E 0 0 2 PTMTM l 0 0 0 4 5 * 0 0 3 5 5 0 0 3 5 6 0 1 5 4 2
E 0 0 4 PTMTM 2 0 0 0 4 6 *
E 0 0 6 PTMTM 3 0 0 0 4 7 *
E 7 0 0 RAMOFS 0 0 0 2 1 * 0 0 1 1 1
0 0 4 0 7 004 2 4 01258 0 1 3 0 1
F 07 9 REA D
01157 *01176 01186
F C 9 4 RE G 4
F CC 3 REGAGN 0 1 1 6 7 0 1 1 8 9 *
F C 7 0 RE(:C H 3 01 1 0 4 0 1 1 3 5 *
F C 9 0 REGCNG 0 1 1 4 9 0 1 1 6 4 *
F C 5 0 RE GMSK 0 1 1 2 3 * 0 1 1 3 7
F C B l REGNXC 0 1 1 6 5 0 1 1 7 7 *
01647
01653
01426
00886 00897
01364
01255 01260 01265 01267 01278 01299 01300
01637
01358 01374 01620 01633
01677
01452 01579 01612
00896 00983 01082 01142 01146 01396 01430
01093 01161 01439 01581 01616 01679
01023
00045 00046 00047 00259 00355 00356 00358
01336*01412
8-72
PAG E
037
ASS I ST 0 9 . SA : 0
FC78
FC81
FC92
FAS 3
FC6F
FC9S
F CAA
F CC 9
F C D6
F CS B
F837
F83D
FOOO
DF6 6
F800
0 80 0
F F D4
F A DS
DF 9 7
FABC
FAF O
F 9EC
F8C9
008C
DFF 8
0007
DF 5 1
FEC3
FFE8
F F DC
F AD8
F F D8
F AD8
DFFB
DF90
F8B5
F 8A 8
F895
F87D
REGP l
REGP2
REGP3
REGPRS
REGPRT
REGRTN
REGSKP
REGTF l
REGTF 2
REGTWO
RESET
RESET2
ROM20F
ROM2WK
ROMBEG
ROMS I Z
RSRVD
RSRVDR
RSTACK
RT I
RTS
SEND
S I GNON
SKIP2
SLEVE L
S PACE
STAC K
STLDFT
SWI
SWI 2
SWI 2 R
SWI 3
SW I 3 R
SWI BF L
SWI CNT
SWI DN E
SWI LP
SWI R
SWI VTB
DF 9 1
DF51
0009
DFC 2
TRACE C
TSTACK
VCTRSW
VECTAB
DFAO
DF O O
FA7 2
FA6E
F ADS
F AD 3
F A2 A
FAll
FAOF
F8E6
F 8 D2
WI N DOW
WORKPG
XQC I D'r
XQPA U S
Z B KCMD
ZBK PNT
Z I N2
Z I NCH
Z I N CH P
Z MONT 2
Z MONTR
ASS I ST0 9 - MC 6 8 0 9 �1ON ITOR
01138*01143 01159
01140 01144*
01151 01155*
00755 007 6 8 * 0 0 7 9 9
00768 01102 01134*
01162*01201
01172*01175
01191*01194
01197*01200
01181 01183 *
00 2 1 7 * 0 0 2 4 1 0 1 7 2 4 0 1 7 2 6
00219*00223
00023*00202
00155*
0 0 0 2 0 * 0 0 0 2 3 0 0 1 1 1 00 1 6 7 0 1 7 1 6
00022*00023 01716
01703*01717
00234 00809*
00141*00345 00788
00774*00816
00787 00841*00844 00845
0056 8 * 0 0 6 2 4 00640 00668 00682
00342*00350
00049*00863 01154 01220 01523
00123*00746 01553 01556
00063*01047 01054 01056 01073
00158*00217
01551 01555*
01708*01722
01705*01719
00236 00806*
01704*01718
00235 00807*
00119*00301 00311 01363
0 0 1 4 9 * 0 0 296 0 0 6 4 1 00743
00302 00306 00311*
00305*00308
0 0 2 3 9 0 0 29 6 *
00283*00283 00284 00285 00286
0 0 29 3 0 0 2 9 4 0 0 3 17
0 0 1 4 7 * 0 0 4 0 3 0 0 7 59 0 0 7 6 2 0 1 5 3 6
00157*01189
00065*
00125*00183 00348 00349 00353
00725 00825 00837 00853 00857
01485 01507 01508 01510 01540
01708 017 0 9
00131*01245 01470
00111*00112 00113
00612 00709 00716 00725*
00611 00700 00715 00724*00869
00756 00758 00760 0076 3 00765
00293 00310 00799*00810
00622 00625*
00283 00612*00615 00617
00611*00613
00347 0 0 3 5 3*
0029 1 00345*
8-73
01173 01423
00287 00288 00289 00290 00291 00292
00429 00432 00568 00594 00625 00724
00860 00977 00981 00985 01025 01224
01547 017 0 3 01704 01705 01706 01707
00800*
P AG E
038
F 9F2
F9FO
FA2E
F A3 7
FA3 9
F 9 D9
F 9 E6
FA4E
FA3 D
FA3C
F A4 0
FA48
FA4 6
F 9F6
F 9 FA
ASS I ST0 9 . SA : 0
Z OT2HS
ZOT 4 H S
Z OTCH1
Z OTCH 2
Z OTCH 3
Z OUT2H
Z OUTHX
Z PAUSE
Z PCRLF
Z PCRLS
Z P DATA
Z PDTA1
Z P DTLP
Z S PACE
ZVSWTH
ASS I ST0 9 - M C 6 8 0 9 MON I TO R
00287 00571*
00288 00570*
00284 00636*
00582 00640*
00593 00598 00600 00620 00626 00641*00 7 0 4
00 557*00570 0 0 5 7 1 0 1 0 3 0 01393
00561 00564*01052
00294 00700*
00289 00654*
00637 00652*00654
00286 00667*
00285 00683*
006 39 00682*00685
00290 00581*
00292 00591*
8-74
AP PEN DIX C
MAC H I N E CODE TO INSTRUCTION C ROSS REFEREN C E
C.1 I NTRO D U CT I O N
Thi s appendix contai ns a cross reference between the mach i ne code, represented i n hex­
adeci mal and the i n struction and addressing mode that it represents. The n u m ber of
M PU cycles and the n u m ber of program bytes is a l so g iven . Refer to Table C-1 .
C-1
'o
Table C·1. M achine Code to Instruction Cross Reference
OP
Mnem
Mode
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
N EG
Dir ct
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
10
lE
lF
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
I
OP
Mnem
6
2
COM
LSR
6
6
2
2
ROR
ASR
A S L, LSL
ROL
DEC
6
6
6
6
6
. 2
2
2
2
2
LEAX
LEAY
LEAS
LEAU
PSHS
PULS
PSHU
PULU
INC
TST
JMP
CLR
6
6
3
6
2
2
2
2
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Direct
Page 2
Page 3
NOP
SYNC
I nherent 2
Inherent 4
LBRA
LBSR
Relative 5
Relative 9
3
3
DAA
ORCC
I nherent 2
Immed 3
1
2
ANDCC
S EX
EXG
TFR
Immed 3
I nherent 2
Immed 8
Immed 6
2
1
2
2
BRA
BRN
BHI
BLS
B H S , BCC
B LO, BC5
BNE
B EQ
BVC
BVS
BPL
BMI
BGE
B LT
BGT
B LE
Relative
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Relative
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
Mode
r
4+
4+
4+
Ind xed 4 +
I mmed 5 +
5+
5+
I mmed 5+
I nherent
�
I
RTS
ABX
RTI
CWAI
MUL
#
OP
Mnem
Mode
2+
2+
2+
2+
2
2
2
2
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
N EG
Indexed
5
3
6/ 1 5
20
11
SWI
Inherent
NEGA
I nherent 2
19
1
2
1
70
71
72
73
74
75
76
n
78
79
7A
7B
7C
70
7E
7F
COMA
LSRA
2
2
RORA
ASRA
AS LA, LSLA
R O LA
DECA
2
2
2
2
2
I N CA
TSTA
2
2
CLRA
Inherent 2
50
51
52
NEGB
Inherent 2
80
81
82
53
COMB
LSRB
2
2
83
RORB
A5RB
A S L B , LSLB
R O LB
DECB
2
2
2
2
2
INCB
T5TB
2
2
CLRB
I nherent 2
54
55
56
57
58
59
5A
5B
5C
50
5E
5F
LEG E N D :
- N umber o f M P U cycles ( less possible push pull or indexed-mode cycles)
I Number of program bytes
• Denotes unused opcode
C-2
84
85
86
87
sa
89
8A
8B
8C
80
8E
8F
I
6+
2+
COM
LS R
6+
6+
2+
2+
ROR
ASR
ASL, LS L
ROL
DEC
6+
6+
6+
6+
6+
2+
2+
2+
2+
2+
INC
TST
JM P
CLR
6+
6+
3+
6+
2+
2+
2+
2+
Indexed
N EG
Extended 7
3
COM
LS R
7
7
3
3
ROR
ASR
AS L, L S L
ROL
DEC
7
7
7
7
7
3
3
3
3
3
7
7
4
Extended 7
3
3
3
3
INC
TST
JMP
CLR
S U BA
C M PA
S B CA
SUBD
ANDA
BITA
LOA
Immed
2
2
2
4
2
2
2
2
2
2
3
2
2
2
EO R A
ADCA
ORA
ADDA
CMPX
B5R
LOX
2
2
2
2
Immed 4
Relative 7
Immed 3
2
2
2
2
3
2
3
Table C·1 . M achine Code to Instruction Cross Reference (Continued)
OP
#
OP
Mnem
Mode
2
CO
SUBB
I mmed
Cl
CMPB
C2
S B CB
Mnem
Mode
90
S U BA
Direct
91
C M PA
4
2
92
S B CA
4
2
4
93
S U BD
6
2
94
ANDA
4
2
95
BITA
4
2
96
LOA
4
2
97
STA
4
2
98
99
EO R A
4
2
ADCA
4
2
9A
ORA
4
2
9B
ADDA
4
2
9C
C M PX
6
2
2
1 021
LBRN
2
2
1 022
LBHI
4
C6
5(6)
LOB
Immed
2
2
1 023
LBLS
5(6)
4
4
C7
1 024
2
LBHS, LBCC
5(6)
C9
2
2
LBCS , L B LO
5(6)
4
ADCB
1 025
1 026
LBNE
5(6)
4
4
CA
ORB
2
2
1 027
LBEQ
C t3
ADr 3
5(6)
2
2
1 028
LBVC
4
CC
LDD
5(6)
3
3
1 029
LBVS
5(6)
4
1 02A
LBPL
5(6)
4
1 02B
LBMI
5(6)
4
1 02C
LBGE
5(6)
4
1 020
L B LT
5(6)
4
5
2
CF
A2
S B CA
4+
2+
A3
S U BD
6+
2+
A4
A N DA
4+
2+
AS
B ITA
4+
2+
A6
LOA
4+
2+
A7
STA
4+
2+
AS
EO R A
4+
2+
A9
ADCA
4+
2+
AA
ORA
4+
2+
AB
ADDA
4+
2+
AC
C M PX
6+
2+
AD
JSR
7+
2+
AE
LOX
5+
2+
AF
STX
5+
2+
I ndexed
BO
S U BA
Extended 5
3
Bl
CMPA
5
3
B2
S B CA
5
3
B3
S U BO
7
3
B4
ANOA
5
3
B5
B ITA
5
3
B6
LOA
5
3
B7
STA
5
3
B8
EORA
5
3
B9
AOCA
5
3
BA
ORA
5
3
BB
ADOA
5
BC
CMPX
7
BD
JSR
8
BE
LOX
6
BF
STX
Extended 6
3
3
3
3
3
NOTE: All u n used opcodes a re both u ndefined
and i llegal
4
2
STX
2+
5
EOR B
9F
2+
R elative
C8
2
4+
3
2
I m med
2
4+
4
Page 2 and 3 Machine
Codes
BITB
5
I n dexed
2
2
C5
7
C M PA
r
2
2
ADDD
LOX
S U BA
#
Mode
ANDB
JSR
Al
Mnem
C4
90
AO
OP
2
C3
9E
D irect
#
2
CD
CE
LOU
I mmed
3
3
DO
SUBB
Direct
4
2
01
CMPB
4
2
02
SBCB
4
2
03
ADDD
6
2
04
ANDB
4
2
05
BITB
4
2
06
LOB
4
2
07
STB
4
2
08
EO R B
4
2
09
ADCB
4
2
DA
ORB
4
2
DB
ADDB
4
2
t
DC
LDD
5
2
DO
STD
5
2
DE
LOU
5
2
OF
STU
5
2
EO
SUBB
4+
2+
El
CMPB
4+
2+
E2
S B CB
4+
2+
E3
ADDD
6+
2+
E4
ANOB
4+
2+
E5
BITB
4+
2+
E6
LOB
4+
2+
E7
STB
4+
2+
Direct
Indexed
E8
EO R B
4+
2+
E9
AOCB
4+
2+
EA
ORB
4+
2+
EB
AOOB
4+
2+
EC
LDD
5+
2+
ED
STO
5+
2+
EE
LOU
5+
2+
EF
STU
5+
2+
Indexed
FO
SUBB
Extended 5
3
Fl
CMPB
5
3
F2
SBCB
5
3
F3
ADOO
7
3
F4
ANOB
5
3
F5
BITB
5
3
F6
LOB
5
3
F7
STB
5
3
F8
EO R B
5
3
F9
AOCB
5
3
FA
ORB
5
3
FB
ADOB
Extended 5
3
FC
LDD
Extended 6
FD
STO
FE
LOU
FF
STU
t
�
Extended 6
C-3/C-4
3
3
3
3
1 02E
LBGT
5(6)
4
1 02F
LBLE
Relative
5(6)
4
l 03F
SWI2
I n herent
20
2
1 083
CMPD
I m med
5
4
l OSC
CMPY
5
4
l OSE
LOY
I m med
4
4
1 093
C M P. D
Direct
7
3
1 09C
CMPY
7
3
l09E
LOY
l 09 F
STY
1 0A3
CMPD
1 0AC C M P Y
I
Di
i
ct
I ndexed
�
6
3
6
3
7+
3+
7+
3+
6+
3+
1 0AE
LOY
l OAF
STY
1 0B3
CMPD
Extended 8
4
10BC C M P Y
: �
4
l OB E
LOY
10BF
STY
1 0C E
LOS
I ndexed
6+
3+
4
ExtenQed 7
4
I m med
4
4
l OD E LOS
Direct
6
3
1 0D F S T S
Direct
6
3
3+
1 0EE
LOS
I n dexed
6+
1 0EF
STS
I n dexed
6+
1 0FE
LOS
Extended 7
4
4
1 0FF
STS
Extended 7
1 1 3F
SWI3
I n herent
1 1 83
CMPU
I mmed
1 1 8C
CMPS
1 1 93
CMPU
1 1 9C
l 1 A3
3+
20
2
5
4
I m med
5
4
Direct
7
3
CMPS
Direct
7
3
CMPU
I ndexed
7+
3+
1 1 AC C M P S
I ndexed
7+
l l B3
3+
CMPU
Extended 8
4
l l BC CMPS
Extended 8
4
AP PEN DIX D
P ROG RAM M I N G AI D
D.1 I NTRO DUCTION
'
This appendix contains a com p i l ation of data th at w i l l assist you i n p rogramm i ng the
M6809 processor. Refer to Table 0-1 .
Table D·1 . Program ming Aid
Branch InsbUcdons
Addressing
Addreaing
Mode
IllSIrUction
BCC
Forms
BCC
Branch C - O
•
•
•
·
•
5(6)
4
Long B ranch
•
•
•
•
·
lBCC
10
BCS
25
3
2
Branch C = 1
•
·
•
•
•
10
5(6)
4
Long B ranch
•
•
·
•
·
24
BCS
lBCS
BLS
BEC
27
3
2
B ranch Z = O
•
•
·
·
•
LBEC
10
5(6)
4
Long B ranch
•
•
·
·
•
BGE
2C
3
2
Branch � Zero
·
•
•
•
·
10
5(6)
4
Long B ranch � Zero
•
·
•
·
•
lBGT
2E
3
10
5(6)
2
4
B ranch > Zero
·
•
•
•
•
Long B ranch > Zero
•
·
•
•
·
BLT
BHS
BHI
22
3
LBHI
10
5(6)
BHS
22
24
3
2
4
2
B ranc�, nigher
•
•
•
·
•
Long B ranch H ig her
•
•
•
·
•
Branch H igher
•
•
•
·
5(6)
4
Long B ranch Higher
2F
3
10
5(6)
2
4
2
4
10
B lE
lBlE
24
BLE
•
•
·
•
B ranch s Zero
•
•
•
·
•
Long B ranch s Zero
•
•
•
•
•
BPL
BRN
25
3
B ranch lower
•
•
•
·
•
Long B ranch lower
·
•
•
·
•
L B lO
10
5(6)
2
Branch Lower
5 3 2 1 0
H N Z V C
•
•
•
·
•
10
5(6)
4
Long B ranch Lower
·
•
·
·
·
or Same
B LT
20
3
L B LT
10
5(6)
BMI
2B
3
LBMI
10
5(6)
2
4
B ranch < Zero
·
·
·
·
·
Long B ranch < Zero
·
·
·
•
•
2
4
B ranch Minus
·
•
·
•
·
Long B ranch M inus
·
·
·
·
·
BNE
26
3
2
B ranch Z .. O
·
·
•
•
·
LBNE
10
5(6)
4
Long Branch
·
·
•
·
·
Z .. O
BPL
2A
�
LBPL
10
5(6)
'!
4
B ranch Plus
•
•
·
•
•
Long B ranch Plus
·
·
·
·
·
BRA
20
lBRA
16
3
5
2
B ranch Always
BRN
21
3
LBRN
10
5
•
•
•
•
•
3
2
Long Branch Always
•
•
·
·
·
B ranch Never
·
·
·
•
·
4
Long B ranch Never
·
•
•
•
·
2
B ranch to S ubroutine
•
·
·
·
•
Long Branch to
·
·
·
•
·
Branch V = O
·
•
•
•
·
Long B ranch
·
·
•
•
•
B ranch V - I
•
·
•
•
•
Long B ranch
•
•
·
·
•
21
or Same
B LO
3
Description
2A
BRA
BSR
BSR
lBSR
80
17
7
9
3
S ubroutine
2F
BlO
23
26
•
•
,
2B
BNE
or Same
lBHS
aIati\
-
20
BMI
2E
BHI
OP
23
Z=O
LBGE
BGT
BLS
L B LS
2C
BGT
Forms
or Same
C= 1
27
BGE
Instruction
c=o
25
BEC
Description
Mode
5 3 2 1 0
H N Z V C
Relative
OP ,
24
3" 2
BVe
BVe
28
3
LBVC
10
5(6)
2
4
28
25
BVS
0-1
V=O
BVS
29
3
lBVS.
10
5(6)
29
2
4
V= I
Table D·1. Programming Aid (Continued)
SIMPLE BRANCHES
,
OP
BRA
lBRA
20
16
3
5
2
3
BRN
lBRN
21
1 021
3
5
2
4
BSR
lB S R
80
7
2
3
9
17
SIMPLE CONDITIONAL BRANCHES ( Notes 1 -41
Test
True
OP
False
OP
N=l
Z= l
V= l
C=l
BMI
B EQ
BVS
BCS
2B
BPl
BNE
BVC
BCC
2A
26
29
25
28
24
UNSIGNED CONDITIONAL BRANCHES ( Notes 1 -41
SIGNED CONDITIONAL BRANCHES (Notes 1 -41
Test
True
OP
False
OP
Test
True
r> m
r�m
r=m
rs m
r< m
BGT
BGE
BEQ
BlE
B lT
2E
BlE
B lT
BNE
BGT
BGE
2F
20
26
2E
2C
r> m
r� m
r=m
r :s m
r< m
BHI
BHS
B EQ
BlS
B lO
2C
27
2F
20
27
OP
22
24
27
23
25
False
BlS
B lO
BNE
BHI
BHS
OP
23
25
26
22
24
N otes:
1.
All conditional branches have both short and long variations.
2. All short branches a re 2 bytes and require 3 cycles.
3.
All conditional long branches are formed by prefixing the short branch opcode with $ 1 0 and uSing a 1 6-bit destination offset.
4.
All conditional long branches require 4 bytes and 6 cycles if the branch is taken or 5 cycles if the branch is not taken .
0·2
Table D·1 . Programming Aid (Continued)
Addressi ng
Immediate
Instruction
Direct
Modes
Indexed
Extended
-
#
Op
-
#
Op
-
I
Op
-
I
B + X - X ( U nSigned )
•
•
•
•
ADCA
B9
2
2
99
4
2
A9
4+
2+
B9
5
A + M + C- A
A DC B
I
I
I
I
2
2
D9
4
I
C9
2
E9
4+
2+
F9
5
3
3
B + M + C- B
I
I
I
I
I
ADDA
8B
2
2
9B
4
2
A8
4+
2+
BB
5
A+ M-A
I
I
I
I
I
CB
2
2
DB
4
2
EB
4+
2+
FB
3
B + M- B
ADD D
5
3
ADDB
I
I
4
I
I
C3
I
3
D3
6
2
E3
6+
2+
F3
7
3
D + M:M + 1 - D
•
I
I
I
I
ANDA
B4
2
2
94
4
2
A4
4+
2+
B4
3
AA M-A
•
I
•
C4
I
0
ANDB
5
2
2
D4
4
2
E4
4+
2+
F4
5
3
B A M-B
•
I
1C
I
0
A N D CC
3
2
ABX
AD C
ADD
AN D
ASL
08
6
68
2
6+
2+
78
7
2
1
2
1
3
47
2
1
57
2
1
B I TA
85
2
BITB
C5
2
CLR
CLRA
2
2
07
6
2
67
6+
2+
77
7
3
95
4
2
A5
4+
2+
5
3
E5
4 +
B5
F5
D!:
4
2
2+
5
CLR
Description
} [H 1 1 1 1 1 1 1 f.- o
�
�} I I I I I I I�
A
B
M
+-
c
b7
A
bO
----.
bo
7
c
8 i t Test A ( M A A )
A
•
•
7
8
I
I
I
8
I
I
I
I
8
I
I
I
I
I
8
I
I
•
I
8
I
I
•
I
8
I
I
•
I
•
I
I
0
•
•
I
I
0
•
4F
2
1
O- A
•
0
1
0
0
5F
2
1
3
C LR B
B i t Te�t B 1 M
Bi
•
0
1
0
0
6
2
6F
6+
2+
7F
7
O- B
OF
3
O- M
•
0
1
0
0
CMPA
81
2
2
91
4
2
A1
4+
2+
B1
5
3
CMPB
Compare M from A
8
2
2
D1
4
I
E1
2+
F1
5
3
Compare M from B
8
10
5
2
4+
I
I
C1
I
4
10
7
7+
I
I
I
3
10
I
3+
10
8
4
Compare M : M + 1 from D
•
I
I
I
I
8
4
Compare M : M + 1 from S
•
I
I
I
I
8
4
Compare M : M + 1 from U
•
I
I
I
I
CMPD
93
83
CMPS
11
5
4
8C
CMPU
11
A3
7
11
3
9C
11
5
4
11
CMPX
8C
4
3
9C
CMPY
10
5
4
10
8C
B3
7+
3+
7
11
3
7+
3+
A3
6
7
11
BC
AC
93
83
11
B3
2
AC
6+
2+
BC
7
3
Compare M : M + 1 from X
•
I
I
I
10
I
3
7+
3+
10
8
4
Compare M : M + 1 from Y
•
I
I
I
I
A- A
•
I
I
0
1
•
I
I
0
1
•
I
I
0
9C
BC
AC
COMA
43
2
1
COMB
53
2
1
COM
CW A I
03
3C
�
6
2
63
6+
2+
73
7
3
2
DECA
DECB
DEC
B- B
M- M
CC
DAA
DEC
3
ASR
ASR
COM
3A
I
1
ASRB
BIT
CMP
-
48
58
ASLB
ASL
Op
CC A I M M - C C
A S LA
ASR
5 3 2 1 0
H N Z V C
Inherent
Op
Forms
OA
6
2
6A
6+
2+
7 4.
7
3
A
I M M - C C Wait for I n terrupt
1
7
19
2
1
Decimal Adjust A
•
I
I
0
I
4A
2
1
A- 1-A
•
I
I
•
5A
2
1
B- 1-B
•
I
I
I
I
.
M- 1-M
•
I
I
I
•
•
EORA
88
2
2
98
4
2
A8
4+
2+
B8
5
3
A ¥- M - A
•
•
EO R B
C8
2
2
DB
2
E8
4+
2+
F8
5
I
0
4
I
3
•
I
I
0
•
EXG
R 1 . R2
1E
8
2
B J,l- M - B
R 1 - R 22
•
•
•
•
•
INC
INCA
A+ 1-A
•
I
I
I
B+ 1-B
•
I
I
I
•
•
EOR
INCB
4C
5C
2
2
1
1
•
OC
6
2
6C
6+
2+
7C
7
3
I
I
I
OE
3
2
6E
3+
2+
7E
4
3
M+ 1-M
EA J - PC
•
JMP
•
•
•
•
•
JSR
9D
7
2
AD
7+
2+
BD
8
3
J u m p to S u broutine
•
•
•
•
•
5
3
M-A
•
I
I
0
•
3
M- B
•
I
I
0
•
INC
LD
LDA
86
2
2
96
4
2
A6
4+
2+
B6
LDB
C6
2
2
D6
4
2
E6
4+
2+
F6
5
LDD
CC
3
3
DC
5
2
EC
5+
2+
FC
6
3
M:M + 1 - D
•
0
•
4
10
6
3
10
I
10
4
I
LDS
6+
3+
10
7
4
M:M + 1-S
•
I
I
0
•
DE
CE
EE
CE
3
3
DE
5
2
EE
5+
2+
6
3
M:M + 1 - U
•
I
0
•
3
4
3
9E
5
2
AE
2+
6
3
M:M + 1 - X
•
10
6
3
6+
3+
7
4
M:M + 1 - Y
•
I
0
10
I
4
BE
10
•
I
BE
10
5+
FE
LDX
I
I
0
•
EA3 _ S
EA 3 _ U
•
•
•
•
•
•
•
•
•
•
•
•
I
•
•
•
•
I
•
•
LDY
8E
9E
4+
2+
4+
2+
LEAX
33
30
4+
2+
LEAY
31
4+
2+
32
LEAU
Legend :
OP
BE
AE
LEAS
LEA
FE
LDU
M
Operation Code ( H exadeci mal)
EA3 _ X
E A3 _ y
Complement of M
Test and set if true, cleared otherwise
Transfer I nto
•
Not Affected
N umber of MPU Cycles
H
Half-carry (from bit 3)
#
N umber of Program Bytes
N
Negative (sign bit)
+
Arithmetic Plus
Z
Zero ( R eset)
V
Logical or
Arithmetic Minus
V
Overflow, 2's complement
A
Log ical and
M u ltiply
C
Garry from ALU
¥-
Logical Exclusive or
•
CC
Condition Code R egister
Concatenation
0 ·3
Table D·1 . Programming Aid (Continued)
Addressing
I mmediate
Instruction
LSL
Forms
Op
-
,
LSLA
LSLB
LSL
LSR
Direct
Op
08
LSRA
LSRB
LS R
04
-
6
6
,
2
2
Modes
Indexed1
Op
68
64
-
6+
6+
,
2+
2+
Extended
Op
78
-
7
74
Inherent
I
N EG A
NEGB
NEG
00
6
2
60
6+
2+
70
ORA
ORB
ORCC
PSHS
PSHU
PSH
PUL
PULS
P U LU
ROL
8A
2
CA
1A
2
3
34 5 + 4
36 5 + 4
35 5 + 4
37 5 + 4
2
2
2
4
4
2
2
AA 4 +
EA
+
2+
l+
BA
FA
2
44
54
2
2
Description
�}[H I I I I I I I �
�} -+/ I I I I I I I f-t{]
7
5
5
....---
A
1
1
O
c
2
1
1
b7
b()
0
b7
bO
c
5 3 2 1 0
H N Z V C
•
0
0
I
I
I
I
I
I
•
I
I
I
I
I
I
•
•
I
•
9
8
I
I
I
I
I
I
I
I
I
•
•
•
•
•
I
I
I
b
I
I
I
•
•
3D
11
1
A
40
50
2
2
1
1
A+ 1-A
B+ 1 - B
M+ 1-M
8
I
I
I
12
2
1
N o O pera t i o n
•
•
•
•
•
A V M-A
B V M-B
CC V I M M - CC
•
I
I
I
I
0
0
•
3
3
3
x
B - D ( U nSigned)
8
•
•
7
2
2
P ush Registers on S Stack
•
•
•
•
•
Push Registers on U S taCk
•
•
•
•
•
2
2
Pull Registers from S S tack
•
•
•
•
•
P u l l Registers from U S tack
•
•
•
•
•
•
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
•
•
I
I
I
•
I
I
I
R O LA
ROLB
ROL
ROR
9A
DA
48
58
,
3
NOP
OR
-
3
MUL
NEG
Op
09
RORA
RORB
ROR
06
6
6
2
2
69
66
6+
6+
2+
2+
79
76
7
7
49
59
2
2
1
1
46
2
56
2
1
1
3
�}4HI I I I I I I P
�} 4}+j I I I I I I I P
c
c
3
b7
b7
b()
b()
•
•
•
•
•
RTI
3B 6m
1
Return From I n terrupt
RTS
39
1
Return from S ubroutine
•
•
•
•
•
A - M - C- A
B - M - C- B
8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
•
I
I
I
I
I
I
0
0
0
•
•
I
I
I
I
I
I
I
I
I
I
I
I
SBC
S B CA
SBCB
82
2
2
C2
2
2
92
02
4
4
97
07
DO
10
4
4
5
6
2
2
4+
4+
2+
2+
B2
F2
5
5
3
3
Sig n Extend B into A
•
A7
E7
ED
10
EF
EF
AF
10
AF
4+
4+
5+
6+
2+
2+
2+
3+
B7
5
5
6
7
A-M
B-M
0-M:M + 1
S-M:M + 1
•
F7
3
3
3
4
5+
5+
2+
2+
3
3
1D
STA
STB
STD
STS
2
2
2
3
OF
STU
STX
STY
SUBA
SUBB
SUBD
SWl o
SUB
SWI
OF
9F
10
9F
80
2
2
CO
2
2
83
90
DO
4
3
93
5
5
6
4
4
6
2
2
3
2
2
2
FD
10
6+
3+
BF
10
BF
4+
EO 4 +
A3 6 +
2+
SO
2+
FO
2+
B3
AO
4
U-M:M + 1
X-M:M + 1
Y-M:M + 1
5
5
7
3
3
3
A- M-A
B - M- B
0 - M:M + 1 - D
T STA
TSTB
T ST
•
•
•
0
•
0
•
0
0
•
•
•
I .
•
8
8
•
•
•
•
•
•
•
2
Software I n terrupt 1
Software I nterrupt 2
•
•
•
•
•
20
1
SoftwC!re I nterrupt 3
•
•
•
•
•
�4
1
Syn c hronize to Interrupt
•
•
•
•
•
:.!
R 1 - R2
•
•
•
•
•
Test A
Test B
Test M
•
I
I
I
I
I
I
0
0
0
•
19
20
11
3F
13
3F
10
1
3F
SYNC
TST
1
6
6
7
SWI36
R 1 , R2
2
8
FF
FF
SWI26
T FR
7
A2
E2
S EX
ST
5
1F
6
2
40
5D
OD
6
2
6D
6+
2+
70
7
2
2
3
1
1
•
•
•
•
Notes:
1.
This column g ives a base cycle and byte count. To obtain total count, add the values obtained from the I N D EX E D A D D R E S S I N G M O D E table,
in Appendix F.
2. R 1 and R 2 may be any pair of 8 bit or any pair of 16 bit reg isters.
The 8 bit reg isters are: A, B, C C , D P
T h e 1 6 b i t reg isters are: X , Y , U , S , D ,P C
3.
E A i s the effective address.
4.
The P S H and P U L i nstructions req u i re 5 cycles plus 1 cycle for each byte pushed or pulled.
5.
5(6) means: 5 cycles if branch not taken , 6 cycles if taken ( B ranch instructions) .
6.
SWI sets I and F bits. SWI2 and SWI3 do not affect I and F .
7.
Conditions Codes set as a direct result o f t h e instruction .
8.
Value of half-carry fla g is undefined .
9.
S pecial Case - Carry set if b7 is S ET .
0·4
AP PEN DIX E
ASCII C H ARACTER SET
E.1 I NTRO D U CT I O N
Th is appendix contain s the standard 1 1 2 character ASCII character set (7-bit code).
E.2 CHARACTER REPRESENTAT I O N A N D CODE I DENTI FICATION
The ASC I I character set is g iven in F i g u re E-1 .
�
Sir.
0
0
0
b6 b6
0
0
0
.b4
I
b3
b2
,
b1 ...... Column
I RoW Hex
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
NUL
OLE
SP
0
P
.
p
1
1
SOH
DCl
I
1
@
A
0
a
q
0
2
2
S TX
DC2
..
2
B
R
b
r
1
1
3
3
ETX
DC3
,
3
C
S
c
s
1
0
0
4
4
EOT
DC4
$
4
0
T
d
t
1
0
1
5
5
ENO
NAK
%
5
E
U
e
u
,
0
1
1
0
6
6
ACK
SYN
&
6
F
V
f
v
0
1
1
1
7
7
BEL
ETB
·
7
G
W
9
w
1
0
0
0
8
8
BS
CAN
(
8
H
X
h
x
1
0
0
1
9
9
HT
EM
)
9
I
Y
i
y
1
0
1
0
10
A
LF
SUB
·
J
Z
j
Z
1
U
1
1
11
Ii
VT
ESC
+
;
K
[
1
1
0
0
12
C
FF
FS
·
<
L
\
Ie
1
1
0
1
13
0
CR
GS
1
1
1
0
14
E
SO
RS
1
"
1
1
1
1
15
F
SI
US
-
/
=
M
.>
N
?
0
Figure E·1 . ASCI I Character Set
E-1
I
I
I
m
J
n
-
0
DEL
Each 7-bit character i s represented with bit seven as the h i gh-order bit and bit one as the
low-order bit as shown i n the fol low ing exam ple:
b7
1
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
bO
1
The bit representation for the character "A" is d eve loped f rom the bit pattern for bits
seven through five found above the col umn des i g n ated 4 and the bit pattern for bits fou r
through one found t o the l eft of t h e row des i g n ated 1 .
A hexadec i m a l notat ion is commonly used to i nd i cate the code for each character. Th i s
i s easily developed b y assu m i ng a log i c zero i n t h e non-exi stant bit eight position f o r t h e
col u m n n u m bers and u s i n g t h e hexadecimal n u m ber for the row n u m bers.
E.3 CONTROL C HARACTERS
The characters located in col umns zero and one of Fig ure E-1 are considered control
characters. By defi n i tion , these are characters whose occ u rrance i n a particular context
i n it i ates, mod i fies, or stops an action that affects the record i n g , processi n g , t ran s m i s­
sion, or i nterpretation of data. Table E-1 provides the mean i ngs of the control characters.
Table E·1 . Control Characters
Mnemonic
Meaning
Meaning
Mnemonic
Null
OLE
Data Link Escape
SOH
Start of Heading
DC1
Device Control 1
STX
Start of Text
DC2
Device Control 2
ETX
End of Text
DC3
Device Control 3
NUL
EOT
End of Transmission
DC4
ENO
Enquiry
NAK
ACK
Acknowledge
SYN
BEL
Bell
ETB
End of TransmiSSion Block
BS
Backspace
CAN
Cancel
Device Control 4
•
Negative Acknowledge
Synchronous Idle
HT
Horizontal Tabulation
EM
End of Medium
LF
Line Feed
SUB
S u bstitute
VT
Vertical Tabulation
ESC
Escape
FF
Form Feed
FS
File Separator
CR
carriage Return
GS
G roup Separator
SO
Shift Out
RS
Record Separator
SI
Shift I n
US
U nit Separator
DEL
Delete
E.4 G RA P H I C C H A RACTERS
The characters in co l u mns two through seven are considered graphic characters. These
characters have a visual representat ion which is normal ly d i s p l ayed or pri nted . These
characters and their names are g iven in Table E-2.
E-2
Table E·2. Graphic Characters
Symbol
SP
Name
S pace ( Normally Nonprinting)
Exclamation Point
Quotation Marks ( Diaeresis)
,
N umber Sign
$
Dollar Sign
%
Percent Sign
&
Ampersand
Apostrophe ( Closing Single Quotation Mark; Acute Accent)
Opening Parenthesis
Closing Parenthesis
Asterisk
+
Plus
Comma ( Cedilla)
Hyphen ( Minus)
Period ( Decimal Point)
I
0 . . .9
Slant
Digits 0 Through 9
Colon
S emicolon
<
Less Than
Equals
>
Greater Than
7
Question Mark
@
A . . .Z
Commercial At
U ppercase Latin Letters A Through Z
[
Opening Bracket
\
Reverse Slant
1
Closing Bracket
1\
Circumflex
U nderline
Opening Single Quotation Mark ( G rave Accent!
a. . .z
Lowerca� Latin Letters a Through z
Opening Brace
Vertical Line
Closing Brace
Tilde
E·3/E-4
APPENDIX F
OPCODE MAP
F.1 I NTRO D U CTION
Th is appendix contains the opcode map and add itional information for cal c u l at i n g re·
q u i red mch i n e cycles.
F . 2 OPCO D E MAP
Table F-1 is the opcode map for M6809 p rocessors. The number(s) by each i n struction in·
d icates the n u m ber of machine cycles req u i red to execute that i n struction. When the
n u m ber contai ns an " I " (e.g ., 4 + I), it indicates that the i ndexed addressing mode i s being
used and that an add itional n u mber of m ach i n e cycles may be requ i red. Refer to Tabl e
F-2 t o determ i ne t h e add itional machi n e cycles t o b e added .
Some i n struct ions i n the opcode map have two n u m bers, the second one i n parenthesis.
Th i s indicates that the i nstruction i nvolves a branch. The parenthet ical number appl ies if
the branch i s taken .
The "page 2, page 3" notation i n col u m n one means that al l page 2 instructions are
preceded by a hexadeci mal 1 0 opcode and al l page 3 instructions are preceded by a hex·
adec i m al 1 1 opcode .
F-1
Table F·1 . Opcode Map
Most-Significant Four Bits
OIR
0000
0
6
0000 0 NEG
0001
1
3 BRA
ACCA
Acca
001 1
0100
0101
3
4
2
EXT
OIR
INO
EXT
1001
1010
101 1
7
IMM
1000
8
9
A
7
2
4
4+ 1
01 1 1
5
INO
01 10
6
2
6+ 1
PAGE2
4+ 1
LEAX
3 BRNI
PAGE3 5 l B R N
4+ 1
lEAY
2
4
2
NOP
3 BHII
5(6) L B H I
4+ 1
lEAS
2
4
6
001 1 3 COM
2
SYNC
3 BlSI
5(6) l B l S
4+ 1
lEAU
2
2
6
0100 4 L S R
-
3 BHS
5(6) I B CC)
5+ 11 by
PSHS
2
2
-
3 B lO
5161 1 BCS)
5 + l l by
P U lS
6
01 1 0 6 ROR
5
lBRA
3 BNEI
5(6) l B N E
5 + l l by
PSHU
2
2
6
1:
01 1 1 7 ASR
9
lBSR
3 BEQI
5(6) lBEQ
5 + l l by
P U LU
2
2
000 1 1
0010 2
."
N
REL
0010
2
.f!
III
...
:J
If ·
�
I
]
0101 5
-
-
-
6 ASl
1 000 8 I lS LI
3 BVCI
5(6) lBVC
-
NEG
5
4+ 1
5
6+ 1
7
4+ 1
5
4+ 1
5
4+ 1
5
4
4+ 1
STB
5
4+ 1
5
4+ 1
5
4+ 1
5
4+ 1
5
5+ 1
6
5+ 1
STD
6
2
4
4+ 1
5
2
4
4
6
2
4
2
4
/
7
6+ 1
7
4+ 1
5
2
4
4+ 1
5
2
4
4
4+ 1
STA
5
4+ 1
5
2
4
4+ 1
5
2
4
4+ 1
5
2
4
4+ 1
5
2
4
3
5
7
2
4
6+ 1
7
2
4
2
4
3
3 BGEI
ANDCC � (6) L B G E
20
CWAI
2
2
6
1 1 01 0 TST
2
SEX
11
MUL
2
2
3
1 1 10 E JMP
8
EXG
6
1 1 1 1 F ClR
7
TFR
6+ 1
7
3+ 1
4
4,6,6 + 1 ,7
CMPX
I NC
I
2
3,5,5 + 1 ,6
lOX
JMP
6+ 1
2
7
_
ClR
-----
-
--
--
-
1
7
8
ADCB
9
ORB
AOOA
/
/
6,6 + 1 ,7
STY
B
LDD
8
4,6,6 + 1 ,7
lOY
/
A
AODB
5,7.7 + 1 ,8
CMPS
7+1
JSR
5,5 + 1 ,6
STX
6
EOR B
5,7,7 + 1 ,8
CMPY
7
7
BSR
TST
-
/
5
lOB
ORA
7
4
BITB
ADCA
6+ 1
3
ANDB
EORA
6/ 1 5
RTI
2
ADDD
lOA
-
1
SBCB
5,7,7 + 1 ,8
CMPU
ANDA
6+ 1
0
CMPB
4
DEC
- -
4+ 1
5
2
6+ 1
6
1 100 C I N C
5(6) lBlE
5
5
ROl
19120/20
SWII2/3
4+ 1
4+ 1
4
2
'- -
4
2
2
--- '----
2
7
3
ABX
'--- '---
7
6+ 1
ASl l lS LI
3 BPLI
5(6) lBPl
� BLEI
4
4+ 1
5,7,7 + 1 ,8
CMPD
2
3
ORCC
5(6) lBGT
E
2
SUBB
S B CA
/
2
6
1 010 A DEC
5(6) lBlT
6+ 1
4,6,6 + 1 ,7
SUBD
ASR
2
� BGTI
7
ROR
2
� B lTI
D
5
BITA
5
RTS
101 1 B
6+ 1
lSR
3 BVSI
5(6) lBVS
-
EXT
1111
F
S U BA
COM
2
OAA
-
IND
1 1 10
CMPA
6
1001 9 ROl
3 BMII
5(6) l B M I
DIR
1 101
B
IMM
1 100
C
5
3,5,5 + 1 ,6
lOU
1
C
/
5,5 + 1 ,6
STU
4,6,6 + 1 ,7
lOS
/
.,,6 + 1 ,7
STS
0
E
F
Table F·2. Indexed Addressing Mode Data
N o n I ndirect
Forms
Type
Constant O ffset F r o m R
(twos complement offsetl
Acc u m u lator O ffset From R
(twos complement offsetl
Auto I n c r e m ent/Decrem ent R
Assem bler
Form
Extended I n d i rect
-
#
L RI
Postbyte
OP Code
l R R 1 0 l 00
,R
l R R 00 1 00
0
0
OR R n n n n n
1
0
8 Bit Offset
n, R
l R R 0 1 000
1
1
(n, R ]
l R R l l 000
1 6 B it Offset
n, R
1 R R 0 1 00 l
4
2
(n, R ]
l R R 1 1 00 1
A - R eg i ster O ffset
B - R eg i ster Offset
o - R eg i ster Offset
A, R
l R ROOl l 0
1
0
(A, R ]
l RR 1 01 1 0
B, R
l R R 00 1 0 1
1
0
(B , R ]
l RR 1 0l 0l
0, R
1 RROl 01 1
4
0
(0, R ]
1 R R 1 1 01 1
5 Bit Offset
I n cre m e nt By 1
,R+
l R R OOOOO
2
0
I n crement By 2
, R ++
1 R R OOOO l
3
0
Decrement Bv 1
,-R
l R R OO0 1 0
2
0
+
+
-
#
3
0
4
7
2
defa u lt s to 8 - b i t
1
4
4
7
0
6
0
0
0
0
not a l l owed
( . R ++ ]
I
l R R 1 000 1
n ot a l l owed
,--R
l R R OOOl l
3
0
(, - - R ]
l R R 1 00 1 1
6
8 Bit Offset
n , PCR
l XX01 1 00
1
1
( n , PC R ]
l XX l l 1 00
4
1
1 6 B it Offset
n , PCR
l XX01 1 0 1
5
2
(n, PCR]
l XX 1 1 1 0 1
8
2
-
-
-
(n]
1 00 1 1 1 1 1
5
2
-
1 6 B it Address
R
=
x, Y, U or 5
X
=
Don't Care
x -- 00
U
=
10
Y -- 0 1
5 = 11
+ a n d + I n d i cate t h e n u m be r of addit i o n a l cycles a n d bytes for t h e p a r t i c u l a r v a r i at i o n .
-
I n direct
+
Assem bler
Form
x
n, R
N o Offset
Decrement By 2
Constant O ffset F r o m PC
(twos complement offsetl
Postbyte
OP Code
#
F·3/F·4
APPENDIX G
PIN ASSIGNMENTS
G .1 I NTRO DUCTIO N
of the p i n assi gnm ents for the M C6S09
This appe ndix i s p rovid ed for a q u ick refer ence
. Desc riptio ns of thes e pin assi gnm ents are
and M C6S09E p roce ssor s. Refe r to Fig u re G·1
g iven i n Sect ion 1 .
M C6809 E
M C6809
HAlT
HAi:T
NMi
TSC
LIC
XTAL
IRa
EXTAL
4
RffiT
5
M
a
RffiT
AVMA
R OY
a
E
OMA/BREa
R/W
BUSY
R/W
DO
DO
01
A3
01
A4
02
AS
03
A6
D4
A6
D4
A7
05
A7
05
AS
D6
AS
D6
AS
07
AS
07
02
03
Al0
A15
Al0
Al l
A14
Al l
A12
A13
A12
20
Figure G·1 . Pin Assignments
G·1 /G·2
21
A15
A14
A13
AP PEN DIX H
CONVERSION TAB LES
H .1 I NTRO D U CTI O N
This appendix p rovides some conversion tables for you r convenience.
H .2 POWERS OF 2, POWERS O F 1 6
Refer t o Table H-1 .
Table H·1 . Powers of 2; Powers of 1 6
161Tl
m=
2n
n=
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
1
-
2
-
3
-
Value
1
2
4
8
16
32
64
1 28
256
512
1 ,024
2,048
4 , 096
8 , 1 92
1 6,384
32,768
16fT1
m=
2n
n=
4
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
5
-
6
-
7
-
H-1
Value
65,536
1 3 1 ,072
262 , 1 44
524,288
1 ,048,576
2,097 , 1 52
4, 1 94,304
8,388 , 608
1 6,7n,21 6
33,554,432
67 , 1 08,864
1 34,21 7 ,728
268,435,456
536,870,91 2
1 ,073,741 ,824
2 , 1 47,483,648
H .3 H EXAD ECI M AL AN D D ECIMAL CONVERSI O N
Table H -2 i s a ch art that can be u sed for convert i n g n u m bers. fro m either hexadec imal to
decimal or dec i m a l to hexadec i m a l .
H .3.1 CONVERTI N G H EXAD ECI MAL TO DECIMAL. Find the decimal weights for cor­
responding hexadec imal characters beg i n n i ng with the least-s i g n ificant character. The
s u m of the dec i m a l wei g hts is the deci mal val ue of the hexadecimal n u m ber.
H .3.2 CO NVERT I N G DECIMAL TO H EXADECI MAL. Find the h i ghest decimal value in the
table which is lower than or equal to the decimal n u m ber to be converted . The correspon­
d i ng hexadec i mal character is the most-s i g n ificant d i g it of the f i n a l n u m ber. Subtract the
decimal val u e fo und from the decimal n u m ber to be converted . Repeat the above step to
determ ine the hexadec imal character. Repeat this process to f i n d the su bseq uent hex­
adecimal n u m bers.
Table H -2. Hexadecimal and Decimal Conversion Chart
15
15
Hex
Byte
Char
12
Dec
11
Hex
Char
8
7
8
7
Dec
Hex
0
Byte
Char
4
Dec
3
Hex
Char
0
Dec
0
0
0
0
0
0
0
0
1
4,096
1
256
1
16
1
1
2
8, 192
2
512
3
32
2
2
3
1 2 ,288
3
768
3
48
3
3
4
16,384
4
1 ,024
4
64
4
4
5
20,480
5
1 ,280
5
80
5
5
6
24,576
6
1 ,536
6
96
6
6
7
28,672
7
1 ,792
7
1 12
7
7
8
32,768
8
2,048
8
1 28
8
8
9
36,864
9
2,304
9
1 44
9
9
A
40,960
A
2,560
A
1 60
A
10
B
45,056
B
2,816
B
1 76
B
11
C
49, 1 52
C
3,072
C
1 92
C
12
0
53,248
0
3,328
0
2(S
0
13
E
57,344
E
3,584
E
224
E
14
F
61 ,440
F
3 .840
F
240
F
15
H -2
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applicalions intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees ariSing out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and ® are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
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_®
MOTOROLA
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