COLOSSUS Block Diagram
Transcription
COLOSSUS Block Diagram
5 4 2 1 Colossus 15/17 DIS_OPT Schematic IVY Bridge (rPGA989) Intel PCH (Panther Point) D C D C REV:-1 2012-01-05. B A 3 DY:No stuff DIS_OPT:DISCRTE OPTIMUS installed DY_35W:No stuff on 35W CPU DY_45W:No stuff on 45W CPU CR_Balen17:Stuff for 17" CR_Goya:Stuff for 15" B <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Document Number Cover Page Date: Wednesday, January 04, 2012 5 4 3 Rev 1 Colossus 2 Sheet 1 of 1 103 A 5 4 3 2 1 SYSTEM DC/DC COLOSSUS Block Diagram TPS51461 INPUTS 5V_S5 CPU DC/DC 48 OUTPUTS VCCSA=0D85V_S0 42~44 VT1323 INPUTS OUTPUTS DCBATOUT(5V_S5) VCC_CORE SYSTEM DC/DC VRAM/DDR3 VRAM/DDR3 64MBx16 D 88,89,90,91 45 SN1003055RUWR 64MBx16 4 INPUTS Project code : 91.4ST01.001 PCB P/N : 11254 Revision : -1 4 88,89,90,91 DDR3 SYSTEM DC/DC 41 RT8223M_5V/3D3V INPUTS DDRIII 1600/1333 Channel A DDRIII Slot 0 14 1600/1333 IVY Bridge-M D 5V_S5/3D3V_S5 1D05V_S0 Intel CPU Nvidia N13P GL OUTPUTS OUTPUTS 5V_AUX_S5 3D3V_AUX_S5 5V_S5 3D3V_S5 DCBATOUT PCIe x8 DDRIII 1600/1333 Channel B SYSTEM DC/DC DDRIII Slot 1 15 1600/1333 46 RT8207MZ INPUTS 83,84,85,86,87 OUTPUTS 1D5V_S3 0D75V_S0 DDR_VREF_S3 DCBATOUT 4,5,6,7,8,9,10 GFX DC/DC FDIx2 2.7GT/s C 42~44 VT1323 DMI2.0x4 5GT/s INPUTS DCBATOUT(5V_S5) LED Panel LVDS(Dual Channel) 49 VGA RGB CRT 50 HDMI 1.4 INPUTS PCH Panther Point-M 74 RJ45 CONN B Cardreader Realtek RTS5229 32 Gigabit NIC Realtek RTL8111F 31 59 ETHERNET (10/100/1000Mb) PCIE WEBCAM OUTPUTS AD+ BT+ DCBATOUT 49 USB 2.0 CONN x1 USB 2.0 ACPI 1.1 USB 3.0 CONN x3 USB3.0 SYSTEM DC/DC 82 3D3V_S5 SM Bus AMP HPA0929RTJR 2nd SPEAKE HD Audio IDT 92HD91 802.11a/b/g/n Bluetooth combo LPC debug port 71 KBC 30 Subwoofer AMP TPA3111D1 OUTPUTS 3D3V_S0 1D5V_S0 1D5V_S3 3D3V_VGA_S0 1D5V_VGA_S0 1V05_VGA_S0 INPUTS HDD1 56 1D5V_S3 5V_S5 3D3V_S5 HDD2 56 D/A ODD 56 27 A/D mSATA 103 1D5V_S0 5V_S0 3D3V_S0 L2:GND L6:Signa L3:Signal L7:GND L4:Signal L8::Bottom ENE KB9016QF 36 OUTPUTS PCB LAYER (DISCRETE) L1:Top L5:VCC 58 A Woofer LPC Bus Accelerometer HP3DC2 79 SPI Flash60 8MB 93 INPUTS 26 Switches SATA 29 2nd AMP TPA2012D2R B SYSTEM DC/DC Mini-Card 65 PCIE+USB2.0 AUDIO CODEC HP 1D8V_S0 VT385FCX SPI Internal Digital MIC OUTPUTS 62 17,18,19,20,21,22,23,24,25 MIC IN 47 RT8068A INPUTS LPC I/F PCIE INPUTS 26 PCIE ports (8) 40 BQ24738 High Definition Audio SATA ports (6) VGA_CORE CHARGER USB 3.0/2.0 ports (14) SD/MMC CONN 92 OUTPUTS DCBATOUT Finger Printer AES2665 64 HDMI 51 VCC_GFXCORE NCP3218G Intel CRT C OUTPUTS A 58 <Core Design> Wistron Corporation PWM FAN 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 28 Main SPEAKER Title Touch PAD69 5 4 Int. KB69 Block Diagram Thermal G709/P2800 3 28 Size A3 25 Date: 2 Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 2 of 103 5 PCH Strapping Name SPKR D 4 3 Processor Strapping Chief River Schematic Checklist Rev0.72 Schematics Notes Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ - 10-kΩ weak pull-up resistor. INIT3_3V# Weak internal pull-up. Leave as "No Connect". GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51 GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail. Configuration (Default value for each bit is 1 unless specified otherwise) CFG[2] PCI-Express Static Lane Reversal 1: 0: CFG[6:5] Disable Danbury:Left floating, no pull-down required. C HAD_DOCK_EN# /GPIO[33] CFG[7] Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. GPIO8 0 11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training D 11 1 DMI termination voltage. Weak internal pull-up. Do not pull low. Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions. HDA_SDO GPIO15 1 15 -> 0, 14 -> 1, ... PCI-Express Port Bifurcation Straps Disable Danbury: Leave floating (internal pull-down) NC_CLE Normal Operation. Lane Numbers Reversed Default Value Disabled - No Physical Display Port attached to 1: Embedded DisplayPort. Enabled - An external Display Port device is 0: connectd to the EMBEDDED display Port Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. NV_ALE Chief River Schematic Checklist Rev0.72 Strap Description CFG[4] Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor] 1 Pin Name SPI_MOSI Enable Danbury: 2 Voltage Rails POWER PLANE VOLTAGE 5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_S0 VCCSA_OD85V 0D75V_S0 VCC_CORE VCC_GFXCORE 3D3V_VGA_S0 1D5V_VGA_S0 1D05V_VGA_S0 5V 3.3V 1.8V 1.5V 1.05V 0.9 - 0.675V 0.75V 0.35V to 1.5V 0.4 to 1.25V 3.3V 1D5V 1D05V DESCRIPTION S0 5V_USBX_S3 1D5V_S3 DDR_VREF_S3 5V 1.5V 0.75V S3 BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5 6V-14.1V 6V-14.1V 5V 5V 3.3V 3.3V 1D05V_LAN 1.05V 3D3V_M 1D05V_M 3.3V 1.05V S0/M0, SX/M3, WOL_EN 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3 and 3D3V_S5 in Sx ACTIVE IN Low(0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality. High(1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality. Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail. GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled. C CPU Core Rail Graphics Core Rail All S states AC Brick Mode only S0/M0, SX/M3 ON whenever iAMT is active B B GPIO27 Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails. PCIe Routing LANE1 A N/A LANE2 17"Card Reader LANE3 15"Card Reader LANE4 Mini Card1(WLAN) LANE5 N/A LANE6 Intel GBE LAN / LAN LANE7 N/A LANE8 N/A USB2.0 Table Pair 0 1 2 3 4 5 6 7 8 9 10 11 12 13 N/A I 2 C / SMBus Addresses FREE BT WLAN combo FREE FREE Fingerprint USB 2.0 I/O CONN. Camera FREE FREE FREE USB3.0 Table USB Pair 1 2 3 4 Device I/O CONN. 1 FREE I/O CONN. 2 I/O CONN. 3 Device Chief River CRV Ref Des Address Hex Bus EC SMBus 1 Battery CHARGER BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA EC SMBus 2 PCH eDP SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK HDD1 1 mSATA 2 HDD2 3 N/A 4 ODD 5 N/A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 4 Device 0 <Core Design> Date: 5 SATA SMBus ADDRESSES USB 3.0 I/O CONN. 1 USB 3.0 I/O CONN. 3 SATA Table Pair Device USB 3.0 I/O CONN. 2 ON for iAMTLegacy WOL 3 2 Table of Content Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 3 of 103 5 4 3 2 1 CPU(1/7) IVY BRIDGE PROCESSOR (DMI,DP,PEG,FDI) PEG Compensation D D 1D05V_S0 1 OF 9 CPU1A 19 DMI_RXN[3:0] 19 DMI_RXP[3:0] C 19 FDI_TX_N[7:0] B28 B26 A24 B23 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 G21 E22 F21 D21 DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 G22 D22 F20 C21 DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3 FDI_TX_P0 FDI_TX_P1 FDI_TX_P2 FDI_TX_P3 FDI_TX_P4 FDI_TX_P5 FDI_TX_P6 FDI_TX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3 19 FDI_FSYNC0 19 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC 19 FDI_INT H20 FDI_INT 19 FDI_LSYNC0 19 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC A18 A17 B16 EDP_COMPIO EDP_ICOMPO EDP_HPD C15 D15 EDP_AUX EDP_AUX# C17 F16 C16 G15 EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3 C18 E16 D16 F15 EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3 19 FDI_TX_P[7:0] DP Compensation, within 500mil DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 FDI_TX_N0 FDI_TX_N1 FDI_TX_N2 FDI_TX_N3 FDI_TX_N4 FDI_TX_N5 FDI_TX_N6 FDI_TX_N7 Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap. Note: Lane reversal does not apply to FDI sideband signals. DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3 PCI EXPRESS* - GRAPHICS 19 DMI_TXP[3:0] B27 B25 A25 B24 Intel(R) FDI Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap. DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI IVY-BRIDGE 19 DMI_TXN[3:0] R4021 2 24D9R2F-L-GP 4mil 12mil NOTE: EDP_HPD Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up resistor on the motherboard. This signal can be left as no connect if entire eDP interface is disabled. Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. DP_COMP 633996-302 eDP 1D05V_S0 B PEG_COMP 1 R401 NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO J22 J21 H22 2 24D9R2F-L-GP PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_C_TXN0 PEG_C_TXN1 PEG_C_TXN2 PEG_C_TXN3 PEG_C_TXN4 PEG_C_TXN5 PEG_C_TXN6 PEG_C_TXN7 C416 C 416 DIS_OPT C415 C 415 DIS_OPT C414 C 414 DIS_OPT C413 C DIS_OPT413 C412 C 412 DIS_OPT C411 C 411 DIS_OPT C410 C 410 DIS_OPT C409 C DIS_OPT409 1 1 1 1 1 1 1 1 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN[0..7] 83 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_C_TXP0 PEG_C_TXP1 PEG_C_TXP2 PEG_C_TXP3 PEG_C_TXP4 PEG_C_TXP5 PEG_C_TXP6 PEG_C_TXP7 C432 C 432 DIS_OPT C431 C 431 DIS_OPT C430 C 430 DIS_OPT C429 C 429 DIS_OPT C428 C 428 DIS_OPT C427 C DIS_OPT427 C425 C 425 DIS_OPT C426 C 426 DIS_OPT 1 1 1 1 1 1 1 1 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP 2SCD22U10V2KX-1GP PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP[0..7] 83 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 PEG_RXN[0..7] 83 Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils. PEG_RXP[0..7] 83 C B Hand control CPU1 P/N 2ND = 62.10055.321 A NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort. 3RD = 62.10055.551 1st 2nd 3rd 633996-302 633996-501 633996-301 A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: CPU(1/7): DMI/PEG/FDI Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 4 of 103 5 4 3 2 1 CPU(2/7) IVY BRIDGE PROCESSOR (CLK,MISC,JTAG) 2 OF 9 CPU1B 1D05V_S0 TP501 1 TP_SKTOCC#_R AN34 PROC_SELECT# SKTOCC# 2 Q501 TPAD14-OP-GP C26 H_SNB_IVB# CLOCKS D 22 R501 62R2F-GP MISC 1 IVY-BRIDGE G 27 PROCHOT_EC TPAD14-OP-GP D TP502 42 1 H_CATERR# AL33 A28 A27 CPU_BCLK_P 1 CPU_BCLK_N 2 A16 A15 CLK_DP_P_R CLK_DP_N_R 4 RN501 3 SRN0J-6-GP CLKOUT_DMI_P CLKOUT_DMI_N 18 18 1D05V_S0 DPLL_REF_CLK DPLL_REF_CLK# 2 1 D 3 4 SRN1KJ-7-GP RN504 CATERR# 1 H_PROCHOT# BCLK BCLK# 22,27 AN33 H_PECI H_PROCHOT# 1 R508 H_PROCHOT#_D AL32 2 56R2F-1-GP AN32 22,36 H_THRMTRIP# 1 R518 PM_DRAM_PWRGD Traces impedance= 50 ohm 3D3V_S0 2 PECI PROCHOT# SM_DRAMRST# DDR3 MISC 2 2N7002K-2-GP 84.2N702.J31 2nd = 84.2N702.W31 THERMAL S R525 100KR2J-1-GP SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 PRDY# PREQ# 2 36,46,47 RUNPWROK 1 R531 2 0R2J-2-GP 3 DY 1 1 2 0R2J-2-GP 22 H_CPUPWRGD AM34 R520 H_CPUPWRGD_R 1 2 0R0402-PAD-1-GP AP33 PM_SYNC UNCOREPWRGOOD IN A GND OUT Y 2 1 R532 VCC C502 SC1U6D3V2KX-GP R519 H_PM_SYNC_R 1 2 0R0402-PAD-1-GP PM_DRAM_PWRGD_M 4 1 R512 PM_DRAM_PWRGD_R 2 130R2F-1-GP V8 SM_DRAMPWROK 74VHC1G09DFT2G-GP 73.01G09.AAH BUF_CPU_RST# S0_PWR_GOOD改改0D85V_EN(Follow Gable1.1) DY R531 and stuff R532 -1 1220 AR33 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 AP29 AP27 XDP_PRDY# XDP_PREQ# AR26 AR27 AP30 XDP_TCK XDP_TMS XDP_TRST# RESET# 1D05V_S0 TDI TDO AR28 AP26 XDP_TDI XDP_TDO 1 TP503 TPAD14-OP-GP 1 TP509 TPAD14-OP-GP R516 DBR# BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 AL35 H_DBR#_R 2 1 0R0402-PAD XDP_DBRESET# 19 AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 C 3D3V_S0 1 C 45,48 0D85V_EN IN B 5 2 C503 SCD1U10V2KX-5GP R524 200R2F-L-GP TCK TMS TRST# JTAG & BPM 19 H_PM_SYNC 1 1 19 PM_DRAM_PWRGD 2 2 U501 PWR MANAGEMENT 1 R523 200R2F-L-GP CPUDRAMRST# AK1 A5 A4 THERMTRIP# H_CPUPWRGD_R 10KR2J-3-GP 3D3V_S5 1D5V_S0 R8 R526 75R2J-1-GP 1D05V_S0 2 2 DY DY R522 2 CPUDRAMRST# 1 3RD = 73.17S07.0AG 1 2 Q502 DMN5L06K-7-GP S D XDP_DBRESET# R504 R503 2 DDR3_DRAMRST# 14,15 1KR2J-1-GP 1D05V_S0 PU/PD for JTAG signals 2 G 2ND = 84.00138.H31 3RD = 84.2N702.W31 R510 R514 1 84.05067.031 1 R515 4K99R2F-L-GP XDP_TDO R513 1KR2F-3-GP 2CPUDRAMRST#_R 0R2J-2-GP R527 1K5R2F-2-GP SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 140R2F-GP 43R2J-GP R529 1KR2J-1-GP 25D5R2F-GP 73.01G07.0HG 2ND = 73.01G07.CHH 1D5V_S3 200R2F-L-GP R521 750R2F-GP 74LVC1G07GW-GP Buffered reset to CPU S3 Power Reduction Circuit SM_DRAMRST# 2 R517 1 BUF_CPU_RST#_R 1 1 4 2 Y 1 GND DDR3 Compensation Signals R530 51R2J-2-GP DY 1 3 A 1 2 2 PLT_RST# 1 21,27,31,32,36,65,71,82,83,103 2 3D3V_S0 SCD1U10V2KX-5GP 1 2 NC#1 VCC DY C504 5 2 1 2 U502 1 DY 1 PCH_DDR_RST# 2 SCD047U25V2KX-GP C501 B 8,18 XDP_TMS R506 1 XDP_TDI R509 1 XDP_PREQ# R505 1 XDP_TCK XDP_TRST# 2 51R2J-2-GP 2 51R2J-2-GP DY B 2 51R2J-2-GP RN505 1 2 4 3 SRN51J-GP A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: 5 4 3 2 CPU(2/7): CLK/MISC/JTAG Document Number 1 Sheet Rev 1 Colossus Wednesday, January 04, 2012 5 of 103 5 4 3 2 1 CPU(3/7) IVY BRIDGE PROCESSOR (DDR3) D D 3 OF 9 4 OF 9 CPU1D IVY-BRIDGE 14 M_A_DQ[63:0] C B C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 AE10 AF10 V6 14 M_A_BS0 14 M_A_BS1 14 M_A_BS2 AE8 AD9 AF9 14 M_A_CAS# 14 M_A_RAS# 14 M_A_WE# SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_BS0 SA_BS1 SA_BS2 SA_CAS# SA_RAS# SA_WE# AB6 AA6 V9 SA_CK1 SA_CLK#1 SA_CKE1 AA5 AB5 V10 SA_CK2 SA_CLK#2 SA_CKE2 SA_CK3 SA_CLK#3 SA_CKE3 SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3 DDR SYSTEM MEMORY A M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 IVY-BRIDGE SA_CK0 SA_CLK#0 SA_CKE0 SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14 15 M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14 AB4 AA4 W9 AB3 AA3 W10 AK3 AL3 AG1 AH1 M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14 AH3 AG3 AG2 AH2 M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14 C4 G6 J3 M6 AL6 AM8 AR12 AM15 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_DQS#[7:0] 14 M_A_DQS[7:0] 14 M_A_A[15:0] 14 15 M_B_BS0 15 M_B_BS1 15 M_B_BS2 15 M_B_CAS# 15 M_B_RAS# 15 M_B_WE# C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 AA9 AA7 R6 AA10 AB8 AB9 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_BS0 SB_BS1 SB_BS2 SB_CAS# SB_RAS# SB_WE# SB_CK0 SB_CLK#0 SB_CKE0 AE2 AD2 R9 SB_CK1 SB_CLK#1 SB_CKE1 AE1 AD1 R10 SB_CK2 SB_CLK#2 SB_CKE2 SB_CK3 SB_CLK#3 SB_CKE3 SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3 DDR SYSTEM MEMORY B CPU1C SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15 M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15 AB2 AA2 T9 AA1 AB1 T10 C AD3 AE3 AD6 AE6 M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15 AE4 AD4 AD5 AE5 M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15 D7 F3 K6 N3 AN5 AP9 AK12 AP15 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 C7 G3 J6 M3 AN6 AP8 AK11 AP14 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_DQS#[7:0] 15 M_B_DQS[7:0] 15 B M_B_A[15:0] 15 A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom Date: 5 4 3 2 CPU(3/7): DDR3 Rev 1 Colossus Wednesday, January 04, 2012 Sheet 1 6 of 103 5 4 3 2 1 CPU(4/7) CPU1F POWER IVY BRIDGE PROCESSOR (POWER) 6 OF 9 8.5A IVY-BRIDGE PROCESSOR CORE POWER 1 2 1 1 2 1 2 1 1 2 2 2 2 1 1 1 2 1 1 2 2 2 1 1 2 1 2 1 2 1 2 PEG AND DDR 2 2 1 VIDALERT# AJ29 AJ30 AJ28 R705 1 43R2J-GP 2 2 130R2F-1-GP VR_SVID_ALERT# 42 H_CPU_SVIDCLK 42 H_CPU_SVIDDAT 42 B 1D05V_S0 1 VCC_CORE AJ35 AJ34 R702 2 1 R701 2 0R0402-PAD 1 0R0402-PAD VCCSENSE 42 VSSSENSE 42 1 VCC_SENSE VSS_SENSE 2 R706 100R2F-L1-GP-U VCC_SENSE_R VSS_SENSE_R B10 A10 VTT_SENSE 45 VSSP_SENSE 45 R704 100R2F-L1-GP-U 2 A <Core Design> 1 1 R707 R708 2 VCCIO_SENSE VSS_SENSE_VCCIO 2 2 SVID 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 VIDALERT# VIDSCLK VIDSOUT 1 R703 SENSE LINES 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 1 2 1 2 1 2 1 2 1 2 1 R709 75R2F-2-GP 10R2F-L-GP 2 DY 1D05V_S0 CORE SUPPLY 1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 C724 DY SC22U6D3V5MX-2GP 2 C720 C 1D05V_S0 Differential Sense feedback Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom 4 C705 DY SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP C737 C719 SC22U6D3V5MX-2GP C734 DY Date: 5 C733 SC22U6D3V5MX-2GP C718 SC22U6D3V5MX-2GP C717 SC22U6D3V5MX-2GP C716 SC22U6D3V5MX-2GP C715 C725 10R2F-L-GP C750DY SC10U6D3V5KX-1GP DY C747 SC22U6D3V5MX-2GP C749 SC22U6D3V5MX-2GP DY SC22U6D3V5MX-2GP C748 J23 C732 SC22U6D3V5MX-2GP A VCCIO40 C731 SC10U6D3V5KX-1GP C751 SC22U6D3V5MX-2GP C752 SC22U6D3V5MX-2GP C743 DY SC10U6D3V5KX-1GP DY C744 SC22U6D3V5MX-2GP C745 SC22U6D3V5MX-2GP DY SC22U6D3V5MX-2GP C746 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C730 SC22U6D3V5MX-2GP Power 78.22610.51L VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 C729 SC10U10V5KX-2GP SC22U6D3V5MX-2GP C711 SC22U6D3V5MX-2GP DY SC22U6D3V5MX-2GP C710 C708 SC22U6D3V5MX-2GP C707 C709 SC22U6D3V5MX-2GP C703 SC22U6D3V5MX-2GP DY SC22U6D3V5MX-2GP C712 SC22U6D3V5MX-2GP DY C706 SC22U6D3V5MX-2GP C704 SC22U6D3V5MX-2GP DY SC22U6D3V5MX-2GP C739 SC22U6D3V5MX-2GP C740 C741 SC22U6D3V5MX-2GP B C702 SC22U6D3V5MX-2GP C738 C701 SC10U10V5KX-2GP C742 SC22U6D3V5MX-2GP Place Top AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 SC10U10V5KX-2GP C VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 SC22U6D3V5MX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP C723 D VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SC22U6D3V5MX-2GP C714 C728 SC10U10V5KX-2GP AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 SC10U10V5KX-2GP C736 1D05V_S0 VCC_CORE SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP C726 SC22U6D3V5MX-2GP C721 SC22U6D3V5MX-2GP C735 C727 SC22U6D3V5MX-2GP Place Bottom C722 SC22U6D3V5MX-2GP C713 2 D PROCESSOR UNCORE POWER 53A 3 2 CPU(4/7): PWR Rev 1 Colossus Wednesday, January 04, 2012 Sheet 1 7 of 103 3 2 CPU(5/7) 1 M3 - Processor Generated SO-DIMM VREF_DQ IVY BRIDGE PROCESSOR (GRAPHICS POWER) 84.05067.031 1 POWER 2 DY 1 84.05067.031 R814 0R2J-2-GP DMN5L06K-7-GP DY Q803 G 5,18 PCH_DDR_RST# 1 S 12~16A 1D5V_S0 DY -1 1221 1 C808 10U*6 2 1 C807 2 1 33OU*1 2 2 1 C806 2 1 C805 2 1 2 1 2 C804 1 1 2 1 1 2 2 2 2 1 SENSE LINES TC801 ST330U2D5VDM-9GP 77.23371.13L 2nd = 79.33719.L01 C 6A VCCSA_SENSE VCCSA_VID0 VCCSA_VID1 1 C815 0D85V_S0 1 DY VCCUSA_SENSE H23 VCCUSA_SENSE 48 H_FC_C22 VCCSA_SEL C22 C24 R801 100R2J-2-GP 2 C814 2 1 C813 2 M27 M26 L26 J26 J25 J24 H26 H25 1 VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 2 VREF DDR3 -1.5V RAILS C803 DY C802 DDR_VREF_S3_B4 DDR_VREF_S3_D1 0D85V_S0 SA RAIL 1 2 1 2 M_VREF_DQ_DIMM0_R M_VREF_DQ_DIMM1_R H_FC_C22 VCCSA_SEL 48 48 B 3 4 1 2 DY AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 2 2 D DY SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP VCCIO_SEL A19 RN801 SRN1KJ-11-GP-U H_VCCP_SEL 2 1 1 2 1 1 2 1 2 1 1 2 2 2 2 VCCPLL1 VCCPLL2 VCCPLL3 DY SC10U6D3V5KX-1GP C818 B6 A6 A2 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 C801 R816 1KR2F-3-GP DY SC10U6D3V5KX-1GP C817 C832 SC22U6D3V5MX-2GP C816 SC10U6D3V5KX-1GP C819 DY C834 C833 SC22U6D3V5MX-2GP B C835 SC22U6D3V5MX-2GP 1D8V_S0 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP 1.5A C836 R815 1KR2F-3-GP Q802 DMN5L06K-7-GP R810 0R2J-2-GP G 3RD = 84.2N702.W31 2ND = 84.00138.H31 DDR_VREF_S3_B4 DDR_VREF_S3_D1 B4 D1 SC10U6D3V5KX-1GP 1 Power 78.22610.51L C837 SA_DIMM_VREFDQ SB_DIMM_VREFDQ 0R2J-2-GP R812 1 R813 1 0R2J-2-GP +V_SM_VREF_CNT AL1 B4:VREF_DQ CHA D1:VREF_DQ CHB MISC 1 2 1 2 1 2 1 2 1 1 2 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP 2 C831 SM_VREF 15 M_VREF_DQ_DIMM1 SC10U10V5KX-2GP C830 DY CAD Note: +V_SM_VREF should have 10 mil trace width SC10U6D3V5KX-1GP C829 PCH_DDR_RST# R809 0R2J-2-GP SC2D2U10V3ZY-1GP C828 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP DY SC22U6D3V5MX-2GP DY C827 VCC_AXG_SENSE 42 VSS_AXG_SENSE 42 SC10U6D3V5KX-1GP C826 AK35 AK34 SC10U6D3V5KX-1GP SC4D7U6D3V3KX-GP C VAXG_SENSE VSSAXG_SENSE SC4D7U6D3V3KX-GP Closed to CPU Socket IVY-BRIDGE SCD1U16V2ZY-2GP 22U*6 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 GRAPHICS 1 2 1 2 1 2 1 2 1 C825 SC22U6D3V5MX-2GP 2 1 C824 SC22U6D3V5MX-2GP VCC_GFXCORE C823 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP 2 C822 AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 2ND = 84.00138.H31 3RD = 84.2N702.W31 DY 14 M_VREF_DQ_DIMM0 Under Socket and Closed to CPU C821 7 OF 9 CPU1G D C820 R808 0R2J-2-GP D 470U*2 22U*6 1.8V RAIL VCC_GFXCORE 2 33A DDR_VREF_S3 S 4 D 5 SNB: No Connect IVB: VSS 2 H_SNB_IVB#_PWRCTRL 1 TP801 TPAD14-OP-GP DY Voltage 2 H_VCCP_SEL R817 0R2J-2-GP 1 1 1.05V 0 1.0V R818 0R2J-2-GP 1 DY S3 Power Reduction Circuit Processor VREF_DQ Implementation DDR_VREF_S3 R807 1 A 1 2 R811DY 2 0R2J-2-GP A 0R2J-2-GP <Core Design> Q801 DMN5L06K-7-GP R805 +V_SM_VREF D 2ND = 84.00138.H31 3RD = 84.2N702.W31 1 5,18 PCH_DDR_RST# Wistron Corporation +V_SM_VREF_CNT S 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 84.05067.031 1 2 0R2J-2-GP Title R803 100KR2J-1-GP R802DY 2 0R2J-2-GP Size Document Number Custom 2 DY G 1 14 M_VREF_DQ_DIMM0 19,27,36,46,47,92 PM_SLP_S3# 5 Date: 4 3 2 CPU(5/7): GFX/PWR Wednesday, January 04, 2012 Sheet 1 Rev 1 Colossus 8 of 103 5 4 3 2 1 CPU(6/7) IVY BRIDGE PROCESSOR (GND) 8 OF 9 CPU1H 9 OF 9 CPU1I D D AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 IVY-BRIDGE VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 A IVY-BRIDGE VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 C B A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU (6/7):GND Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 9 of 103 5 4 3 2 1 CPU(7/7) IVY BRIDGE PROCESSOR (RESERVED) D CFG4 Display Port Presence Strap 1 D R1006 1KR2J-1-GP CFG4 0:Enable eDP 1:(Default) Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port 2 DY 5 OF 9 CPU1E IVY-BRIDGE CFG7 VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE AJ26 RSVD#AJ26 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29 J20 B18 RSVD#J20 RSVD#B18 J15 RSVD#J15 1 2 AJ31 AH31 AJ33 AH33 RSVD#T8 RSVD#J16 RSVD#H16 RSVD#G16 RSVD_NCTF#AR35 RSVD_NCTF#AT34 RSVD_NCTF#AT33 RSVD_NCTF#AP35 RSVD_NCTF#AR34 AT26 AM33 AJ27 CFG7 C 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training T8 J16 H16 G16 AR35 AT34 AT33 AP35 AR34 CFG2 PEG Static Lane Reversal DY R1005 1KR2J-1-GP 1:(Default) Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed CFG2 RSVD_NCTF#B34 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#B35 RSVD_NCTF#C35 B34 A33 A34 B35 C35 B CFG6 CFG5 DY RSVD#AJ32 RSVD#AK32 AJ32 AK32 BCLK_ITP BCLK_ITP# AN35 AM35 1 R1001 R1002 R1003 R1004 W8 1 DY DY 2 2 2 2 RSVD#W8 2 DY DY L7 AG7 AE7 AK2 R1009 1KR2J-1-GP R1007 1KR2J-1-GP R1008 1KR2J-1-GP 2 B 1 1 1 1 TP1004 TPAD14-OP-GP PEG DEFER TRAINING RESERVED 49D9R2F-GP 49D9R2F-GP 49D9R2F-GP 49D9R2F-GP 1 DY RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2 RSVD#AT26 RSVD#AM33 RSVD#AJ27 VCC_GFXCORE VCC_CORE VCC_DIE_SENSE 1 C AH27 AH26 2 CFG4 CFG5 CFG6 CFG7 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG CFG2 VCC_DIE_SENSE VSS_DIE_SENSE AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 PCIE Port Bifurcation Straps RSVD_NCTF#AT2 RSVD_NCTF#AT1 RSVD_NCTF#AR1 CFG[6:5] AT2 AT1 AR1 11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU(7/7): CFG/RSVD/DDR3_VRE Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus Tuesday, December 27, 2011 Sheet 1 10 of 103 5 4 3 2 1 D D (Blanking) C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number CPU_XDP Rev 1 Colossus Monday, December 26, 2011 Sheet 1 11 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 12 of 103 5 4 3 2 1 D D C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number AOAC Rev 1 Colossus Monday, December 26, 2011 Sheet 1 13 of 103 4 3 2 DIMM1 REVERSED M_A_DQS#[7:0] M_A_DQS[7:0] DIM1 1 2 1 2 1 2 116 120 6 M_A_DIM0_ODT0 6 M_A_DIM0_ODT1 M_VREF_CA_DIMM0 8 M_VREF_DQ_DIMM0 126 1 30 5,15 DDR3_DRAMRST# 0D75V_S0 DY DY 1st 2nd 3rd 661448-307 661448-306 661448-304 203 204 EVENT# 198 VDDSPD 199 SA0 SA1 197 201 NC#77 NC#122 NC#125/TEST 77 122 125 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQS0# VSS DQS1# VSS DQS2# VSS DQS3# VSS DQS4# VSS DQS5# VSS DQS6# VSS DQS7# VSS VSS DQS0 VSS DQS1 VSS DQS2 VSS DQS3 VSS DQS4 VSS DQS5 VSS DQS6 VSS DQS7 VSS VSS ODT0 VSS ODT1 VSS VSS VREF_CA VSS VREF_DQ VSS VSS RESET# VSS VSS VSS VTT1 661448-307VSS VTT2 VSS 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 4 3 200 202 SODIMM1_1_SMB_DATA_R SODIMM1_1_SMB_CLK_R R1409 1 R1401 1 2 0R0402-PAD-1-GP 2 0R0402-PAD-1-GP PCH_SMBDATA 15,18,103 PCH_SMBCLK 15,18,103 TS#_DIMM0_1 15 3D3V_S0 1D5V_S3 C1402 3D3V_S0 1 C1401 R1402 10KR2J-3-GP Thermal EVENT C 2 SA0_DIM0 SA1_DIM0 DY TS#_DIMM0_1 SODIMM A DECOUPLING 1D5V_S3 DY 4 1 C1419 SC1U10V2KX-1GP B DY A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 62.10017.U01 DDR3 SO-DIMM1 Size Document Number Custom 2nd = 62.10017.U01 3rd = 62.10024.H81 Date: 5 2 2 2 C1418 2 C1417 2 C1416 2 C1415 DY 1 2 DY C1414 DY C1412 1 C1411 1 1 DY 2 2 1 2 C1410 1 1 1 C1409 DY 1 1 C1408 C1413 DY Layout Note: Place these Caps near SO-DIMMA. 2 1 C1407 DDR3-204P-86-GP-U 010412 Update connetor HP P/N, H=9.2mm hanle control but not change library D If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32 1 2 SDA SCL 2 1 2 2 1 2 1 2 1 2 1 2 1 1 2 SC1U6D3V2KX-GP 2 C1423 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 11 28 46 63 136 153 170 187 RN1401 SRN10KJ-5-GP SC10U6D3V5KX-1GP 12 29 47 64 137 154 171 188 M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6 SC1U10V2KX-1GP C1422 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP A C1421 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 102 104 SC10U6D3V5KX-1GP 0D75V_S0 C1420 10 27 45 62 135 152 169 186 CK1 CK1# SA1_DIM0 SC1U10V2KX-1GP Place these caps close to VTT1 and VTT2. M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6 SCD1U10V2KX-5GP DY 101 103 SCD1U10V2KX-5GP C1406 SC2D2U10V3ZY-1GP CK0 CK0# Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30 SA0_DIM0 SCD1U10V2KX-5GP M_VREF_DQ_DIMM0 M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6 SCD1U10V2KX-5GP R1406 1KR2F-3-GP M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6 73 74 SC10U6D3V5KX-1GP 1D5V_S3 114 121 SC10U6D3V5KX-1GP DY CS0# CS1# CKE0 CKE1 SC10U10V5KX-2GP C1404 SC2D2U6D3V3KX-GP M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6 SC10U6D3V5KX-1GP 1 M_VREF_CA_DIMM0 C1405 SCD1U10V2KX-4GP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 110 113 115 1 1 2 R1403 1KR2F-3-GP R1407 1KR2F-3-GP 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 RAS# WE# CAS# SC2D2U6D3V3KX-GP 1D5V_S3 B M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_A[15:0] 6 NP1 NP2 SCD1U16V2ZY-2GP C C1403 SCD1U10V2KX-4GP BA0 BA1 6 2 6 M_A_BS0 6 M_A_BS1 6 M_A_DQ[63:0] R1405 1KR2F-3-GP 109 108 M_A_BS2 1 6 NP1 NP2 1 6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 1 D 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 2 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 2 5 3 2 Rev 1 Colossus Wednesday, January 04, 2012 Sheet 1 14 of 103 4 3 DIM2 2 2 8 M_VREF_DQ_DIMM1 0D75V_S0 126 1 30 5,14 DDR3_DRAMRST# 203 204 SC2D2U10V3ZY-1GP C SODIMM B DECOUPLING 1D5V_S3 DY 2 DY 1 C1513 1 2 DY C1522 B 2 1 2 1 2 C1521 C1520 DY DY A <Core Design> Wistron Corporation 1 DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DDR3-204P-85-GP-U 1st 2nd 3rd 661447-301 661447-306 661447-304 010412 Update connetor HP P/N, hanle control but not change library 62.10017.U21 Title 2ND = 62.10017.T91 3rd = 62.10024.I61 DDR3 SO-DIMM2 Size Document Number Custom H=5.2mm Date: 5 1 1 C1519 DY 1 C1518 C1512 DY 2 C1517 C1511 2 1 C1516 C1510 1 Layout Note: Place these Caps near SO-DIMMB. C1509 2 77.23371.13L 2nd = 79.33719.L01 C1508 2 TC1501 1 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 C1503 2 1 2 DY SC1U6D3V2KX-GP 2 C1502 SC1U6D3V2KX-GP 1 C1501 SC1U6D3V2KX-GP SC1U6D3V2KX-GP 1 C1523 2 A Place these caps close to VTT1 and VTT2. 1D5V_S3 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 DY C1505 1 1 1 2 1 1 2 M_VREF_CA_DIMM1 77 122 125 C1504 2 2 2 1 2 1 116 120 6 M_B_DIM0_ODT0 6 M_B_DIM0_ODT1 SB0_DIM0 SB1_DIM0 SC1U10V2KX-1GP 12 29 47 64 137 154 171 188 197 201 SC10U6D3V5KX-1GP M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 3D3V_S0 199 SC1U10V2KX-1GP DY 10 27 45 62 135 152 169 186 PCH_SMBDATA 14,18,103 PCH_SMBCLK 14,18,103 SC1U10V2KX-1GP C1515 SC2D2U10V3ZY-1GP 2 0R0402-PAD-1-GP 2 0R0402-PAD-1-GP TS#_DIMM0_1 14 SCD1U10V2KX-5GP C1514 SCD1U10V2KX-4GP R1504 1 R1505 1 SODIMM0_1_SMB_DATA_R SODIMM0_1_SMB_CLK_R 198 SCD1U10V2KX-5GP R1509 1KR2F-3-GP M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 200 202 SCD1U10V2KX-5GP M_VREF_DQ_DIMM1 11 28 46 63 136 153 170 187 SCD1U10V2KX-5GP R1508 1KR2F-3-GP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQS0# VSS DQS1# VSS DQS2# VSS DQS3# VSS DQS4# VSS DQS5# VSS DQS6# VSS DQS7# VSS VSS DQS0 VSS DQS1 VSS DQS2 VSS DQS3 VSS DQS4 VSS DQS5 VSS DQS6 VSS DQS7 VSS VSS ODT0 VSS ODT1 VSS VSS VREF_CA VSS VREF_DQ VSS VSS RESET# VSS VSS VSS VTT1 VSS 661447-301 VTT2 VSS Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34 M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6 SC10U6D3V5KX-1GP 1D5V_S3 B VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 D SC10U6D3V5KX-1GP DY NC#1 NC#2 NC#/TEST 4 3 SRN10KJ-5-GP SC10U10V5KX-2GP C1507 SC2D2U6D3V3KX-GP SA0 SA1 1 2 SC10U6D3V5KX-1GP C1506 SCD1U10V2KX-4GP EVENT# VDDSPD 102 104 RN1501 SB1_DIM0 SB0_DIM0 SC10U6D3V5KX-1GP R1507 1KR2F-3-GP SDA SCL M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6 ST330U2D5VDM-9GP 1 M_VREF_CA_DIMM1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6 101 103 2 2 R1506 1KR2F-3-GP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6 73 74 1 1 1D5V_S3 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 CK1 CK1# BA0 BA1 114 121 SCD1U16V2ZY-2GP C M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 CK0 CK0# M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6 2 109 108 CKE0 CKE1 3D3V_S0 110 113 115 1 M_B_BS2 6 M_B_BS0 6 M_B_BS1 6 M_B_DQ[63:0] CS0# CS1# DIMM2 REVERSED 2 6 RAS# WE# CAS# NP1 NP2 1 D NP1 NP2 2 6 M_B_DQS[7:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 1 1 6 M_B_DQS#[7:0] 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 2 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_A[15:0] 2 6 2 1 5 4 3 2 Rev 1 Colossus Wednesday, January 04, 2012 Sheet 1 15 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 16 of 103 A B RTCRST# G22 SRTCRST# 2 1MR2J-1-GP INTRUDER# K22 INTRUDER# R1710 1 2 330KR2J-L1-GP RN1701 8 7 6 5 PCH_INTVRMEN C17 INTVRMEN HDA_BIT_CLK N34 HDA_BCLK HDA_SYNC L34 HDA_SYNC 1 2 3 4 29 HDA_RST#_CODEC 29 HDA_SYNC_CODEC 29 HDA_BITCLK_CODEC 29 HDA_SPKR 2 2 SRN33J-7-GP 1 2 0R0402-PAD-1-GP EC1702 SC2200P50V2KX-2GP SC2200P50V2KX-2GP EC1701 DY_RF R1711 DY_RF -1 1220 PCH_HDA_SPKR T10 SPKR PCH_HDA_RST# K34 HDA_RST# 29 HDA_SDIN0_CODEC HDA_SDO RN1704 1 2 4 3 HDD_HALTLED_R SRN1KJ-11-GP-U Q1701 FWH4/LFRAME# D36 LPC_FRAME#_R 2 R1726 LDRQ0# LDRQ1#/GPIO23 E36 K36 SERIRQ HDA_SYNC_C E34 HDA_SDIN0 G34 HDA_SDIN1 C34 HDA_SDIN2 A34 HDA_SDIN3 A36 HDA_SDO C36 HDA_DOCK_EN#/GPIO33 N32 HDA_DOCK_RST#/GPIO13 3 27 ME_UNLOCK 82 HDD_HALTLED LPC_AD0_L LPC_AD1_L LPC_AD2_L LPC_AD3_L ISO_PREP# SATA 29 HDA_SDOUT_CODEC R1709 1 C38 A38 B37 C37 LPC D20 FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 SATA 6G RTC_RST# SRTC_RST# RTC 1 RTC_AUX_S5 1 2ND = 82.30001.B21 RTCX2 GAP-OPEN 7pF20PPM X-32D768KHZ-34GPU RTCX1 C20 RTC_RST# 1 1 S R1736 2K2R2J-2-GP SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA_RXN2 56 SATA_RXP2 56 SATA_TXN2 56 SATA_TXP2 56 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AB8 AB10 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP Y7 Y5 AD3 AD1 Y3 Y1 AB3 AB1 Y11 JTAG_TMS SATAICOMPO K5 JTAG_TDI PCH_JTAG_TDO H1 JTAG_TDO SATAICOMPI SATA3RCOMPO TPAD14-OP-GP TP1702 1 SPI_CS1# SPI_CLK SPI_CS0# T1 SPI_CS1# 2 60 PCH_SPI_MOSI 60 PCH_SPI_MISO V4 SPI_MOSI U3 SPI_MISO HDD1 mSATA HDD2 3 SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56 ODD 1D05V_S0 Y10 SATA_COMP R1713 1 2 37D4R2F-GP 1D05V_S0 AB12 SATA3COMPI AB13 SATA3_COMP R1714 SATA3RBIAS AH1 RBIAS_SATA3 2 49D9R2F-GP 1 5V_S0 1 R1715 2 750R2F-GP DY R1716 10KR2J-3-GP NEED TO PLACE CLOSE TO PCH SPI T3 Y14 SATALED# SATA_LED# P3 SATA0GP/GPIO21 V14 SATA1GP/GPIO19 P1 4 27 AD7 AD5 AH5 AH4 PCH_JTAG_TDI 60 PCH_SPI_CS#0 INT_SERIRQ SATA1RXN SATA1RXP SATA1TXN SATA1TXP JTAG_TCK 27,71 27,71 27,71 27,71 TP1701 TPAD14-OP-GP 1 V5 SATA_RXN1 103 SATA_RXP1 103 SATA_TXN1 103 SATA_TXP1 103 H7 LPC_AD3 LPC_AD2 LPC_AD0 LPC_AD1 LPC_FRAME# 27,71 AM10 AM8 AP11 AP10 PCH_JTAG_TMS 60 PCH_SPI_CLK 1 33R2J-2-GP SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56 SATA5RXN SATA5RXP SATA5TXN SATA5TXP 2 2 R1737 100KR2J-1-GP 2N7002K-2-GP RN1705 SRN47J-8-GP 8 7 6 5 AM3 AM1 AP7 AP5 J3 JTAG D PCH_GPIO23 1 2 3 4 SATA0RXN SATA0RXP SATA0TXN SATA0TXP PCH_JTAG_TCK_BUF G 27 RTCRST_ON LPC_AD3_L LPC_AD2_L LPC_AD0_L LPC_AD1_L 1 1 2 2 1 G1701 1 82.30001.661 A20 RTC_X2 IHDA 1 2 2 C1704 SC1U10V2KX-1GP C1703 3 SC6D8P50V2CN-GP SC6D8P50V2CN-GP C1702 2 1 OF 10 RTC_X1 2 20KR2J-L2-GP 4 1 1 2 PCH_INTVRMEN 330KR2J-L1-GP 1 DY R1707 27,71 LPC_AD[0..3] INTVRMEN- Integrated SUS 1.05V VRM Enable High - Enable internal VRs PCH1A 2 X1701 4 2 RTC_X2 RTC_AUX_S5 R1708 1 E PCH(1/9) R1705 1 20KR2J-L2-GP C1701 SC1U10V2KX-1GP R1706 1 2 10MR2J-L-GP D 2 RTC_AUX_S5 RTC_X1 C PCH_GPIO19 SATA_LED# 82 2 10KR2J-3-GP 2 SATA0GP_GPIO21 22 3D3V_S0 1 R1731 PANTHER-GP-NF 3D3V_S5 R1724 1 2 1KR2J-1-GP R1729 1 2 10KR2J-3-GP ISO_PREP# HDA_SYNC RTC Battery 3D3V_AUX_S5 RTC_AUX_S5 U1701 3D3V_S5 2 +RTC_VCC RTC1 3 5V_S0 NO REBOOT STRAP R1730 10KR2J-3-GP 2 3D3V_S0 G HDA_SPKR 2 10KR2J-3-GP HDA_SYNC_C 1 R1723 INT_SERIRQ 2 10KR2J-3-GP DY_PCHXDP 1 Low = Default HDA_SPKR High = No Reboot 1 DY R1722 3 1 S PCHXDP HDA_SDO_G 84.05067.031 2ND = 84.00138.H31 3RD = 84.2N702.W 31 HDA_SYNC D DMN5L06K-7-GP U1703 1 2 3 4 +RTC_VCC 1 R1720 2 4 PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO 8 7 6 5 B RTC PW R 1 1KR2J-1-GP CH715FPT-GP 83.R0304.B81 20.F1637.002 SRN100F-GP R1721 1 2 51R2J-2-GP R1727 1 DY 2 1KR2J-1-GP R1728 1 DY 2 20KR2J-L2-GP C1705 SC1U10V3ZY-6GP ACES-CON2-18-GP 2ND = 83.R2004.C81 <Core Design> PCH_JTAG_TCK_BUF HDD_HALTLED_R HDA_SDO 1 2ND = 20.F1864.002 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. LAYOUT NOTE: JTAG_TMS TERMINATIONS JTAG_TDI TERMINATIONS JTAG_TDO TERMINATIONS JTAG_TCK TERMINATIONS NEED NEED NEED NEED TO TO TO TO BE BE BE BE PLACED PLACED PLACED PLACED NEAR NEAR NEAR NEAR Title PCH PCH XDP PCH Size A3 Date: A 2 1 PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI RN1703 No Reboot Strap R1722 1 2 210R2F-L-GP 2 210R2F-L-GP 2 210R2F-L-GP 2 PCHXDP PCHXDP PCHXDP R1717 1 R1718 1 R1719 1 C D PCH(1/9): HDA/JTAG/SATA Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet E 17 of 103 C 2 OF 10 WLAN 31 31 31 31 LAN PCIE_RXN4_W LAN PCIE_RXP4_W LAN PCIE_TXN4_W LAN PCIE_TXP4_W LAN C1809 1 C1807 1 PCIE_RXN6_LAN PCIE_RXP6_LAN PCIE_TXN6_LAN PCIE_TXP6_LAN C1810 1 C1811 1 2 SCD1U10V2KX-5GP PCIE_TXN4_C 2 SCD1U10V2KX-5GP PCIE_TXP4_C 2 SCD1U10V2KX-5GP PCIE_TXN6_C 2 SCD1U10V2KX-5GP PCIE_TXP6_C PERN3 PERP3 PETN3 PETP3 BF36 BE36 AY34 BB34 PERN4 PERP4 PETN4 PETP4 BG37 BH37 AY36 BB36 PERN5 PERP5 PETN5 PETP5 BJ38 BG38 AU36 AV36 PERN6 PERP6 PETN6 PETP6 BG40 BJ40 AY40 BB40 PERN7 PERP7 PETN7 PETP7 BE38 BC38 AW38 AY38 PERN8 PERP8 PETN8 PETP8 R1808 1KR2J-1-GP 3 1 Q1801 SML0ALERT#/GPIO60 SML0CLK SML0DATA 2N7002K-2-GP R1809 1 2 0R2J-2-GP PCIECLKRQ0#/GPIO73 AB49 AB47 GPIO18 CLKOUT_PCIE1N CLKOUT_PCIE1P M1 PCIECLKRQ2#/GPIO20 32 CLK_PCIE_MEDIA# 32 CLK_PCIE_MEDIA Y37 Y36 CLKOUT_PCIE3N CLKOUT_PCIE3P 32 CLKREQ_MEDIA# A8 65 CLK_PCIE_W LAN# 65 CLK_PCIE_W LAN Y43 Y45 G12 PCH_SML0_DATA 1 TP1805 TPAD14-OP-GP E14 PCH_SML1CLK M16 PCH_SML1DATA 1 6 2 5 3 4 PCH_SMB_DATA PCH_SMBCLK 14,15,103 DMN66D0LDW -7-GP 84.DMN66.03F C1801 XTAL25_IN 1 2 SC15P50V2JN-2-GP CL_CLK1 M7 R1805 1MR2J-1-GP CL_DATA1 T11 CL_RST1# P10 X1801 XTAL-25MHZ-155-GP 3D3V_AUX_S5 12pF30PPM 3D3V_S5 RN1802 SRN2K2J-4-GP C1802 XTAL25_OUT 1 82.30020.D41 2ND = 82.30020.G71 -1 1220 2 SC15P50V2JN-2-GP 3RD = 82.30020.G61 R1804 M10 CLKREQ_PEG_A#_C CLKOUT_PEG_A_N CLKOUT_PEG_A_P AB37 AB38 CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P AV22 AU22 CLKOUT_DP_N CLKOUT_DP_P AM12 AM13 CLKIN_DMI_N CLKIN_DMI_P BF18 BE18 CLK_BUF_EXP_N CLK_BUF_EXP_P 1 2 CLKIN_GND1_N CLKIN_GND1_P BJ30 BG30 CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P 1 2 1 2 0R0402-PAD-1-GP CLKREQ_PEG_A# 83 4 RN1810 3 SRN0J-6-GP 1 2 PCH_SML1CLK PCH_SML1DATA 3 3D3V_S5 CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83 U1802 PCH_SML1DATA CLKOUT_PCIE2N CLKOUT_PCIE2P V10 82 CLKREQ_MEDIA#17 TPAD14-OP-GP 14,15,103 PCH_SMBDATA SML1CLK/GPIO58 PCIECLKRQ1#/GPIO18 AA48 AA47 82 CLK_PCIE_MEDIA17# 82 CLK_PCIE_MEDIA17 TP1803 SML1DATA/GPIO75 DY 17"Card Read 1 PCH_GPIO74 CLKOUT_PCIE0N CLKOUT_PCIE0P J2 4 U1801 PCH_SML0_CLK C13 CLOCKS GPIO73 S 65 CLKRQ_W LAN#_C 2 1KR2J-1-GP 5,8 C8 SML1ALERT#/PCHHOT#/GPIO74 PEG_A_CLKRQ#/GPIO47 Y40 Y39 CLKRQ_W LAN# PCH_DDR_RST# PCH_SMB_CLK G D A12 3D3V_S0 3D3V_S5 PCH_SMB_DATA 69 R1807 1 2 3D3V_S0_W LAN PCH_SMB_DATA 4 3 2 1 65 65 65 65 15UP_17DY 15UP_17DY BG36 BJ36 AV34 AU34 C9 SMBDATA RN1803 SRN2K2J-1-GP PCH_SMB_CLK 69 5 6 7 8 32 PCIE_TXN3_MEDIA 32 PCIE_TXP3_MEDIA 2 SCD1U10V2KX-5GP PCIE_TXN3_C 2 SCD1U10V2KX-5GP PCIE_TXP3_C PCH_SMB_CLK 4 C1805 1 C1806 1 SMBCLK H14 1 10KR2J-3-GP EC_SW I# 27 1 32 PCIE_RXN3_MEDIA 15"Card Read 32 PCIE_RXP3_MEDIA E12 1 4 SMBALERT#/GPIO11 2 2 SCD1U10V2KX-5GP PCIE_TXN2_C 2 SCD1U10V2KX-5GP PCIE_TXP2_C PERN2 PERP2 PETN2 PETP2 Link C1808 1 C1812 1 17"Card Read BE34 BF34 BB32 AY32 SMBUS PCIE_RXN2_MEDIA17 PCIE_RXP2_MEDIA17 PCIE_TXN2_MEDIA17 PCIE_TXP2_MEDIA17 Controller 82 82 82 82 R1806 PCI-E* 15DY_17UP 15DY_17UP PERN1 PERP1 PETN1 PETP1 4 3 PCH(2/9) 2 BG34 BJ34 AV32 AU32 E 3D3V_S0 3 PCH1B D 3D3V_S5 1 2 B 2 A CLKOUT_DMI_N 5 CLKOUT_DMI_P 5 27,29,79,86 SML1_CLK 1 6 2 5 3 4 SML1_DATA 27,29,79,86 PCH_SML1CLK DMN66D0LDW -7-GP RN1806 CLOCK TERMINATION FOR FCIM 84.DMN66.03F 4 3 SRN10KJ-5-GP RN1807 WLAN 2 CLKRQ_W LAN# GPIO44 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4#/GPIO26 V45 V46 CLKOUT_PCIE5N CLKOUT_PCIE5P L14 G24 E24 CLK_BUF_DOT96_N CLK_BUF_DOT96_P 1 2 4 3 SRN10KJ-5-GP CLKIN_SATA_N CLKIN_SATA_P AK7 AK5 CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P REFCLK14IN K45 CLK_BUF_REF14 1 2 R1802 1 2 10KR2J-3-GP PCH_SMB_CLK PCH_SMB_DATA All resistors need very close to PCH 31 CLK_PCIE_LAN# 31 CLK_PCIE_LAN CLKIN_PCILOOPBACK H45 XTAL25_IN XTAL25_OUT V47 V49 XCLK_RCOMP Y47 XCLK_RCOMP CLKOUTFLEX0/GPIO64 K43 CLK_48_USB30 CLKOUTFLEX1/GPIO65 F47 CLK_27_NSSC CLKOUTFLEX2/GPIO66 H47 CLKOUTFLEX3/GPIO67 K49 1D05V_S0 PEG_B_CLKRQ#/GPIO56 V40 V42 CLKOUT_PCIE6N CLKOUT_PCIE6P T13 PCIECLKRQ6#/GPIO45 21 XTAL25_IN XTAL25_OUT 1 R1803 CLK_14M_KBC_P 2 90D9R2F-1-GP 1 LAN CLKOUT_PEG_B_N CLKOUT_PEG_B_P E6 2 4 3 SRN10KJ-5-GP CLK_PCI_FB GPIO56 RN1801 SRN2K2J-1-GP RN1809 PCIECLKRQ5#/GPIO44 AB42 AB40 3D3V_S5 4 3 PCIECLKRQ3#/GPIO25 L12 4 3 SRN10KJ-5-GP RN1808 1 2 15"Card Read CLKRQ_W W AN# CLKOUT_PCIE7N CLKOUT_PCIE7P K12 PCIECLKRQ7#/GPIO46 AK14 AK13 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P 1 DY C1803 1 TP1801 TPAD14-OP-GP 1 TP1802 TPAD14-OP-GP TP1804 TPAD14-OP-GP 2 V38 V37 FLEX CLOCKS 31 CLKREQ_LAN# SC68P50V2JN-1GP CLK_27M_VGA 86 CLK_14M_KBC_P 1 1 <Core Design> PANTHER-GP-NF RN1804 CLKREQ_LAN# PCH_GPIO74 CLKRQ_W W AN# GPIO44 3D3V_S5 1 2 3 4 5 10 9 8 7 6 SRN10KJ-L3-GP 3D3V_S5 Wistron Corporation 3D3V_S0 CLKRQ_W LAN# GPIO56 CLKREQ_MEDIA# GPIO73 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RN1805 1 2 4 3 GPIO18 CLKREQ_MEDIA#17 Size A3 SRN10KJ-5-GP Date: A B C D PCH(2/9): PCIE/SMBUS/CLK Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet E 18 of 103 A B C D E DSWODVREN - On Die DSW VR Enable PCH(3/9) PCH1C 4 DMI_RXN[3:0] 4 4 DMI_RXP[3:0] 4 DMI_TXN[3:0] 1 R1903 BC24 BE20 BG18 BG20 DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 BE24 BC20 BJ18 BJ20 DMI0RXP DMI1RXP DMI2RXP DMI3RXP FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_TX_N0 FDI_TX_N1 FDI_TX_N2 FDI_TX_N3 FDI_TX_N4 FDI_TX_N5 FDI_TX_N6 FDI_TX_N7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_TX_P0 FDI_TX_P1 FDI_TX_P2 FDI_TX_P3 FDI_TX_P4 FDI_TX_P5 FDI_TX_P6 FDI_TX_P7 FDI_INT FDI_TX_N[7:0] 4 R1917 1 AY24 AY20 AY18 AU18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP AW16 FDI_INT DMI_COMP_R BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 4 BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 4 FDI_LSYNC1 BB10 FDI_LSYNC1 4 DSWVRMEN A18 DSW ODVREN DPWROK E22 PCH_DPW ROK FDI Disabled FDI_TX_P[7:0] 4 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI LOW (R1917 UNSTUFFED, R1901 STUFFED 4 DMI0TXN DMI1TXN DMI2TXN DMI3TXN RBIAS_CPY 2 750R2F-GP Enabled (DEFAULT) RTC_AUX_S5 AW24 AW20 BB18 AV18 1D05V_S0 2 49D9R2F-GP DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 4 DMI_TXP[3:0] R1902 1 3 OF 10 HIGH (R1917 STUFFED, R1901 UNSTUFFED DSW ODVREN 2 330KR2J-L1-GP R1901 1 2 330KR2J-L1-GP DY 4 4 3D3V_S0 3 SUSACK#_R 1 C12 5 XDP_DBRESET# 36 SYS_PW ROK 27,36 S0_PW R_GOOD SUSACK# R1906 1 2 0R0402-PAD-1-GP PM_SYSRST#_R K3 SYS_RESET# R1907 1 2 0R0402-PAD-1-GP SYS_PW ROK_R P12 SYS_PWROK 1 1 2 0R0402-PAD-1-GP PM_PCH_PW ROK 2 0R0402-PAD-1-GP R1908 R1909 L22 APW ROK L10 B13 5 PM_DRAM_PW RGD 41 RSMRST# 2 R1920 PWROK APWROK DRAMPWROK WAKE# B9 CLKRUN#/GPIO32 N3 1 R1904 R1905 1 DY 1 27 PM_PW RBTN# 27,86 AC_PRESENT PCH_GPIO72 PM_RI# RSMRST# TP1901 TPAD14-OP-GP 3D3V_S5 RN1901 SUSCLK/GPIO62 SLP_S5#/GPIO63 D10 PCH_SUSCLK_KBC PCH_GPIO63 1 TP1904 AC_PRESENT 27 1 2 3 4 PM_RI# PCIE_W AKE# TPAD14-OP-GP SRN10KJ-6-GP K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S4# H4 SLP_S4#_R R1911 1 SLP_S3# F4 SLP_S3#_R R1912 1 R1910 1 PWRBTN# SLP_A# G10 PM_SLP_A#_R SLP_SUS# 0R0402-PAD-1-GP 2 DY R1913 1 PM_SLP_S4# 27,46 0R0402-PAD-1-GP 2 2 0R2J-2-GP PM_SLP_S3# 8,27,36,46,47,92 0R0402-PAD-1-GP PM_SLP_A# 1 2 TP1905 3D3V_S0 TPAD14-OP-GP PM_CLKRUN# H20 ACPRESENT/GPIO31 SLP_SUS# G16 E10 BATLOW#/GPIO72 PMSYNCH AP14 A10 RI# K14 SLP_LAN#/GPIO29 1 TP1908 1 R1915 H_PM_SYNC 5 SLP_LAN# 3D3V_S5 SRN10KJ-5-GP R1914 RSMRST# Intel ME-EC Interaction Signal List with and without M3 support Signal Name 1 2 SUS_PW R_ACK PCH_GPIO72 RSMRST#_KBC 27 2 1 1KR2F-3-GP 3 4 RN1902 Platform Without M3 Support 3D3V_S5 SLP_LAN# SUSPWRDNACK(GPIO30) Required Required ACPRESENT(GPIO31) Required Required 2 2 8K2R2J-3-GP TPAD14-OP-GP PANTHER-GP-NF Platform With M3 Support (e.g., Intel AMT) 8 7 6 5 -1 1220 100KR2J-1-GP 2 20R0402-PAD-1-GP 2 10KR2J-3-GP PM_CLKRUN# 27 PCH_GPIO61 N14 RSMRST# E20 3 -1 1220 PCIE_W AKE# 27,31 G8 SUS_STAT#/GPIO61 C21 1 27 SUS_PW R_ACK System Power Management TPAD14-OP-GP TP1903 1 R1919 2 10KR2J-3-GP <Core Design> 1 SLP_A# (Tie to SLP_S3#) Note: If SLP_S3# is not routed from PCH to EC, then SLP_A# becomes required from Intel ME-EC prespecrive. Required Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: A B 1 C D PCH(3/9): DMI/FDI/PM Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet E 19 of 103 A B C D E PCH(4/9) 3D3V_S0 4 4 OF 10 J47 M45 L_BKLTEN L_VDD_EN 49 BKLT_CTL P45 L_BKLTCTL 49 LCD_SMBCLK 49 LCD_SMBDATA T40 K47 L_DDC_CLK L_DDC_DATA T45 P39 L_CTRL_CLK L_CTRL_DATA L_CTRL_CLK L_CTRL_DATA 2 LVD_IBG 2K37R2F-GP AF37 AF36 LVD_IBG LVD_VBG AE48 AE47 LVD_VREFH LVD_VREFL 49 TXCLKA_L49 TXCLKA_L+ AK39 AK40 LVDSA_CLK# LVDSA_CLK 49 TXOUTA_L049 TXOUTA_L149 TXOUTA_L2- AN48 AM47 AK47 AJ48 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 49 TXOUTA_L0+ 49 TXOUTA_L1+ 49 TXOUTA_L2+ AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 49 TXCLKB_L49 TXCLKB_L+ AF40 AF39 LVDSB_CLK# LVDSB_CLK 49 TXOUTB_L049 TXOUTB_L149 TXOUTB_L2- AH45 AH47 AF49 AF45 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 49 TXOUTB_L0+ 49 TXOUTB_L1+ 49 TXOUTB_L2+ AH43 AH49 AF47 AF43 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 50 PCH_BLUE 50 PCH_GREEN 50 PCH_RED N48 P49 T49 CRT_BLUE CRT_GREEN CRT_RED 50 CRT_DDC_CLK 50 CRT_DDC_DATA T39 M40 CRT_DDC_CLK CRT_DDC_DATA 50 CRT_HSYNC 50 CRT_VSYNC M47 M49 CRT_HSYNC CRT_VSYNC T43 T42 DAC_IREF CRT_IRTN 3 CLOSED IN PCH1 8 7 6 5 PCH_RED PCH_GREEN PCH_BLUE 2 1 2 3 4 RN2003 SRN150F-1-GP 1 DAC_IREF SDVO_STALLN SDVO_STALLP AM42 AM40 SDVO_INTN SDVO_INTP AP39 AP40 P38 M39 DDPB_AUXN DDPB_AUXP DDPB_HPD AT49 AT47 AT40 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 DDPC_CTRLCLK DDPC_CTRLDATA P46 P42 DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPD_CTRLCLK DDPD_CTRLDATA 3 3D3V_S0 RN2001 SRN2K2J-1-GP M43 M36 DDPD_AUXN DDPD_AUXP DDPD_HPD AT45 AT43 BH41 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 PCH_HDMI_CLK 51 PCH_HDMI_DATA 51 DPD_AUXN DPD_AUXP TP2002 TP2001 1 1 TPAD14-OP-GP TPAD14-OP-GP HDMI_PCH_DET 51 2 HDMI_DATA2_R# 51 HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51 PANTHER-GP-NF 2 R2003 1KR2D-1-GP AP43 AP45 SDVO_CTRLCLK SDVO_CTRLDATA Digital Display Interface 1 R2005 SDVO_TVCLKINN SDVO_TVCLKINP 4 3 27 L_BKLT_EN 49 LCDVDD_EN LVDS 3 4 RN2002 SRN2K2J-1-GP CRT 2 1 PCH1D 1 2 4 <Core Design> 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: A B C D PCH(4/9): LVDS/CRT/DDI Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet E 20 of 103 B C 3D3V_S0 PCH1E R2113 1 PCH_GPIO51 2 10KR2J-3-GP 4 USB3.0 Table USB Pair 1 2 3 4 DY PE_GPIO0 2 10KR2J-3-GP R2111 62 USB3_RXN1 3D3V_S0 62 USB3_RXN3 82 USB3_RXN4 62 USB3_RXP1 R2110 DY 2 10KR2J-3-GP 3 2 1 62 USB3_RXP3 82 USB3_RXP4 62 USB3_TXN1 SRN8K2J-3-GP 3 ACCEL_INT# 4 NMI_SMI_DBG# 62 USB3_TXN3 82 USB3_TXN4 62 USB3_TXP1 RN2101 62 USB3_TXP3 82 USB3_TXP4 RN2102 INT_PIRQA# INT_PIRQD# INT_PIRQB# INT_PIRQC# 3D3V_S0 1 2 3 4 5 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 B21 M20 AY16 BG46 TP21 TP22 TP23 TP24 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4 RN2105 1 2 PCH_GPIO5 PCH_GPIO52 DGPU_HOLD_RST# DGPU_PW R_EN# 4 3 INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# SRN8K2J-3-GP K40 K38 H38 G38 PIRQA# PIRQB# PIRQC# PIRQD# C46 C44 E40 REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 D47 E42 F46 GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 G42 G40 C42 D44 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 K10 PME# SRN8K2J-2-GP-U 83 DGPU_HOLD_RST# 1 PCH_GPIO52 TPAD14-OP-GP TP2107 1 TPAD14-OP-GP TP2103 1 PCH_GPIO51 CAMERA_ON PE_GPIO0 TPAD14-OP-GP TP2102 93 DGPU_PW R_EN# 2 79 ACCEL_INT# 56 SATA_ODD_DA# 27 NMI_SMI_DBG# 3D3V_S5 NMI_SMI_DBG# PCH_GPIO5 R2102 1 2 10KR2J-3-GP PCI_PME# PCI_PLTRST# 27 CLK_PCI_KBC 18 CLK_PCI_FB 71,103 CLK_PCI_DEBUG CLK_PCI_KBC R2103 1 2 22R2J-2-GP R2105 1 2 22R2J-2-GP TPAD14-OP-GP TP2108 TPAD14-OP-GP TP2106 R2107 1 2 22R2J-2-GP AT10 BC8 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 RSVD23 RSVD24 AV5 AV10 RSVD25 AT8 RSVD26 RSVD27 AY5 BA2 RSVD28 RSVD29 AT12 BF3 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USB Pair 0 1 2 3 4 5 6 7 8 9 10 11 12 13 USB 3.0 I/O CONN. 4 N/A USB 3.0 I/O CONN. USB 3.0 I/O CONN. FREE BT WLAN combo FREE FREE Fingerprint USB 2.0 CONN(Debug) Camera FREE FREE FREE USB 3.0 Conn. 1 USB 3.0 Conn. 2 USB 3.0 Conn. 3 (UB1) BT WLAN combo Fingerprint USB 2.0 Conn. 1 (UB1) Camera USBRBIAS# USBRBIAS B33 OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 USB_BIAS R2101 1 2 2 22D6R2F-L1-GP 3D3V_S5 R2104 OC# 1 2 10KR2J-3-GP RN2108 USB_PP3 1 USB_PN3 2 4 3 USB_PP3_2 82 USB_PN3_2 82 15DY_17UP PCI_PLTRST# 2 USB_PP9 1 USB_PN9 2 AND GATE U2101 1 3 B VCC 5 Y 4 A SRN0J-6-GP RN2109 4 3 PLT_RST# PLT_RST# 5,27,31,32,36,65,71,82,83,103 GND 73.01G08.L04 2ND = 73.7SZ08.EAH 3RD = 73.7SZ08.DAH DY (UB2) 1 15DY_17UP -1 12/15 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. R2108 100KR2J-1-GP Title Size A3 Date: B (UB2) USB_PP9_2 82 USB_PN9_2 82 <Core Design> SRN0J-6-GP 74LVC1G08GW -1-GP A Device C24 USB_PN0 62 A24 USB_PP0 62 C25 B25 C26 USB_PN2 62 RN2106 A26 USB_PP2 62 USB_PN3 1 K28 4 USB_PN3_1 82 USB_PP3 2 H28 3 USB_PP3_1 82 E28 SRN0J-6-GP D28 C28 15UP_17DY USB_PN5 65 A28 USB_PP5 65 C29 B29 N28 M28 L30 USB_PN8 64 RN2107 K30 USB_PP8 64 USB_PP9 1 G30 USB_PN9 4 USB_PP9_1 82 USB_PN9 2 E30 USB_PP9 3 USB_PN9_1 82 C30 USB_PN10 49 SRN0J-6-GP A30 USB_PP10 49 L32 15UP_17DY K32 G32 -1 12/15 E32 C32 A32 C33 DY_RF 1 2 2 RSVD5 RSVD6 USB2.0 Table 2 1 SC12P50V2JN-3GP DY_RF CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 AY7 AV7 AU3 BG4 EC2102 SC12P50V2JN-3GP EC2101 H49 H43 J48 K42 H40 PLTRST# 5 OF 10 RSVD1 RSVD2 RSVD3 RSVD4 PANTHER-GP-NF 3D3V_S5 1 1 CLK_PCI_DEBUG 1 1 C6 CLK_PCI_SIO_R CLK_PCI_FB_R CLK_OUT_PCI2 CLK_OUT_PCI3 CLK_PCI_KBC_R E 3 3D3V_S0 3D3V_S0 10 9 8 7 6 BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 USB 1 CAMERA_ON PCH(5/9) PCI 1 Device I/O CONN. 1 LEFT_DOWN FREE I/O CONN. 2 LEFT_UP I/O CONN. 3 RIGHT_UP D RSVD A C D PCH(5/9): PCI/USB/NVM Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet E 21 of 103 A B C D E PCH(6/9) 3D3V_S0 3D3V_S0 RP2201 TP2222 3D3V_S0 4 3D3V_S5 R2204 1 1 CRD_REQ#_R_R BMBUSY#/GPIO0 TACH4/GPIO68 C40 PCH_GPIO1 A42 TACH1/GPIO1 TACH5/GPIO69 B41 UMA_DIS# PCH_GPIO6 DGPU_PRSNT# 27 EC_SCI# DY 2 10KR2J-3-GP PCH_GPIO24 RN2204 1 2 mSATA_DET# LAN_DIS# 4 3 2 1 SRN10KJ-5-GP 3 PCH_GPIO38 4 PCH_GPIO39 T7 H36 TACH2/GPIO6 TACH6/GPIO70 C41 EC_SCI# E38 TACH3/GPIO7 TACH7/GPIO71 A40 C10 GPIO8 TPAD14-OP-GP TP2229 1 PCH_GPIO8 TPAD14-OP-GP TP2202 1 LAN_DIS# TLS_ENcrytion C4 LAN_PHY_PWR_CTRL/GPIO12 G2 GPIO15 U2 SATA4GP/GPIO16 RN2205 2 DGPU_PW ROK 10KR2J-3-GP 56 SATA_ODD_DET# 103 mSATA_DET# 3D3V_S0 TP2230 1PCH_GPIO28 GPIO34 2 SATA2GP_GPIO36 1 R2231 10KR2J-3-GP E16 GPIO27 P8 GPIO28 K1 STP_PCI#/GPIO34 K4 GPIO35 V8 SATA2GP/GPIO36 H_A20GATE 27 AU16 H_PECI_R 1 R2209 P5 2 DY 0R2J-2-GP PROCPWRGD AY11 THRMTRIP# AY10 PCH_THRMTRIP#_R INIT3_3V# T14 INIT3_3V# DF_TVS AY1 DF_TVS TS_VSS1 AH8 TS_VSS2 AK11 TS_VSS3 AH10 TS_VSS4 AK10 H_PECI 5,27 H_RCIN# 27 H_CPUPW RGD DY R2222 56R2J-4-GP 5 1 2 R2210 390R2F-2GP TP2203 TPAD14-OP-GP 1 H_THRMTRIP# 5,36 PROC_SELECT 1D8V_S0 SATA3GP_GPIO37 M5 SATA3GP/GPIO37 PCH_GPIO38 N2 SLOAD/GPIO38 PCH_GPIO39 M3 SDATAOUT0/GPIO39 V13 SDATAOUT1/GPIO48 R2201 2K2R2J-2-GP UMA_DIS# NC_1 3 P37 1 R2202 2 1KR2J-1-GP H_SNB_IVB# 5 2 DY GPIO6_DF_DY GPIO22_35W GPIO1_Goya15 2 V3 SATA5GP/GPIO49/TEMP_ALERT# D6 GPIO57 A4 VSS_NCTF_1#A4 A44 VSS_NCTF_2#A44 A45 VSS_NCTF_3#A45 A46 VSS_NCTF_15#BG2 BG2 VSS_NCTF_16#BG48 BG48 DMI & FDI Termination Voltage VSS_NCTF_17#BH3 BH3 VSS_NCTF_18#BH47 BH47 VSS_NCTF_19#BJ4 BJ4 VSS_NCTF_20#BJ44 BJ44 VSS_NCTF_21#BJ45 BJ45 VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 BJ46 A5 VSS_NCTF_5#A5 VSS_NCTF_23#BJ5 BJ5 A6 VSS_NCTF_6#A6 VSS_NCTF_24#BJ6 BJ6 B3 VSS_NCTF_7#B3 VSS_NCTF_25#C2 C2 B47 VSS_NCTF_8#B47 VSS_NCTF_26#C48 C48 BD1 VSS_NCTF_9#BD1 VSS_NCTF_27#D1 D1 VSS_NCTF_28#D49 D49 BD49 BE1 BE49 VSS_NCTF_10#BD49 VSS_NCTF_11#BE1 VSS_NCTF_12#BE49 SNB: "1" IVB: "0" DF_TVS 3D3V_S0 R2233 10KR2J-3-GP DY 1 10KR2J-3-GP 27 PCH_TEMP_ALERT# 2 DGPU_PRSNT# 2 10KR2J-3-GP R2230 10KR2J-3-GP NCTF R2216 NCTF TEST PIN: A4,A44,A45,A46,A5,A6,B3,B47, BD1,BD49,BE1,BE49,BF1,BF49, BG2,BG48,BH3,BH47,BJ4,BJ44, BJ45,BJ46,BJ5,BJ6,C2,C48,D1, D49,E1,E49,F1,F49 R2215 1 R2212 1 GPIO69_DIS 1 2 2 2 PCH_GPIO6 PCH_GPIO22 PCH_GPIO1 10KR2J-3-GP 1 2 10KR2J-3-GP 1 R2205 1 R2206 10KR2J-3-GP 1 R2211 10KR2J-3-GP 3 2 2 GPIO22_45W GPIO1_Balen17 GPIO24 P4 2 TPAD14-OP-GP E8 4 1 PCH_GPIO24 SCLOCK/GPIO22 CPU/MISC 3D3V_S0 TACH0/GPIO17 T5 GPIO D40 93 DGPU_PW ROK GPIO6_FF PECI RCIN# PCH_GPIO22 SATA_ODD_PW R_EN 56 1D05V_S0 A20GATE SRN10KJ-5-GP 1 R2218 2 10KR2J-3-GP 2 10KR2J-3-GP 1 TPAD14-OP-GP SRN10KJ-L3-GP R2207 1 R2208 1 6 OF 10 PCH1F 2 3D3V_S0 H_A20GATE H_RCIN# 10 9 8 GPIO34 7 6 EC_SCI# 2 PCH_TEMP_ALERT# SATA_ODD_PW R_EN VSS_NCTF_29#E1 VSS_NCTF_30#E49 R2232 10KR2J-3-GP E1 "H"GDDR5 "L"DDR3 E49 VRAM BF1 VSS_NCTF_13#BF1 VSS_NCTF_31#F1 F1 BF49 VSS_NCTF_14#BF49 VSS_NCTF_32#F49 F49 DDR3 1 1 2 3 4 5 PANTHER-GP-NF 3D3V_S0 3D3V_S0 3D3V_S0 1 R2217 1 SATA3GP_GPIO37 200KR2J-L1-GP 2 10KR2J-3-GP 2 DY 1 R2226 FDI TERMINATION VOLTAGE OVERRIDE GPIO37 (FDI_OVRVLTG) LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT) SATA0GP_GPIO21 17 RN2202 1 2 1 R2213 SATA2GP_GPIO36 200KR2J-L1-GP 2 10KR2J-3-GP 4 3 SATA_ODD_DET# 2 DY 1 R2227 SRN10KJ-5-GP <Core Design> 3D3V_S5 Wistron Corporation DMI TERMINATION VOLTAGE OVERRIDE GPIO36 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 R2214 LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT) 2 TLS_ENcrytion 1KR2J-1-GP Title PCH(6/9): GPIO/NTCF/RSVD Size A3 Date: A 1 B C D Document Number Rev 1 Colossus Thursday, January 05, 2012 Sheet E 22 of 103 5 4 3 2 1 3D3V_S0 2 PCH(7/9) VCC_PCH: 6A DY 3D3V_DAC_S0 R2307 0R3J-0-U-GP 5V_S0 U2301 1 1mA AN21 VCCIO17 AN26 VCCIO18 AN27 VCCIO19 C2302 VCCIO26 VCCDFTERM1 AG16 BH29 VCC3_3_3 VCCDFTERM2 AG17 VCCDFTERM3 AJ16 VCCDFTERM4 AJ17 2 +V1.05S_VCCDPLL_FDI AP17 VCCVRM2 VCCAFDIPLL VCCIO27 +V1.05S_VCC_DMI VCCDMI2 1 2 1 1 2 2 1 1 2 42mA C2319 SC1U10V2KX-1GP 1D05V_S0 2 20mA 0R0603-PAD-1-GP -1 1220 1D8V_S0 C2303 190mA B 3D3V_S5 VCCSPI 20mA V1 SC1U10V2KX-1GP AU20 1D05V_S0 R2301 1 2 0R0402-PAD 1 R2306 VCCIO25 BG6 1 AB36 VCCCLKDMI AN34 +V1.05S_VCCAPLL_FDI 2 1 VCCCLKDMI AN33 2 0R3J-0-U-GP 1 CRT LVDS VCCDMI1 AT20 2 VCCIO24 160mA +VCCAFDI_VRM 1 AT24 C C2318 2 VCCIO23 C2309 1 VCCIO22 AP26 AP16 -1 1220 AT16 C2307 2 AP24 +VCCAFDI_VRM 0R0603-PAD-1-GP VCCVRM3 PANTHER-GP-NF 1 1 R2303 VCCIO21 DFT / SPI 1 DY V34 C2306 +V1.05S_VCC_DMI C2304 SCD1U10V2KX-4GP 2 1 R2302 VCC3_3_7 3D3V_S0 SCD1U10V2KX-4GP 1D05V_S0 V33 SC1U10V2KX-1GP 3D3V_S0 B VCC3_3_6 2nd = 74.70233.03F 60mA VCCIO20 AP23 C2301 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 1 C2320 2 1 1 C2321 2 1 C2311 SC1U6D3V2KX-GP SC1U10V3KX-3GP 2 C2310 2 1 AP21 AP37 D C2305 2 1 SC: decap AP36 VCCTX_LVDS4 C2308 1D8V_S0 2 VCCIO16 VCCTX_LVDS3 1 2 3 74.09090.D3F 3D3V_S0 2 AN17 DY VCCTX_LVDS2 AM38 FDI 1D05V_S0 C2317 AM37 266mA 2 SC10U6D3V3MX-GP C VCCTX_LVDS1 VIN GND EN 1 VCCIO15 AK37 NC#4 2 VCCAPLLEXP AN16 VSSALVDS HVCMOS BJ22 AK36 VOUT 4 G9090-330T11U-GP SC10U6D3V5KX-1GP +V1.05S_VCCAPLL_EXP 1 2 IND-1UH-100-GP C2312 SC1U10V2KX-1GP 1mA VCCALVDS SCD1U10V2KX-4GP VCCIO28 DY U47 C2323 SCD01U16V2KX-3GP L2301 1D05V_S0 AN19 VSSADAC C2322 SCD01U16V2KX-3GP 2.925A DMI 1D05V_S0 VCCIO 2 1 1 1 2 1 2 2 DY VCCADAC U48 5 SC1U10V2KX-1GP SC1U6D3V2KX-GP DY C2316 VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE17 7 OF 10 SCD1U10V2KX-4GP C2315 SC1U10V2KX-1GP C2314 SC1U6D3V2KX-GP SC10U6D3V3MX-GP C2313 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 POWER VCC CORE PCH1G 1.3A SCD01U16V2KX-3GP 1D05V_S0 D +VCCAFDI_VRM A 1D5V_S0 1 R2304 1D8V_S0 1 R2305 2 0R3J-0-U-GP DY 2 0R3J-0-U-GP <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PCH(7/9): PWR1 Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 23 of 103 A B C 1 R2405 2 0R3J-0-U-GP PCH1J +VCCACLK AC31 VCCASW11 AD29 VCCASW12 VCCASW13 W21 VCCASW14 W23 VCCASW15 W24 VCCASW16 W26 VCCASW17 W29 VCCASW18 W31 VCCASW19 W33 VCCASW20 1 AA16 VCC3_3_8 W16 VCC3_3_4 T34 VCC3_3_2 AJ2 1 CH751H-40-1-GP A 2 C2417 SC1U10V2KX-1GP 2ND = 83.R2004.B8F 3RD = 83.R3004.A8F 3D3V_S0 C2418 C2419 266mA 3D3V_S0 C2422 SCD1U10V2KX-4GP 2 VCCIO7 VCCDIFFCLKN1 VCCDIFFCLKN2 VCCDIFFCLKN3 1 1 VCC3_3_1 VCCIO5 AF13 VCCIO12 AH13 VCCIO13 AH14 VCCIO6 AF14 VCCAPLLSATA VCCVRM1 2 C2423 AK1 +V1.05S_VCCAPLL_SATA3 AF11 +VCCAFDI_VRM 1D05V_S0 2 1D05V_S0 DY 2 L2404 IND-10UH-193-GP C2425 SC10U6D3V3MX-GP 1 DY AC16 VCCIO3 AC17 VCCIO4 AD17 1 VCCIO2 1D05V_S0 C2430 1 2PCH_DCPSST V16 SCD1U10V2KX-4GP DCPSST T17 V19 DCPSUS1 DCPSUS2 BJ8 V_PROC_IO 1D05V_S0 VCCASW22 T21 VCCASW23 V21 VCCASW21 T19 <Core Design> PANTHER-GP-NF VCCSUSHDA 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. C2438 SCD1U10V2KX-4GP Title 2 DY Wistron Corporation 10mA P32 1 VCCRTC RTC 1 A22 C2437 PCH(8/9): PWR2 Size A3 Date: A B 1 3D3V_S5 6uA 2 1 C2436 DY 2 2 C2435 SC1U10V2KX-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP 1 RTC_AUX_S5 CPU 2 1 C2434 MISC +V1.05M_VCCSUS C2431 SC1U10V2KX-1GP C2428 2 VCCSSC HDA 2 1 2 0R3J-0-U-GP 2 1 2 P22 3 C2416 SC1U6D3V2KX-GP 1 P20 VCCSUS3_3_5 R2403 10R2J-2-GP SC1U10V2KX-1GP 1 VCCADPLLB AF17 AF33 AF34 AG34 AG33 SC1U6D3V2KX-GP C2429 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U10V3KX-3GP 2 VCCSUS3_3_4 1mA D2402 83.R0304.D8F 3D3V_S5 1 VCCADPLLA BF47 95mA 1 1 VCCVRM4 DY C2433 N22 5V_S0 2 BD47 1mA C2432 N20 VCCSUS3_3_3 DCPRTC SATA 1 2 1D05V_S0 1D05V_S0 1 VCCSUS3_3_2 +V5S_PCH_VCC5REF 2ND = 83.R2004.B8F 3RD = 83.R3004.A8F 2 1 2 1 2 1 2 2 1 2 SC1U6D3V2KX-GP SC1U6D3V2KX-GP DY C2415 DY P34 3D3V_S0 SC1U6D3V2KX-GP Y49 160mA 1D05V_S0 1 R2404 AN24 SCD1U10V2KX-4GP AD31 VCCSUS3_3_1 C2409 SCD1U10V2KX-4GP +VCCA_USBSUS 2 VCCASW10 DCPSUS4 +V5A_PCH_VCC5REFSUS 1 AC29 83.R0304.D8F AN23 V5REF 1mA R2402 10R2J-2-GP 2 VCCASW9 M26 1mA D2401 CH751H-40-1-GP K A AC27 V5REF_SUS 2 VCCASW8 T26 1 AC26 PCI/GPIO/LPC VCCASW7 Clock and Miscellaneous 2 2 2 VCCASW6 AA31 VCCIO34 SCD1U10V2KX-4GP C2421 SC1U10V2KX-1GP TC2402 SC22U6D3V5MX-2GP C2420 SC1U10V2KX-1GP TC2401 SC22U6D3V5MX-2GP C2426 VCCASW5 AA29 N16 +V1.05S_VCCA_B_DPL 55mA P24 5V_S5 K VCCASW4 +VCCAFDI_VRM +V1.05S_VCCA_A_DPL 1D05V_S0 C2427 VCCSUS3_3_6 3D3V_S5 C2407 SCD1U10V2KX-4GP 1D05V_S0 1 AA26 +VCCRTCEXT C2424 SCD1U10V2KX-4GP AF33, AF34 and AG34 should be VCCDIFFCLKN[3:1] 1D05V_S0 V24 1 VCCASW3 +V1.05S_VCCA_B_DPL 2 VCCSUS3_3_10 C2406 SCD1U10V2KX-4GP 3D3V_S5 2 AA24 80mA DY VCCSUS3_3_9 V23 2 VCCASW2 2 VCCASW1 AA21 +V1.05S_VCCA_A_DPL DY T24 2 1 DCPSUS3 AA19 68.1001D.10E 2ND = 68.1001E.10N VCCSUS3_3_8 97mA 1 VCCIO14 1 1 1 1 C2414 SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 1 C2413 SC1U6D3V2KX-GP 2 C2412 80mA L2403 1 2 IND-10UH-215-GP T23 SC1U10V2KX-1GP C2411 1 2 IND-10UH-215-GP VCCSUS3_3_7 4 3D3V_S5 1 VCCAPLLDMI2 AL29 AA27 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP 68.1001D.10E L2402 T29 VCC3_3_5 BH23 AL24 2ND = 68.1001E.10N 1D05V_S0 T27 VCCIO33 1 2 +VCCSUS1 1.01A 3 VCCIO32 2 T38 2 DCPSUSBYP C2402 1 1D05V_S0 DY DY C2410 VCCIO31 P28 2 +VCCAPLL_CPY_PCH C2408 SC1U10V2KX-1GP 1D05V_S0 P26 1 V12 USB C2405 N26 VCCIO30 VCCDSW3_3 1 1 2 1 IND-10UH-193-GP C2439 SC10U6D3V3MX-GP 2 1 2 SC1U10V2KX-1GP SC10U6D3V3MX-GP C2404 VCCIO29 2 DY L2405 VCCACLK 1 1D05V_S0 2ND = 68.1001E.10N T16 C2403 SCD1U10V2KX-4GP PCH_VCCDSW C2401 SCD1U10V2KX-4GP +V3.3S_VCC_CLKF33 DY -1 1220 2 68.1001D.10E 1D05V_S0 10 OF 10 2 +VCCPDSW 1 +V3.3S_VCC_CLKF33 2.925A POWER SC1U6D3V2KX-GP L2401 1 2 IND-10UH-215-GP AD49 2 0R0603-PAD-1-GP 3D3V_S0 4 DY 3D3V_S5 1 R2401 E PCH(8/9) 1D05V_S0 2mA D C D Document Number Rev 1 Colossus Tuesday, December 27, 2011 Sheet E 24 of 103 A B 9 OF 10 PCH1I AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 4 3 2 1 C VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 D E PCH(9/9) 8 OF 10 PCH1H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 4 3 2 PANTHER-GP-NF <Core Design> 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PANTHER-GP-NF Size A3 Date: A B C D Document Number PCH(9/9): GND Rev 1 Colossus Monday, December 26, 2011 Sheet E 25 of 103 5 4 3 2 1 D D (Blanking) C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number PCH_XDP Rev 1 Colossus Monday, December 26, 2011 Sheet 1 26 of 103 5 4 KROW[0..7] 78 77 80 79 39,40 BAT_SDA 39,40 BAT_SCL 18,29,79,86 SML1_DATA 18,29,79,86 SML1_CLK C PCIE_WAKE# 19,31 BLON_OUT 49 USB_PWR_EN# 61,62 A_SD# 29 S5_ENABLE 36 PM_PWRBTN# 19 RSMRST#_KBC 19 AD_OFF 38 NMI_SMI_DBG# 21 S0_PWR_GOOD 19,36 RTCRST_ON 17 AC_PRESENT 19,86 C2712 SC20P50V2JN-1GP GPXIOD0 GPXIOD1 GPXIOD2 GPXIOD3 GPXIOD4 GPXIOD5 GPXIOD6 GPXIOD7 SDA0 SCL0 SDA1 SCL1 109 110 112 114 115 116 117 118 BAT_IN# EC_GPIO70 EC_ENABLE# KBC_PWRBTN#_R TP2747 DC_BATFULL 34 65 E51_TXD 65 E51_RXD 17 ME_UNLOCK 38 CHARGE_LED 65 WIFI_RF_EN 30 31 90 92 95 1 D85V_PWRGD H_PECI_R1 1 R2745 TPAD14-OP-GP TPAD14-OP-GP 1 TP2750 TP2751 R2731 2 2 GPIO1A GPIO53 GPIO55 36 91 93 WLAN_LED# 65 EC_WLAN_LED# PWRLED 82 1 C MODEL_ID 68 GPIO59 GPIO57 GPIO50 GPIO18 GPIO8 GPIO7 GPIO4 GPIO0A GPIO0D GPIO19 GPIO16 GPIO17 GPIO52 GPIO54 GPIO56 GPIO5A GPIO5C GPIO5B GPIO58 1 TP2739 123 TPAD14-OP-GP PCH_SUSCLK_KBC 127 121 89 32 15 14 6 CHG_ON# 40 BLUETOOTH_EN 1 0R2J-2-GP KBC_ECWP_C R2744 2 ECSWI#_KBC 1 SLP_A# 122 R2726 100KR2F-L1-GP 19 3D3V_AUX_S5 65 3D3V_AUX_KBC KBC_ECWP# EC_AGND PM_SLP_S4# 19,46 STOP_CHG# 40 PM_SLP_S3# 8,19,36,46,47,92 EC_SPI_CS#_C1 EC_SPI_DO_C1 EC_SPI_DI_C1 EC_SPI_CLK_C1 128 120 119 126 R2737 R2743 R2742 R2719 2 2 2 2 1 1 1 1 2 GPIO5E 2 GPIO5D GPIO0B GPIO0C 1 1 EC_SPI_CS#_C 60 EC_SPI_DO_C 60 EC_SPI_DI_C 60 EC_SPI_CLK_C 60 R2729 10KR2F-2-GP R2733 10KR2F-2-GP DY 33R2J-2-GP 33R2J-2-GP 0R2J-2-GP 33R2J-2-GP PM_PWRBTN# D2702 KBC_ECWP# KB9016QF-A3-GP KB_BL_DETECT 71.09016.B0G K 2 R2711 1 0R0402-PAD A SPI_WP#_C 60 1SS355GP-GP 18 EC_SWI# 2 R2715 1 0R0402-PAD ECSWI#_KBC 22 EC_SCI# 2 R2712 1 0R0402-PAD ECSCI#_KBC 1 83.00355.F1F EC_AGND 2 3RD = 84.2N702.W31 2ND = 84.07002.I31 84.2N702.J31 3D3V_AUX_KBC B R2732 BAT_IN# 1 Prevent G 2 R2770 1KR2J-1-GP BIOS data loss solution B 69 KB_BL_ON_R# 84.T3906.A11 2nd = 84.03906.F11 1 2 R2723 10KR2J-3-GP 28,36,86 PURE_HW_SHUTDOWN# 1 PURE_HW_SHUTDOWN#_B B GPIO06-->PWRBTN 2N7002K-2-GP PURE_HW_SHUTDOWN# EC GPIO standard PH/PL BAT_SCL BAT_SDA 3D3V_AUX_KBC 4 3 SRN4K7J-8-GP 3D3V_AUX_KBC 1 2 3D3V_AUX_KBC KBC_PWRBTN#_R1 R2757 470R2J-2-GP 2 KBC_PWRBTN# 82 ECRST# ADT_TYPE 2 R2716 1 2 10KR2J-3-GP 2ND = 83.00099.M11 3RD = 83.00099.T11 1 83.00099.K11 C2715 SCD1U10V2KX-5GP GPIO70-->PWR_CHG_ACOK# 2 R2734 12K4R2F-GP R2725 2 L_BKLT_EN 1 3D3V_S0 2 100KR2J-1-GP 1 R2714 10KR2J-3-GP FAN_TACH1 2 A C2713 SCD1U10V2KX-5GP 1 2 PWR_CHG_ACOK# 40 0R0201-PAD-GP <Core Design> 2 28 EC_AGND LOW active R2768 EC_GPIO70 1 R2738 C2717 DY SC220P50V2KX-3GP 2 3 1 BAV99PT-GP-U D2701 1 R2706 10KR2J-3-GP 1 2 RN2701 1 R2705 10KR2J-3-GP D HP Limit Signal Detect 1KR2F-3-GP 3D3V_AUX_S5 Q2701 MMBT3906-4-GP KB_BL_ON S AD_OFF ECRST# Q2703 2 100KR2J-1-GP A 2 EC_AGND R2724 10KR2F-2-GP MODEL_ID R2730 100KR2J-1-GP 1 2 3D3V_AUX_KBC 1 PSCLK1 PSDAT1 PSCLK2 PSDAT2 PSCLK3 PSDAT3 51KR2J-1-GP LIMIT_SIGNAL 1 1 2 R2728 100KR2F-L1-GP MODEL ID 42,48 PCH_TEMP_ALERT# 22 SUS_PWR_ACK 19 H_PECI 5,22 2 38 69 KB_BL_DETECT_C 16 19 LID_CLOSE# L_BKLT_EN 1 PCB_VER_AD 39 1 82 20 17 18 KB_BL_DETECT R2727 64K9R2F-1-GP PCB_1 TPAD14-OP-GP 2 69 LOGO_BL_ON 2 R2735 100KR2F-L1-GP 1 83 84 85 86 87 88 1 1 3D3V_AUX_KBC 01/05/12 43R2J-GP 69 KBC_CLK1 69 KBC_DATA1 38 AD_DETECT 86 GPU_PROTECT# 69 TPCLK 69 TPDATA 2 2 2 1 1 2 PCB VERSION PCH_SUSCLK_KBC 1 69 GPXIOA0 GPXIOA1 GPXIOA2 GPXIOA3 GPXIOA4 GPXIOA5 GPXIOA6 GPXIOA7 GPXIOA8 GPXIOA9 GPXIOA10 GPXIOA11 WLAN_PME_DIS_C 97 98 99 100 101 102 103 104 105 106 107 108 2 2 R2736 10KR2J-3-GP TPAD14-OP-GP TPAD14-OP-GP 1 2 1 TP2748 TP2749 1 1 2 2 1 KROW7 3D3V_AUX_KBC EC_AGND 1 1 KROW6 2 C2714 ADT_TYPE CPU_THRM SYS_THRM MODEL_ID AIRLINE_VOLT_RC 2 KROW5 KROW4 TP2735 GAP-CLOSE-PWR KROW5 TP2737 GAP-CLOSE-PWR KROW6 TP2738 GAP-CLOSE-PWR KROW7 TP2740 GAP-CLOSE-PWR SCD1U10V2KX-5GP 1DY PCB_VER_AD 63 64 65 66 75 76 73 74 D E 2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 TP2742 TPAD14-OP-GP 1 QUICKWEB_BTN# 82 PROCHOT_EC 5 WLAN_PME_DIS_C 65 AD_IA 40 PROCHOT_EC C2701 C 1 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 FAN1_DAC 68 70 71 72 EC_AGND C2704 DY 2 KROW4 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 55 56 57 58 59 60 61 62 2 SC4D7U6D3V3KX-GP C2705 1 KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 DA0 DA1 DA2 DA3 1 C2711 C2706 2 KCOL[0..17] FANPWM0 FANPWM1 FANFB0 FANFB1 V18R 124 C2707 SCD1U10V2KX-5GP 69 20110608 for vendor debug V18R C2708 DY SCD1U10V2KX-5GP 28 FAN1_PWM 68 CAP_LED 28 FAN_TACH1 65 AOAC_EN# PWM0 PWM1 PWM2 C2709 SCD1U10V2KX-5GP 26 27 28 29 C2710 SCD1U10V2KX-5GP 21 23 25 KB_BL_ON EC_AGND SCD1U10V2KX-5GP FPR_OFF 1 69 11 24 35 94 113 3D3V_AUX_S5 R2703 1 2 0R0603-PAD-1-GP SC2D2U10V3KX-1GP TP2745 68 TOUCHPAD_LED AGND GND GND GND GND GND 3D3V_AUX_KBC VBAT SCD1U10V2KX-5GP TPAD14-OP-GP ECRST# 2 R2702 1 0R0402-PAD SC2D2U10V3KX-1GP ECSCI#_KBC VBAT 125 22 33 111 96 9 67 1 H_RCIN# 19 PM_CLKRUN# VCC VCC VCC VCC VCC VCC AVCC 2 17 INT_SERIRQ 22 H_A20GATE 22 H_RCIN# 5,21,31,32,36,65,71,82,83,103 PLT_RST# For EC power consumption reserver 3D3V_AUX_KBC PCICLK LFRAME# LAD0 LAD1 LAD2 LAD3 SERIRQ GA20 KBRST# PCIRST# SCI# CLKRUN# ECRST# 1 17,71 LPC_AD[0..3] D 12 4 10 8 7 5 3 1 2 13 20 38 37 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 1 3D3V_AUX_KBC U2701 21 CLK_PCI_KBC 17,71 LPC_FRAME# 2 2 SSID = KBC 3 Wistron Corporation C2718 1 AIRLINE_VOLT_RC 40 AIRLINE_VOLT R2739 1 10KR2J-3-GP 2 SCD1U16V2KX-3GP 2 S5_ENABLE R2740 1 10KR2J-3-GP BLUETOOTH_EN 1 DY R2713 10KR2J-3-GP 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 Title RN2713 pull-Low 10K Resistor to DY on BLUETOOTH_EN. HP AIRLINE COMBO Size A2 Date: 5 4 3 2 Document Number EC CONTROLLER Rev 1 Colossus Thursday, January 05, 2012 Sheet 1 27 of 103 5 4 3 2 1 3D3V_S0 1 2 R2813 1 0R0402-PAD R2809 100KR2J-1-GP Q2802 2 DY THERM_SYS_SHDN# S D D D 27,36,86 PURE_HW_SHUTDOWN# DY DY 2 2 R2812 10KR2J-3-GP 1 1 G IMVP_PWRGD 36,42 C2811 2N7002K-2-GP SCD1U10V2KX-5GP 84.2N702.J31 2ND = 84.07002.I31 3RD = 84.2N702.W31 DY 90 C 3D3V_S0 U2803 R2806 R2801 1 2 3 THERM_SYS_SHDN# VCC HYST 2 1 150R2F-1-GP 4 HYST SET GND OUT# VCC 5 1 SET G709T1UF-GP 2 222K1R2F-L-GP 1 C2817 SCD1U10V2KX-5GP 3D3V_S0 R2810 2 74.00709.A7F R2811 2 1 DY 0R2J-2-GP 1 0R2J-2-GP -1 1226 C C B B 1 5V_S0 0R2J-2-GP R2807 1 DY 2 2 R2805 10KR2J-3-GP 27 FAN_TACH1 A FAN_TACH1_C K D2801 CH551H-30GP-GP FOR PWM FAN 83.R5003.J8F 2ND = 83.R5003.H8H -1 0102 20 mil 5V_S0_FAN 5 FAN1 5V_S0_FAN R2814 5V_S0_FAN 1 FAN1_PWM_R AFTE14P-GP AFTP45 1 FAN_TACH1_C AFTE14P-GP AFTP47 1 DY ACES-CON4-19-GP L2801 MLVS0402M04-GP -1 1226 K 1 C2440 D2802 CH551H-30GP-GP 2 1 AFTE14P-GP AFTP46 2 3 4 6 AFTE14P-GP AFTP49 1 SC4D7U6D3V3KX-GP A R2815 1 FAN1_PWM 2 27 2 0R0402-PAD FAN1_PWM_R 2 1KR2J-1-GP FAN_TACH1_C 1 1 A 5V_S0 A 83.R5003.J8F 2ND = 83.R5003.H8H <Core Design> -1 0104 Wistron Corporation 20.F1637.004 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2nd = 20.F1808.004 3rd = 20.F1579.004 Title Size A2 Date: 5 4 3 2 Document Number Thermal/FAN Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 28 of 103 4 BITCLK 5 17 HDA_SDOUT_CODEC 10 17 HDA_SYNC_CODEC R2903 17 HDA_SDIN0_CODEC 2 33R2J-2-GP 1 HDA_SDIN0_CODEC_C SYNC 8 SDATA_IN R2903 Need close to Codec 11 17 HDA_RST#_CODEC RESET# 1 MUTE# R2913 49 DMIC_CLK 49 DMIC_DATA 1 1 2 R2901 10KR2J-3-GP 36 CAP- 35 7 VREFFILT CAP2 VVREG(+2.5V) 2 1 1 2 2 1 1 1 2 1 1 2 C2916 SC2D2U6D3V3KX-GP D Port Arrangement Port A---> Mic In Port B---> HeadPhone Port C---> x Port D--->Main SPKR Port E---> x Port F---> 2ND SPKR SPKR_R+ 58 SPKR_R- 58 MONO_OUT 30 12 AUO_BEEP 21 22 34 37 AUD_VREFFILT AUD_CAP2 AUD_VAUD_VREG C2918 1 C2919 1 C2920 1 C2921 1 2 2 2 2 SC10U10V5KX-2GP SCD1U10V2KX-5GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP Place close to codec PVSS 49 5 AUD_AGND SPKR_L+ 58 SPKR_L- 58 DVSS 42 C PCBEEP CAP- A 1SS355GP-GP 1 DY 2 R2927 0R2J-2-GP 26 30 33 AVSS1 AVSS2 AVSS2 GND AUD_AGND C 83.00355.F1F 2ND = 83.00355.D1F 30,58 CAP+ OUT 4 74.01085.03FC2915 FSPK_L 58 FSPK_R 58 2 D2901 K A_SD# CAP+ C2906 SC4D7U6D3V3KX-GP +VREFOUT_A NR HP_OUT_L HP_OUT_R 25 MONO_OUT 3D3V_S0 MIC_L0 2SC1U16V3KX-5GP 2 SC1U16V3KX-5GP MIC_R0 44 43 PORTD_+R PORTD_-R SPDIFOUT0/GPIO3 DMIC1/GPIO0/SPDIFOUT1 1 1 40 41 PORTD_+L PORTD_-L DMIC_CLK/GPIO1 DMIC_0/GPIO2 48 46 C2913 C2917 17 18 EAPD 2 4 68 MUTE_LED_CTRL CAP CLOSED IN CODEC 27 47 2100R2F-L1-GP-U DMIC_CLK_R DMIC_DATA_RF1 2 1 R2926 0R0402-PAD MIC_L MIC_R C2914 EN GND IN 15 16 PORTE_L PORTE_R PORTF_L PORTF_R EC2905 2 2 DY_RF SC18P50V2JN-1-GP SC18P50V2JN-1-GP EC2906 1 1 DY_RF 28 29 23 AVDD_CODEC 3 2 1 19 20 24 PORTC_L PORTC_R VREFOUT_C/GPIO4 DMIC_CLK_R DMIC_DATA_RF1 SENSE_A SENSE_B 31 32 PORTB_L PORTB_R SDATA_OUT 13 14 2 1 1 1 2 2 2 2 1 1 2 1 2 2 PORTA_L PORTA_R VREFOUT_A 6 17 HDA_BITCLK_CODEC SENSE_A SENSE_B Vout = 4.75 V HPA01085DBVR-GP AVDD_CODEC_EN SCD01U16V2KX-3GP DVDD AUD_AGND 45 39 PVDD PVDD R2919 10KR2J-3-GP SCD1U10V2KX-5GP 9 27 38 AVDD1 AVDD2 DVDD_IO 1 Q2901 C2911 SC10U10V5KX-2GP DVDD_CORE 3 C2910 SC1U10V2KX-1GP 1 C2909 SCD1U10V2KX-5GP U2901 C2907 SC1U10V2KX-1GP D C2908 SCD1U10V2KX-5GP C2901 SCD01U16V2KX-3GP C2904 SCD1U10V2KX-5GP SCD1U10V2KX-5GP HDA_RST#_CODEC C2903 SC1U10V2KX-1GP C2902 AUDIO CODEC(92HD91) 2 DVDD_CORE C2905 3D3V_S0 SC10U10V5KX-2GP 1 3D3V_S0 R2902 4K7R2J-2-GP 2 5V_S0 5V_S0 1 3D3V_S0 3 AVDD_CODEC 2 5 92HD91B2X5NLGXYAX-GP AUD_AGND 3D3V_S0 MUTE# R2904 DY 1 2 MUTE_LED_CTRL 10KR2J-3-GP +VREFOUT_A R2922 1 1 R2923 4K7R2J-2-GP MONO_L_1 2 C2926 AUO_BEEP 1 SCD1U16V2KX-3GP MIC_L0 2 R2924 1 R2908 100KR2F-L1-GP B 1 2 1 EC2901 SCD01U16V2KX-3GP 2 D C2925 G 2ND = 84.07002.I31 3RD = 84.2N702.W31 17 AUD_AGND HDA_SPKR AUD_AGND 2 SENSE_A DY C2923 SC1KP50V2KX-1GP EC2902 R2918 1 22.10270.E11 2ND = 22.10270.F61 AUD_AGND B SENSE_A_jack 2 AUD_AGND 39K2R2F-L-GP audio ground must be connect to digital ground with an 80 mil copper 2 1 MIC_R0_jack 84.2N702.J31 GAP-CLOSE-PWR-3-GP AUD_AGND 4 3 6 2 1 BLM18PG600SN-2GP 2 1 2 1 AVDD_CODEC 1 SC220P50V2KX-3GP GAP-CLOSE-PWR-3-GP G2903 1 2 GAP-CLOSE-PWR-3-GP G2904 1 2 GAP-CLOSE-PWR-3-GP G2905 1 2 AUD_AGND R2911 10KR2J-3-GP Q2902 2N7002K-2-GP 5 MIC_L0_jack SC220P50V2KX-3GP GAP-CLOSE-PWR-3-GP G2902 1 2 If sense A total length is greater than 6 inches. Change C2922 to 0.1uF MIC_R0 2 2 S 1 1 BLM18PG600SN-2GP 2 R2925 1 2 2 100KR2J-1-GP C2924 R2910 1 MONO_L_0 1 2 SCD1U16V2KX-3GP 1 MONO_L 2 2 0818 IDT request Place under U2901 C2922 SC1KP50V2KX-1GP SENSE_B MIC1 AUDIO-JK306-GP 9 8 7 AUD_AGND G2901 Close to Pin14 ME update MIC1 Jack 2 SC1U6D3V2KX-GP 4K7R2J-2-GP R2906 2K49R2F-GP SENSE_A MIC IN C2927 AVDD_CODEC R2909 10KR2J-3-GP 1 Close to Pin13 PC BEEP Tie Analog GND and Digital GND under codec by a single point 1 Digital GND & AUD_AGND Headphone Trace = 15mil AVDD_CODEC 2 SENSE Detect ADD TEST PAD bridge located directly under codec AUD_AGND -1 12/15 Add AFTP 30 & 31 to prevent ESD latch up. HeadPhone AUD_AGND 1 1 1 1 AUD_AGND SENSE_A_jack MIC_L0_jack MIC_R0_jack AFTP31 AFTP30 AFTP21 AFTP27 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP 5V_S0 2 HPA_OUT_R_jack 22.10270.E11 2ND = 22.10270.F61 2 2 1 1 1 2 HPA_OUT_L_jack 1 AFTP16 AFTE14P-GP HPA_OUT_R_jack 1 AFTP22 AFTE14P-GP 20KR2F-L-GP SENSE_JACK 1 AFTP35 AFTE14P-GP AUD_AGND 1 AFTP36 AFTE14P-GP 5 4 14 11 C2933 AUD_AGND AUD_AGND SENSE_JACK 1 2 CPN CPP LEFTINM LEFTINP CPVSS CPVSS RIGHTINM RIGHTINP HPLEFT HPRIGHT GND GND GND GND GND GND 7 8 2 SD# 15 16 C2928 3 9 10 13 19 21 6 2 5 3 4 SML1_CLK 18,27,79,86 2N7002KDW-GP SML1_DATA 18,27,79,86 84.2N702.A3F SC2D2U10V3KX-1GP HP_DATA A 2nd = 84.2N702.E3F 3RD = 84.2N702.F3F C2934 <Core Design> HPA00929RTJR-GP AUD_AGND Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Audio Codec 92HD91/HeadphoneAMP Size A2 Date: 3 1 CPVSS AUD_AGND 4 PQ2903 HP_CLK -1 12/15 Add AFTP 35 & 36 5 RN2901 SRN2K2J-1-GP HP_DATA HP_CLK 1 2 SDA SCL 6 4 3 1 RIGHTINM RIGHTINP 2 SC1U10V2KX-1GP R2915 HPA_OUT_L1 2 30R3F-GP HPA_OUT_R1 2 R2916 30R3F-GP SC1U10V2KX-1GP AUD_AGND 1 2 R2914 HPA_OUT_L HPA_OUT_R SC1U10V2KX-1GP C2932 1 LEFTINM LEFTINP 2 SC1U10V2KX-1GP AUD_AGND SENSE_A C2931 1 HP_OUT_R EC2903 SC220P50V2KX-3GP A SC220P50V2KX-3GP EC2904 HP_OUT_L 4 3 6 2 1 17 18 SD# 1 1 HPA_OUT_L_jack BLM18PG600SN-2GP 2 2 2 1 HPA_OUT_R 1 EL2902 1 HPA_OUT_L C2929 1 AUD_AGND SC1U10V2KX-1GP 5 CPN 2CPP VDD VDD 1 1 BLM18PG600SN-2GP EL2901 R2917 10KR2J-3-GP U2902 12 20 2 9 8 7 5V_S0 C2935 SCD1U10V2KX-5GP HP1 AUDIO-JK306-GP 1 SC1U10V2KX-1GP ME update HP1 Jack 2 3D3V_S0 C2930 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 29 of 103 5 4 3 2 1 PVCC DCBATOUT R3001 D BSN#26 26 BSNL W OOFER_OUTN SCD47U25V3KX-1GP 26 0 32 1 OUTN#25 25 GAIN0 PGND 24 G1 6 GAIN1 OUTN#23 23 R3002 1 DY 2 AVCC BSN#22 22 10R5J-GP AGND BSP#21 21 9 GVDD OUTP#20 20 10 PLIMIT PGND 19 11 INN OUTP#18 18 12 INP BSP#17 17 36 1R3010 WOOFER 210KR2J-3-GP PVCC 13 NC#13 PVCC 16 14 AVCC PVCC 15 R3003 1 DY 2 BSPL 1 C3009 W OOFER 1 SC10U25V5KX-GP 28K7R2F-GP WOOFER 2 WOOFER 2 1 1 1 2 2 2 2 C3012 AFTP29 AFTE14P-GP 1 AFTP28 AFTE14P-GP 1 AFTP48 AFTE14P-GP W OOFER1 3 1 2 4 1 DY ACES-CON2-18-GP SC1000P50V3JN-GP-U 2ND = 20.F1864.002 PVCC C 20.F1637.002 W OOFER_+ WOOFER 68.00206.051 2ND = 68.00216.031 C3010 SC1000P50V3JN-GP-U G1=0 G0=0 G1=0 G0=1 G1=1 G0=0 G1=1 G0=1 C3011 GAIN=6dB GAIN=12dB GAIN=18dB GAIN=24dB HPF=275Hz GAIN=16dB WOOFER WOOFER WOOFER WOOFER WOOFER R3013 0R0603-PAD 1 1 C3013 74.00836.01G C3006 SC1000P50V3JN-GP-U C3008 BSPL_R_G SCD1U25V3KX-GP 2 2 SCD47U25V3KX-1GP SC1U25V3KX-1-GP SC1U16V3KX-5GP 2 1 DY L3002 1 2 PBY201209T-800Y-N-1GP TPA3111D1-GP R3011 R312 0R0603-PAD 2 SC1000P50V3JN-GP-U 10R5J-GP W OOFER_OUTP C3016 WOOFER BSNL_R_G 1 W OOFER_+ W OOFER_C3007 2 1 NC#4 5 2 R3009 1 2 49K9R2F-L-GP SC1U16V3KX-5GP 100KR2J-1-GP 100KR2J-1-GP L3001 1 2 PBY201209T-800Y-N-1GP 4 C3015 1 68.00206.051 2ND = 68.00216.031 W OOFER_- 1 1 1 R3007 DY WOOFER 1 0 R3006 1 20 2 G0 R3008 1 2 10R5J-GP 7 2 1 C3014 SC1U25V3KX-1-GP 8 2 GAIN 0 1 G0 0 2 C G1 C3005 1 SC4D7U25V5KX-GP NC#3 D 1 2 PVCC 3 C3001 1 FAULT# 27 2 2 100KR2J-1-GP 28 1 DY GAIN 26dB 29 2 R3005 1 2 100KR2J-1-GP GND PVCC 2 5V_S0 R3004 1 SD# C3002 SC4D7U25V5KX-GP 1 MUTE# 1 29,58 2 WOOFER WOOFER WOOFER U3001 C3003 SCD1U25V3KX-GP WOOFER WOOFER WOOFER C3004 SC1KP50V2KX-1GP 2 1 WOOFER AMP 1 2 0R0603-PAD-1-GP 1 SC1U16V3KX-5GP 2 B SC1U16V3KX-5GP 2 1 C3017 C3018 B WOOFERWOOFER Woofer use in AUD_AGND ground MONO_OUT 29 <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Audio AMP_SPK/WOOFER Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 30 of 103 5 4 3 2 1 Regout power plane(1D05V) LAN CHIP-RTL8111F USE EFuse No ASF W HITE_LED# 59 2 DY 1 C3115 2 1 C3116 2 1 2 C3135 SCD1U16V2KX-3GP 1 2 1 2 LAN_GPO DY C3121 cap near pin3,6,9,13,29,41,45 VDD10 VDD10 LANXOUT LANXIN VDD33 VDD33 DY C3107 SCD1U10V2KX-5GP RSET VDD33 D SCD1U10V2KX-5GP 2 2K49R2F-GP Put cap near pin21 SCD1U16V2KX-3GP R3104 1 EEPROM LED OPTION USE '00' => LED0 : ACT (Amber) => LED1 : LINK (White) (BOTH 10/100 & GIGA CHIP) (Power down => Kept high) C3120 SCD1U10V2KX-5GP 2 1 C3123 SCD1U10V2KX-5GP AMBER_LED# 59 R3117 1 2 0R0603-PAD C3109 VDD10 cap near pin12,27,39,42,47,48 <200mils Avoid Leakage C3112 SCD1U16V2KX-3GP 1 2 Place closed to Pin 34,35 1 C3106 2 C3119 2 1 2 1 2 1 2 1 2 SCD1U16V2KX-3GP 2 2 SRN10KJ-5-GP C3114 SC4D7U10V3KX-GP 2 1 C3118 SCD1U10V2KX-5GP 3 4 C3117 SCD1U10V2KX-5GP RN3101 EEDI EECS DY C3103 SCD1U10V2KX-5GP DY C3122 SCD1U10V2KX-5GP 2 10KR2J-3-GP 1 1 2 0R0603-PAD C3124 SCD1U10V2KX-5GP R3118 1 VDDREG SC1U6D3V2KX-GP 1 2 0R0603-PAD SCD1U10V2KX-5GP D LAN_SMBDATA R3131 1 2 1KR2J-1-GP 1 R3106 1 SCD1U16V2KX-3GP 40 mils R3130 LAN_GPO 1 VDD33 2 3D3V_S5 1 EVDD10 VDD33 C C VDD10 59 59 MDIP1 MDIN1 VDD10 59 59 MDIP2 MDIN2 VDD10 59 59 MDIP3 MDIN3 VDD33 13 14 15 16 17 18 19 20 EVDD10 21 22 23 24 B Using Efuse Without ASF 36 35 34 33 32 31 30 29 28 27 26 25 Lan (1) (2) (3) (4) REGOUT VDDREG ENSW REG EEDI PCIE_W AKE# 19,27 ISOLATE# PLT_RST# 5,21,27,32,36,65,71,82,83,103 LANXOUT 2 PCIE_RXP6_R 1 2 C3111 SCD1U10V2KX-5GP 2 C3110 SCD1U10V2KX-5GP KBC Reserved Pin Isolate# => Low , Isolate LanChip GPO => EFuse Strap Pin PCIE_RXP6_LAN 18 ENSWREG (REGOUT 1D05V) PH = Enable PL = Disable Isolate Strap Pin 3D3V_S0 1 3 4 R3111 1KR2J-1-GP C3105 2 Crystal +/- 20 ppm 4 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. R3114 15KR2F-GP LANXIN SC18P50V2JN-1-GP 5 A 1 2 1 ISOLATE# 2 <Core Design> 2 3RD = 82.30020.G61 2ND = 82.30020.G71 1 1 PCIE_RXN6_LAN 18 X3101 XTAL-25MHZ-155-GP 82.30020.D41 1 R3119 2 0R0402-PAD Close to LanChip SC18P50V2JN-1-GP A B VDD33 CLK_PCIE_LAN# 18 CLK_PCIE_LAN 18 C3104 2 Put 4D7U L + 22U cap near pin36 <200mils (2nd = 78.22610.81L) VDD33 PCIE_TXN6_LAN 18 PCIE_TXP6_LAN 18 1 DY EECS VDD10 ENSW REG 18 CLKREQ_LAN# 25MHz Crystal Power Inductance Spec IDC >= 600mA Tolerance < 20% RDC <= 0.8ohms(Max) Efficiency >= 80% C3113 Regout Switch PCIE_RXN6_R 1 LAN_SMBDATA C3101 2 REGOUT VDDREG VDDREG ENSWREG EEDI/SDA LED3/EEDO EECS/SCL DVDD10 LANWAKE# DVDD33 ISOLATE# PERST# 71.08111.N03 VDD10 RTL8111F-CGT-GP 1 48 47 46 45 44 43 42 41 40 39 38 37 MDIP0 MDIN0 AVDD10 MDIP1 MDIN1 AVDD10 MDIP2 MDIN2 AVDD10 MDIP3 MDIN3 AVDD33 DVDD10 SMBCLK SMBDATA CLKREQ# HSIP HSIN REFCLK_P REFCLK_N EVDD10 HSOP HSON GND +3.3V_LAN_S5 Rising time (10%~90%) Spec >1mS and <100mS 1 2 3 4 5 6 7 8 9 10 11 12 1 2 IND-4D7UH-192-GP 68.4R750.20C SCD1U10V2KX-5GP LanChip Power MDIP0 MDIN0 GND L3101 SC4D7U10V3KX-GP 59 59 REGOUT AVDD33 AVDD33 RSET AVDD10 CKXTAL2 CKXTAL1 AVDD33 DVDD10 LED0 DVDD3 GPO/SMBALERT LED1/EESK U3101 49 60 mils Title Size A3 Date: 3 2 Document Number LAN_RTL8111F Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 31 of 103 5 4 3 2 RTS5229 -1 12/15 CLKREQ_MEDIA# 18 PLT_RST# 5,21,27,31,36,65,71,82,83,103 SD_CD#_C SD_W P_C 3D3V_S0_L R3211 1 SP5 SP7 R3201 1 R3202 1 SP9 SP10 R3203 1 R3204 1 SP12 SP14 R3205 1 R3206 1 SD_CD#_C SD_W P_C R3209 1 R3210 1 2 0R0201-PAD-GP 2 0R0201-PAD-GP 15UP_17DY 15UP_17DY 0R0201-PAD-GP 2 2 0R0201-PAD-GP 15UP_17DY 15UP_17DY SD_D1 SD_D0 74 74 SD_CLK SD_CMD 74 74 SD_D3 SD_D2 74 74 SD_CD# SD_W P 74 74 D 2 100KR2J-1-GP R3207 1 2 10KR2J-3-GP 15UP_17DY 2 0R0201-PAD-GP 2 0R0201-PAD-GP 15UP_17DY 15UP_17DY 2 0R0201-PAD-GP 2 0R0201-PAD-GP 15UP_17DY 15UP_17DY (RTS5229)U3201 closed near CLKREQ# PERST# MS_INS# SD_CD# SD_WP GPIO 24 23 22 21 20 19 Vendor info update design issue U3201 0201 0 Ohm change to short pad 3D3V_S0 15UP_17DY D 1 C3216 AV12 RREF 7 8 9 10 11 12 RTS5229-GR-1-GP C DV33_18 15UP_17DY 2 SP5 C3206 SCD1U16V2KX-3GP C3205 SC4D7U10V5ZY-3GP 2 SC10U6D3V5KX-1GP SCD1U16V2KX-3GP 2 C3204 SC4D7U10V5ZY-3GP 1 C3208 CARD_DV12_S 2 1 1 3D3V_S0 C3207 15UP_17DY 15UP_17DY B 2 15UP_17DY 15UP_17DY 1 2 RREF 1 R3208 6K2R2F-GP CARD1_3V3 2 1 CARD_DV12_S C3201 SC1U6D3V2KX-GP 15UP_17DY 1 GND SP14 SP12 SP10 DV33_18 SP9 SP7 2 25 18 17 16 15 14 13 1 15UP_17DY 15UP_17DY C SP6 SP5 SP4 DV33_18 SP3 SP2 2 SCD1U16V2KX-3GP 2PCIE_RXP3_MEDIA_C 2PCIE_RXN3_MEDIA_C SCD1U16V2KX-3GP HSIP HSIN REFCLKP REFCLKN HSOP HSON 1 C3209 1 C3210 1 1 2 3 4 5 6 SC5P50V2CN-2GP PCIE_TXP3_MEDIA PCIE_TXN3_MEDIA CLK_PCIE_MEDIA CLK_PCIE_MEDIA# PCIE_RXP3_MEDIA PCIE_RXN3_MEDIA AV12 RREF 3V3_IN CARD_3V3 DV12_S SP1 18 18 18 18 18 18 C3203 SCD1U16V2KX-3GP 15UP_17DY 15UP_17DY B 15UP_17DY 15UP_17DY <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Card Reader-RTS5229 Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 32 of 103 5 4 3 2 1 D D (Blanking) C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 1394 Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 33 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 34 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 35 of 103 5 4 3 2 1 Power Sequence R3614 CRB : 1K R3623 1 R3614 28,42 IMVP_PW RGD SYS_PW ROK 2 0R0201-PAD-GP 2 1 0R0402-PAD 3D3V_S5 U3608 D3603 1 3 19,27 S0_PW R_GOOD 1 D SYS_PW ROK 19 2 BAS16-6-GP 5,46,47 RUNPW ROK 8,19,27,46,47,92 C3612 SCD01U50V2KX-1GP PM_SLP_S3# 1 B 2 A 3 2 DY 83.00016.K11 2ND = 83.00016.F11 VCC 5 Y 4 D PW R_1D05V_1V_EN 45 GND 74LVC1G08GW -1-GP 73.01G08.L04 2ND = 73.7SZ08.DAH DY DY 4 1 0R0402-PAD 1 3D3V_S0 5 2 4 DY SCD1U25V2KX-GP G 4 78.10324.2FL R3612 100KR2J-1-GP 3 84.DMN66.03F 0D75V_S0 Q3604 2 22R2J-2-GP B 6 C3611 1 1 5 2 4 3 R3620 1 DMN66D0LDW -7-GP 84.DMN66.03F 1D5V_S0 2 220R2F-GP 2 MAX Current 3000 mA Design Current 2100 mA Q3605 2N7002K-2-GP 1D5V_S3 R3621 1 1 SCD1U25V2KX-GP 1D5V_S0 DMN66D0LDW -7-GP 1D5V_S0 2 DY 2nd = 84.02657.037 PS_S3CNTRL R3624 1KR2J-1-GP QM3004M3-GP C3609 1 84.30043.037 PS_S3CNTRL 5V_S0 8 7 6 5 2 2 D D D D 1 2 3 4 U3605 S S S G D D D D 8 7 6 5 Total= 11.39A G 1 2 1 PM_SLP_S3# C3616 1 C3615 SCD01U50V2KX-1GP 3D3V_S5 U3607 1 S 2 S 3 S D A 83.9R103.D3F 2ND = 83.9R103.F3F 2 8,19,27,46,47,92 1 SCD1U25V2KX-GP 2nd = 84.02657.037 RUN_PW R_ON_G Q3603 C 2 D3602 MMPZ5239BPT-GP 2 R3618 470R2J-2-GP C3614 SCD1U10V2KX-5GP DY 84.30043.037 K 2 C3613 SCD1U10V2KX-5GP B DY SCD1U25V2KX-GP TPCA8062-H-GP PS_S3CNTRL C3610 1 84.08062.037 2ND = 84.00460.037 S 1 QM3004M3-GP C3608 1 R3622 C 6 G SCD1U25V2KX-GP RUN_ENABLE 5V_S5 5V_S0 8 7 6 5 1 2 D D D D 2 U3604 1 S 2 S 3 S 1 2 C3607 1 R3619 330KR2J-L1-GP 3D3V_AUX_S5 5V_S5 5V_S0 DCBATOUT 2 ANNIE Run Power Run power follow TOP-1 2 DY SCD1U25V2KX-GP -1 0103 check Power list E H_THRMTRIP# 5,22 H_PW RGD_R MMBT2222ALT1G-GP Q3601 2 R3616 PLT_RST# 1 4K7R2J-2-GP 2 84.02222.X11 2ND = 84.02222.V11 1 5,21,27,31,32,65,71,82,83,103 C 1 B C3602 SCD1U10V2KX-5GP 2 R3632 2K2R2J-2-GP 83.R0304.D8F 2ND = 83.R2004.B8F A D3601 A 3V_5V_EN R3602 200KR2J-L1-GP R3603 CH751H-40-1-GP 2 1 2KR2F-3-GP <Core Design> PURE_HW _SHUTDOW N# Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. S5_ENABLE 27 DY Title Size A3 Date: 5 4 A 27,28,86 2 1 41 3RD = 83.R3004.A8F K 3 2 Power Plane Enable Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 36 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number ADAPTER Rev 1 Colossus Monday, December 26, 2011 Sheet 1 37 of 103 5 4 3 2 1 Adaptor in to generate DCBATOUT AD+ AD_JK DC_PIN1 3 5 7 9 LIMIT_SIGNAL AD_JK ACES-CONN10D-4-GP 27 20.81633.010 1Pin=3A 2nd = 20.81772.010 C 83.0SM24.A11 2ND = 83.0024V.0A1 AD_OFF 2 PWR_ADJK_EN 40 E R2 AD_JK PR3808 100KR2J-1-GP DY DY 84.00124.K1K C R1 DY C DY PDTA124EU-1-GP PQ3801 B B AD+ 1 PG3801 2 PDTC124EU-1-GP 1 GAP-CLOSE-PWR PG3802 2 2ND = 84.00024.01K 84.00124.H1K 2ND = 84.05124.011 1 GAP-CLOSE-PWR PG3803 2 1 GAP-CLOSE-PWR PG3804 2 1 GAP-CLOSE-PWR PG3805 2 1 GAP-CLOSE-PWR PG3806 2 1 GAP-CLOSE-PWR PG3807 2 DY -1 1222 PR3802 to save 100mW when battery full. DC_PIN2 PQ3803_C 1 PR3802 510R2J-1-GP PL3801 1 DY 2 MLVS0402M04-GP 2 PU3801 27 DC_BATFULL 4 3 5 2 6 1 5V_AUX_S5 ADD TEST PAD CHARGE_LED 27 1 PR3811 510R2J-1-GP PL3802 1 DY 2 MLVS0402M04-GP 2nd = 84.2N702.E3F 2 DC_PIN2 DC_PIN1 2 1 200KR2F-L-GP PR3809 -1 1222 PR3802 to save 100mW when battery full. AFTP33 AFTE14P-GP AFTP34 AFTE14P-GP 1 1 1 1 1 AFTP20 AFTE14P-GP AFTP23 AFTE14P-GP AFTP24 AFTE14P-GP 1 1 1 AFTP25 AFTE14P-GP AFTP26 AFTE14P-GP AFTP50 AFTE14P-GP 5V_AUX_S5 <Core Design> PQ3804 G PR3803 D S 1 E CHARGE_LED 2 B 10KR2J-3-GP 2N7002K-2-GP 84.2N702.J31 2nd = 84.2N702.W31 PQ3803_C C 1 2 2 1 34K8R2F-1-GP PR3810 SCD1U50V3KX-GP A B AD_JK AC Present = White Standby = White pulsing Charging = Amber *LED’s are off if no AC jack pluged in AD_DETECT 27 PC3809 C GAP-CLOSE-PWR AFTP32 AFTE14P-GP 1 LIMIT_SIGNAL DC_PIN1 AD_JK DY 84.DM601.03F DMN601DWK-7-GP B 1 1 2 1 PWR_ADJK_EN 83.P6SMB.KAG 2ND = 83.P6SBM.DAG 2 PC3805 SC1KP50V2KX-1GP EC3801 1 4 6 8 10 1 1 2 2 R1 DC_PIN2 E 2ND = 84.06675.030 SCD1U25V2KX-GP PQ3802 84.07121.037 PC3806 1 2 K 1 A DY DCIN1 D DY PR3807 200KR2F-L-GP 3 PWR_AD+_2 PC3807 SCD1U50V3KX-GP SCD1U50V3KX-GP PD3803 P6SMB27A-1-GP 2 2 PD3802 PC3808 SM24DTCT-GP-U SC1KP50V2KX-1GP R2 1 D 1 2 3 4 PU3802 SI7121DN-T1-GE3-GP S D 8 S D 7 S D 6 G D 5 2 LIMIT_SIGNAL MMBT3906-4-GP PQ3803 84.T3906.A11 2nd = 84.C3906.A11 3rd = 84.03906.R11 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Document Number DCIN JACK Rev 1 Colossus Date: Wednesday, January 04, 2012 Sheet 38 of 103 A 5 4 3 2 1 BATT Connector D D BT+ BATT EMI close to conn. EC3901 1 2 SCD1U50V3KX-GP DY PD3911 P4SSMJ27APT-GP Battry conn direction DY A 2 PC3902 SC2200P50V2KX-2GP 1 K BT+ AFTE14P-GP AFTP89 BT+ 4 3 2 1 BAT_IN# 1 27,40 BAT_SDA 27,40 BAT_SCL 5 6 7 8 BAT_SDA0 BAT_SCL0 PN3901 PC3905 DY SCD1U50V3ZY-1-GP C BAT_TH# BAT_SCL0 BAT_SDA0 BAT_TH# A 1 2 3 4 5 6 7 8 10 EC3904 DY DY 2 2 SYN-CON8-23-GP DY SC220P50V2KX-3GP 3rd = 83.5R603.Q3F EC3903 SC220P50V2KX-3GP 83.5R603.D3F 2ND = 83.5R603.K3F SC220P50V2KX-3GP PD3901 MMPZ5232BPT-GP-U EC3902 1 1 K 2 BT+ 2 27 BAT1 9 1 SRN33J-7-GP C 1 20.81713.008 2nd = 20.81717.008 3rd = 20.81761.008 -1 1226 Close to Batt Connector 3D3V_AUX_KBC 3D3V_AUX_KBC D3902 B D3901 2 BAT_TH# B 1 6 2 5 BAT_SCL0 3 1 BAV99PT-GP-U BAT_SDA0 83.00099.K11 3 4 BAV99S-GP 2ND = 83.00099.M11 83.00099.AAE 2ND = 83.BAV99.AAE 3RD = 83.00099.T11 ADD TEST PAD BT+ BAT_TH# BAT_SCL0 BAT_SDA0 A 1 1 1 1 1 1 AFTP8 AFTP7 AFTP2 AFTP3 AFTP4 AFTP5 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number BATT CONN Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 39 of 103 5 4 3 2 1 AD+_IN_P AD+_IN_G D PQ4009 2N7002A-7-GP 84.2N702.E31 2ND = 84.07002.I31 G 4 1 2 1 2 2 PC4005 SCD1U25V2KX-GP PR4008 4K02R2F-GP 1 1 1 1 2 2 1 2 5 6 7 8 3 2 1 84.30043.037 2 1 PC4020 1 2 DY 1 1 PC4015 DY PC4014 PC4016 2 PG4004 2 PG4003 2 2 1 PC4017 PR4021 74.24738.073 SCD1U25V2KX-GP 0R0402-PAD-1-GP PR4024 0R0402-PAD-1-GP 2 1 BQ24738_AGND PR4025 2 PR4035 100KR2J-1-GP 2 3 2 1 K 4 BQ24738RGRR-GP 1 2 A 2 SRN GND 1 2 1 PWR_CHG_BAT_SRN 12 2 D01R3721F-GP-U SC10U25V5KX-GP IOUT PWR_CHG_BAT_SRP 13 SRP ACPRES PWR_CHG_BAT_PHASE_R 1 SC10U25V5KX-GP 1 14 GND SCL PR4002 2 IND-3D3UH-57GP 68.3R310.20A 2ND = 68.3R31C.10P PU4003 SC10U25V5KX-GP R2 PR4016 SDA 1 GAP-CLOSE-PWR PR4029 121KR2F-L-GP PR4020 10KR2F-2-GP PWR_CHG_BAT_SRP_R 0R0402-PAD-1-GP PWR_CHG_BAT_SRN_R 1 STOP_CHG# to KBC GPIO24 5V_AUX_S5 2 S 5 6 7 8 PC4027 1 2 PU4007 LM393DR-GP -1 12/20 Power request short pad PC4022 SCD1U25V2KX-GP B BQ24738_AGND 2IN+ 2IN2OUT VCC SC100P50V2JN-3GP PC4021 SCD1U25V2KX-GP PC4018 SC100P50V2JN-3GP DY 1 1 G STOP_CHG# 27 2 2 PR4012 1 0R0402-PAD-1-GP 1 23K7R2F-GP BQ24738_AGND 2 2 PQ4003 2N7002-7F-GP 3D3V_AUX_S5 LODRV S S S R1 90W_R1 BQ24738_AGND PL4001 ILIM G PWR_CHG_BAT_REGN PR4019 10KR2F-2-GP SC100P50V2JN-3GP 2 PR4022 1 PWR_CHG_BAT_IOUT 7 0R0402-PAD-1-GP PC4019 PWR_CHG_BAT_REGN PWR_CHG_BAT_LODRV C BT+ GAP-CLOSE-PWR AD_IA PWR_CHG_BAT_PHASE 15 2 QM3004M3-GP 27 3D3V_AUX_S5 19 1 SCD047U25V3KX-3-GP 21 1 2 BAT_SCL 18 PWR_CHG_BAT_HIDRV SC10U25V5KX-GP 27,39 PWR_CHG_BAT_BTST D D D D SCD01U50V2KX-1GP PG4002 PWR_CHG_BAT_SDA 8 2 1 GAP-CLOSE-PWR-3-GP PWR_CHG_BAT_SCL 9 2 1 GAP-CLOSE-PWR-3-GP PWR_CHG_BAT_ACOK 5 PG4001 27,39 BAT_SDA B HIDRV 17 3.3uH, 10*10*4 Rdc: TYP=10.8mohm MAX=11.8mohm Idc=10A, Isat=16A PC4012 ACDET PHASE BQ24738_AGNDBQ24738_AGND 2 10 PWR_CHG_BAT_REGN 1 6 PWR_CHG_BAT_ILIM PWR_CHG_BAT_BATDRV 16 2 2 PWR_CHG_BAT_ACDET BTST ACDRV 11 1 4 REGN CMSRC 84.30043.037 2 PWR_CHG_BAT_ACDRV BATDRV ACP 5 6 7 8 3 PC4013 PR4018 59KR2F-GP 1 1 1 2 2 2 PWR_CHG_BAT_CMSRC PC4011 SC1U25V3KX-1-GP PWR_CHG_BAT_VCC 2 1 2 1 PWR_CHG_BAT_ACP 4 83.1R504.A8F 2ND = 83.1R004.H8F PC4009 SC10U25V5KX-GP PR4015 100KR2F-L1-GP 2 20 VCC S S S 1 PR4014 4K02R2F-GP AD+_IN_G ACN PC4008 PU4002 PD4005 SD103AWS-1-GP BQ24738_AGND PU4001 PWR_CHG_BAT_ACN 1 BQ24738_AGND 1 QM3004M3-GP SCD1U25V2KX-GP PC4007 2 SC1U16V3KX-5GP G SC1U16V3KX-5GP BQ24738_AGND BQ24738_AGND D D D D DY PC4003 1 2 SC10U25V5KX-GP PC4006 PC4004 3D3V_AUX_S5 D DCBATOUT PR4003 PR4017 20R5F-1GP 20R5F-1GP SCD1U25V2KX-GP PR4011 4K02R2F-GP -1 1220 27 PWR_CHG_ACOK# PC4023 PWR_CHG_BAT_BATDRV_R 1 DY PR4010 68KR2F-GP C 1 G PR4006 GAP-CLOSE-PWR 2 2 1 0R0402-PAD-1-GP 1 2 3 1 PR4005 GAP-CLOSE-PWR PR4007 1 DY 2 100KR2J-1-GP 1 38 PWR_ADJK_EN S S S 2 +VBAT_DEBUG D D D D 1 1 DY 2 PR4033 8 7 6 5 2 2 2 PC4001 D01R3721F-GP-U 1 DY SC2200P50V2KX-2GP PC4002 1 2 1 2 2 1 PR4004 AD+ PR4009 430KR2F-GP PC4010 SC2D2U25V5KX-1GP 8 7 6 5 G 1 2 4 1 D D D D D QM3004M3-GP PU4005 SCD01U50V2KX-1GP SC2200P50V2KX-2GP PR4013 2D2R5J-1-GP 1 S 2 S 3 S AD+_IN_P BT+ 84.30043.037 2ND = 84.02657.037 DCBATOUT PR4001 SCD1U25V2KX-GP PC4025 1 2 SCD1U25V2KX-GP PC4024 G AD+_IN 2ND = 84.02657.037 2 QM3004M3-GP PU4004 1 2 3 2 S S S 1 D D D D 4 1 2 3D3MR2J-GP 8 7 6 5 1 1 2 1MR2F-GP 84.30043.037 QM3004M3-GP PU4006 S PR4030 510KR2F-GP PR4031 1 84.30043.037 2ND = 84.02657.037 2 AD+ D 84.27002.N31 2ND = 84.2N702.X31 BQ24738_AGND 4 3 2 1 GND 1IN+ 1IN1OUT BQ24738_AGND 1129_PU4007 Phase in 1st 74.00393.H21 BQ24738_AGND 74.00393.H21 2ND = 74.10393.A21 3RD = 74.00393.S21 3D3V_AUX_S5 1 PWR_CHG_BAT_ILIM HP AIRLINE COMBO PD4004 3D3V_AUX_KBC 2 2 SCD1U50V3KX-GP A 3 CHG_ON# 27 1 2 PR4026 15K4R2F-GP AIRLINE_VOLT PR4027 100KR2F-L1-GP 27 AD<=17V, disable charger function DY 1 BAV99W-1-GP <Core Design> 2 S G 1 PC4026 1 PQ4007 2N7002A-7-GP 2 D PR4032 100KR2J-1-GP A Wistron Corporation AD+ 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 84.2N702.E31 2ND = 84.07002.I31 Title Size A2 Date: 5 4 3 2 Document Number Charger_BQ24738 Sheet 1 Rev 1 Colossus Thursday, January 05, 2012 40 of 103 5 4 2 1 3D3V_S5 DCBATOUT PG4119 2 1 GAP-CLOSE-PW R PG4120 2 1 GAP-CLOSE-PW R PG4121 2 2 1 DCBATOUT_5V PD4104 PDZ27B-3-GP 83.27R03.E3F 2nd = 83.27R03.C3F Acoustic 1125 PW R_5V_ENTIP D GAP-CLOSE-PW R PG4105 1 2 1 1 PC4120 PC4122 PC4123 1 GAP-CLOSE-PW R 2 2 2 2 RT8223M for 3V5V 2 1 PC4107 SC18P50V2JN-1-GP DY DCBATOUT_5V -1 1220 RT8223_PW R 1 2 PW R_5V3V_TON LGATE1 19 PW R_5V_LG 7 VOUT2 VOUT1 24 PW R_5V_VO 2 PW R_5V_FB FB1 2 ENTRIP2 A 25 ENC 18 PR4107 0R2J-2-GP 2 2ND = 77.92271.03L 77.C3371.15L 77.C3371.15L 2ND = 77.23371.11L 2ND = 77.23371.11L 1 PR4110 31K6R2F-GP 2 2 17 1 PG4129 1 2 PR4113 20KR2F-L-GP GAP-CLOSE-PW R-3-GP PR4121 1 2 3V_5V_EN 36 0R0402-PAD-1-GP Vout=2*(1+R1/R2) SKIPSEL GND VREF VREG3 DEM PWM Ultrasonic Ultrasonic 200k/CH1 250k/CH2 300k/CH1 375k/CH2 400k/CH1 500k/CH2 400k/CH1 500k/CH2 VREG5 <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. PR4119 2 1 0R2J-2-GP TONSEL Title Size A3 Date: 4 B PC4118 2 PC4117 77.52271.09L PT4103 2 GAP-CLOSE-PW R-3-GP PT4102 51125_FB1_R PC4115 SC18P50V2JN-1-GPDY 5V_AUX_S5 5V_AUX_S5_51123 2 1 PG4128 DY 1 2 VREG5 PW R_5V3V_ENC PT4101 PG4127 1 1 0R2J-2-GP 2 PR4118 1 0R0402-PAD-1-GP DY 15 GND RSMRST# 19 RT8223MZQW -GP-U 8 1 0R2J-2-GP PR4117 2 PGND SKIPSEL SC10U6D3V5KX-1GP DY 2VREF PW R_5V_ENTIP TONSEL 2 0R2J-2-GP PR4116 2 PW R_5V_PGD 1 SC22U6D3V5MX-2GP DY 23 REF PR4115 1 2ND = 68.R8810.10G PR4111 1 2 0R0402-PAD-1-GP PGOOD 3D3V_AUX_S5_5_51123 DY 68.R8810.201 Iomax=20A OCP>30A 45WUP_35WDY IND-D88UH-GP ENTRIP1 EN 1 2 2 PR4114 2 1 0R0402-PAD-1-GP 3D3V_AUX_S5 5 5V_S5 PL4102 1 2 FB2 VREG3 PW R_5V3V_SKIP 14 1 3D3V_AUX_S5 2 1 PHASE1 LGATE2 2PW R_5V_BOOT1_R 1 1R3J-L1-GP 1 PW R_5V_PH PHASE2 4 3D3V_AUX_S5 2VREF Close to VFB Pin (pin5) PW R_5V_HG FDMS3600-02-RJK0215-COLAY-GP 84.03664.037 1 1 1 2 51125_FB2_R DY PC4116 SC18P50V2JN-1-GP 2 1 1 84.07692.A37 FDMC7692 Rdson=9.5~11.5mohm, Idc=10.6A, Qg=10~20nc 1 PR4112 10KR2F-2-GP PW R_5V_BOOT1 21 2 8 7 6 5 D D D D G 1 2 1 S 2 S 3 S 1 2 2 PR4109 0R2J-2-GP 22 UGATE1 12 RT8223_PW R PC4114 DY BOOT1 UGATE2 20 PW R_3V_FB 5 1 PR4105 2 249KR2F-GP 1 2PW R_5V3V_EN13 PR4106 100KR2F-L1-GP PW R_3V_ENTIP6 2VREF 2VREF 3 G C ST330U6D3VDM-29-GP PR4108 6K8R2F-2-GP 4 BOOT2 FDMS3600-02-RJK0215-COLAY-GP 84.03664.037 SE220U6D3VM-30-GP S PW R_3V_VO 84.08065.B37 SCD22U10V2KX-1GP B PW R_3V_LG PC4113 SCD1U25V3KX-GP PR4104 11 PU4105 TPCC8065-H-GP -1 1226 7 6 5 8 GAP-CLOSE-PWR-3-GP -1 0102 with power check PW R_3V_PH PG4126 GAP-CLOSE-PWR-3-GP 77.C2271.00L 2ND = 77.22271.27L 2ND = 68.2R21A.20I 9 7 6 5 ST330U6D3VDM-29-GP PC4119 ST220U6D3VDM-15GP 9 2 PC4112 PR4103 SCD1U25V3KX-GP 2 1PW R_3V_BOOT_R1 2PW R_3V_BOOT9 4D7R3J-L1-GP PW R_3V_HG 10 2 3 4 10 1 2 VIN PU4103 PL4101 1 2 IND-2D2UH-46-GP-U D 45WUP_35WDY_65BOM 8 3V_PW R 68.2R210.20B 1 G S Iomax=5A OCP>9A PC4109 SCD1U25V3KX-GP 16 G 4 PU4104 2 3 4 10 1 8 7 6 5 84.08067.A37 1 S 2 S 3 S C PU4101 TPCC8067-H-GP D D D D SC10U25V5KX-GP 2 1 PU4102 D PC4125 ST15U25VM-1-GP 77.C1561.02L DCBATOUT PC4108 GAP-CLOSE-PW R PG4106 1 2 45WUP_35WDY 1 DY PR4102 51KR2F-L-GP GAP-CLOSE-PW R GAP-CLOSE-PW R PG4104 1 2 PR4101 86K6R2F-GP 2 K 77.C1561.02L PC4106 SC18P50V2JN-1-GP DY 1 GAP-CLOSE-PW R PG4125 2 1SS355GP-GP 83.00355.F1F 2ND = 83.00355.D1F GAP-CLOSE-PW R PG4103 1 2 PC4126 ST15U25VM-1-GP SC10U25V5KX-GP 1 K PR4123 1 2 0R0603-PAD SC10U25V5KX-GP GAP-CLOSE-PW R PG4124 2 DY PC4105 SC10U25V5KX-GP 1 DCBATOUT 33R5J-2-GP 83.00355.F1F 2ND = 83.00355.D1F PD4103 GAP-CLOSE-PW R PG4123 2 PW R_3V_ENTIP 1 2 0R0603-PAD A BT+ +VBAT_DEBUG_R 2 2 1SS355GP-GP PR4124 2 K A 1 PR4122 1 DY 1 PD4101 1 RT8223_PW R GAP-CLOSE-PW R PG4122 2 1 PG4102 1 2 +VBAT_DEBUG AD+ A D DCBATOUT_5V DCBATOUT 1 SCD1U25V3KX-GP 2 1 3V_PW R 3 3 2 RT8223M_5V/3D3V Document Number Rev 1 Colossus Thursday, January 05, 2012 Sheet 1 41 of 103 4 3 5 H_PROCHOT# 1D05V_S0 PR4226 54D9R2F-L1-GP 1 2 1 PR4204 887ohm 825ohm 1V 215ohm 191ohm 1 2 1 1 2 1 2 1 1 2 2 2 1 2 2 1 1 1 2 1 PR4265 0V D 45WUP_35W475R 45WUP_35W191R 45WUP_35W0R PWR_VCORE_R_SEL1 2 2 1 2 1 Boot Voltage 402R2F-GP 20KR2F-L-GP 147R2F-GP 475R2F-L1-GP 887R2F-L-GP 2 PR4210 PR4209 PR4208 PR4207 PR4265 45WUP_35W706R PWR_VCORE_R_OSC 0R0402-PAD-1-GP PWR_VCORE_R_SEL0 442R2F-GP SCD1U10V2KX-5GP 2 PR4262 1 100KR2J-1-GP PWR_VCORE_VR_ENABLE 2 GND_1318 45WUP_35W75KR SCD1U10V2KX-5GP 1 PC4237 PR4223 PWR_VCORE_R_SEL4 PWR_VCORE_VR_TT# PWR_VCORE_VR_READY1 PWR_VCORE_VR_READY2 PWR_VCORE_R_SEL6 115R2F-1-GP PC4214 0R0402-PAD-1-GP PR4231 10R2F-L-GP PC4211 SC1U16V2KX-GP 825R2F-GP PR4263 100KR2F-L1-GP PR4201 PWR_VCORE_VIN_UVLO_R PR4205 3D3V_S5 PR4211 1D8V_S0 PR4260 866KR2F-GP PR4204 45WUP_35W21.5R 27,48 D85V_PWRGD 1 7 H_CPU_SVIDCLK D Volterra's suggestion: The total output MLCC is 30x22uF for 3-PHASE VCC The total output MLCC is 20x22uF+4x10uF for 2-PHASE VCCAXG PR4225 130R2F-1-GP 1 2 7 H_CPU_SVIDDAT 5V_S5 1 PR4224 75R2F-2-GP 1 DY 2 7 VR_SVID_ALERT# 2 SSID = CPU.Regulator 2 2 PR4266 1 0R0402-PAD-1-GP 2 PR4253 1 0R0402-PAD-1-GP 28,36 IMVP_PWRGD 2 5 1 13K3R2F-L1-GP VCCSENSE 7 VSSSENSE 13 14 15 16 17 18 19 20 21 22 23 24 2 2 2 44 2 PR4252 1 0R0402-PAD-1-GP 2 PR4254 1 0R0402-PAD-1-GP PWR_AXG_SENSE2_N 1 45WUP_35WDY 2 499R2F-2-GP PR4246 1 2 PR4229 1K96R2F-1-GP 1 1 2 499R2F-2-GP 45WUP_35W1KR DY C 2 1 2 1 2 1 PWR_AXG_SENSE2_P PR4247 1 2 45WUP_35WDY PR4218 PR4212 0R2J-2-GP 0R2J-2-GP 2 1 1 1 1 2 1 2 1 2 1 7 GND_1318 PR4251 1 2 PWR_VCORE_SENSE_P 0R0402-PAD-1-GP GND_1318 SC10P50V2JN-4GP 2 45WDY_35W0R VCC_AXG_SENSE 8 VSS_AXG_SENSE 8 2 1 30K1R2F-L-GP 45WUP_35W220PF 45WUP_35W845R 45WUP_35W1D78K 45WUP_35W20K 74.01318.B73 -1 1228 by power 44 PWR_AXG_IPH2_1_R SC33P50V2JN-3GP PR4235 VCORE_IN1_L0 6K81R2F-1-GP SC330P50V2JC-2-GP PR4264 2VCORE_IN1_R1 2 0R2J-2-GP PC4238 1 2 45WUP_35W56PF 45WUP_35W15.8K SC10P50V2JN-4GP 2 523R2F-GP PR4236 1 1 1 DY DY PR4237 1 DY DY 45WDY_35W0R 1 PWR_AXG_PWM2_2 44 PWR_AXG_PWM2_1 44 PWR_AXG_TS_FAULT#2 44 25K5R2F-GP SC22P50V2JN-4GP 2 DY VT1318MFQX-2-GP PR4215 14K3R2F-GP PR4258 0R2J-2-GP PWR_AXG_A_ERR2 PWR_AXG_A2_IN2 PWR_AXG_A2_OUT2 PWR_AXG_A3_IN2 PWR_AXG_A3_OUT2 PWR_VCORE_A3_OUT1 PWR_VCORE_A3_IN1 PWR_VCORE_A2_OUT1 PWR_VCORE_A2_IN1 PWR_VCORE_A_ERR1 2 PR4234 1VCORE_IN1_R0 DY PR4261 PR4219 0R2J-2-GP0R2J-2-GP PC4236 1 PC4232 DY 2 DY PC4230 SC10P50V2JN-4GP 2 SC10P50V2JN-4GP SC10P50V2JN-4GP PC4231 SC22P50V2JN-4GP PC4228 36 35 34 33 32 31 30 29 28 27 26 25 DY C R_SEL2 R_SEL3 R_REF IPH2_2 R_SEL5 PWM2_2 PWM2_1 TS_FAULT#2 IPH2_1 MRAMP2 SENSE2+ SENSE2- 45WUP_35W15.4KR PR4216 1K96R2F-1-GP PC4229 2 2 21K96R2F-1-GP 2 VDD3 VDD VDD VIN_UVLO PWM1_3 PWM1_2 PWM1_1 TS_FAULT#1 IPH1_3 IPH1_2 IPH1_1 MRAMP1 PC4202 1 PR4217 1 1 1 2 3 4 5 6 7 8 9 10 11 12 PC4201 PR4241 499R2F-2-GP 45WUP_35WDY 1 2 PR4232 1 2 PR4256 1 2499R2F-2-GP 499R2F-2-GP PWR_VCORE__PWM3 PWR_VCORE__PWM2 PWR_VCORE__PWM1 PWR_VCORE__TP_FAULT#1 PWR_AXG_IPH2_2_R PR4230 1K96R2F-1-GP PR4257 PWR_VCORE_VIN_UVLO PWR_VCORE__PWM3 PWR_VCORE__PWM2 PWR_VCORE__PWM1 PWR_VCORE__TP_FAULT#1 PWR_VCORE_IPH1_3 PWR_VCORE_IPH1_2 PWR_VCORE_IPH1_1 PWR_VCORE_MRAMP1 45WUP_35WDY PWR_VCORE_R_SEL2 PWR_VCORE_R_SEL3 PWR_VCORE_R_REF PWR_AXG_IPH2_2 PWR_VCORE_R_SEL5 PWR_AXG_PWM2_2 PWR_AXG_PWM2_1 PWR_AXG_TS_FAULT#2 PWR_AXG_IPH2_1 PWR_AXG_MRAMP2 2 PWR_VCORE_VDD3 SENSE1+ SENSE1A_ERR1 A2_IN1 A2_OUT1 A3_IN1 A3_OUT1 A3_OUT2 A3_IN2 A2_OUT2 A2_IN2 A_ERR2 43 PWR_VCORE_IPH1_1_L PR4220 1K96R2F-1-GP 48 47 46 45 44 43 42 41 40 39 38 37 GND 1D8V_S0 43 43 43 43 R_SEL6 VR_READY2 VR_READY1 VR_TT# R_SEL4 ALERT# VDIO VCLK VR_ENABLE R_OSC R_SEL0 R_SEL1 PU4201 43 PWR_VCORE_IPH1_2_L 49 GND_1318 43 PWR_VCORE_IPH1_3_L PR4250 1 2 PWR_VCORE_SENSE_N 0R0402-PAD-1-GP 1 PR4233 10KR2F-2-GP PC4235 SC22P50V2JN-4GP 1 B SC22P50V2JN-4GP 1 2 PC4234 PR4255 1 PC4233 2 PC4218 2 1 AXG_IN2_L1 2 PR4244 1 DY 48D7KR2F-GP SC56P50V2JN-2GP 45WUP_35W30.1K 45WUP_35W1KpF 2 AXG_IN2_R0 6K81R2F-1-GP 1 B PR4249 PR4238 1 PC4213 2 VCORE_IPH1_R0 1K02R2F-1-GP 45WUP_35W1.3K 1 2 PG4201 GAP-CLOSE-PWR 1 1 PR4245 2 2 10KR2F-2-GP PR4239 2AXG_IN2_R1 1 10K7R2F-GP SCD01U16V2KX-3GP 45WUP_35W7.87K 45WUP_35W4.7nF PC4219 GND_1318 1 2 DY2 SC22P50V2JN-4GP 1 PR4240 2 1 698R2F-GP 45WUP_35W0R 2 953R2F-GP 45WUP_35W665R PR4243 AXG_IPH2_R0 1 SC2200P50V2KX-2GP 45WUP_35W10nF 2 1K27R2F-L-GP 45WUP_35W3.24KR 3D3V_S0 VCC_CORE PR4222 SRN10KJ-5-GP 2 3 1 4 2 PWR_VCORE_MRAMP1 44K2R2F-1-GP 1 45WUP_35W60.4K VCC_GFXCORE PWR_VCORE_VR_READY1 PWR_VCORE_VR_READY2 RN4201 PR4227 2 56KR2F-GP 1 PWR_AXG_MRAMP2 45WDY_35W56.2K A A 1D05V_S0 <Core Design> PR4206 PWR_VCORE_VR_TT# 2 DY Wistron Corporation 1 62R2J-GP 2 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. PC4203 SC47P50V2JN-3GP Title VT1318_CPUCORE(1/3) DY Size A2 Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 42 of 103 5 4 3 2 1 5V_S5 5V_S5 42 PWR_VCORE__TP_FAULT#1 TS_FAULT# PR4301 B2 42 PWR_VCORE__PWM1 B3 ISENSE PWM PC4303 2 2 A2 1 2 PC4327 SC1U10V2KX-1GP 2 1 PC4326 SC1U10V2KX-1GP 2 1 PC4322 SC10U6D3V3MX-GP 2 1 PC4321 SC10U6D3V3MX-GP 2 1 C4 45WUP_35WDY 45WUP_35WDY 45WUP_35WDY 45WUP_35WDY 45WUP_35WDY PWR_CORE_BT3 45WUP_35WDY 1 PWR_CORE_VX1 PWR_VCORE_PU4303_VDD 1D8V_S0 B2 42 PWR_VCORE__PWM3 B3 ISENSE PWM VX#H4 VX#H3 VX#H2 VX#H1 VX#F4 VX#F3 VX#F2 VX#F1 VX#D4 VX#D3 VX#D2 VX#D1 H4 H3 H2 H1 F4 F3 F2 F1 D4 D3 D2 D1 PC4329 SCD22U10V3KX-2GP 45WUP_35WDY PWR_CORE_VX3 PC4324 2 10R2F-L-GP E1 E2 E3 E4 G1 G2 G3 G4 J1 J2 J3 J4 VT1323SFCX-1-GP 42 PWR_VCORE_IPH1_3_L VDD 74.01323.A7Z PR4304 1 VCC B1 45WUP_35WDY GND SCD1U25V2KX-GP 45WUP_35WDY B4 2 A4 PC4328 SC4D7U10V3KX-GP 74.01323.A7Z 1 10R2F-L-GP PC4301 SCD22U10V3KX-2GP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 42 PWR_VCORE_IPH1_1_L D PC4325 SCD1U10V2KX-5GP 1 2 A2 GND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1D8V_S0 H4 H3 H2 H1 F4 F3 F2 F1 D4 D3 D2 D1 1 VX#H4 VX#H3 VX#H2 VX#H1 VX#F4 VX#F3 VX#F2 VX#F1 VX#D4 VX#D3 VX#D2 VX#D1 VDD 2 VCC B1 BST SCD1U25V2KX-GP 45WUP_35WDY VT1323SFCX-1-GP E1 E2 E3 E4 G1 G2 G3 G4 J1 J2 J3 J4 PWR_VCORE_PU4301_VDD C3 PU4303 A1 C2 C1 PR4307 0R0402-PAD-1-GP TS_FAULT#_DR3 1 2 VDDH PWR_CORE_BT1 B4 VDDH BST 2 PC4302 SC4D7U10V3KX-GP 2 1 A4 VDDH 1D8V_S0 PC4323 SC10U6D3V3MX-GP 2 1 PC4330 SC10U6D3V3MX-GP 2 1 1 2 PC4309 SC1U10V2KX-1GP 2 1 PC4308 SC1U10V2KX-1GP 2 1 PC4307 SC10U6D3V3MX-GP 2 1 PC4306 SC10U6D3V3MX-GP 2 1 C4 C3 C2 PC4310 SCD1U10V2KX-5GP 1 TS_FAULT# Small caps close to slave for placement VDDH A1 VDDH TS_FAULT#_DR1 VDDH 42 PWR_VCORE__TP_FAULT#1 PU4301 VDDH PR4305 0R0402-PAD-1-GP 1 2 VDDH 1D8V_S0 C1 D PC4305 SC10U6D3V3MX-GP 2 1 PC4304 SC10U6D3V3MX-GP 2 1 Small caps close to slave for placement 45WUP_35WDY 45WUP_35WDY PG4301 PG4303 1 2 1 2 GAP-CLOSE-PWR C C GAP-CLOSE-PWR GND_1323S_1 GND_1323S_3 5V_S5 1 2 PC4319 SC1U10V2KX-1GP 2 1 PC4320 SC1U10V2KX-1GP 2 1 PC4313 SC10U6D3V3MX-GP 2 1 PC4312 SC10U6D3V3MX-GP 2 1 PC4314 SC10U6D3V3MX-GP 2 1 C4 PWR_VCORE_PU4302_VDD 2 1D8V_S0 PR4302 B 1 B1 42 PWR_VCORE_IPH1_2_L B2 42 PWR_VCORE__PWM2 B3 VDD ISENSE PWM PC4317 2 H4 H3 H2 H1 F4 F3 F2 F1 D4 D3 D2 D1 2ND = 68.5001N.10T PC4316 SCD22U10V3KX-2GP 45WUP_35WDY PL4301 68.5001N.10Q PWR_CORE_VX2 5 6 3 4 1 PR4303 100R2F-L1-GP-U 2 IND-50NH-21-GP PL4301 and PL4302 Colay B 74.01323.A7Z 1 2 A2 35WUP_45WDY GND SCD1U25V2KX-GP 10R2F-L-GP VX#H4 VX#H3 VX#H2 VX#H1 VX#F4 VX#F3 VX#F2 VX#F1 VX#D4 VX#D3 VX#D2 VX#D1 2 VCC IND-50NH-16-GP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 A4 PC4315 SC4D7U10V3KX-GP 1 BST PWR_CORE_BT2 B4 2 C3 C2 Iomax=94A Itdc=56A 1 TS_FAULT# DY-35W PC4318 SCD1U10V2KX-5GP VCC_CORE VDDH A1 VDDH 42 PWR_VCORE__TP_FAULT#1 PU4302 TS_FAULT#_DR2 VDDH PR4306 0R0402-PAD-1-GP 1 2 VDDH 1D8V_S0 C1 PC4311 SC10U6D3V3MX-GP 2 1 Small caps close to slave for placement 1 2 E1 E2 E3 E4 G1 G2 G3 G4 J1 J2 J3 J4 VT1323SFCX-1-GP 3 PG4302 1 4 PL4302 2 GAP-CLOSE-PWR 68.5001N.10M GND_1323S_2 DY-45W 2nd = 68.5001N.10U CPU35W DY=BLUE CPU45W DY=RED A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title VT1323_CPUCORE(2/3) Size A2 Date: 5 4 3 2 Document Number Rev 1 Colossus Thursday, January 05, 2012 1 Sheet 43 of 103 5 4 3 2 1 D D 5V_S5 TS_FAULT# 1 2 PC4407 SC1U10V2KX-1GP 2 1 PC4406 SC10U6D3V3MX-GP 2 1 PC4405 SC10U6D3V3MX-GP 2 1 PC4404 SC10U6D3V3MX-GP 2 1 Iomax=46A Itdc=38A C4 C3 C2 PC4408 SCD1U10V2KX-5GP VCC_GFXCORE BST B4 PWR_AXG_BT1 DY-35W PR4402 1D8V_S0 B1 42 PWR_AXG_IPH2_1_R B2 42 PWR_AXG_PWM2_1 B3 VDD ISENSE PWM H4 H3 H2 H1 F4 F3 F2 F1 D4 D3 D2 D1 2 VX#H4 VX#H3 VX#H2 VX#H1 VX#F4 VX#F3 VX#F2 VX#F1 VX#D4 VX#D3 VX#D2 VX#D1 74.01323.A7Z PR4401 1 PWR_AXG_PU4401_VDD VCC PC4409 SCD22U10V3KX-2GP PWR_AVG_VX1 2 1 2 A2 GND SCD1U25V2KX-GP 3 IND-240NH-GP C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 10R2F-L-GP 2 100R2F-L1-GP-U BPW10040 45WUP_35WDY PC4402 C 1 PL4401 4 2 2 1 A4 PC4401 SC4D7U10V3KX-GP 1 1 A1 VDDH TS_FAULT#_DR4 VDDH PU4401 VDDH 42 PWR_AXG_TS_FAULT#2 PR4403 0R0402-PAD-1-GP 1 2 VDDH 1D8V_S0 C1 PC4403 SC10U6D3V3MX-GP 2 1 Small caps close to slave for placement 68.2415N.101 2ND = 68.CTX17.101 E1 E2 E3 E4 G1 G2 G3 G4 J1 J2 J3 J4 VT1323SFCX-1-GP PG4401 1 2 GAP-CLOSE-PWR GND_1323S_4 PL4402 5V_S5 1 2 IND-D1UH-26-GP Small caps close to slave for placement C4 C3 1 2 PC4416 SC1U10V2KX-1GP 2 1 PC4412 SC10U6D3V3MX-GP 2 1 PC4411 SC10U6D3V3MX-GP 2 1 PC4413 SC10U6D3V3MX-GP 2 1 DY-45W SCD1U10V2KX-5GP 45WUP_35WDY 45WUP_35WDY 45WUP_35WDY 45WUP_35WDY 45WUP_35WDY 45WUP_35WDY BST B4 PWR_AXG_BT2 A4 PC4417 SC4D7U10V3KX-GP 2 1 B PWR_AXG_PU4402_VDD B1 45WUP_35WDY 1D8V_S0 PR4404 B2 42 PWR_AXG_PWM2_2 B3 ISENSE PWM PC4414 45WUP_35WDY H4 H3 H2 H1 F4 F3 F2 F1 D4 D3 D2 D1 B PC4418 SCD22U10V3KX-2GP 45WUP_35WDY PWR_AVG_VX2 74.01323.A7Z 1 2 A2 GND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 10R2F-L-GP VX#H4 VX#H3 VX#H2 VX#H1 VX#F4 VX#F3 VX#F2 VX#F1 VX#D4 VX#D3 VX#D2 VX#D1 VDD SCD1U25V2KX-GP VT1323SFCX-1-GP 45WUP_35WDY E1 E2 E3 E4 G1 G2 G3 G4 J1 J2 J3 J4 1 42 PWR_AXG_IPH2_2_R VCC 2 1 TS_FAULT# VDDH A1 VDDH TS_FAULT#_DR5 C2 PU4402 VDDH 42 PWR_AXG_TS_FAULT#2 PR4405 0R0402-PAD-1-GP 1 2 VDDH 1D8V_S0 C1 PC4410 SC10U6D3V3MX-GP 2 1 35WUP_45WDY PC4415 45WUP_35WDY PG4402 1 2 GAP-CLOSE-PWR GND_1323S_5 A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title VT1323_CPUCORE(3/3) Size A2 Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 44 of 103 5 4 3 2 1 Iomax=16A OCP>26A D D 5V_S5 1 1 1 2 SC100P50V2JN-3GP PC4524 1 2 2 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 PWR_VCCP_SW 2 1 3D3V_S0 PW R_1D05V_1V_EN 36 10KR2J-3-GP 2 2 1 1 C PC4529 SC1U6D3V2KX-GP DY 0R2J-2-GP 1 2 16 8 17 SW VIN#17 VIN#16 PR4527 SN1003055RUW R-GP 2 PC4527 PR4521 0R0402-PAD-1-GP 2 2 1 5K6R2F-2-GP SCD01U16V2KX-3GP SC680P50V2KX-2GP 2 2 0R0402-PAD PR4526 0R0402-PAD-1-GP GND_1003055 74.10355.043 1 1 PGND 2 PC4522 1 0D85V_EN 5,48 PR4503 PR4528 PW R_VCCP_VBST VCCP_RUN ON PR4501 1 2 0R0402-PAD-1-GP PW R_VCCP_FET PW R_VCCP_MODE PW R_VCCP_IMON 9 1 PR4523 2KR2F-3-GP PGND 2 PC4528 7 1 2 PW R_VCCP_SS PR4524 PC4511 SC560P50V2KX-2GP 22K1R2F-L-GP SC1800P50V2KX-1GP 2 1 GND_1003055 PC4526 SC22U6D3V5MX-2GP 12 11 10 SC22U6D3V5MX-2GP FSET MODE IMON 4 5 6 SC22U6D3V5MX-2GP VFB VOUT SS PW R_VCCP_VFB SC22U6D3V5MX-2GP 14 13 SC22U6D3V5MX-2GP 15 PGOOD EN SC22U6D3V5MX-2GP VBST GND COMP SC22U6D3V5MX-2GP VCCA 2 PW R_VCCP_COMP 3 SC22U6D3V5MX-2GP 1 SC22U6D3V5MX-2GP PW R_VCCP_VCCA PR4504 2D2R3-1-U-GP 1 2 SC22U6D3V5MX-2GP PC4510 SCD22U10V3KX-2GP SC22U6D3V5MX-2GP 1 0R0402-PAD-1-GP PC4525 SC1U6D3V2KX-GP 68.R4210.20C PC4509 4D7R2J-2-GP SC22U6D3V5MX-2GP SCD01U16V2KX-3GP SCD01U16V2KX-3GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP 2 PC4501 PC4502 PC4503 PC4504 PC4505 PC4506 PC4507 PC4508 PC4518 PC4519 PC4520 PC4521 IND-D42UH-6-GP PR4525 3D3V_S5 2 1 1 1 1 PC4517 2 1 PC4516 2 1 PC4515 2 1 PC4514 2 1 PC4513 2 1 2 PC4512 PU4501 C 1D05V_S0 PL4501 GND_1003055 1 PG4501 2 GAP-CLOSE-PW R 1 1 GND_1003055 GND_1003055 Close to pin4 2 2 PR4529 PR4522 3K09R2F-1-GP20KR2F-L-GP B B VSSP_SENSE 7 VTT_SENSE 7 Differential <Variant Name> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SN1003055RUWR Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 45 of 103 5 4 3 2 1 SSID = PWR.Plane.Regulator_1p5v0p75v D D 5 3D3V_S0 1 1D5V_S3 / 0D75V_S0 R3710 10KR2J-3-GP 0D75V_EN A PR4615 0D75V_EN -1 0102 by Power 1 DCBATOUT 2 PU4602 3D3V_S0 PC4611 C 1 19 3 2 1 VDD PWR_1D5V_UGATE 1 2 Iomax=13A, OCP>20A. 12 S3 PHASE 16 PWR_1D5V_PHASE 15 PWR_1D5V_LGATE 1 2 COIL-D82UH-2-GP VLDOIN LGATE DY 5 6 7 8 PGND PU4603 14 2nd = 68.R6810.10Z TPCC8062-H-GP 2 3 2 1 DY PC4610 SC18P50V2JN-1-GP 1D5V_S3 RT8207MZQW-GP-U PG4608 2 PWR_1D5V_VDDQ 1 GAP-CLOSE-PWR R2 B PR4609 30KR2F-GP PR4607 1 2 DDR_VREF_S3 0R0402-PAD-1-GP PC4608 SCD033U16V2KX-GP Close to output cap pin1, not inside of the output cap Close to PIN6 2 0D75V_S0 1 2 1PWR_1D5V_VTTREF B +0.75VS Iomax: 1.2A 77.23371.13L 2nd = 79.33719.L01 3rd = 77.23371.13L 2 VTTREF GND -1 1220 4 21 PR4608 30K9R2F-GP R1 1 FB VTTSNS 84.08062.A37 4 PWR_1D5V_FB 6 1 VTT GND 2 3 20 S S S Close to pin19 0D75V_S0 PWR_1D5V_VDDQ 5 G VDDQ PT4601 ST330U2D5VDM-9GP VTTGND PC4613 68.R8210.10V D D D D 1 1D5V_S3 PL4601 S5 SC1U16V3KX-5GP PC4603 SC10U6D3V3MX-GP 17 2 GAP-CLOSE-PWR 7 UGATE 1 1D5V_S3 PWR_1D5V_VTTIN 18 SCD1U25V3KX-GP TON 1 PWR_0D75V_EN PG4606 2 8 BOOT PGOOD 2 PWR_1D5V_EN 9 PWR_1D5V_PHASE_L 1 PWR_1D5V_TON 4 PC4609 PR4606 PWR_1D5V_BOOT 1 2 2D2R3-1-U-GP 2 PR4616 1 2 620KR2F-GP VDDP 13 CS 2 10 5,36,47 RUNPWROK DCBATOUT 84.08067.A37 PU4601 74.08207.C73 S S S Close to pin19 G PR4602 100KR2J-1-GP 11 1 TPCC8067-H-GP PC4607 2 1 1 PC4601 SC1U10V2KX-1GP 5V_S5 D D D D PWR_1D5V_CS 1 PR4605 2 0R0603-PAD 2 PWR_1D5V_VDDP 1 1 10K7R2F-GP 2 1 PC4612 SCD1U10V2KX-5GP 2 DY PC4602 SC10U25V5KX-GP C 5V_S5 PC4606 SC1U10V2KX-1GP 2 PWR_1D5V_EN 2 0R0402-PAD-1-GP PWR_0D75V_EN SC10U25V5KX-GP SC1KP50V2KX-1GP PR4610 1 PR4603 1 1 0R0402-PAD-1-GP PR4604 2 1 5D1R2F-GP PWR_1D5V_VCC5 19,27 PM_SLP_S4# 2 C3705 SCD47U25V3KX-1GP R&C delay 1 CH751H-40-1-GP 2 K PM_SLP_S3# 5 6 7 8 D3705 2 8,19,27,36,47,92 2 83.R0304.D8F 2ND = 83.R2004.B8F 3RD = 83.R3004.A8F 2 1 Vout=0.75*(1+R1/R2) PC4604 SC10U6D3V3MX-GP A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RT8207MZ_1D5V & 0D75V Size A2 Date: 5 4 3 2 Document Number Rev 1 Colossus Thursday, January 05, 2012 1 Sheet 46 of 103 5 4 3 2 1 RT8068A for 1D8V_S0 D D 3D3V_S5 PG4702 1 2 4 68.2R21D.10Y 7 2ND = 68.2R21A.201 FB 6 EN PR4703 20KR2F-L-GP PC4705 R1 PGOOD GND 11 RT8068AZQW ID-GP-U PW R_1D8V_FB 2ND = 74.05671.043 1 PR4702 2 0R0402-PAD-1-GP 1 74.08068.A43 2 1 2 PR4704 10KR2F-2-GP PC4706 1 3 2 5 LX#3 NC#7 1 SVIN 1 2 IND-2D2UH-207-GP 2 8 PL4701 PW R_1D8V_PHASE 1 2 2 1 1 2 5,36,46 RUNPW ROK 1 LX#2 PC4707 SC10U6D3V3MX-GP 2 1 PW R_1D8V_SVIN PC4703 SC1U6D3V2KX-GP PW R_1D8V_S0_EN LX#1 PVIN SC10U6D3V3MX-GP 2 PC4702 PVIN 9 SC100P50V2JN-3GP PM_SLP_S3# DY SC10U6D3V3MX-GP 8,19,27,36,46,92 SC10U6D3V3MX-GP C PC4701 10 1 PW R_1D8V_PVDD PR4701 1 2 2D2R2F-GP GAP-CLOSE-PW R-3-GP PG4707 1 2 GAP-CLOSE-PW R-3-GP Iomax=2.2A OCP>3.2A 1D8V_S0 PU4701 2 GAP-CLOSE-PW R-3-GP PG4706 1 2 C R2 Vo=0.6*(1+(R1/R2)) PC4704 SC22P50V2GN-GP DY B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number RT8068A_1D8V Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 47 of 103 5 4 3 2 1 TPS51461 for VCCSA D D 1 3D3V_S0 5V_S5 1 1 2 PR4808 100KR2J-1-GP PC4814 SC1U10V2KX-1GP D85V_PW RGD_C 2 2 PR4806 1R2F-GP 2 PR4812 1 PC4816 SC2D2U10V3KX-1GP 1 0R0402-PAD-1-GP DY L L 0.9V L H 0.8V H L 0.725V H H 0.675V D85V_PW RGD 27,42 2 1KR2F-3-GP 2 PR4804 1 0R0402-PAD-1-GP 2 PR4805 1 0R0402-PAD-1-GP PW R_VCCSA_VID0 VID1 VCCSA_SEL 8 H_FC_C22 2 PR4801 1 0R0402-PAD-1-GP 1 PW R_VCCSA_EN PWR_VCCSA_V5DRV 0D85V_EN 5,45 PC4804 SC1U6D3V2KX-GP 0D85V_PW R PL4801 2 1 1 2 1 2 1 PC4807 GAP-CLOSE-PW R PG4812 1 2 GAP-CLOSE-PW R PG4813 1 2 GAP-CLOSE-PW R PG4814 1 2 1 1 PC4806 SCD01U50V2KX-1GP PC4810 SC22U6D3V5MX-2GP 8 SC22U6D3V5MX-2GP PWR_VCCSA_COMP PWR_VCCSA_VREF VCCUSA_SENSE PW R_VCCSA_SLEW PC4808 SC22U6D3V5MX-2GP 68.R4710.20G 2ND = 68.R4710.20D SC22U6D3V5MX-2GP PR4811 100R2F-L1-GP-U 1 TPS51461RGER-GP PC4809 GAP-CLOSE-PW R PG4815 1 2 PR4802 4K99R2F-L-GP PWR_VCCSA_COMP_1 GAP-CLOSE-PW R PG4817 1 2 GAP-CLOSE-PW R PC4817 SC3300P50V3KX-1GP 1 2 2 1 B GAP-CLOSE-PW R PG4816 1 2 2 B 0D85V_S0 PG4810 2 GAP-CLOSE-PW R PG4811 1 2 COIL-D47UH-9-GP 1 0D85V_S0 74.51461.043 0D85V_PW R 1 2 PW R_VCCSA_SW 2 12 11 10 9 8 7 BST SW#11 SW#10 SW#9 SW#8 SW#7 Design Current =6 A 6.6A<OCP< 7.8A 2 PGND PGND PGND VIN VIN VIN GND SCD1U25V3KX-GP PR4807 PC4805 PW R_VCCSA_BST 1 2 PW R_VCCSA_BST_R 1 2 0R0603-PAD-1-GP 2 1 2 1 2 1 2 PC4815 SC10U10V3MX-GP GAP-CLOSE-PW R-3-GP PC4813 SC10U10V3MX-GP GAP-CLOSE-PW R-3-GP PG4809 1 2 PC4801 SC10U10V3MX-GP GAP-CLOSE-PW R-3-GP PG4802 1 2 PW R_VCCSA_VIN 19 20 21 22 23 24 25 1 2 3 4 5 6 PG4801 1 2 GND VREF COMP SLEW VOUT MODE 5V_S5 C V5DRV V5FILT PGOOD VID1 VID0 EN PU4801 C 18 17 16 15 14 13 2 DY VCCSA 8 2 1 PW R_VCCSA_VID1 VID0 PR4809 PC4802 SCD22U10V2KX-1GP <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 TPS51461_VCCSA Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 48 of 103 3 LVDS1 48 2 SBY100505T-601Y-N-GP DMIC_CLK 29 43 DCBATOUT EC4909 SC22P50V2JN-4GP F4901 44 1 POLYSW -1D1A24V-GP-U C FUSE Main:69.50007.A41 Second:69.50007.A31 69.50007.A31 2nd = 69.50007.A41 45 WEBCAM 46 R4905 2 21 USB_PN10 R4906 2 USB_CAMERA 1 0R0402-PAD 1 0R0402-PAD USB_CAMERA# 47 U4902 G5285T11U-GP Layout 40 mil LCDVDD_EN OUT GND EN EC4902 49 4 IPEX-CONN40-2R-GP-U IN#5 5 20.F1093.040 EC4901 RF 2 EC4903 RF RF 1 R4901 2 1KR2J-1-GP RF BLON_OUT_C 2 EC4905 RF DMIC_DATA_RF2 DMIC_CLK_RF2 1 EC4907 RF RF <Core Design> 2 2 1 2 CAP CLOSED IN LVDS1 A EC4910 SC5D6P50V2CN-1GP 1 C4904 SC5D6P50V2CN-1GP 100KR2J-1-GP R4904 SC100P50V2JN-3GP 1 2 BLON_OUT B EC4906 SC5D6P50V2CN-1GP 2 1 3D3V_S0 SC5D6P50V2CN-1GP EC4904 SC5D6P50V2CN-1GP 27 RF LCDVDD 1 2ND = 20.F1289.040 C4906 2ND = 74.09724.09F 2 74.05285.07F 1 1 C DCBATOUT_LCD TXOUTB_L0- 20 TXOUTB_L0+ 20 TXOUTB_L1- 20 TXOUTB_L1+ 20 TXOUTB_L2- 20 TXOUTB_L2+ 20 TXCLKB_L- 20 TXCLKB_L+ 20 SC5D6P50V2CN-1GP 1 TXOUTA_L0- 20 TXOUTA_L0+ 20 TXOUTA_L1- 20 TXOUTA_L1+ 20 TXOUTA_L2- 20 TXOUTA_L2+ 20 TXCLKA_L- 20 TXCLKA_L+ 20 IN#4 B BKLT_CTL 20 LCD_SMBCLK 20 LCD_SMBDATA 20 SC4D7U6D3V3KX-GP 2 C4903 SC4D7U6D3V3KX-GP 100KR2J-1-GP R4907 DMIC -1 12/20 Delete TR4901 2 20 3 2 1 3D3V_S0 10R0402-PAD DMIC_DATA_C 10R0402-PAD DMIC_CLK_C 2 1KR2J-1-GP SC5D6P50V2CN-1GP LCDVDD DMIC_DATA_RF2 ER4901 2 DMIC_CLK_RF2 ER4902 2 LCD_BRIGHTNESS R4903 1 BLON_OUT_C SC5D6P50V2CN-1GP USB_PP10 21 WEBCAM -1 12/22 1 1 SCD1U50V3KX-GP C4907 USB_CAMERA USB_CAMERA# 2 2 2 LCDVDD 3D3V_S0 1 DCBATOUT_LCD 2 1 1 5V_S0_LOGO_BL D DY C4901 SC1U6D3V2KX-GP SCD1U10V2KX-5GP 1 EL4902 DMIC_CLK_C C4905 C4902 2 LCD_SMBCLK LCD_SMBDATA SC1U6D3V2KX-GP 1 3 4 42 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 51 2 EC4908 SC22P50V2JN-4GP 2 RN9401 SRN2K2J-1-GP DCBATOUT_LCD 50 1 1 DMIC_DATA 29 2 41 2 SBY100505T-601Y-N-GP 1 2 1 1 LVDS CONNECTOR AUO B156HB01 V0 2 DMIC_DATA_C D LVDS Impedance:90 ohm EL4901 3D3V_S0 1 1 D_MIC by EMI 2 1 4 2 5 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 LCD Connector Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 49 of 103 5 4 3 CRT Connector 2 1 CRT DDCDATA & DDCCLK level shift Pull High 5V Design on CRT Board CRT_RED CRT_GREEN CRT_BLUE VSYNC HSYNC 20.20961.015 1 CRT_DDCDATA_CON CRT_DDCCLK_CON 1 2 3 CRT_R CRT_G CRT_B 14 13 CRT_VSYNC_CON CRT_HSYNC_CON C5012 SCD01U16V2KX-3GP RN5002 SRN2K2J-1-GP -1 0102 by ME 1 2 3 4 3 4 5V_CRT_S0 D 2ND = 83.R5003.H8H -1 0102 3D3V_S0 Q5001 20 CRT_DDC_DATA AFTP9 AFTP10 AFTP11 AFTP12 AFTP13 AFTP14 AFTP15 AFTP18 AFTP19 AFTP17 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP 1 6 2 5 3 CRT_DDCDATA_CON CRT_IN#_R 4 2N7002KDW -GP 20 CRT_DDC_CLK 84.2N702.A3F 2nd = 84.2N702.E3F 3RD = 84.2N702.F3F CRT_DDCCLK_CON C 2 0R2J-2-GP CRT_BLUE_RR 1 2 BLM15BB470SN1D-2GP 1 2 C5005 1 1 2 1 C5008 DY C5006 SC8P50V2CN-3GP 2 1 C5004 SC8P50V2CN-3GP 2 CRT_B SC8P50V2CN-3GP 1 2 3 4 C5003 SC8P50V2CN-3GP SC8P50V2CN-3GP SC8P50V2CN-3GP -1 1220 C5002 2 1 8 7 6 5 C5001 68.00084.A71 C5009 DY DY C5010 1 R5007 1 DY 2 20 PCH_BLUE CRT_G 1 1 2 BLM15BB470SN1D-2GP C5011 SC100P50V2JN-3GP CRT_GREEN_RR SC18P50V2JN-1-GP 2 0R2J-2-GP SC18P50V2JN-1-GP R5006 1 SC100P50V2JN-3GP 20 PCH_GREEN L5003 CRT_DDCDATA_CON CRT_HSYNC_CON CRT_VSYNC_CON CRT_DDCCLK_CON 68.00084.A71 2 L5002 RN5004 SRN150F-1-GP CRT_R 1 2 BLM15BB470SN1D-2GP 2 CRT_RED_RR 2 0R2J-2-GP 1 R5005 1 20 PCH_RED 68.00084.A71 1 L5001 2 CRT RGB 2 C 83.R5003.J8F RN5003 SRN10KJ-6-GP 2ND = 20.21019.015 1 1 1 1 1 1 1 1 1 1 D5001 CH551H-30GP-GP 3D3V_S0 ADD TEST PAD CRT_DDCDATA_CON CRT_DDCCLK_CON CRT_R CRT_G CRT_B CRT_VSYNC_CON CRT_HSYNC_CON CRT_IN#_R A 12 15 K GND GND GND GND GND GND GND 5V_HDMI R5004 0R0402-PAD 5V_CRT_S0 8 7 6 5 5 6 7 8 10 16 17 500mA 2 DDCDATA_ID1 DDCCLK_ID3 D 3D3V_S0 9 3D3V_S0_DDC VCC_CRT 2 1 NC#4 NC#11 1 4 11 5V_CRT_S0 D-SUB-15-136-GP 2 CRT1 D5003 B 1 6 2 5 3 4 CRT_VSYNC_CON CRT EMI B CRT_IN#_R 5V_CRT_S0 EC5001 2 EC5002 2 1 SCD1U25V2KX-GP 5V_S0 DY 5V_S0 1 SCD1U25V2KX-GP CRT_HSYNC_CON DY BAV99S-GP 83.00099.AAE CRT Hsync & Vsync level shift 5V_CRT_S0 1 2ND = 83.BAV99.AAE 20 CRT_HSYNC OE# 2 A 3 GND 2 U5001 1 VCC 5 Y 4 74AHCT1G125GW -1-GP 73.1G125.0JH 2ND = 73.1G125.D0G 3RD = 73.07125.0AG A 20 CRT_VSYNC SCD1U10V2KX-5GP 73.1G125.0JH 2ND = 73.1G125.D0G 3RD = 73.07125.0AG C5007 U5002 1 OE# 2 A 3 GND VCC 5 <Core Design> A RN5005 Y HSYNC_5 VSYNC_5 4 74AHCT1G125GW -1-GP 1 2 4 3 CRT_HSYNC_CON CRT_VSYNC_CON Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SRN33J-5-GP-U Title Size A3 Date: 5 4 3 2 Document Number CRT_CONN Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 50 of 103 5 4 3 2 1 HDMI Level Shifter & CONNECTOR HDMI CONN 3 TR5101 FILTER-4P-49-GP AFTP95 AFTE14P-GP 1 AFTP94 AFTE14P-GP HDMI_DATA2_R_C_CON 1 AFTP41 AFTE14P-GP 1 AFTP42 AFTE14P-GP HDMI_DATA1_R_C_CON 1 AFTP37 AFTE14P-GP HDMI_DATA1_R_C#_CON 1 AFTP38 AFTE14P-GP HDMI_DATA0_R_C_CON 1 AFTP43 AFTE14P-GP HDMI_DATA0_R_C#_CON 1 AFTP44 AFTE14P-GP HDMI_CLK_R_C_CON 1 AFTP72 AFTE14P-GP HDMI_CLK_R_C#_CON 1 5V_HDMI HDMI_DATA1_R_C_CON 1 HDMI_DATA1_R_C 3 HDMI_CLK_R_C_CON 1 HDMI_CLK_R_C 1 HDMI_DATA2_R_C#_CON HDMI1 TR5103 FILTER-4P-49-GP 20 HDMI_DATA2_R_C_CON 1 HDMI_DATA1_R_C# HDMI_DATA2_R_C_CON AFTP81 AFTE14P-GP DDC_CLK_HDMI 1 AFTP80 AFTE14P-GP HDMI_DATA0_R_C#_CON HDMI_CLK_R_C_CON DDC_DATA_HDMI 1 AFTP93 AFTE14P-GP HDMI_CLK_R_C#_CON HPD_HDMI_CON 1 AFTP130 AFTE14P-GP 5V_HDMI F5101 2 1 C5102 HDMI_DATA2_R_C#_CON 69.10118.111 20 HDMI_DATA0_R# 20 HDMI_DATA0_R HDMI DISCRETE/ UMA Co-lay C5103 C5104 1 1 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP HDMI_CLK_R_C# HDMI_CLK_R_C C5105 C5106 1 1 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP HDMI_DATA0_R_C# HDMI_DATA0_R_C HDMI_DATA1_R_C# HDMI_DATA1_R_C HDMI_DATA2_R_C# HDMI_DATA2_R_C 2ND = 22.10296.751 C SCD1U10V2KX-5GP SCD1U10V2KX-5GP 66.68136.08L=>680ohm for UMA 66.47136.A8L=>470ohm for GPU 2HDMI_HPD_B 150KR2J-L1-GP R5110 200KR2J-L1-GP 84.03904.L06 DY 2nd = 84.03904.P11 HDMI_HPD_E 1 2 R5128 0R0402-PAD HDMI_PCH_DET 20 R5112 20KR2F-L-GP 5V_S0 8 7 6 5 Close to HDMI Connector RN5107 SRN470J-5-GP D5102 BAW 56-5-GP 83.00056.Q11 1 2 3 4 1 2 3 4 RN5106 SRN470J-5-GP 3 8 7 6 5 Q5102 PMBS3904-1-GP 1 2 2 2 2nd = 69.50007.771 3RD = 69.50007.C21 1 2 2 1 1 69.50007.691 2 20 HDMI_DATA2_R# 20 HDMI_DATA2_R 1 1 C5108 C5109 DDC_CLK_PH1 1 HDMI_PLL_GND DDC_DATA_PH1 2 20 HDMI_DATA1_R# 20 HDMI_DATA1_R SCD1U10V2KX-5GP SCD1U10V2KX-5GP FUSE-1D1A6V-4GP-U 3D3V_S0 1 R5111 C5110 C5107 1 3 20 HDMI_CLK_R# 20 HDMI_CLK_R SKT-HDMI21-4-GP 22.10296.711 Close to GPU C 2 HDMI_DATA2_R_C# HPD_HDMI_CON HDMI_DATA0_R_C#_CON 69.10118.111 SCD1U10V2KX-5GP 21 HDMI_DATA0_R_C# 5V_S0 DDC_CLK_HDMI DDC_DATA_HDMI 4 2 TR5104 FILTER-4P-49-GP 4 2 TR5102 FILTER-4P-49-GP HDMI_DATA1_R_C#_CON HDMI_DATA0_R_C_CON 2 1 HDMI_DATA2_R_C 3 HDMI_DATA0_R_C_CON 1 HDMI_DATA0_R_C HDMI_DATA1_R_C#_CON 69.10118.111 HDMI_DATA2_R_C#_CON HDMI_DATA1_R_C_CON 1 HDMI_CLK_R_C#_CON 69.10118.111 3 HDMI_CLK_R_C# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4 2 4 D 2 D 3RD = 83.00056.K11 B 3D3V_S0 4 3 S G B 2nd = 83.00056.G11 3D3V_S0 Q5106 RN5101 SRN2K2J-1-GP 6 1 D DDC_CLK_HDMI 84.2N702.J31 2ND = 84.2N702.W 31 D2 SRN0J-6-GP DDC_DATA_Q ME2N7002DKW -G-GP 84.2N702.F3F DDC_DATA_HDMI 2ND = 84.2N702.E3F A <Core Design> Routing Guidelines: CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm). The total delay on CTRLDATA should be longer than CTRLCLK. 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Date: 4 3 2 A Wistron Corporation Size A3 5 HDMI_PLL_GND G1 3 4 2 S2 S1 2 1 3 G2 20 PCH_HDMI_CLK 20 PCH_HDMI_DATA 5 D1 RN5117 4 1 2 Q5104 DDC_CLK_Q 2N7002K-2-GP HDMI Level Shifter/Conn Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 51 of 103 5 4 3 2 1 D D (Blanking) C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Display Port Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 52 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 53 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 54 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 55 of 103 5 4 3 2 1 SATA HDD2 Connector SATA HDD1 Connector CHECK HDD conn model pin define_ME wire HDD2 HDD1 1 2 SCD1U10V2KX-5GP SC10U10V5KX-2GP 2 C5606 TP5601 1FFS_INT0 TPAD14-OP-GP NP2 23 FOX-CON20-1-GP-U 20.F1546.020 2nd = 20.F1473.020 3D3V_S0 C SATA_TXP0_C 1 AFTP111 AFTE14P-GP SATA_TXN0_C 1 AFTP110 AFTE14P-GP SATA_RXN0_C 1 AFTP109 AFTE14P-GP SATA_RXP0_C 1 AFTP108 AFTE14P-GP 1 AFTP184 AFTE14P-GP 1 AFTP185 AFTE14P-GP 1 AFTP183 AFTE14P-GP 5V_S0 21 NP1 SATA_TXP2_C SATA_TXN2_C SATA_TXP2_C 1 AFTP107 AFTE14P-GP SATA_TXN2_C 1 AFTP106 AFTE14P-GP SATA_RXN2_C 1 AFTP96 AFTE14P-GP SATA_RXP2_C 1 AFTP97 AFTE14P-GP 1 AFTP104 AFTE14P-GP 1 AFTP103 AFTE14P-GP 1 AFTP182 AFTE14P-GP 3D3V_S0 5V_S0 D 1 5V_S0 SCD1U10V2KX-5GP C5605 C5603 DY SC10U10V5KX-2GP 1 5V_S0 C5602 DY 2 1 2 2 DY SCD1U10V2KX-5GP SC10U6D3V5KX-1GP DY C5601 SCD1U10V2KX-5GP C5604 17 SATA_RXN2 17 SATA_RXP2 3D3V_S0 SC10U6D3V5KX-1GP 1 3D3V_S0 C5618 C5619 2 2 1 C5623 1 C5622 2 3 15DY_17UP SATA_RXN2_C 45 1 2 SCD01U16V2KX-3GP 15DY_17UP SCD01U16V2KX-3GP SATA_RXP2_C 1 2 6 7 15DY_17UP 8 15DY_17UP 9 10 11 12 13 14 15 16 C5621 C5620 17 TP5602 1FFS_INT1 18 19 TPAD14-OP-GP 20 24 1 2 SCD01U16V2KX-3GP SATA_RXN0_C 2 SCD01U16V2KX-3GP SATA_RXP0_C 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 24 1 C5616 C5615 17 SATA_RXN0 17 SATA_RXP0 1 C5614 SATA_TXP0_C 1 C5613 SATA_TXN0_C 2 2 SCD01U16V2KX-3GP SCD01U16V2KX-3GP SATA_TXP2 SATA_TXN2 2 SCD01U16V2KX-3GP SCD01U16V2KX-3GP SATA_TXP0 SATA_TXN0 1 17 17 17 17 2 D 22 1 21 NP1 2 22 1 SATA_RX- and SATA_RX+ Trace Length match within 20 mil 15DY_17UP 15DY_17UP NP2 23 FOX-CON20-1-GP-U 20.F1546.020 2nd = 20.F1473.020 15DY_17UP C ODD Connector 3D3V_S0 SATA Zero Power ODD SATA_ODD_DET# 22 SATA_ODD_DA# 21 2 SCD01U16V2KX-3GP 2 SCD01U16V2KX-3GP SATA_TXN4_C C5611 1 SATA_TXP4_C C5612 1 2 SCD01U16V2KX-3GP 2 SCD01U16V2KX-3GP SATA_RXP4 SATA_RXN4 SATA_TXN4 SATA_TXP4 17 17 C5624 SC10U6D3V5KX-1GP 17 17 B C5617 ODD_PW R_5V 5V_S0 C5609 2 1 22 SATA_ODD_PW R_EN SC10U6D3V5KX-1GP When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON 2nd = 74.02001.079 Current limit Active High typ =>2A 1 ODD_PWRGT# ODD_PW R_5V AFTE14P-GP 1 AFTP186 AFTE14P-GP 4 AFTE14P-GP AFTP102 S1 AFTP101 1 Wistron Corporation D1 SATA_RXP4_C 1 A <Core Design> 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 3 2ND = 84.2N702.E3F 5 84.2N702.F3F AFTE14P-GP 6 AFTE14P-GP AFTP100 G1 AFTP98 SATA_RXN4_C 1 SATA_ODD_DA#_C D2 SATA_TXN4_C 1 G2 Q5601 ME2N7002DKW -G-GP S2 AFTE14P-GP 2 AFTP99 1 SATA_TXP4_C 1 C5610 SC10U6D3V5KX-1GP 74.06288.079 R5603 100KR2J-1-GP SUPPORT ZERO SATA ODD ODD_PW R_5V 8 7 6 5 SY6288CCAC-GP 5V_S0 2nd = 20.F1473.020 A 100 mil GND OUT#8 IN#2 OUT#7 IN#3 OUT#6 EN/EN# OCB 2 FOX-CON20-1-GP-U 20.F1546.020 U5601 1 2 3 4 1 SATA_RXP4_C C5608 1 SATA_RXN4_C C5607 1 DY 2 1 ODD_PW R_5V 2 DY 1 2 1 0R2J-2-GP R5601 2 B SATA_ODD_DET# SATA_ODD_DA#_C R5602 10KR2J-3-GP DY 2 NP2 23 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 24 R5606 10KR2J-3-GP SCD1U10V2KX-5GP 22 1 2 ODD1 21 NP1 1 1 3D3V_S0 Title HDD/ODD SATA_ODD_PW R_EN SATA_ODD_DA# Size A3 Date: Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 56 of 103 5 4 3 2 1 D D C C (Blanking) B B A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ESATA Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 57 of 103 5 4 3 2 Main Speaker Connector 1 SPK1 5 SPK Trace = 40mil SPKR_R+_R 29 SPKR_R+ L5801 1 2 29 29 29 SPKR_RSPKR_L+ SPKR_L- L5802 1 L5803 1 L5804 1 PBY160808T-121Y-GP 2 2 PBY160808T-121Y-GP 2 PBY160808T-121Y-GP PBY160808T-121Y-GP 1 1 SC2200P50V2KX-2GP 1 AFTP114 AFTE14P-GP 6 SPKR_L-_R 1 AFTP112 AFTE14P-GP 1 EC5808 2ND = 20.F1937.004 1 2 1 2 2 EC5807 R5804 3D3R2F-GP 2 2 R5803 3D3R2F-GP EC5806 1 1 2 2 SC2200P50V2KX-2GP 1 1 2 AFTE14P-GP SPKR_L+_R 20.F1621.004 EC5805 2 1 2 2 AFTE14P-GP AFTP113 SC220P50V2KX-3GP 1 AFTP105 1 D SC220P50V2KX-3GP 2 1 SPKR_R-_R ACES-CON4-17-GP-U1 SC220P50V2KX-3GP R5802 3D3R2F-GP SPKR_R+_R 2 3 4 C5804 SC220P50V2KX-3GP R5801 3D3R2F-GP 1 68.00206.021 C5803 SPKR_L-_C SPKR_R-_C SPKR_R+_C Colse to Codec C5802 SPKR_L+_C SC2200P50V2KX-2GP C5801 SC2200P50V2KX-2GP 1 D SPKR_R-_R SPKR_L+_R SPKR_L-_R C C 2ND Speaker Connector GAIN 18dB 5V_S0 DFDY dB_G1 2 dB_G0 1 R5805 1 2 100KR2J-1-GP R5806 1 2 DY 100KR2J-1-GP R5808 100KR2J-1-GP 1 2 R5807 100KR2J-1-GP DY DFDY 5V_S0 B B 29,30 MUTE# 1 AFTP118 AFTE14P-GP OUT_L- 1 AFTP117 AFTE14P-GP 15 1 G0 G1 1 1 1 5 1 2 3 4 DFDY 6 SC820P50V2KX-1GP DFDY 20.F1621.004 Wistron Corporation 2ND = 20.F1937.004 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SPEAKER CONN Size A3 Date: 5 4 3 A <Core Design> ACES-CON4-17-GP-U1 2 2 1 7 8 SDL# SDR# AFTE14P-GP OUT_L+ DFDY DFDY 2 6 10 SC820P50V2KX-1GP -1:12/09 R58010.R58011 Change into R5810 R5811 SC820P50V2KX-1GP DFDY SC820P50V2KX-1GP 18 TPA2012D2RTJR-GP A AFTE14P-GP AFTP116 OUT_R- 2 DFDY SCD047U16V2KX-1-GP FSPK_L+ 2 DFDY1K96R2F-1-GP AFTP115 1 OUT_L+ OUT_LOUT_R+ 2 5 14 11 GND FSPK_L1 OUTL+ OUTLOUTR+ OUTR- DFDY 21 1 R5812 2 INR+ INRINL+ INL- EC5804 C5811 1 16 17 20 19 2DFDYFSPK_R+ 21K96R2F-1-GP 1K96R2F-1-GP DFDY 1 OUT_R- SPK2 EC5803 1 R5810 1 R5811 OUT_R+ SPK Trace = 40mil EC5802 FSPK_L C5810 1 SCD047U16V2KX-1-GP FSPK_R1 2 C5808 1 2 DFDY SCD047U16V2KX-1-GP DFDY PGND PGND FSPK_R 12 4 U5801 2 1K96R2F-1-GP PVDD PVDD DFDY SCD047U16V2KX-1-GP AGND 1 R5809 2 DFDY 3 13 2nd Speaker AMP 9 2 1 2 SCD1U16V2KX-3GP EC5801 29 DFDY NC#6 NC#10 29 DFDY AVDD C5809 1 GND near by CODEC C5807 SC1U16V3KX-5GP 1 2 SC10U6D3V3MX-GP DFDY 1 C5806 C5805 2 Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 58 of 103 5 4 3 2 1 close to XF1 close to XF1 D D XF5901 MDIN3 31 MDIP3 13 15 14 SCD01U16V2KX-3GP 31 16 18 17 MDIN2 31 MDIP2 31 MDIN1 31 MDIP1 31 MDIN0 31 MDIP0 19 21 20 22 24 23 1CT:1CT 31 1CT:1CT XRF_RDC 1CT:1CT 1 1CT:1CT C5906 2 12 10 11 RJ45-8 9 7 8 RJ45-5 6 4 5 RJ45-6 3 1 2 RJ45-2 MCT2 RJ45-7 1 MCT2_C 2 SCD01U50V2KX-1GP 1 MCT3_C 2 SCD01U50V2KX-1GP C5901 SRN75J-1-GP MCT3 RJ45-4 C5902 MCT0 RJ45-3 1 MCT0_C 2 SCD01U50V2KX-1GP 1 MCT1_C 2 SCD01U50V2KX-1GP C5907 MCT1 RJ45-1 C5908 1 2 3 4 8 7 6 5 RN5901 XFORM-24P-60-GP 68.IH160.30A 2ND = 68.89246.301 C C AMBER = LAN ACK RJ451 B B RJ451 31 W HITE_LED# AMBER_LED# 1 R5902 470R2J-2-GP 2 1 C5905 SCD1U16V2KX-3GPDY DY 3D3V_S5 C5903 SCD1U16V2KX-3GP 2 1 31 AMBER_LED# W HITE_LED# 1 R5901 470R2J-2-GP WHITE 10/100 13 9 10 AMBER_R_LED# 2 2 RJ45-1 1 RJ45-2 RJ45-3 RJ45-4 RJ45-5 RJ45-6 RJ45-7 RJ45-8 2 3 4 5 6 7 8 W HITE_R_LED# 11 12 14 5V_S5 CHASSIS AMBER -1 1220 (1)route WHITE CHASSIS WHITE 10/100 RJ45-LED-12P-14-GP-U1 20 mils 3D3V_S5 A RJ45-1 1 AFTP120 2nd = 22.10177.N81 AFTE14P-GP 1 AFTP128 AFTE14P-GP RJ45-2 1 AFTP121 AFTE14P-GP 1 AFTP127 AFTE14P-GP RJ45-3 1 AFTP122 AFTE14P-GP RJ45-4 1 AFTP119 AFTE14P-GP RJ45-5 1 AFTP123 AFTE14P-GP Wistron Corporation RJ45-6 1 AFTP124 AFTE14P-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. RJ45-7 1 AFTP125 AFTE14P-GP RJ45-8 1 AFTP126 AFTE14P-GP AMBER_R_LED# 1 AFTP169 AFTE14P-GP W HITE_R_LED# 1 AFTP168 AFTE14P-GP 5V_S5 22.10277.W 71 on bottom as differential pairs. (2)Tx+/Tx- are pairs. Rx+/Rx- are pairs. (3)No vias, No 90 degree bends. (4)pairs must be equal lengths. (5)6mil trace width,12mil separation. (6)36mil between pairs and any other trace. (7)Must not cross ground moat, except RJ-45 moat. 1 AFTP129 <Core Design> AFTE14P-GP Title Size A3 Date: 5 4 A 3 2 Document Number RJ45+Transformer Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 59 of 103 5 4 3 2 1 SSID = Flash.ROM SPI FLASH ROM (8M byte) for PCH & KBC 3D3V_S5 D 3D3V_SPI 3D3V_SPI 3D3V_S5 8 7 6 5 1 1 DY C6004 SCD1U10V2KX-5GP R6011 1 2 C6003 SC10U6D3V5KX-1GP 2 1 C6002 2 1 2 3 4 RN6001 SRN4K7J-10-GP C6001 2 2 DY D SCD1U10V2KX-5GP 3D3V_SPI SC10U6D3V5KX-1GP 1 0R0402-PAD Notes: The total SPI interface signal between EC and PCH can’t not exceed 6500mil. The mismatch between SPI signal must be within 500mil PCH 3D3V_SPI PCH U6002 17 PCH_SPI_CS#0 1 R6001 17 PCH_SPI_MISO 2 SPI_SO 33R2J-2-GP C 1 2 SPI_W P#3 4 CS# DO/IO1 WP#/IO2 GND VCC HOLD#/IO3 CLK DI/IO0 8 7 6 5 SPI_HOLD_0# PCH_SPI_CLK 17 PCH_SPI_MOSI 17 C W 25Q64FVSSIG-GP 72.25Q64.F01 2nd = 72.25640.D01 KBC -1_ 0102 1 1 1 1 R6012 2 27 SPI_W P#_C 1 0R2J-2-GP R6007 R6008 R6009 DY R6010 DY DY DY 2 2 2 2 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP EC_SPI_CS#_C 27 EC_SPI_DO_C 27 EC_SPI_DI_C 27 EC_SPI_CLK_C 27 1 1 TP6005 AFTE14P-GP 1 1 TP6006 AFTE14P-GP 1 1 TP6007 AFTE14P-GP 1 1 TP6008 AFTE14P-GP AFTE14P-GP TP6001 AFTE14P-GP TP6002 AFTE14P-GP TP6003 AFTE14P-GP TP6004 B B -1 1223 Reversed TP6001~TP6008 / R6007~R6010 is DY 以以。 1, 測測測測測測14mil, 測測測測測測75mil以 2, ,測測測測測測Top層 層. A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Flash Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 60 of 103 5 4 3 2 1 RESERVED USB 2.0/3.0 BD Power switcher Low active SSID = USB USB30_VCCB 5V_S5 27,62 USB_PW R_EN# R6101 2 EN1# EN2# 1 9 GND GND TPS2060C-GP 1USB30B_ON#0 0R0402-PAD 74.02060.A79 DY 1 C6101 2 2 DY 2 3 4 C6102 1 1 FLT1# FLT2# OUT1 OUT2 SC10U10V5KX-2GP IN 8 5 7 6 100 mil SCD1U16V2KX-3GP 2 2 C6103 SCD1U10V2KX-5GP DY D U6101 1 D TC6101 ST100U6D3VBM-24-GP 77.81071.06L DY 2ND = 74.02182.079 LOW ACTIVE TYPE!! C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title USB Power SW_USB IO Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 61 of 103 5 4 3 2 1 USB 3.0 Connector Pin definition Power switcher Low active 74.02060.A79 EN1# EN2# 27,61 USB_PW R_EN# GND GND 1 9 1USB30A_ON#0 TPS2060C-GP 0R0402-PAD LOW ACTIVE TYPE!! USB 2.0 D+ 4 GND TC6201 ST100U6D3VBM-24-GP 5 StdA_SSRX- 77.81071.06L 6 StdA_SSRX+ 7 GND 1 C6201 2 3 4 2 R6214 2 C6202 DY 2 FLT1# FLT2# SC10U10V5KX-2GP 8 5 SCD1U16V2KX-3GP DY USB 2.0 D- 3 100 mil 7 6 1 OUT1 OUT2 1 IN 1 C6203 SCD1U10V2KX-5GP POWER 2 U6201 2 D 1 USB30_VCCA 2ND = 74.02182.079 2 5V_S5 D 8 StdA_SSTX- 9 StdA_SSTX+ SuperSpeed RX SuperSpeed TX USB30_VCCA USB3_1 USB3_2 1 AFTP166 AFTE14P-GP 1 AFTP240 AFTE14P-GP USB3_RXN3_R 1 AFTP150 AFTE14P-GP USB3_RXP3_R 1 AFTP152 AFTE14P-GP USB3_TXN3_R 1 AFTP149 AFTE14P-GP USB3_TXP3_R 1 AFTP151 AFTE14P-GP USB_PN2_R 1 AFTP153 AFTE14P-GP USB_PP2_R 1 AFTP155 AFTE14P-GP USB3_RXN1_R 1 AFTP157 AFTE14P-GP USB3_RXP1_R 1 AFTP154 AFTE14P-GP USB3_TXN1_R 1 AFTP156 AFTE14P-GP 22.10339.F81 USB3_TXP1_R 1 AFTP158 AFTE14P-GP 2ND = 22.10339.H01 USB_PN0_R 1 AFTP160 AFTE14P-GP 3rd = 22.10339.K21 USB_PP0_R 1 AFTP162 AFTE14P-GP USB30_VCCA EC3602 USB30_VCCA EC3601 2 1 USB32 2 1 SCD1U25V2KX-GP USB31 SCD1U25V2KX-GP 1 USB_PN0_R USB_PP0_R C 2 3 10 11 12 13 VBUS STDA_SSRXSTDA_SSRX+ 5 6 STDA_SSTXSTDA_SSTX+ 8 9 DD+ CHASSIS#10 CHASSIS#11 CHASSIS#12 CHASSIS#13 GND 4 GND_DRAIN 7 USB3_RXN1_R USB3_RXP1_R 1 USB_PN2_R USB_PP2_R 2 3 USB3_TXN1_R USB3_TXP1_R 10 11 12 13 VBUS STDA_SSRXSTDA_SSRX+ 5 6 STDA_SSTXSTDA_SSTX+ 8 9 DD+ CHASSIS#10 CHASSIS#11 CHASSIS#12 CHASSIS#13 GND 4 GND_DRAIN 7 22.10339.F81 2ND = 22.10339.H01 69.10103.041 3rd = 22.10339.K21 69.10103.041 21 21 USB3_TXN1 21 USB3_TXN3 21 USB3_TXP3 4 USB3_TXN1_R 1 USB3_TXP1_R C6207 SCD1U16V2KX-3GP 2 1USB3_TXN3_L 3 4 USB3_TXN3_R 1USB3_TXP3_L 2 1 USB3_TXP3_R 2 FILTER-4P-6-GP 3 USB3_TXN3_R USB3_TXP3_R FILTER-4P-6-GP C6206 SCD1U16V2KX-3GP Ultra Low Capacitance TVS Arrays (Pin5.6.7.8 No Internal Connection) TR6205 2 USB3_TXP1 1 USB3_TXP1_L 2 U6202 C6205 SCD1U16V2KX-3GP B C SKT-USB13-52-GP SKT-USB13-52-GP C6204 SCD1U16V2KX-3GP 2 1 USB3_TXN1_L USB3_RXN3_R USB3_RXP3_R USB3_RXN1_R USB3_RXP1_R TR6204 USB3_TXN1_R USB3_TXP1_R 1 2 G1 3 4 DY 8USB3_RXN1_R 7USB3_RXP1_R G2 6USB3_TXN1_R 5USB3_TXP1_R L1#1L1#8 L2#2L2#7 GNDGND L3#3L3#6 L4#4L4#5 B 69.10103.041 RCLAMP0524P-GP FILTER-4P-6-GP 21 21 69.10103.041 21 USB3_RXP3 2 1 USB3_RXP3_R FILTER-4P-6-GP 21 USB3_RXN3 3 4 USB3_RXN3_R USB3_RXP1 2 1 USB3_RXP1_R USB3_RXN1 3 4 USB3_RXN1_R Ultra Low Capacitance TVS Arrays (Pin5.6.7.8 No Internal Connection) TR6206 U6203 USB3_RXN3_R USB3_RXP3_R TR6203 -1 0103 by -1 0103 by USB3_TXN3_R USB3_TXP3_R EMI 1 2 G1 3 4 EMI DY 8USB3_RXN3_R 7USB3_RXP3_R G2 6USB3_TXN3_R 5USB3_TXP3_R L1#1L1#8 L2#2L2#7 GNDGND L3#3L3#6 L4#4L4#5 RCLAMP0524P-GP 69.10103.041 FILTER-4P-6-GP 69.10103.041 A FILTER-4P-6-GP 21 USB_PN0 2 21 USB_PP0 3 1 USB_PN0_R 4 USB_PP0_R 21 USB_PN2 3 4 USB_PN2_R 21 USB_PP2 2 1 USB_PP2_R <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TR6202 TR6201 Title SWAP 0105 SWAP 0105 Size A3 Date: 5 A 4 3 2 Document Number USB3.0 Rev 1 Colossus Thursday, January 05, 2012 Sheet 1 62 of 103 5 4 3 2 1 D D C C (Blanking) B B <Variant Name> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Resered(Bluetooth) Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 63 of 103 5 4 3 2 1 Finger Printer D D 1 AFTP165 AFTE14P-GP USB_PN8 1 AFTP167 AFTE14P-GP USB_PP8 1 AFTP164 AFTE14P-GP 1 AFTP159 AFTE14P-GP 1 AFTP180 AFTE14P-GP 3D3V_S0 C C 5V_S0 FP1 ACES-CON6-52-GP 20.K0721.006 2ND = 20.K0382.006 8 3D3V_S0 6 5 4 3 2 USB_PP8 USB_PN8 U6401 5V_S0 DY 1 B B 21 USB_PN8 1 2 3 ESD I/O1 GND ESD I/O2 ESD I/O4 VP ESD I/O3 6 5 4 7 USB_PP8 21 3D3V_S0 DFDY IP4220CZ6-GP -1 12/23 FP1 change source <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. A A Title Size A4 Document Number Finger Print Conn Date: Wednesday, January 04, 2012 5 4 3 Rev 1 Colossus 2 Sheet 64 of 1 103 5 4 3 2 1 SSID = Wireless Mini-Card--WLAN 3D3V_S0_WLAN 3D3V_S5 Half minicard 53 NP1 1 20 mil 27 WLAN_PME_DIS_C 2 0R3J-0-U-GP 18 CLKRQ_WLAN#_C 18 CLK_PCIE_WLAN# 18 CLK_PCIE_WLAN 27 27 E51_RXD E51_TXD 18 PCIE_RXN4_WLAN 18 PCIE_RXP4_WLAN 18 PCIE_TXN4_WLAN 18 PCIE_TXP4_WLAN B Pin 5 20 47 51 Active High(3V) High(3V) Reserved Reserved Function GPIO/BT_WAKE WIFI_Enable 27 BT_PRISEL(coexistence) BTCX_STAT(coexistence) 5V_S0 BLUETOOTH_EN 1 R6503 2 DY 0R2J-2-GP 2 R6504 1 0R0402-PAD 2 3 5 7 9 11 13 15 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 NP2 54 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 DY_RF 1 1 EC6503 2 DY_RF DY_RF EC6504 2 EC6502 2 2 2 1 R6502 1 1 1 EC6501 WLAN1 SC68P50V2JN-1GP 1 1D5V_S0 SC2200P50V2KX-2GP 3D3V_S0 Q6501 DMP2305U-7-GP 84.02305.G31 2ND = 84.03419.031 1D5V_S0 SC68P50V2JN-1GP C DY DY 3D3V_S0_WLAN SC2200P50V2KX-2GP 3D3V_S0_WLAN C6502 SCD01U16V2KX-3GP DY D 2 10KR2J-3-GP 3D3V_S0_WLAN CLOSED IN WLAN1 DY_RF C WIFI_RF_EN 27 PLT_RST# 5,21,27,31,32,36,71,82,83,103 USB_PN5_RFEL6501 2 1 USB_PP5_RF EL6502 2 0R0402-PAD 1 0R0402-PAD USB_PN5 21 USB_PP5 21 B WLAN_LED# 27 1 S 1AOAC_EN#_R G 2 AOAC_EN# Mini-Card--WLAN Half minicard R6505 4K7R2J-2-GP 2 27 2 2 SCD1U10V2KX-5GP DY D C6504 SCD01U16V2KX-3GP DY R6501 C6503 SC10U6D3V5KX-1GP SCD1U10V2KX-5GP C6501 2 1 C6505 1 1 D 3D3V_S0 SKT-MINI52P-58-GP-U 1-1 1226 del TR6501 20.F1697.052 2ND = 20.F1697.052 3RD = Main:62.10043.F91 <Core Design> Wistron Corporation 677869-FM8 A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1st 2nd 3rd 4th 677869-FM8 677869-AM8 677869-BM8 677869-LM8 Title MINICARD(WLAN+Bluetooth)/CONN Size A4 Document Number Rev Date: Wednesday, January 04, 2012 5 4 3 1 Colossus 2 Sheet 65 of 1 103 A 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 66 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 67 of 103 5 4 3 1 5V_S0 Touchpad LED (Amber) SSID = User.Interface D 2 On Keyboard LEDs DRC5143Z0L-GP C B R1 E R2 27 TOUCHPAD_LED TPLED1 TP_PWRLED_L 1 R6806 330R2J-3-GP 2 TP_PWRLED_R K 83.00193.J70 Q6803 27 1 2ND = 83.19217.J70 2 DY DRC5143Z0L-GP C B R1 E R2 CAP_LED D LED-O-63-GP 84.05143.011 2ND = 84.00043.011 Cap locks LED (White) A CAP_LED#_Q 1 R6801 1KR2J-1-GP 2 MUTE_LED#_Q 1 R6802 330R2J-3-GP 2 EC6801 SCD1U25V2KX-GP CAP_LED#_R1 69 Q6801 84.05143.011 2ND = 84.00043.011 C Mute LED (Amber) 29 MUTE_LED_CTRL DRC5143Z0L-GP C B R1 E R2 C MUTE_LED#_R1 69 Q6802 84.05143.011 2ND = 84.00043.011 Wireless LED (White-On, Amber-Off) 1 5V_S0 B B R6803 330R2J-3-GP 3D3V_S0 1 2 L6801 1 DY 2 MLVS0402M04-GP 69 WIRELESS_AMBER# R6805 DY 100KR2J-1-GP 1 5V_S0 2 R6804 1KR2J-1-GP 4 3 5 2 6 1 DMN601DWK-7-GP 69 WIRELESS_WHITE# 84.DM601.03F A 2 U6801 EC_WLAN_LED# 27 L6802 1 DY 2 MLVS0402M04-GP <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2nd = 84.2N702.E3F Title Size A4 LED Bard/Power Button Document Number 1 Colossus Date: Wednesday, January 04, 2012 Sheet Rev 68 of 103 A 4 27 KCOL[0..17] 27 C 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 KROW 7 KROW 6 KCOL9 KROW 4 KROW 5 KCOL0 KROW 2 KROW 3 KCOL5 KCOL1 KROW 0 KCOL2 KCOL4 KCOL7 KCOL8 KCOL6 KCOL3 KCOL12 KCOL13 KCOL14 KCOL11 KCOL10 KCOL15 KCOL16 KCOL17 W IRELESS_W HITE# 68 W IRELESS_AMBER# 68 MUTE_LED#_R1 68 CAP_LED#_R1 68 AFTP227 AFTE14P-GP AFTP228 AFTE14P-GP AFTP189 AFTE14P-GP AFTP190 AFTE14P-GP AFTP191 AFTE14P-GP AFTP197 AFTE14P-GP AFTP211 AFTE14P-GP AFTP193 AFTE14P-GP AFTP194 AFTE14P-GP AFTP196 AFTE14P-GP AFTP202 AFTE14P-GP AFTP221 AFTE14P-GP AFTP198 AFTE14P-GP AFTP199 AFTE14P-GP AFTP200 AFTE14P-GP AFTP201 AFTE14P-GP AFTP214 AFTE14P-GP AFTP203 AFTE14P-GP AFTP204 AFTE14P-GP AFTP205 AFTE14P-GP AFTP206 AFTE14P-GP AFTP207 AFTE14P-GP AFTP208 AFTE14P-GP AFTP209 AFTE14P-GP AFTP210 AFTE14P-GP AFTP220 AFTE14P-GP AFTP212 AFTE14P-GP AFTP213 AFTE14P-GP AFTP219 AFTE14P-GP AFTP215 AFTE14P-GP AFTP216 AFTE14P-GP AFTP217 AFTE14P-GP R6904 1 2 DFDY0R2J-2-GP Q6902 DMP2305U-7-GP 5V_S0 S LOGO BACKLIGHT(LVDS1) C6904 5V_S0_LOGO_BL_L 1 D R6902 10KR2J-3-GP DY D 2nd = 84.03419.031R6905 1 KROW 1 1 1 1 KCOL16 1 KCOL17 1 KCOL15 1 KCOL10 1 KCOL11 1 KCOL14 1 KCOL13 1 KCOL12 1 KCOL3 1 KCOL6 1 KCOL8 1 KCOL7 1 KCOL4 1 KCOL2 1 KROW 0 1 KCOL1 1 KCOL5 1 KROW 3 1 KROW 2 1 KCOL0 1 KROW 5 1 KROW 4 1 KCOL9 1 KROW 6 1 KROW 7 1 KROW 1 1 CAP_LED#_R1 1 MUTE_LED#_R1 1 W IRELESS_W HITE# 1 W IRELESS_AMBER# 1 KB_BL_DETECT_C1 1 5V_S0 33 2 DFDY 510R2J-1-GP 5V_S0_LOGO_BL C6905 SCD1U10V2KX-5GP DY DY DY SCD1U10V2KX-5GP 2 KB1 D A Cover Logo Backlight KB_BL_DETECT HIGH = BL SKU LOW = NON-BL SKU Internal KeyBoard Connector 1 2 KROW [0..7] 2 G SSID = KBC 3 2 5 2 1 DY C6906 SCD1U10V2KX-5GP Q6903 G LOGO_BL_C LOGO_BL_ON 27 D S 2N7002K-2-GP DY 84.2N702.J31 2nd = 84.2N702.W 31 C 5V_S0 KB_BL_DETECT_C 27 LTB1 34 AFTE14P-GP AFTP231 5V_S0_LOGO_BL 1 4 2 5V_S0_LOGO_BL PTW O-CONN32-GP 1 AFTE14P-GP AFTP233 1 20.K0661.032 Touch Pad 2 DY KBL1 18 PCH_SMB_CLK 18 PCH_SMB_DATA 3 4 SRN33J-5-GP-U 10/6 TP Vendor request RN6903 1 2 27 KBC_CLK1 27 KBC_DATA1 ACES-CON4-39-GP 27 KB_BL_ON_R# DY 4 3 SRN33J-5-GP-U 20.K0722.004 2nd = 20.K0397.004 3rd = main: 20.K0722.004 -1 1223 KBL1 Change Source 2 1 3 4 2 TP_CLK TP_DATA 3 4 RN6902 B 1 2 3 4 5 6 PCH_SML0_CLK_C PCH_SML0_DATA_C EC6904 8 2 RN6904 2 1 2ND = 20.K0382.006 7 EC6903 DY DY SC5P50V2CN-2GP C6903 SCD1U10V2KX-5GP 2 1 TPCLK TPDATA 1 1 27 27 15FFUP_17DY 20.F1639.002 2nd = 20.F1841.002 20.K0721.006 TPAD1 SRN33J-5-GP-U 5 2 2 2 2 R6903 1 25V_S0_KB_BL_C 1 0R3J-0-U-GP AFTE14P-GP AFTP192 1 2 3 1 4 AFTE14P-GP AFTP195 6 SC5P50V2CN-2GP SCD1U10V2KX-5GP 2 DY C6902 SCD1U10V2KX-5GP5V_S0_KB_BL G R6901 10KR2J-3-GP ACES-CON2-20-GP RN6905 SRN4K7J-8-GP SCD1U10V2KX-5GP 3 4 D 1 1 C6901 2 2 1 RN6901 SRN4K7J-8-GP 2nd = 84.03419.031 1 S 5V_S0_KB_BL EC6902 1 Q6901 DMP2305U-7-GP 5V_S0 B EC6901 DY SCD1U10V2KX-5GP Internal KeyBoard Backlight Connector 1 3D3V_S5 1 3D3V_S5 1 3 EC6905 SCD1U25V2KX-GP 2nd = 20.K0660.032 3rd = 20.K0676.032 ACES-CON6-52-GP -1 12/23 TPAD1 change source 3D3V_S5 A 1 AFTP223 AFTE14P-GP TP_DATA 1 AFTP187 AFTE14P-GP TP_CLK 1 AFTP188 AFTE14P-GP Wistron Corporation 1 AFTP222 AFTE14P-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. PCH_SML0_DATA_C1 AFTP229 AFTE14P-GP PCH_SML0_CLK_C 1 AFTP230 AFTE14P-GP <Core Design> A Title Size A3 Date: 5 4 3 2 Key Board/Touch Pad Document Number Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 69 of 103 5 4 3 2 1 D D C C (Hall sensor at Power BD ) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Hall Sensor Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 70 of 103 5 4 3 2 1 D D DEBUG BD for Factory Test 3D3V_S0 DB1 11 1 RN7101 17,27 LPC_AD0 17,27 LPC_AD1 17,27 LPC_AD2 17,27 LPC_AD3 17,27 LPC_FRAME# 5,21,27,31,32,36,65,82,83,103 PLT_RST# C 1 2 3 4 DY 8 7 6 5 LPC_AD0_R LPC_AD1_R LPC_AD2_R LPC_AD3_R 2 3 4 5 6 7 8 9 10 12 SRN0J-5-GP 21,103 CLK_PCI_DEBUG C PAD-10P-177042-GP ZZ.00PAD.Y41 -1 0102 B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Dubug connector Size A4 Document Number Date: Wednesday, January 04, 2012 5 4 3 Rev 1 Colossus 2 Sheet 71 of 1 103 A 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 72 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 73 of 103 5 4 3 2 1 D D 2 IN1 CARD-READER (SD/MMC) CARD1_3V3 CARD1_3V3_C DY F7401 2 CARD1_3V3_C Socket C7403~7406 pls close to chip C7402 C 15UP_17DY CR1 4 VDD 7 8 9 1 DAT0 DAT1 DAT2 CD/DAT3 DY DY DY DY 2 2 C7403 C7404 C7405 C7406 32 32 2 SD_D0 SD_D1 SD_D2 SD_D3 2 32 32 32 32 2 15UP_17DY SC10U10V5ZY-1GP C7401 SCD1U16V2KX-3GP GAP-CLOSE-PWR C 1 2 1 F7402 1 2 1 FUSE-1D1A6V-4GP-U SD_CLK 5 SD_CMD 2 CD_PIN WP_PIN NP1 NP2 NP1 NP2 VSS VSS 3 6 CLK CMD 10 12 CD#_WP_PIN/GND GND GND SD_CD# 32 SD_WP 32 11 13 14 15UP_17DY 1 AFTP172 AFTE14P-GP SD_D3 1 AFTP174 AFTE14P-GP SD_CLK 1 AFTP173 AFTE14P-GP SD_CMD 1 AFTP175 AFTE14P-GP SD_CD# 1 AFTP177 AFTE14P-GP SD_WP 1 AFTP176 AFTE14P-GP 1 AFTP178 AFTE14P-GP 1 AFTP179 AFTE14P-GP 1 SD_D2 1 AFTE14P-GP SKT-SDCARD-24-GP-U1 62.10051.891 SC5P50V2CN-2GP AFTP171 SC5P50V2CN-2GP 1 SC5P50V2CN-2GP 1 AFTE14P-GP SC5P50V2CN-2GP CARD1_3V3_C A SD_D1 AFTP170 1 B SD_D0 1 B <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CARD Reader CONN Size A4 Document Number Date: Wednesday, January 04, 2012 5 4 3 Rev 1 Colossus 2 Sheet 74 of 1 103 A 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Express Card Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 75 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 76 of 103 5 4 3 2 1 D D (Blanking) C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number TPM Rev 1 Colossus Monday, December 26, 2011 Sheet 1 77 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 78 of 103 5 4 3 D 2 1 D ACCELEROMETER R7903 1 2 0R2J-2-GP 1 2 SC4D7U6D3V3KX-GP C C7901 C7902 SCD1U16V2ZY-2GP 2 1 3D3V_S0_WLAN U7901 C 1 VDD_IO 14 VDD 11 9 INT1 INT2 RES#10 RES#13 RES#15 RES#16 D7901 ADY 21 ACCEL_INT# ACCEL_INT#_R K 1SS355GP-GP 1 R7901 2G_CS 8 CS 2 3 NC#2 NC#3 10 13 15 16 SCL/SPC SDA/SDI/SDO 4 6 SDO/SA0 7 G_CLK G_DATA G_SDO 1 R7902 DY 2 0R2J-2-GP 0R0402-PAD 3D3V_S0_WLAN GND GND 5 12 HP3DC2TR-GP 3D3V_S0_WLAN 74.HP3DC.ABZ B B 4 3 Must be placed in the center of the system RN7901 SRN2K2J-1-GP 1 2 Q7901 G_CLK 1 6 2 5 3 4 SML1_CLK 18,27,29,86 <Core Design> 2N7002KDW-GP 84.2N702.A3F SML1_DATA 18,27,29,86 Wistron Corporation G_DATA A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2nd = 84.2N702.E3F 3RD = 84.2N702.F3F Title Size A4 Document Number ACCELEROMETER Date: Wednesday, January 04, 2012 5 4 3 2 Sheet Rev 1 Colossus 79 of 1 103 A 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 80 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 81 of 103 5 4 Card Reader BD 15"=DY 3 2 17"=PHASE IN 1 USB BD(USB3.0*1+USB2.0*1) CRBD1 13 3D3V_S0 1 D 2 3 4 5 6 7 8 9 10 11 12 18 PCIE_RXN2_MEDIA17 18 PCIE_RXP2_MEDIA17 18 PCIE_TXN2_MEDIA17 18 PCIE_TXP2_MEDIA17 18 CLK_PCIE_MEDIA17# 18 CLK_PCIE_MEDIA17 18 CLKREQ_MEDIA#17 5,21,27,31,32,36,65,71,83,103 PLT_RST# 1 AFTP242 AFTE14P-GP PCIE_RXN2_MEDIA17 1 AFTP243 AFTE14P-GP 3D3V_S0 USB30_VCCB UB1 USB3_TXN4 1 AFTP139 AFTE14P-GP USB3_TXP4 1 AFTP140 AFTE14P-GP USB3_RXP4 1 AFTP137 AFTE14P-GP USB3_RXN4 D 21 1 PCIE_RXP2_MEDIA17 1 AFTP244 AFTE14P-GP PCIE_TXN2_MEDIA17 1 AFTP245 AFTE14P-GP PCIE_TXP2_MEDIA17 1 AFTP246 AFTE14P-GP CLK_PCIE_MEDIA17# 1 AFTP247 AFTE14P-GP CLK_PCIE_MEDIA17 1 AFTP248 AFTE14P-GP CLKREQ_MEDIA#17 1 AFTP249 AFTE14P-GP PLT_RST# 1 AFTP250 AFTE14P-GP 1 AFTP251 AFTE14P-GP USB30 CONN 14 ACES-CON12-13-GP 15DY_17UP 21 21 USB3_TXN4 USB3_TXP4 21 21 USB3_RXP4 USB3_RXN4 3D3V_S5 USB_PN3_1 USB_PP3_1 5V_S0 21 21 USB20 CONN 20.K0423.012 2nd = 20.K0426.012 17 SATA_LED# 17 HDD_HALTLED 27 PW RLED 21 USB_PN9_1 21 USB_PP9_1 5V_S5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 AFTP138 AFTE14P-GP USB_PN3_1 1 AFTP142 AFTE14P-GP USB_PP3_1 1 AFTP141 AFTE14P-GP USB_PN9_1 1 AFTP143 AFTE14P-GP USB_PP9_1 1 AFTP144 AFTE14P-GP 5V_S5 1 AFTP145 AFTE14P-GP USB30_VCCB 1 AFTP147 AFTE14P-GP 1 AFTP146 AFTE14P-GP 1 AFTP148 AFTE14P-GP SATA_LED# 1 AFTP226 AFTE14P-GP HDD_HALTLED 1 AFTP252 AFTE14P-GP 1 AFTP225 AFTE14P-GP 1 AFTP224 AFTE14P-GP 25 24 3D3V_S5 23 22 PW RLED FOX-CON20-3-GP PW RLED C 20.F2030.020 HDD_HALTLED 1 AFTE14P-GP C8202 PW RLED_C 1 LID_CLOSE#_C 1 AFTP236 AFTE14P-GP 3D3V_AUX_KBC 1 AFTP238 AFTE14P-GP 5V_S5 1 AFTP237 AFTE14P-GP 1 AFTP239 AFTE14P-GP 1 1 2 2 1 AFTP234 AFTE14P-GP USB_PP3_2 1 AFTP235 AFTE14P-GP USB_PN9_2 1 AFTP253 AFTE14P-GP USB_PP9_2 1 AFTP254 AFTE14P-GP 1 21 21 USB_PN3_2 USB_PP3_2 21 21 USB_PN9_2 USB_PP9_2 2 3 4 5 6 15DY_17UP 8 MLX-CON6-24-GP-U 20.F1352.006 LID_CLOSE# 2nd = 20.F1804.006 For ESD -1 01/04 3RD = 20.F1639.006 QUICKW EB_BTN# LID_CLOSE# PW RLED KBC_PW RBTN# 1 3 5 7 EC8201 2 4 6 8 TOUCHPAD BD PAGE 69 B SRC220P50VK-GP -1 12/26 AFTP232 TPAD26-OP-GP ZZ.00PAD.0K1 PW R1 AFTP218 AFTE14P-GP ACES-CON8-40-GP 7 USB_PN3_2 2 1 2 1 2 AFTP241 1 EC8204 SCD1U25V2KX-GP KBC_PW RBTN#_C UB2 R8201 100KR2F-L1-GP SCD1U10V2KX-5GP QUICKW EB_BTN#_C 1 SCD1U10V2KX-5GP B C8201 5V_S5 EC8203 SCD1U25V2KX-GP 3D3V_AUX_KBC SCD1U25V2KX-GP 2 EC8202 3D3V_AUX_KBC C 2ND = 20.F2139.020 1 SATA_LED# POWER BUTTON BD 5V_S0 10 8 7 6 5 4 3 2 KBC_PW RBTN#_C PW RLED_C LID_CLOSE#_C QUICKW EB_BTN#_C 3D3V_AUX_KBC 5V_S5 1 ER8201 1 ER8202 1 ER8203 1ER8204 DY 1 9 20R0402-PAD-1-GP 20R0402-PAD-1-GP 20R0402-PAD-1-GP 33R5J-2-GP 2 R8202 1 2 DY KBC_PW RBTN# 27 PW RLED 27 LID_CLOSE# 27 QUICKW EB_BTN# 27 3D3V_AUX_KBC 100KR2F-L1-GP 20.K0667.008 2ND = 20.K0665.008 A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number IO Board Connector Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 82 of 103 5 4 3 2 1 1D05V_VGA_S0 dGPU Reset 4 PEG_RXP5 PEG_RXN5 C8311 C8312 C8313 C8314 DIS_OPT AP17 AP18 1 2 AK18 PEG_C_RXN6 AJ18 SCD22U10V2KX-1GP 1 2 DIS_OPT PEG_C_RXP7 AL19 SCD22U10V2KX-1GP 1 2 PEG_C_RXN7 AK19 SCD22U10V2KX-1GP 1 2 DIS_OPT PEG_TXP7 PEG_TXN7 AN20 AM20 AK20 AJ20 AP20 AP21 AH20 AG20 AN21 AM21 B AK21 AJ21 AN23 AM23 AL22 AK22 AP23 AP24 AK23 AJ23 AN24 AM24 AP26 AP27 AL25 AK25 AN27 AM27 PEX_SVDD_3V3 1 2 2 2 2 1 1 1 1 2 2 2 2 2 1 1 1 1 AH12 C 3D3V_VGA_S0 AG12 PEX_TX6 PEX_TX6# PEX_RX6 PEX_RX6# DIS_OPT PEX_TX7 PEX_TX7# PEX_RX7 PEX_RX7# 3.3V +/- 5% 120mA DIS_OPT DIS_OPT (See NV DG) C8325 C8324 C8333 X7R, Under GPU. PEX_TX8 PEX_TX8# VDD_SENSE PEX_RX8 PEX_RX8# GND_SENSE L4 NV_VCCSENSE 92 L5 NV_VSSSENSE 92 POWER IC PEX_TX9 PEX_TX9# PEX_RX9 PEX_RX9# B PEX_TX10 PEX_TX10# NC_3V3AUX P8 PEX_RX10 PEX_RX10# PEX_TX11 PEX_TX11# DY PEX_RX11 PEX_RX11# PEX_TX12 PEX_TX12# PEX_TSTCLK_OUT PEX_TSTCLK_OUT# AJ26 PEXTSTCLK_OUT AK26 PEXTSTCLK_OUT# 1 R8304 1.05V +/- 3% 120mA (See NV DG) 2 100R2J-2-GP PEX_RX12 PEX_RX12# 1D05V_VGA_S0 R8308 PEX_TX13 PEX_TX13# PEX_PLLVDD AG26 VCC1R05VIDEO_PEX_PLLVDD PEX_RX13 PEX_RX13# PEX_TX14 PEX_TX14# TESTMODE R8303 AK11 TESTMODE 1 DIS_OPT PEX_RX14 PEX_RX14# PEX_TX15 PEX_TX15# PEX_RX15 PEX_RX15# PEX_TERMP R8301 AP29 PEX_TERMP 1 C8327 2 10KR2J-3-GP DIS_OPT C8326 DIS_OPT SC1U10V2KX-1GP AK24 AJ24 PEX_PLL_HVDD PEX_RX5 PEX_RX5# SC4D7U6D3V3KX-GP AN26 AM26 PEX_TX5 PEX_TX5# SCD1U10V2KX-5GP AH23 AG23 10U mid TO GPU PEX_RX4 PEX_RX4# SC4D7U6D3V3KX-GP AN18 AM18 4.7U NEAR TO GPU PEX_TX4 PEX_TX4# SC4D7U6D3V3KX-GP PEG_TXP6 PEG_TXN6 1U Under GPU C8337 PEX_RX3 PEX_RX3# SCD1U10V2KX-5GP C8315 C8316 PEG_TXP5 PEG_TXN5 DIS_OPT SCD22U10V2KX-1GP PEG_C_RXP6 DIS_OPT PEG_RXP7 PEG_RXN7 AN17 AM17 PEG_C_RXP5 AH17 SCD22U10V2KX-1GP 1 2 PEG_C_RXN5 AG17 SCD22U10V2KX-1GP 1 2 DIS_OPT PEG_RXP6 PEG_RXN6 PEG_TXP4 PEG_TXN4 PEX_TX3 PEX_TX3# C8336 1 2 HCB1608KF-121T20-GP 1 DIS_OPT PEG_C_RXP4 AK17 SCD22U10V2KX-1GP 1 2 PEG_C_RXN4 AJ17 SCD22U10V2KX-1GP 1 2 PEX_RX2 PEX_RX2# C8323 C8328 2 PEG_RXN[0..7] AN15 AM15 10U mid TO GPU 1 C8309 C8310 DIS_OPT 4 PEG_TXP3 PEG_TXN3 C8335 2 PEG_RXP4 PEG_RXN4 PEG_RXP[0..7] AP14 AP15 C8320 SC22U6D3V5MX-2GP DIS_OPT 4 PEG_TXN[0..7] PEG_TXP2 PEG_TXN2 DIS_OPT C8318 SC22U6D3V5MX-2GP PEG_C_RXP3 AL16 SCD22U10V2KX-1GP 1 2 PEG_C_RXN3 AK16 SCD22U10V2KX-1GP 1 2 C8330 SC1U10V2KX-1GP C8307 C8308 PEX_TX2 PEX_TX2# C8329 SC1U10V2KX-1GP PEG_RXP3 PEG_RXN3 C8334 DIS_OPTDIS_OPTDIS_OPTDIS_OPTDIS_OPT DIS_OPTDIS_OPT SC4D7U6D3V3KX-GP PEG_C_RXP2 AK15 SCD22U10V2KX-1GP 1 2 PEG_C_RXN2 AJ15 SCD22U10V2KX-1GP 1 2 PEX_RX1 PEX_RX1# SC10U6D3V5KX-1GP DIS_OPT C8305 C8306 PEX_TX1 PEX_TX1# AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28 SC10U6D3V5KX-1GP C AN14 AM14 PEG_RXP2 PEG_RXN2 DIS_OPT 4 PEG_TXP[0..7] PEG_TXP1 PEG_TXN1 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 2 DIS_OPT 4.7U NEAR TO GPU 1D05V_VGA_S0 PEX_RX0 PEX_RX0# 1 DIS_OPT PEG_C_RXP1 AH14 SCD22U10V2KX-1GP 1 2 PEG_C_RXN1 AG14 SCD22U10V2KX-1GP 1 2 PEX_TX0 PEX_TX0# C8322 2 C8303 C8304 AN12 AM12 1 PEG_RXP1 PEG_RXN1 PEG_TXP0 PEG_TXN0 2 DIS_OPT PEX_REFCLK PEX_REFCLK# AG19 AG21 AG22 AG24 AH21 AH25 1 2 0R2J-2-GP DIS_OPT PEX_CLKREQ# C8321 2 AL13 AK13 PEG_C_RXP0 AK14 SCD22U10V2KX-1GP 1 2 DIS_OPT PEG_C_RXN0 AJ14 SCD22U10V2KX-1GP 1 2 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6 PEX_RST# 1 C8301 C8302 PEX_WAKE# 2 1 AK12 18 CLK_PCIE_VGA 18 CLK_PCIE_VGA# PEG_RXP0 PEG_RXN0 R8307 DIS_OPT AJ12 PEX_CLKREQ# 1 2N7002K-2-GP VGA_RST# 2 R8311 10KR2J-3-GP 1 3D3V_S5 DIS_OPT 1 S AJ11 R8310 10KR2J-3-GP C8319 2 DY 1 G D 2 SC 2 Q8301 DY 18 CLKREQ_PEG_A# 1/17 PCI_EXPRESS C8331 SC22U6D3V5MX-2GP R8309 100KR2F-L1-GP C8332 SC22U6D3V5MX-2GP R8306 2ND = 73.7SZ08.EAH 3RD = 73.01G08.L04 1 DY 2 0R2J-2-GP 1 OF 17 VGA1A SC10U6D3V5KX-1GP 3D3V_VGA_S0 SC1U10V2KX-1GP 4 SC1U10V2KX-1GP Y SC4D7U6D3V3KX-GP GND 73.01G08.EHG 2 B U74LVC1G08G-AL5-R-GP-U 1 1 DIS_OPTDIS_OPTDIS_OPTDIS_OPTDIS_OPT DIS_OPT DIS_OPT SC10U6D3V5KX-1GP 3 5 2 PLT_RST# D DIS_OPT VCC 1 2 A 2 5,21,27,31,32,36,65,71,82,103 1U Under GPU 3D3V_VGA_S0 U8301 1 21 DGPU_HOLD_RST# 1 D OPT DIS_OPT 2 2K49R2F-GP DIS_OPT N13P-GS-A1-GP 71.0N13P.00U 669120-001 A A <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU_PCIE/STRAPPING(1/5) Size A2 Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 83 of 103 5 4 3 2 1 LVDS Interface 11 OF 17 VGA1K 6/17 IFPC 10 OF 17 VGA1J 5/17 IFPAB ALL PINS NC FOR GF117 D D ALL PINS NC FOR GF117 AF8 IFPA_TXC# IFPA_TXC AJ8 IFPAB_RSET AF7 IFPA_TXD0# IFPA_TXD0 IFPAB_PLLVDD AN6 AM6 AH8 IFPAB_PLLVDD IFPA_TXD1# IFPA_TXD1 AN3 AP3 IFPC_RSET IFPC_PLLVDD AM5 AN5 IFPC IFPA_TXD2# IFPA_TXD2 IFPA_TXD3# IFPA_TXD3 AH9 AJ9 IFPB_TXD4# IFPB_TXD4 AF6 4 3 IFPB_IOVDD IFPB_TXD5# IFPB_TXD5 RN8402 SRN10KJ-5-GP DIS_OPT IFPC_AUX_I2CW_SDA# IFPC_AUX_I2CW_SCL TXC TXC IFPC_L3# IFPC_L3 TXD0 TXD0 IFPC_L2# IFPC_L2 TXD1 TXD1 IFPC_L1# IFPC_L1 TXD2 TXD2 IFPC_L0# IFPC_L0 IFPC_IOVDD GPIO15 AG2 AG3 AG4 AG5 AH4 AH3 AJ2 AJ3 AJ1 AK1 P2 N13P-GS-A1-GP RN8401 SRN10KJ-5-GP DIS_OPT DIS_OPT AL7 AM7 I2CW_SDA I2CW_SCL AM8 AN8 1 2 IFPB_TXD6# IFPB_TXD6 AP5 AP6 DP 1 2 IFPA_IOVDD AG9 AH6 AJ6 4 3 IFPB_TXC# IFPB_TXC AG8 AK6 AL6 DVI/HDMI IFPB_TXD7# IFPB_TXD7 C AL8 AK8 12 OF 17 VGA1L 7/17 IFPD C ALL PINS NC FOR GF117 GPIO14 IFPAB N4 AN2 IFPD_RSET DVI/HDMI DP I2CX_SDA I2CX_SCL IFPD_AUX_I2CX_SDA# IFPD_AUX_I2CX_SCL N13P-GS-A1-GP AG7 DIS_OPT 71.0N13P.00U IFPD_PLLVDD IFPD 13 OF 17 VGA1M 8/17 IFPEF TXC TXC IFPD_L3# IFPD_L3 TXD0 TXD0 IFPD_L2# IFPD_L2 TXD1 TXD1 IFPD_L1# IFPD_L1 TXD2 TXD2 IFPD_L0# IFPD_L0 ALL PINS NC FOR GF117 DVI-DL DVI-SL/HDMI IFPEF_RSET IFPE B IFPDE_PLL_IO_VDD AC7 TXC TXC TXC TXC IFPE_L3# IFPE_L3 TXD0 TXD0 TXD0 TXD0 IFPE_L2# IFPE_L2 TXD1 TXD1 TXD1 TXD1 IFPE_L1# IFPE_L1 TXD2 TXD2 TXD2 TXD2 IFPE_L0# IFPE_L0 HPD_E HPD_E AL4 AL3 AM4 AM3 AM2 AM1 4 3 AB4 AB3 IFPF_AUX_I2CZ_SDA# IFPF_AUX_I2CZ_SCL AC5 AC4 DIS_OPT AC3 AC2 IFPD_IOVDD GPIO17 M6 N13P-GS-A1-GP RN8404 SRN10KJ-5-GP 71.0N13P.00U DIS_OPT HDMI Interface AC1 AD1 B AD3 AD2 R1 AF2 AF3 IFPF_IOVDD TXC TXC IFPF_L3# IFPF_L3 TXD3 TXD3 TXD0 TXD0 IFPF_L2# IFPF_L2 TXD4 TXD4 TXD1 TXD1 IFPF_L1# IFPF_L1 TXD5 TXD5 TXD2 TXD2 IFPF_L0# IFPF_L0 4 3 RN8403 SRN10KJ-5-GP DIS_OPT 1 2 GPIO18 IFPE_IOVDD I2CZ_SDA I2CZ_SCL AC8 IFPE_AUX_I2CY_SDA# IFPE_AUX_I2CY_SCL IFPEF_PLLVDD 1 2 AD6 I2CY_SDA I2CY_SCL AK5 AK4 DP AG6 I2CY_SDA I2CY_SCL AB8 AK2 AK3 IFPF HPD_F GPIO19 AF1 AG1 AD5 AD4 AF5 AF4 AE4 AE3 P3 N13P-GS-A1-GP A 71.0N13P.00U A DIS_OPT <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU Memory(2/5) Size A2 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 1 Sheet 84 of 103 5 4 3 2 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 OPT 1 R8516 10KR2J-3-GP OPT C TPAD14-OP-GP C12 C20 1D5V_VGA_S0 D6 D7 C6 B6 F26 E26 A26 A27 FBA_PLL_AVDD H17 GPU FBVDDQ Decoupling 1 1 C8517 C8522 DY SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP DY 2 C8523 SC10U10V5KX-2GP SC4D7U6D3V3KX-GP 1 2 C8519 DY 2 2 C8514 DY DY 1 C8513 1 C8525 SC10U10V5KX-2GP DY 1 C8508 C8527 SC4D7U6D3V3KX-GP DY SC4D7U6D3V3KX-GP DY B 1D5V_VGA_S0 DY 1 C8531 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP DY 2 C8518 2 C8524 1 2 C8521 DY 1 C8516 SC10U10V5KX-2GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP DIS_OPT DIS_OPT DIS_OPT C8515 SC4D7U6D3V3KX-GP DY SC10U10V5KX-2GP DY C8512 DY C8530 C8526 2 C8511 1 C8529 DY SCD1U10V2KX-5GP F2 C8503 C8504 SCD1U10V2KX-5GP F1 FB_GND_SENSE SC1U6D3V2KX-GP FBVDDQ_SENSE SC1U6D3V2KX-GP 1 C8507 PLACE CLOSE TO GPU BALLS SCD1U10V2KX-5GP TP8501 C8528 C8501 C8502 SC1U6D3V2KX-GP TPAD14-OP-GP AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27 SCD1U10V2KX-5GP FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 FBVDDQ_44 2 DIS_OPT B PLACE CLOSE TO GPU BALLS VGA1D 14/17 FBVDDQ 1 4 OF 17 C8510 Place under GPU near Place under GPU near DIS_OPT 1D5V_VGA_S0 SC:decap X7R 2 DIS_OPT SC1U6D3V2KX-GP SC22U6D3V5MX-2GP 71.0N13P.00U 1 N13P-GS-A1-GP 2 C8506 DIS_OPT DIS_OPT 1 30ohm@100MHz ESR=0.2 2 FBB_PLL_AVDD F8 E8 A5 A6 D24 D25 B27 C27 1 2 90 90 91 91 2 FBB_WCKB1 FBB_WCKB1# FBB_WCKB23 FBB_WCKB23# FBB_WCKB45 FBB_WCKB45# FBB_WCKB67 FBB_WCKB67# THE FBB_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GF108 AND FOR GF117 FBB_CLK0 FBB_CLK0# FBB_CLK1 FBB_CLK1# 1 FBB_WCK1 FBB_WCK1# FBB_WCK23 FBB_WCK23# FBB_WCK45 FBB_WCK45# FBB_WCK67 FBB_WCK67# 10KR2J-3-GP 2 FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 DIS_OPT D12 E12 E20 F20 2 2 60D4R2F-GP 1 FBB_CLK0 FBB_CLK0# FBB_CLK1 FBB_CLK1# R8509 1 R8510 1 2 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 G14 G20 SC1U16V3KX-5GP C8505 DIS_OPT R8515 10KR2J-3-GP OPT SC1U16V3KX-5GP 1 C8520 R8514 10KR2J-3-GP OPT DIS_OPT FBB_DEBUG0 FBB_DEBUG1 FCM1005KF-300T03-GP N13P-GS-A1-GP R8513 10KR2J-3-GP OPT 1 1 D9 E4 B2 A9 D22 D28 A30 B23 R8512 10KR2J-3-GP OPT 2 FBA_PLL_AVDD U27 FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 R8511 10KR2J-3-GP OPT SC1U16V3KX-5GP 1D05V_VGA_S0 L8501 90 90 90 90 91 91 91 91 D10 D5 C3 B9 E23 E28 B30 A23 R8508 10KR2J-3-GP OPT SC1U16V3KX-5GP J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 R8507 10KR2J-3-GP 1 K31 L30 H34 J34 AG30 AG31 AJ34 AK34 90 90 90 90 91 91 91 91 TPAD14-OP-GP 2 FBA_PLL_AVDD 88 88 89 89 1 FBA_CMD2 FBA_CMD3 FBA_CMD5 FBA_CMD18 1 FB_VREF FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# FBB_CMD31 OPT FBB_CMD2 FBB_CMD3 FBB_CMD5 FBB_CMD18 2 FBA_WCKB1 FBA_WCKB1# FBA_WCKB23 FBA_WCKB23# FBA_WCKB45 FBA_WCKB45# FBA_WCKB67 FBA_WCKB67# R30 R31 AB31 AC31 10KR2J-3-GP FBB_CMD_RFU0 FBB_CMD_RFU1 R8518 10KR2J-3-GP OPT 1 FBA_WCK1 FBA_WCK1# FBA_WCK23 FBA_WCK23# FBA_WCK45 FBA_WCK45# FBA_WCK67 FBA_WCK67# 2 2 60D4R2F-GP DIS_OPT FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 R8517 10KR2J-3-GP 2 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 DIS_OPT R8503 1 R8506 1 E11 E3 A3 C9 F23 F27 C30 A24 91 91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 TP8512 FBB_CMD19 TPAD14-OP-GP 2 FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# R28 AC28 FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 TP8515 1 90 90 90 90 91 91 91 91 90 90 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 91 TP8513 2 2 R32 AC32 1 90 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 1 TPAD14-OP-GP FBB_CMD17 FBB_CMD0 1 1 91 FBB_D[56..63] 1 2 FBA_DEBUG0 FBA_DEBUG1 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 71.0N13P.00U 91 FBB_D[48..55] FBB_CMD1 2 H26 89 89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 TP8509 D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17 1 FB_VREF FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 91 FBB_D[40..47] FBA_CMD19 FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 1 1 TP8505 TPAD14-OP-GP 88 88 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 89 TP8508 TPAD14-OP-GP 2 TP8503 1 88 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 1D5V_VGA_S0 THE FBA_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GF108 AND FOR GF117 TPAD14-OP-GP FBA_CMD31 1 91 FBB_D[32..39] FBA_CMD0 2 M30 H30 E34 M34 AF30 AK31 AM34 AF32 FBA_CMD17 1 1 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 FBA_CMD_RFU0 FBA_CMD_RFU1 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 1 88 88 88 88 89 89 89 89 M31 G31 E33 M33 AE31 AK30 AN33 AF33 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31 2 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 2 88 88 88 88 89 89 89 89 90 FBB_D[24..31] 1 P30 F31 F34 M32 AD31 AL29 AM32 AF34 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 90 FBB_D[16..23] 2 88 88 88 88 89 89 89 89 Place close to Ball D SCD1U10V2KX-5GP C DIS_OPT FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 1 89 FBA_D[56..63] 90 FBB_D[8..15] C8509 1 89 FBA_D[48..55] X7R G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26 2 89 FBA_D[40..47] Layout note:FBA_PLL_AVDD=16mil 2 89 FBA_D[32..39] FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 FBA_PLL_AVDD K27 SCD1U10V2KX-5GP 88 FBA_D[24..31] FB_DLL_AVDD 90 FBB_D[0..7] E1 SC1U16V3KX-5GP 88 FBA_D[16..23] FB_CLAMP SCD1U10V2KX-5GP 88 FBA_D[8..15] FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 2 D 3 OF 17 VGA1C 3/17 FBB L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33 1 2 OF 17 VGA1B 2/17 FBA 88 FBA_D[0..7] FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 2 DY DIS_OPT DIS_OPT DIS_OPT X7R, Under GPU. FB_VDDQ_SENSE 1D5V_VGA_S0 TP8502 1 TPAD14-OP-GP FB_GND_SENSE R8501 2 FB_CAL_PD_VDDQ J27 FB_CAL_PU_GND H27 FB_CAL_TERM_GND H25 1 40D2R2F-GP DIS_OPT FB_CAL_PD_VDDQ FB_CAL_PU_GND FB_CAL_TERM_GND 2 2 N13P-GS-A1-GP 1 51R2J-2-GP 42D2R2F-GP OPT R8502 1 R8504 A 71.0N13P.00U DIS_OPT A OPT <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU_DP/LVDS/CRT/GPIO(3/5) Size A1 Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 85 of 103 5 4 3 2 1 3D3V_VGA_S0 14 OF 17 VGA1N 4/17 DACA 1 2 AL9 FCM1608KF-181T00-GP 1 DIS_OPT 2 D DIS_OPT NC VID_PLLVDD GF117 C8602 SCD1U10V2KX-5GP VIDEO_CLK_XTAL_SS 1 TPAD14-OP-GP H1 XTAL_SSIN H3 XTAL_OUTBUFF XTAL_IN XTAL_OUT N12P_XTAL_OUTBUFF J4 H2 N13P-GS-A1-GP 20PF 5% 50V +/-0.25PF 0402 DIS_OPT 71.0N13P.00U R8607 10KR2J-3-GP R8609 27MHZ_IN 2 SC4D7U6D3V3KX-GP SCD1U10V2KX-5GP 2 PLLVDD SP_PLLVDD GF108/GKx C8604 TP8603 71.0N13P.00U AD8 AE8 AD7 C8603 SC22U6D3V5MX-2GP DIS_OPT C8601 GPU_PLL_VDD SP_PLLVDD 1 L8602 AL10 N13P-GS-A1-GP 15 OF 17 VGA1O 11/17 XTAL_PLL C8606 DY R8608 10KR2J-3-GP 2 1 DIS_OPT 1 DACA_BLUE FCM1005KF-181T00-GP C8605 DIS_OPT DIS_OPT 1 DACA_GREEN NC AK9 2 NC D AM9 AN9 1 DACA_RED NC DACA_RSET 2 1 DACA_HSYNC DACA_VSYNC NC L8601 1 2 NC NC 22K2R2J-2-GP 22K2R2J-2-GP TSEN_VREF DACA_VREF AP8 R4 1 R8605 R5 1 R8606 2 I2CA_SCL I2CA_SDA 2 AP9 GF108/GKx SC22U6D3V5MX-2GP NC NC SCD1U10V2KX-5GP GF117 NC 2 DIS_OPT GF117 DACA_VDD 1 1 AG10 NV request to need to be keeped 1D05V_VGA_S0 GF108/GKx DACA_VDD R8612 10KR2J-3-GP 1 1MR2J-1-GP 2 27MHZ_OUT 2 X8601 DIS_OPTDIS_OPT DIS_OPT DIS_OPT DIS_OPT DIS_OPT 1 4 2 3 R8610 390R2J-1-GP DIS_OPT 01/04/12 N13P-GL 1 DIS_OPT A Y 3 5 DY 4 1 GND 2 27MHZ_IN 82.30034.641 R8638 0R2J-2-GP 74LVC1G08GW-1-GP C8608 SC12P50V2JN-3GP DIS_OPT 2ND = 82.30034.651 3RD = 82.30034.681 73.01G08.L04 2ND = 73.7SZ08.DAH 3D3V_VGA_S0 R8630 2 DIS_OPT C8607 SC12P50V2JN-3GP XTAL-27MHZ-85-GP SB 2 VCC 2 92,93 PWR_VGA_CORE_PGOOD 1 B 2 1 18 CLK_27M_VGA 27MHZ_OUT_R 1 3D3V_S0 U8602 DY 1 0R0402-PAD 3D3V_VGA_S0 PURE_HW_SHUTDOWN# Q8601 1 6 2 5 3 4 27,28,36 SML1_CLK 18,27,29,79 SML1_DATA SMBD_THERM_NV 1 2 2N7002KDW-GP U8601 2N7002K-2-GP DIS_OPT 3D3V_VGA_S0 84.2N702.A3F SMBC_THERM_NV SMBD_THERM_NV G 2nd = 84.2N702.E3F 3RD = 84.2N702.F3F S 18,27,29,79 DIS_OPT D 4 3 SMBC_THERM_NV RN8601 SRN4K7J-8-GP C C GPIO8_OVERT# 3D3V_VGA_S0 3D3V_S0 I2CC_SCL I2CC_SDA AM10 AP11 AM11 AP12 AN11 R7 1 R8603 R6 1 R8604 2 22K2R2J-2-GP 22K2R2J-2-GP 1 2 RN8602 SRN10KJ-5-GP 2 10KR2J-3-GP GPU_DPRSLP 92 3 VGAGPIO16 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO16 GPIO20 GPIO21 R2 PDTC144EU-1-GP Q8603 P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 R8 P4 P1 1 R1 DIS_OPT 2 1 DIS_OPT DIS_OPT DIS_OPT DIS_OPT JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST# R8636 1 R1 2 THERMDP 4 3 N12P_GPIO_JTAG_TRST DIS_OPT 3 1 DIS_OPT 3D3V_VGA_S0 VID4 VID3 N12P_GPIO7_H51 GPIO8_OVERT# N12P_GPIO9_J71 GPIO10_VREFCTRL TP8607 VID0 2ND = 84.05144.011 84.00144.I11 R8617 10KR2J-3-GP 2ND = 84.05144.011 DIS_OPT TPAD14-OP-GP TP8610 TPAD14-OP-GP 1 R8611 10KR2J-3-GP DIS_OPT 92 D8601 PWR_LEVEL A VID5 92 TP8608 TPAD14-OP-GP VGAGPIO16 1 84.00144.I11 R8635 2K2R2J-2-GP DIS_OPT 3D3V_VGA_S0 92 92 VID1 92 VID2 92 TPAD14-OP-GP TP8609 R2 PDTC144EU-1-GP 2 N12P_JTAG_TMS N12P_JTAG_TDI N12P_JTAG_TDO 1 1 1 K3 THERMDN R8637 2K2R2J-2-GP Q8602 22K2R2J-2-GP 22K2R2J-2-GP 1 TP8602 TP8606 TP8601 P2800_GPU_DXP 1 K4 R2 1 R8601 R3 1 R8602 84.2N702.J31 2ND = 84.2N702.W31 DY 2 TPAD14-OP-GP TPAD14-OP-GP TPAD14-OP-GP TP8605 P2800_GPU_DXN 1 DIS_OPT SMBC_THERM_NV SMBD_THERM_NV 1 TPAD14-OP-GP TP8604 I2CB_SCL I2CB_SDA T4 T3 2 TPAD14-OP-GP 3D3V_VGA_S0 17 OF 17 I2CS_SCL I2CS_SDA 1 DIS_OPT VGA1Q 10/19 MISC1 K AC_PRESENT 19,27 1SS355GP-GP 83.00355.F1F 2ND = 83.00355.D1F D8602 A N13P-GS-A1-GP K DIS_OPT GPU_PROTECT# 27 1SS355GP-GP 83.00355.F1F 71.0N13P.00U 2ND = 83.00355.D1F DIS_OPT 3D3V_VGA_S0 16 OF 17 VGA1P 2 12/17 MISC2 B B R8632 10KR2J-3-GP STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 J2 J7 J6 J5 J3 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 ROM_SI ROM_SO ROM_SCLK H6 ROM_CS# H5 H7 H4 ROM_SI_D3 ROM_SO_C4 ROM_SLK_D4 1 DY ROM_CS# 3D3V_VGA_S0 2 R8634 BUFRST# L2 2 UP N13P-GL 1 10KR2J-3-GP J1 MULTI_STRAP_REF0_GND CEC L3 R8633 10KR2J-3-GP 1 STRAP_REF0_GND_N9 1 R8633=UP R8633=DY N13P-GL N13P-GS/GT R8613 2 40K2R2F-GP DIS_OPT N13P-GS-A1-GP DIS_OPT 3D3V_VGA_S0 3D3V_VGA_S0 10KR by NV 1 2 1 2 2 1 DY R8620 15KR2F-GP R8614 10KR2J-3-GP 2 2 ROM SI_D R8615 15KR2F-GP DIS_ROM_SCLK_D 2 24K9R2F-L-GP 1 1 1 1 A R8621 20KR2F-L-GP DY R8627 2 1 1 R8625 45K3R2F-L-GP DIS_STRAP1_D 2 DY 2 2 2 DIS_STRAP4_D DIS_STRAP3_D R8619 10KR2F-2-GP DY ROM_SI_D3 ROM_SO_C4 ROM_SLK_D4 R8623 2KR2J-1-GP 1 R8616 10KR2J-3-GP R8618 2KR2F-3-GP DY 2 1 R8626 10KR2F-2-GP R8624 DIS_STRAP2_U 34K8R2F-1-GP 2 2 2 DY STRAP0 STRAP1 STRAP2 1 STRAP3 STRAP4 R8631 4K99R2F-L-GP R8622 45K3R2F-L-GP DY 2 DY 1 1 R8629 4K99R2F-L-GP 45K3R2F-L-GP A DIS_STRAP0_U 1 R8628 1 3D3V_VGA_S0 DIS_ROM_S0_D <Core Design> Wistron Corporation N13P-GL 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU_POWER(4/5) Size A1 Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 86 of 103 5 4 3 2 VGA1I EDP 60A (TDP 55W) A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 A33 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AA15 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22 VGA_CORE 6 OF 17 VGA1F 13/17 NVVDD Under GPUSC:decap AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22 D C8702 2 2 C8701 2 C8703 1 1 1 1 2 1 2 C8704 SC4D7U6D3V3KX-GP 2 DIS_OPTDIS_OPT SC4D7U6D3V3KX-GP 2 DY SC4D7U6D3V3KX-GP C8712 DY SC4D7U6D3V3KX-GP 2 C8711 SC10U6D3V3MX-GP C8713 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP C8714 1 1 1 DIS_OPT DIS_OPTDIS_OPT 2 2 1 2 2 1 2 1 2 1 1 1 1 2 2 1 2 2 C8715 2 2 1 1 1 1 1 2 2 2 1 2 1 2 1 2 1 2 1 1 2 2 DY DY C8716 SC4D7U6D3V3KX-GP C8710 DY SC4D7U6D3V3KX-GP 2 C8717 SC1U6D3V2KX-GP 1 C8718 SC1U6D3V2KX-GP C8708 DY SC4D7U6D3V3KX-GP C8705 DY SC4D7U6D3V3KX-GP SC47U6D3V5MX-1-GP SC22U6D3V5MX-2GP SE330U2VDM-L-GP 2 C8725 SC4D7U6D3V3KX-GP C8719 SC1U6D3V2KX-GP C8706 DIS_OPT C8726 NEAR TO GPU SC4D7U6D3V3KX-GP C8707 DY C8720 SC1U6D3V2KX-GP TC8701 DY SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC:decap C8723 C8727 SC4D7U6D3V3KX-GP C8724 C8728 SC4D7U6D3V3KX-GP C8721 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C C8722 C8729 SC4D7U6D3V3KX-GP SC:decap C8730 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP C8731 1 1 1 DIS_OPTDIS_OPTDIS_OPTDIS_OPT DIS_OPTDIS_OPT DIS_OPT VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 1 9 OF 17 15/17 GND_1/2 GND_1 GND_71 GND_5 GND_72 GND_6 GND_73 GND_7 GND_74 GND_8 GND_75 GND_9 GND_76 GND_10 GND_77 GND_11 GND_78 GND_12 GND_79 GND_13 GND_80 GND_14 GND_81 GND_2 GND_82 GND_15 GND_83 GND_16 GND_84 GND_17 GND_85 GND_18 GND_86 GND_19 GND_87 GND_20 GND_88 GND_21 GND_89 GND_22 GND_90 GND_23 GND_91 GND_24 GND_92 GND_3 GND_93 GND_25 GND_94 GND_26 GND_95 GND_27 GND_96 GND_28 GND_97 GND_29 GND_98 GND_30 GND_99 GND_31 GND_100 GND_32 GND_101 GND_33 GND_102 GND_34 GND_103 GND_4 GND_104 GND_35 GND_105 GND_36 GND_106 GND_37 GND_107 GND_38 GND_108 GND_39 GND_109 GND_40 GND_110 GND_41 GND_111 GND_42 GND_112 GND_43 GND_113 GND_44 GND_114 GND_45 GND_115 GND_46 GND_116 GND_47 GND_117 GND_48 GND_118 GND_49 GND_119 GND_50 GND_120 GND_51 GND_121 GND_52 GND_122 GND_53 GND_123 GND_54 GND_124 GND_55 GND_125 GND_56 GND_126 GND_57 GND_127 GND_58 GND_128 GND_59 GND_129 GND_60 GND_130 GND_61 GND_131 GND_62 GND_132 GND_63 GND_133 GND_64 GND_134 GND_65 GND_135 GND_66 GND_136 GND_67 GND_137 GND_68 GND_138 GND_69 GND_139 GND_70 GND_140 8 OF 17 VGA1H AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 16/17 GND_2/2 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_F GND_H GND_OPT_1 GND_OPT_2 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 D AH11 C16 W32 Optional CMD GNDs (2) NC for 4-Lyr cards C N13P-GS-A1-GP DIS_OPT 71.0N13P.00U N13P-GS-A1-GP 71.0N13P.00U DIS_OPT VGA1E 5 OF 17 B N13P-GS-A1-GP 9/17 XVDD 71.0N13P.00U DIS_OPT CONFIGURABLE POWER CHANNELS B XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 7 OF 17 VGA1G 17/17 NC/VDD33 N13P-GS-A1-GP 0.1U Under GPU DIS_OPT 71.0N13P.00U 4.7U NEAR TO GPU XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 DIS_OPT 1 1 X7R C8735 V1 V2 V3 V4 V5 V6 V7 V8 XVDD_1~38=No Connect C8736 2 C8733 2 C8732 2 X7R 1 1 X7R 2 1 2 1 2 C8734 SC4D7U6D3V3KX-GP DIS_OPT X7R SCD1U10V2KX-5GP DIS_OPTDIS_OPT DIS_OPT DIS_OPT C8709 SC1U6D3V2KX-GP SCD1U10V2KX-5GP VDD33_1 VDD33_2 VDD33_3 VDD33_4 SCD1U10V2KX-5GP NC#AC6 NC#AJ28 NC#AJ4 NC#AJ5 NC#AL11 NC#C15 NC#D19 NC#D20 NC#D23 NC#D26 NC#H31 NC#T8 NC#V32 3D3V_VGA_S0 J8 K8 L8 M8 SCD1U10V2KX-5GP AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32 U1 U2 U3 U4 U5 U6 U7 U8 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22 A 1U NEAR TO GPU DIS_OPT 71.0N13P.00U W2 W3 W4 W5 W7 W8 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 A <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU_DPPWR/GND(5/5) Size Custom N13P-GS-A1-GP Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 Sheet 1 87 of 103 5 4 3 2 1 D D Frame Buffer Patition A-Lower Half DMU DML WE# CAS# RAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 1 1 2 2 2 FBA_DQS_WP2 85 FBA_DQS_RN2 85 F3 G3 FBA_DQS_WP1 85 FBA_DQS_RN1 85 K1 FBA_CMD2 85 L2 T2 FBA_CMD4 85,89 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 OPT 1 VRAM1_VREF VRAM2_VREF VRAM_ZQ2 2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ 243R2F-2-GP N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 85,89 FBA_CMD12 85,89 FBA_CMD27 85,89 FBA_CMD26 M2 N8 M3 85 85 FBA_CLK0 FBA_CLK0# J7 K7 85 FBA_CMD3 K9 85 85 FBA_DQM3 FBA_DQM0 D3 E7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU DQSU# DQSL DQSL# ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BA0 BA1 BA2 CK CK# CS# RESET# NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CKE DMU DML L3 K3 J3 85,89 FBA_CMD13 85,89 FBA_CMD15 85,89 FBA_CMD30 VRAM18 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 C8828 OPT OPT 2 K8 K2 N1 R9 B2 D9 G7 R1 N9 FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD14 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 FBA_CMD0 85 FBA_CMD5 85,89 T7 L9 L1 J9 J1 2 1 R8802 C8830 2 OPT C7 B7 1 1 2 1 2 1 1 2 2 1 C8833 WE# CAS# RAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP 72.52G63.A0U 72.52G63.A0U 2 R8807 C8803 SCD1U10V2KX-5GP OPT 2 OPT 2 2 1K33R2F-GP FBA_CLK0# FBA_D[24..31] 85 C7 B7 FBA_DQS_WP3 85 FBA_DQS_RN3 85 F3 G3 FBA_DQS_WP0 85 FBA_DQS_RN0 85 K1 FBA_CMD2 85 L2 T2 C FBA_CMD0 85 FBA_CMD5 85,89 T7 L9 L1 J9 J1 FBA_CMD4 85,89 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 B VRAM2_VREF 1 1 2 1 VRAM1_VREF 2 OPT FBA_D27 FBA_D28 FBA_D26 FBA_D30 FBA_D25 FBA_D31 FBA_D24 FBA_D29 85 OPT 1K33R2F-GP 1 R8806 OPT D7 C3 C8 C2 A7 A2 B8 A3 FBA_D[0..7] R8808 OPT R8809 162R2F-GP FBA_D1 FBA_D4 FBA_D3 FBA_D7 FBA_D2 FBA_D5 FBA_D0 FBA_D6 1 R8805 FBA_CLK0 E3 F7 F2 F8 H3 H8 G2 H7 1D5V_VGA_S0 1 1D5V_VGA_S0 1 L3 K3 J3 CKE C8834 C8820 OPT C8805 SCD1U10V2KX-5GP OPT 2 85,89 FBA_CMD13 85,89 FBA_CMD15 85,89 FBA_CMD30 D3 E7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C8819 DY 1K33R2F-GP FBA_DQM2 FBA_DQM1 CK CK# NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 C8817 DY 1K33R2F-GP 85 85 1 1 2 K9 BA0 BA1 BA2 CS# RESET# 85 1 2 2 J7 K7 FBA_CMD3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 FBA_D[16..23] 2 2 2 2 1 1 1 2 2 1 1 1 1 2 1 2 FBA_CLK0 FBA_CLK0# 85 ODT C8818 DY SCD1U10V2KX-5GP 85 85 DQSL DQSL# FBA_D18 FBA_D20 FBA_D16 FBA_D21 FBA_D17 FBA_D22 FBA_D19 FBA_D23 85 SC1U6D3V2KX-GP M2 N8 M3 SC1U6D3V2KX-GP 85,89 FBA_CMD12 85,89 FBA_CMD27 85,89 FBA_CMD26 DQSU DQSU# D7 C3 C8 C2 A7 A2 B8 A3 FBA_D[8..15] SCD1U10V2KX-5GP N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 VREFDQ VREFCA ZQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 FBA_D9 FBA_D13 FBA_D8 FBA_D14 FBA_D11 FBA_D12 FBA_D10 FBA_D15 SC1U6D3V2KX-GP 243R2F-2-GP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 SC1U6D3V2KX-GP H1 M8 L8 VRAM18 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 SC1U6D3V2KX-GP VRAM1_VREF VRAM2_VREF VRAM_ZQ1 C8814 OPT VRAM17 VDD VDD VDD VDD VDD VDD VDD VDD VDD SCD1U10V2KX-5GP 2 A8 A1 C1 C9 D2 E9 F1 H9 H2 FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD14 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 B OPT K8 K2 N1 R9 B2 D9 G7 R1 N9 SC1U6D3V2KX-GP C OPT C8827 SCD1U10V2KX-5GP 1 R8801 C8829 SC1U6D3V2KX-GP OPT SCD1U10V2KX-5GP SCD1U10V2KX-5GP OPT C8831 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP C8832 C8812 DY C8815 OPT SC1U6D3V2KX-GP C8813 OPT C8821 OPT SC1U6D3V2KX-GP C8810 OPT C8816 OPT VRAM17 C8811 OPT 1D5V_VGA_S0 SC1U6D3V2KX-GP 2 C8806 OPT SC1U6D3V2KX-GP SC1U6D3V2KX-GP OPT SC1U6D3V2KX-GP 2 C8807 1 C8809 OPT SC1U6D3V2KX-GP 2 1 C8808 OPT 1 1 1D5V_VGA_S0 A A <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: 5 4 3 2 GPU-VRAM1,2 (1/4) Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 88 of 103 5 4 3 2 1 Frame Buffer Patition A-Upper Half D D3 E7 L3 K3 J3 85,88 FBA_CMD13 85,88 FBA_CMD15 85,88 FBA_CMD30 B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CKE DMU DML WE# CAS# RAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C7 B7 FBA_DQS_WP4 85 FBA_DQS_RN4 85 F3 G3 FBA_DQS_WP7 85 FBA_DQS_RN7 85 K1 FBA_CMD18 85 L2 T2 FBA_CMD16 85 FBA_CMD5 85,88 T7 L9 L1 J9 J1 1 R8901 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 OPT 1 1 2 2 1 2 1 2 1 C8923 OPT A8 A1 C1 C9 D2 E9 F1 H9 H2 C8924 OPT 2 2 K8 K2 N1 R9 B2 D9 G7 R1 N9 VRAM3_VREF VRAM4_VREF VRAM_ZQ4 2 H1 M8 L8 243R2F-2-GP FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 85,88 FBA_CMD12 85,88 FBA_CMD27 85,88 FBA_CMD26 M2 N8 M3 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 FBA_CMD4 85,88 1 1 2 1 OPT 2 1 2 1 OPT C8922 C8907 OPT 85 85 FBA_CLK1 FBA_CLK1# J7 K7 85 FBA_CMD19 K9 85 85 FBA_DQM5 FBA_DQM6 D3 E7 L3 K3 J3 85,88 FBA_CMD13 85,88 FBA_CMD15 85,88 FBA_CMD30 VRAM20 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREFDQ VREFCA ZQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU DQSU# DQSL DQSL# ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BA0 BA1 BA2 CK CK# CS# RESET# NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CKE DMU DML WE# CAS# RAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP 72.52G63.A0U 72.52G63.A0U FBA_D[40..47] 85 C7 B7 FBA_DQS_WP5 85 FBA_DQS_RN5 85 F3 G3 FBA_DQS_WP6 85 FBA_DQS_RN6 85 K1 FBA_CMD18 85 L2 T2 T7 L9 L1 J9 J1 C FBA_CMD16 85 FBA_CMD5 85,88 FBA_CMD4 85,88 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 B VRAM4_VREF 2 1 1 VRAM3_VREF R8903 C8911 SCD1U10V2KX-5GP OPT OPT 2 2 2 1 2 FBA_CLK1# 1K33R2F-GP OPT FBA_D43 FBA_D46 FBA_D42 FBA_D44 FBA_D41 FBA_D45 FBA_D40 FBA_D47 85 OPT 1K33R2F-GP 1 2 R8905 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D[48..55] R8906 OPT OPT FBA_D49 FBA_D53 FBA_D51 FBA_D52 FBA_D50 FBA_D54 FBA_D48 FBA_D55 1 R8904 R8909 162R2F-GP E3 F7 F2 F8 H3 H8 G2 H7 1D5V_VGA_S0 1 1D5V_VGA_S0 FBA_CLK1 1 FBA_DQM4 FBA_DQM7 CK CK# NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 C8921 C8915 OPT 1K33R2F-GP 85 85 BA0 BA1 BA2 CS# RESET# 85 C8906 OPT 1K33R2F-GP K9 2 2 J7 K7 FBA_CMD19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 FBA_D[32..39] 2 2 1 2 2 1 2 FBA_CLK1 FBA_CLK1# 85 1 1 1 1 1 1 2 1 2 1 2 1 2 85 85 ODT C8905 DY SCD1U10V2KX-5GP M2 N8 M3 DQSL DQSL# FBA_D32 FBA_D36 FBA_D34 FBA_D38 FBA_D33 FBA_D37 FBA_D39 FBA_D35 85 SC1U6D3V2KX-GP 85,88 FBA_CMD12 85,88 FBA_CMD27 85,88 FBA_CMD26 SC1U6D3V2KX-GP N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 DQSU DQSU# D7 C3 C8 C2 A7 A2 B8 A3 FBA_D[56..63] SC1U6D3V2KX-GP FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD14 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 VREFDQ VREFCA ZQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 FBA_D59 FBA_D62 FBA_D58 FBA_D63 FBA_D57 FBA_D61 FBA_D56 FBA_D60 SC1U6D3V2KX-GP 243R2F-2-GP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 SCD1U10V2KX-5GP H1 M8 L8 C8912 DY VRAM20 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 SC1U6D3V2KX-GP 2 VRAM3_VREF VRAM4_VREF VRAM_ZQ3 A8 A1 C1 C9 D2 E9 F1 H9 H2 C8918 OPT VRAM19 VDD VDD VDD VDD VDD VDD VDD VDD VDD SCD1U10V2KX-5GP OPT K8 K2 N1 R9 B2 D9 G7 R1 N9 SC1U6D3V2KX-GP C8930 SCD1U10V2KX-5GP OPT SCD1U10V2KX-5GP OPT C8910 DY SC1U6D3V2KX-GP C8925 OPT 1 R8902 SC1U6D3V2KX-GP C8926 SC1U6D3V2KX-GP SCD1U10V2KX-5GP C C8928 OPT SC1U6D3V2KX-GP SC1U6D3V2KX-GP C8927 OPT C8908 OPT C8916 DY SC1U6D3V2KX-GP VRAM19 C8909 DY C8917 OPT SC1U6D3V2KX-GP C8913 SC1U6D3V2KX-GP 2 1D5V_VGA_S0 SCD1U10V2KX-4GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 C8919 DY 2 C8929 OPT SC1U6D3V2KX-GP 2 1 C8920 OPT 1 1 1D5V_VGA_S0 C8914 SCD1U10V2KX-5GP OPT 2 D A A <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: 5 4 3 2 GPU-VRAM3,4 (2/4) Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 89 of 103 5 4 3 2 1 D D Frame Buffer Patition B-Lower Half 2 1 2 1 1 2 2 CKE VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DMU DML WE# CAS# RAS# K1 FBB_CMD2 85 L2 T2 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 OPT 1 2 1 2 1 OPT 2 2 VRAM5_VREF VRAM6_VREF VRAM_ZQ6 2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ 243R2F-2-GP FBB_CMD9 FBB_CMD11 FBB_CMD8 FBB_CMD25 FBB_CMD10 FBB_CMD24 FBB_CMD22 FBB_CMD7 FBB_CMD21 FBB_CMD6 FBB_CMD29 FBB_CMD23 FBB_CMD28 FBB_CMD20 FBB_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 85,91 FBB_CMD12 85,91 FBB_CMD27 85,91 FBB_CMD26 M2 N8 M3 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 FBB_CMD4 85,91 1 1 2 1 1 R9001 FBB_CMD0 85 FBB_CMD5 85,91 T7 L9 L1 J9 J1 2 1 2 1 FBB_DQS_WP1 85 FBB_DQS_RN1 85 OPT 85 85 FBB_CLK0 FBB_CLK0# J7 K7 85 FBB_CMD3 K9 85 85 FBB_DQM3 FBB_DQM0 D3 E7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU DQSU# DQSL DQSL# ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BA0 BA1 BA2 CK CK# CS# RESET# NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CKE DMU DML L3 K3 J3 85,91 FBB_CMD13 85,91 FBB_CMD15 85,91 FBB_CMD30 VRAM22 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 C9022 WE# CAS# RAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP 72.52G63.A0U 72.52G63.A0U FBB_D[24..31] 85 C7 B7 FBB_DQS_WP3 85 FBB_DQS_RN3 85 F3 G3 FBB_DQS_WP0 85 FBB_DQS_RN0 85 K1 FBB_CMD2 85 L2 T2 C FBB_CMD0 85 FBB_CMD5 85,91 T7 L9 L1 J9 J1 FBB_CMD4 85,91 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 B VRAM6_VREF 2 1 1 VRAM5_VREF R9002 C9011 SCD1U10V2KX-5GP OPT OPT 2 2 2 1 2 FBB_CLK0# 1K33R2F-GP OPT FBB_D26 FBB_D30 FBB_D25 FBB_D31 FBB_D24 FBB_D28 FBB_D27 FBB_D29 85 OPT 1K33R2F-GP 1 2 R9005 D7 C3 C8 C2 A7 A2 B8 A3 FBB_D[0..7] R9006 OPT OPT FBB_D1 FBB_D4 FBB_D3 FBB_D5 FBB_D2 FBB_D6 FBB_D0 FBB_D7 1 R9003 R9009 162R2F-GP E3 F7 F2 F8 H3 H8 G2 H7 1D5V_VGA_S0 1 1D5V_VGA_S0 FBB_CLK0 1 L3 K3 J3 CK CK# FBB_DQS_WP2 85 FBB_DQS_RN2 85 F3 G3 DY C9012 K8 K2 N1 R9 B2 D9 G7 R1 N9 C9014 SCD1U10V2KX-5GP OPT 2 85,91 FBB_CMD13 85,91 FBB_CMD15 85,91 FBB_CMD30 D3 E7 BA0 BA1 BA2 C7 B7 C9025 C9005 DY 1K33R2F-GP FBB_DQM2 FBB_DQM1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C9026 C9006 DY 1K33R2F-GP 85 85 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 85 2 2 1 2 2 2 1 1 2 1 1 2 1 1 2 1 2 K9 CS# RESET# FBB_D[16..23] C9004 OPT SCD1U10V2KX-5GP J7 K7 FBB_CMD3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 C9017 DY SC1U6D3V2KX-GP FBB_CLK0 FBB_CLK0# 85 SC1U6D3V2KX-GP 85 85 ODT FBB_D18 FBB_D20 FBB_D16 FBB_D22 FBB_D17 FBB_D23 FBB_D19 FBB_D21 85 SCD1U10V2KX-5GP M2 N8 M3 DQSL DQSL# D7 C3 C8 C2 A7 A2 B8 A3 FBB_D[8..15] SC1U6D3V2KX-GP 85,91 FBB_CMD12 85,91 FBB_CMD27 85,91 FBB_CMD26 SC1U6D3V2KX-GP N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 DQSU DQSU# VREFDQ VREFCA ZQ FBB_D9 FBB_D13 FBB_D11 FBB_D12 FBB_D10 FBB_D15 FBB_D8 FBB_D14 SCD1U10V2KX-5GP 243R2F-2-GP DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 SC1U6D3V2KX-GP H1 M8 L8 SC1U6D3V2KX-GP VRAM5_VREF VRAM6_VREF VRAM_ZQ5 C9015 OPT VRAM22 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 SC1U6D3V2KX-GP 2 SCD1U10V2KX-5GP OPT A8 A1 C1 C9 D2 E9 F1 H9 H2 C9021 DY VRAM21 VDD VDD VDD VDD VDD VDD VDD VDD VDD SC1U6D3V2KX-GP C9019 K8 K2 N1 R9 B2 D9 G7 R1 N9 C9018 OPT SC1U6D3V2KX-GP SC1U6D3V2KX-GP SCD1U10V2KX-5GP OPT SC1U6D3V2KX-GP OPT C9001 OPT FBB_CMD9 FBB_CMD11 FBB_CMD8 FBB_CMD25 FBB_CMD10 FBB_CMD24 FBB_CMD22 FBB_CMD7 FBB_CMD21 FBB_CMD6 FBB_CMD29 FBB_CMD23 FBB_CMD28 FBB_CMD20 FBB_CMD14 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 B C9008 SCD1U10V2KX-5GP SCD1U10V2KX-5GP C C9024 OPT 1 R9004 C9002 OPT SC1U6D3V2KX-GP SC1U6D3V2KX-GP C9023 OPT C9003 DY C9016 OPT VRAM21 C9007 OPT 1D5V_VGA_S0 1 C9009 OPT SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 1 C9020 DY 2 1 C9013 DY SC1U6D3V2KX-GP 2 1 C9010 DY 2 1 1D5V_VGA_S0 A A <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: 5 4 3 2 GPU-VRAM5,6 (3/4) Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 90 of 103 4 3 Frame Buffer Patition B-Upper Half 85 85 L3 K3 J3 85,90 FBB_CMD13 85,90 FBB_CMD15 85,90 FBB_CMD30 2 1 2 1 1 2 2 D3 E7 FBB_DQM4 FBB_DQM7 CK CK# CKE DMU DML WE# CAS# RAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C7 B7 FBB_DQS_WP4 85 FBB_DQS_RN4 85 F3 G3 FBB_DQS_WP7 85 FBB_DQS_RN7 85 K1 FBB_CMD18 85 L2 T2 T7 L9 L1 J9 J1 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 OPT 1 1 2 1 1 2 2 1 OPT K8 K2 N1 R9 B2 D9 G7 R1 N9 A8 A1 C1 C9 D2 E9 F1 H9 H2 C9121 OPT VRAM7_VREF VRAM8_VREF VRAM_ZQ8 2 H1 M8 L8 243R2F-2-GP FBB_CMD9 FBB_CMD11 FBB_CMD8 FBB_CMD25 FBB_CMD10 FBB_CMD24 FBB_CMD22 FBB_CMD7 FBB_CMD21 FBB_CMD6 FBB_CMD29 FBB_CMD23 FBB_CMD28 FBB_CMD20 FBB_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 85,90 FBB_CMD12 85,90 FBB_CMD27 85,90 FBB_CMD26 M2 N8 M3 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 FBB_CMD4 85,90 C9122 OPT 1 R9102 FBB_CMD16 85 FBB_CMD5 85,90 C9124 C9106 DY 2 OPT 1 1 2 C9123 C9115 OPT 2 2 K9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 85 1 2 2 1 2 1 2 2 1 1 1 2 1 1 2 1 2 J7 K7 FBB_CMD19 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 FBB_D[32..39] C9104 OPT SCD1U10V2KX-5GP FBB_CLK1 FBB_CLK1# 85 BA0 BA1 BA2 CS# RESET# C9105 OPT SC1U6D3V2KX-GP 85 85 SC1U6D3V2KX-GP M2 N8 M3 ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 FBB_D34 FBB_D38 FBB_D32 FBB_D39 FBB_D33 FBB_D37 FBB_D35 FBB_D36 85 SCD1U10V2KX-5GP 85,90 FBB_CMD12 85,90 FBB_CMD27 85,90 FBB_CMD26 DQSL DQSL# D7 C3 C8 C2 A7 A2 B8 A3 FBB_D[56..63] SC1U6D3V2KX-GP N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 C9112 DY SC1U6D3V2KX-GP FBB_CMD9 FBB_CMD11 FBB_CMD8 FBB_CMD25 FBB_CMD10 FBB_CMD24 FBB_CMD22 FBB_CMD7 FBB_CMD21 FBB_CMD6 FBB_CMD29 FBB_CMD23 FBB_CMD28 FBB_CMD20 FBB_CMD14 DQSU DQSU# FBB_D56 FBB_D61 FBB_D58 FBB_D60 FBB_D57 FBB_D63 FBB_D59 FBB_D62 SC1U6D3V2KX-GP VREFDQ VREFCA ZQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 SC1U6D3V2KX-GP 243R2F-2-GP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 SC1U6D3V2KX-GP H1 M8 L8 C9118 DY VRAM24 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 SCD1U10V2KX-5GP VRAM7_VREF VRAM8_VREF VRAM_ZQ7 2 A8 A1 C1 C9 D2 E9 F1 H9 H2 D VRAM23 VDD VDD VDD VDD VDD VDD VDD VDD VDD SC1U6D3V2KX-GP OPT SC1U6D3V2KX-GP SCD1U10V2KX-5GP OPT C9130 K8 K2 N1 R9 B2 D9 G7 R1 N9 C9117 OPT SC1U6D3V2KX-GP C9108 DY SC1U6D3V2KX-GP C9125 SCD1U10V2KX-5GP SCD1U10V2KX-5GP OPT SC1U6D3V2KX-GP C9126 OPT 1 R9104 C9128 OPT SC1U6D3V2KX-GP SC1U6D3V2KX-GP C9127 OPT C9107 OPT C9116 DY VRAM23 C9109 OPT 1 1D5V_VGA_S0 1 1 1 C9113 DY SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 C9119 OPT SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 C9129 DY 2 C9120 OPT 1 1 1D5V_VGA_S0 2 D 2 2 5 85 85 FBB_CLK1 FBB_CLK1# J7 K7 85 FBB_CMD19 K9 85 85 FBB_DQM5 FBB_DQM6 D3 E7 L3 K3 J3 85,90 FBB_CMD13 85,90 FBB_CMD15 85,90 FBB_CMD30 VRAM24 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREFDQ VREFCA ZQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU DQSU# DQSL DQSL# ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BA0 BA1 BA2 CK CK# CS# RESET# NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CKE DMU DML WE# CAS# RAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP 72.52G63.A0U 72.52G63.A0U E3 F7 F2 F8 H3 H8 G2 H7 FBB_D49 FBB_D55 FBB_D51 FBB_D53 FBB_D50 FBB_D54 FBB_D48 FBB_D52 D7 C3 C8 C2 A7 A2 B8 A3 FBB_D42 FBB_D46 FBB_D40 FBB_D47 FBB_D41 FBB_D45 FBB_D43 FBB_D44 FBB_D[48..55] FBB_D[40..47] 85 85 C7 B7 FBB_DQS_WP5 85 FBB_DQS_RN5 85 F3 G3 FBB_DQS_WP6 85 FBB_DQS_RN6 85 K1 FBB_CMD18 L2 T2 FBB_CMD16 85 FBB_CMD5 85,90 T7 L9 L1 J9 J1 C 85 FBB_CMD4 85,90 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9 B B 1 1D5V_VGA_S0 1 1D5V_VGA_S0 R9103 R9106 2 1K33R2F-GP 2 1 OPT OPT C9114 SCD1U10V2KX-5GP OPT 2 1 R9101 C9111 SCD1U10V2KX-5GP 2 1K33R2F-GP 2 OPT FBB_CLK1# VRAM8_VREF 1 VRAM7_VREF 1 R9105 OPT 2 2 1 R9109 162R2F-GP OPT 1K33R2F-GP OPT 1K33R2F-GP FBB_CLK1 A A <Variant Name> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: 5 4 3 2 GPU-VRAM7,8 (4/4) Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 91 of 103 5 4 3 2 1 DCBATOUT DIS_OPT DIS_OPT DIS_OPT PR9243 PC9231 1K65R2F-GP SC150P50V2JN-3GP DIS_OPT DIS_OPT 1 PR9268 2 NV_VCCSENSE 9 VGA_CORE FDMS3600-02-RJK0215-COLAY-GP 1 1 2 PR9258 PC9222 1R3F-GP SCD33U16V3KX-1GP DIS_OPT DIS_OPT DIS_OPT 1 2 2 2 2 1 2 1 2 PC9242 SC1U25V3KX-1-GP 2 VGA_RAMP_L 649KR2F-GP 2 69K8R2F-GP 162KR2F-L-GP 79.47719.2CL 2nd = 79.47719.2GL 79.47719.2CL 2nd = 79.47719.2GL DIS_OPT DIS_OPT DIS_OPT DIS_OPT PR4259 1 200KR2F-L-GP 2 DIS_OPT B DIS_OPT 1 1KR2F-3-GP DIS_OPT 3218_VID5 DY PT9204 PC9240 SC1500P50V2KX-2GP 2 1 PR9240 2 249KR2F-GP PC9235 SC1KP50V2KX-1GP VGA_CSCOMP_SWFB1 PR9242 1 2 1 2 2 2 2 VID2_1 VGA_AGND DIS_OPT DIS_OPT DIS_OPT DIS_OPT PR9239 1 PR9213 DIS_OPT 1K91R2F-1-GP PT9203 DIS_OPT VGA_AGND DCBATOUT PR9276 DY 10KR2J-3-GP PR9275 DY 10KR2J-3-GP VID3_1 PR9274 10KR2J-3-GP PR9273 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP VID5_1 1 1 1 1 NV:HW default boot up voltage to GL=0.95V. need to stuff PR9263, PR9278, PR9273, PR9274, PR9281, PR9282 COIL-D36UH-3-GP-U DIS_OPT 1 1 1 PR9238 PR9214 20KR2F-L-GP 1 PR9241 1 PR9236 1 PR9235 3D3V_VGA_S0 2 2 80K6R2F-GP 2 VGA_AGND PR9272 FDMS3600-02-RJK0215-COLAY-GP PL9202 1 2 SE470U2VDM-6-GP PR9209 13KR2F-GP 2 2 SE470U2VDM-6-GP 2 C DIS_OPTDIS_OPT DIS_OPTDIS_OPT 10R2F-L-GP 1 0R0402-PAD-1-GP DY 7 6 5 8 GAP-CLOSE-PWR-3-GP DIS_OPT PR9263 2 3 4 10 1 9 7 6 5 8 83 PR9271 1 2 PU9205 2 3 4 10 1 PC9203 SC1KP50V2KX-1GP VGA_AGND B 84.03668.037 PU9204 DIS_OPT 1 NV_VSSSENSE RP9261 100R2F-L1-GP-U 84.03668.037 PR9224 DIS_OPT 2 2 49 48 47 46 45 44 43 42 41 40 39 38 37 83 2 PR9248 49D9R2F-GP DIS_OPT 2 PG9216 1 VGA_CORE DIS_OPT 1 0R0402-PAD-1-GP 2 2 PR9247 49D9R2F-GP 1 0R0402-PAD-1-GP 1 PR9269 2 GND VID0 VID1 VID2 VID3 VID4 VID5 VID6 PSI# DPRSLP PH0 PH1 VCC VGA_AGND DIS_OPT DCBATOUT GL -1 1226 1 1 PR9223 34K8R2F-1-GP 5V_S0 1VGA_FB_COMP 1 2 DIS_OPT 79.47719.2CL 2nd = 79.47719.2GL DIS_OPTDIS_OPT 2 2 PT9202 DIS_OPT DIS_OPT PWR_VGA_DRVL2 PWR_VGA_SWFB2 PWR_VGA_SW2 PWR_VGA_DRVH2 PWR_VGA_BST2 13 14 15 16 17 18 19 20 21 22 23 24 1 PWR_VGA_DRVL1 PT9201 79.47719.2CL 2nd = 79.47719.2GL 2 DIS_OPT 2 VGA_FB_SENSE C 2 2 RP9262 100R2F-L1-GP-U 1 1 PR9222 5K11R2F-L1-GP DIS_OPT SC18P50V2JN-1-GP NCP3218GMNR2G-GP PWR_VGA_BST1 PWR_VGA_DRVH1 PWR_VGA_SW1 PWR_VGA_SWFB1 2 PC9234 DIS_OPT 2 36 35 34 33 32 31 30 29 28 27 26 25 BST1 DRVH1 SW1 SWFB1 PVCC DRVL1 PGND DRVL2 SWFB2 SW2 DRVH2 BST2 1 1 EN PWRGD IMON CLKEN# FBRTN FB COMP TRDET# VARFREQ VRTT TTSNS GND IREF RPM RT RAMP LLINE CSREF CSSUM CSCOMP ILIM OD3# PWM3 SWFB3 PR9210 127KR2F-GP 1 2 3 4 5 6 7 8 9 10 11 12 PWR_VGA_FBRTN PWR_VGA_FB PWR_VGA_COMP PWR_VGA_TRDET# 1 PC9238 SC150P50V2JN-3GP 1 2 PWR_VGA_EN 2 2nd = 68.R3610.10T PWR_VGA_IREF PWR_VGA_RPM PWR_VGA_RT PWR_VGA_RAMP PWR_VGA_LLINE PWR_VGA_CSREF PWR_VGA_CSSUM PWR_VGA_CSCOMP PWR_VGA_ILIM PR9262 2 1 74.03218.A33 2 1 PR9233 2 0R0402-PAD-1-GP DY 1 0R2J-2-GP 93 8209A_EN/DEM_VGA 8,19,27,36,46,47 PM_SLP_S3# 86,93 PWR_VGA_CORE_PGOOD PU9209 PR9253 DY 3KR2J-2-GP GAP-CLOSE-PWR-3-GP 1 68.R3610.20S -1 1220 10R2F-L-GP DIS_OPT 1 DIS_OPT COIL-D36UH-3-GP-U PC9226 SC10U25V5KX-GP DIS_OPT VGA_AGND PC9232 SCD33U16V3KX-1GP SE470U2VDM-6-GP 3218_VID0 3218_VID1 3218_VID2 3218_VID3 3218_VID4 3218_VID5 3D3V_S0 PR9259 1R3F-GP SE470U2VDM-6-GP 3D3V_VGA_S0 2PWR_VGA_BST1_C 1 2 1 2 PC9244 SC1U10V2KX-1GP PR9225 VGA_AGND 79.47612.A0L FDMS3600-02-RJK0215-COLAY-GP PL9201 1 2 PG9214 -1 1220 PC9245 SE47U25VM-14-GP VGA_CORE FDMS3600-02-RJK0215-COLAY-GP 1 DY 2 3218_VID0 D 1 3218_VID1 2 PR9251 0R0402-PAD-1-GP 7 6 5 8 2 2 PR9250 0R0402-PAD-1-GP 1 9 7 6 5 8 1 1 VID0 2 3 4 10 1 9 1 VID1 86 0R2J-2-GP 1 86 1 2 PR9234 2 2 1 VID2 86 GPU_DPRSLP PU9202 2 3 4 10 1 PC9237 SC4D7U10V5KX-4GP 86 PU9201 5V_S0 PR9260 10R3F-GP 1 2 PR9244 0R0402-PAD-1-GP 3218_VID2 5V_S0 2 3218_VID3 1 2 PR9245 0R0402-PAD-1-GP 2 1 -1 1226 84.03668.037 PC9225 SC10U25V5KX-GP VID3 84.03668.037 2 1 VID4 86 D GL DIS_OPT 1 1 86 3218_VID4 2 3218_VID5 2 PR9246 0R0402-PAD-1-GP PC9233 SC10U25V5KX-GP 2 PR9249 0R0402-PAD-1-GP 1 1 1 PC9214 SC10U25V5KX-GP VID5 86 2 DIS_OPT VGA_CSCOMP_SWFB2 249KR2F-GP DIS_OPT DIS_OPT 3218_VID4 VGA_AGND 3218_VID3 3218_VID2 3218_VID1 1 1 2 2 2 2 2 2 PR9282 10KR2J-3-GP DY PR9281 10KR2J-3-GP PR9280 10KR2J-3-GP VID4_0 PR9279 DY 10KR2J-3-GP PR9278 10KR2J-3-GP 10KR2J-3-GP PR9277 DY 1 1 1 1 3218_VID0 VID1_0 VID0_0 A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title NCP3218_VGACORE25W Size A2 Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 92 of 103 5 4 3 2 1 VGA chip sequence: 3V_VGA_S0>VGA_CORE>1D5V_VGA>1D05V_VGA 3V_VGA_S0 VGA_CORE 1.5V_VGA_S0 1D5V_VGA_S0 Design current = 9A 2 3D3V_S5 PR9337 10KR2J-3-GP 100mils or Copper Shape 1 D 2 PR9304 0R2J-2-GP DMP2130L-7-GP PQ9302 92 DIS_OPT G 1D5V_VGA_S0 1 1 2 1 1 2 1 PC9340 SC22U6D3V5MX-2GP 2 2 DIS_OPT 68.R2010.10Q 2nd = 68.R2010.20B 2 IND-D2UH-14-GP 1 2 1 1 2 GND GND GND PWR_1D5V_VX 1 1 2 AGND B2 B3 B4 C2 C3 C4 D2 D3 D4 VT385FCX-ADJ-GP DIS_OPT DIS_OPT PG9331 PR9332 13KR2F-GP DGPU_PWR_EN A1 B1 C1 D1 AGND_386 400mils or Copper Shape PL9331 VX#B2 VX#B3 VX#B4 VX#C2 VX#C3 VX#C4 VX#D2 VX#D3 VX#D4 10KR2J-3-GP DIS_OPT PC9336 SC2200P50V2KX-2GP DIS_OPT 1 PQ9304 84.2N702.J31 2ND = 84.07002.I31 3RD = 84.2N702.W31 VDD VDD VDD STAT OE PC9343 SC22U6D3V5MX-2GP SC4700P50V2KX-1GP 2 10KR2F-2-GP DIS_OPT SENSE+ SENSE- PC9341 SC22U6D3V5MX-2GP 2 A4 A5 B5 C5 D5 PC9339 SC22U6D3V5MX-2GP 1 3D3V_S0 PR9336 0R0402-PAD-1-GP 2 PWR_1D5V_STAT 2PWR_1D5V_OE PR9334 1 PC9344 SCD1U10V2KX-4GP 1 A2 A3 8209A_EN/DEM_VGA 1 2 1 3 2 1 PC9342 1D5V_SENSE_1 DY 3.3V_RUN_VGA_1 PR9307 D 1 PR9333 4K02R2F-GP DIS_OPT 2N7002K-2-GP 2 DIS_OPT DIS_OPT PC9335 150R2F-1-GP 1 2 1 2 PR9335 SC3300P50V2KX-1GP 2nd = 84.2N702.E3F 3RD = 84.2N702.F3F DIS_OPT S 21 DGPU_PWR_EN# 1 -1 0104 PWR_1D5V_VSENSE+ PWR_1D5V_VSENSE- 1 2 4 5 6 DIS_OPT 84.2N702.A3F 2 PR9314 470R2J-2-GP PQ9303 2N7002KDW-GP 1 Design Current = 9A DIS_OPT DIS_OPT DIS_OPT DIS_OPT DIS_OPT PU9331 4K02R2F-GP PR9331 DIS_OPT PC9338 SC22U6D3V5MX-2GP PR9317_2 10KR2J-3-GP 2 1 PR9317 2 DIS_OPT PC9334 SC10U6D3V3MX-GP 8209A_EN/DEM_VGA 83.R5003.J8F 2ND = 83.R5003.H8H PC9345 SC22U6D3V5MX-2GP 1 8209A_EN/DEM_VGA A CH551H-30GP-GP SCD1U10V2KX-5GP PR9317_1 K 1 DGPU_PWR_EN PC9333 SC10U6D3V3MX-GP 2 3D3V_VGA discharge 2 PD9301 2ND = 84.03413.A31 DIS_OPT PC9309 2 2 PR9316 10KR2J-3-GP 2 1 D 84.02130.031 DIS_OPT G 2 G DIS_OPT 2 2 10KR2F-2-GP DIS_OPT 1 PR9303 1 PC9332 SC10U6D3V3MX-GP 3D3V_VGA_S0 SC4D7U6D3V3KX-GP PC9346 3D3V_VGA_S0 S 3D3V_S0 D L DIS_OPT PC9337 SCD1U10V2KX-5GP H IGPU with BACO 1 IGPU 1 SCD1U10V2KX-5GP PC9331 DGPU_PWR_EN# D 5V_S5 1D5V_PGD DY 1 2 DIS_OPT DIS_OPT DIS_OPT DIS_OPT DIS_OPT DIS_OPT DIS_OPT 74.00385.03Z 2 GAP-CLOSE-PWR-3-GP AGND_386 DIS_OPT Close to PL9331 C C Close to output MLCC 1D05V_VGA Diff pair PR9338 3D3V_VGA_S0 should ramp-up before VGA_Core should PWR_1D5V_VSENSE+_R VGA_Core 1 2 0R0402-PAD-1-GP ramp-up before 1D5V_VGA_S0 VSENSE-TRACE ROUTED DIFFERENTIALLY PARALLEL TO VSENSE+ 1D5V_VGA_S0 should ramp up 1D05V_VGA_S0 Design current = 3.8A so 1D05V_VGA_S0 EN have to fine tune RC delay after VGA_Core PR9339 1 2 0R0402-PAD-1-GP Close to output MLCC 1D5V_VGA_S0 -1 1220 1 5V_S5 1 PR9351 2 1D05_VGA_VCNTL 2 1 PU9301 1D05V_VGA_EN 2 VIN#5 VOUT#4 VOUT#3 FB GND R1 PR9357 9K1R2J-1-GP 1 DY 2 APL5930KAI-TRG-GP 1D05_VGA_FB 2 74.05930.03D 1 DY PC9355 SC1U6D3V2KX-GP R2 PR9358 28K7R2F-GP B 2 B PC9359 SC100P50V2JN-3GP VCNTL POK EN VIN#9 2 0R0402-PAD-1-GP -1 1220 6 7 8 9 1 1 5 4 3 2 1 1 PR9355 1D5V_PGD 1D05V_VGA_S0 2 PC9350 SC1U6D3V2KX-GP PC9356 SC1U6D3V2KX-GP 0R0402-PAD-1-GP Discharge Circuit PR9305 3D3V_VGA_S0 2 1D05V_VGA_EN#1 1 DIS_OPT 100KR2J-1-GP 2PR9302 0R0201-PAD-GP DGPU_PWROK PC9302 SC100P50V2JN-3GP 3 22 PR9306 1 DIS_OPT PD9204 2 1 83.R0304.A8F 2ND = 83.R2004.B8F CH751H-40PT-GP 2 1 2 1 86,92 PWR_VGA_CORE_PGOOD 1D05V_VGA_DISCHG 2 1D05V_VGA_EN DIS_OPT 2 VGA_CORE DIS_OPT 84.2N702.A3F 2nd = 84.2N702.E3F 3RD = 84.2N702.F3F DY 3D3V_VGA_S0 4 6 1 PQ9301 2N7002KDW-GP PR9301 10KR2J-3-GP 1D5V_VGA_S0 PD9203 2 1 83.R0304.A8F 2ND = 83.R2004.B8F CH751H-40PT-GP 5 3D3V_VGA_S0 Discharge Circuit DIS_OPT 1 1D05V_VGA_S0 470R2J-2-GP DIS_OPT A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DISCRETE VGA POWER Size A1 Date: 5 4 3 2 Document Number Rev 1 Colossus Wednesday, January 04, 2012 1 Sheet 93 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 94 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 95 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Document Number Reserved Rev 1 Colossus Monday, December 26, 2011 Sheet 1 96 of 103 4 2 SPR1 H9 HOLE SPR3 SPR4 SPR5 SPRING-9-GP SPRING-57-GP SPRING-57-GP SPRING-24-GP-U SPRING-24-GP-U 1 DY 1 DY SPR2 1 1 1 1 D 34.49U23.001 34.42T14.002 34.42T14.002 1 1 1 1 1 1 1 D 1 S1 S2 S3 S4 H10 STF237R117H83-1-GP STF237R117H83-1-GP STF237R113H115-GP HOLE335R115-GPSTF256R117H221-GP H4 H5 HOLE335R115-GP HOLE256R115-GP H19 HOLE 1 H1 HOLE335R115-GP 3 1 5 -1 0104 by H11 HOLET335B256R115-GP H12 H13 H14 H15 H16 H17 H18 HOLE276R150-2-GP HOLE276R150-2-GP HOLE276R150-2-GP HOLE276R150-2-GP HOLE276R150-2-GP HOLE276R150-2-GP HOLE276R150-2-GP Thermal H7 H8 HOLE256R115-GP HOLE256R115-GP H20 H21 HOLE256R115-GP HOLE ZZ.PAD01.021 1D05V_S0 3D3V_AUX_KBC ZZ.00PAD.D11 5V_S5 3D3V_AUX_S5 1 2 2 1 2 1 1 2 2 2 2 1 2 1 2 1 2 2 1 1 1 1 2 1 1 2 1 2 EC9752 1 2 1 2 1 2 2 1 1 1 2 1 2 1 2 1 2 2 2 1 1 1 2 1 2 1 1 1 2 1 2 1 2 1 2 1 2 1 2 2 2 1 1 1 2 1 2 1 2 2 2 1 2 1 2 1 2 2 2 1 2 1 1 2 2 2 1 1 2 1 2 B SCD1U50V3KX-GP 2 EC9751 SCD1U50V3KX-GP SCD1U50V3KX-GP <Core Design> EC9749 EC9750 SCD1U50V3KX-GP 1 EC9716 SCD1U25V2KX-GP EC9748 SCD1U50V3KX-GP 2 EC9708 SCD1U25V2KX-GP EC9715 SCD1U25V2KX-GP DY EC9707 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP EC9714 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP EC9706 DCBATOUT SCD1U50V3KX-GP DY EC9738 SCD1U25V2KX-GP EC9737 SCD1U25V2KX-GP DY EC9746 SCD1U25V2KX-GP DY EC9745 SCD1U25V2KX-GP DY EC9744 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP EC9741 EC9742 EC9743 SCD1U25V2KX-GP DY EC9740 SCD1U25V2KX-GP SCD1U25V2KX-GP A EC9739 DY EC9711 EC9712 EC9713 DY EC9747 3D3V_S5 EC9703 EC9704 EC9705 SCD1U25V2KX-GP EC9710 SCD1U25V2KX-GP DY EC9731 SCD1U25V2KX-GP EC9730 SCD1U25V2KX-GP EC9729 SCD1U25V2KX-GP DY EC9728 SCD1U25V2KX-GP DY EC9727 SCD1U25V2KX-GP DY EC9726 SCD1U25V2KX-GP DY EC9725 SCD1U25V2KX-GP DY SCD1U25V2KX-GP DY SCD1U25V2KX-GP DY EC9722 EC9723 EC9724 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP DY EC9721 DY EC9709 SCD1U25V2KX-GP DY EC9720 EC9702 SCD1U25V2KX-GP DY EC9701 SCD1U25V2KX-GP DY EC9717 SCD1U25V2KX-GP DY EC9718 SCD1U25V2KX-GP EC9719 SCD1U25V2KX-GP DY SCD1U25V2KX-GP DY SCD1U25V2KX-GP DY EC9734 EC9735 EC9736 SCD1U25V2KX-GP 5V_S0 DY EC9733 SCD1U25V2KX-GP DY SCD1U25V2KX-GP EC9732 1 C 1 C B 1 1 1 1 1 1 1 1 1 1 1 1 1 H6 HOLE256R115-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 UNUSED PARTS/EMI Capacitors Document Number Date: Wednesday, January 04, 2012 5 4 3 2 Sheet Rev 1 Colossus 97 of 1 103 A 4 SPR10 SPR20 SPR21 SPR22 SPRING-57-GP SPRING-5-GP SPRING-5-GP SPRING-5-GP 3 2 SPR11 1 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 EC9828 EC9824 EC9823 EC9819 EC9818 EC9817 EC9816 EC9815 SC1KP50V2KX-1GP SC1KP50V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP LCDVDD EC9814 EC9813 EC9812 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP VCC_GFXCORE 1D05V_VGA_S0 EC9811 EC9810 EC9809 SCD1U50V3KX-GP SCD1U50V3KX-GP 5V_S0 D 1D5V_VGA_S0 EC9808 EC9807 SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP 0D85V_PW R EC9806 EC9805 EC9804 SCD1U50V3KX-GP 1D05V_S0 EC9803 SCD1U50V3KX-GP SCD1U50V3KX-GP 1 DCBATOUT_5V EC9802 EC9801 2 DCBATOUT SPRING-57-GP 34.42T14.002 34.4Y806.001 2 D SPR10 SPR20 SPR21 SPR22 1 34.42T14.002 for EMI change into change into change into change into 2 1 1 1 1 DDR3 SPR6 SPR7 SPR8 SPR9 1 SPR13 SPRING-63-GP 1 5 3D3V_S0 1 2 1 2 1 1 2 1 1 2 2 1 2 2 SCD1U25V2KX-GP SCD1U50V3KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U50V3KX-GP 2 EC9836 EC9835 EC9834 EC9833 EC9832 EC9831 EC9830 C EC9829 1 G9801 1 2 GAP-CLOSE-PW R-3-GP G9802 1 2 C GAP-CLOSE-PW R-3-GP G9803 1 2 GAP-CLOSE-PW R-3-GP G9804 1 2 GAP-CLOSE-PW R-3-GP G9805 1 2 GAP-CLOSE-PW R-3-GP AUD_AGND B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Change History Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 98 of 103 5 4 3 2 1 Chief River Platform Power Sequence (AC mode) (DC mode) red word: KBC GPIO +RTC_VCC +RTC_VCC T1 >9ms T1 >9ms RTC_RST# RTC_RST# DCBATOUT DCBATOUT Within logic high level and disable if it is less than the logic low level. red word: KBC GPIO T2 T2 3D3V_AUX_S5 3D3V_AUX_S5 KBC GPIO34 control power on by 3V_5V_EN D D S5_ENABLE Press Power button Sense the power button status 5V_S5 T3 Platform to KBC GPXIOD3 KBC_PWRBTN# EC_ENABLE#_1(GPIO31) keep low V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V. 3D3V_S5 T4 +5VA_PCH_VCC5REFSUS 3D3V_AUX_KBC T5 T3 KBC GPIO34 control power on by 3V_5V_EN S5_ENABLE KBC GPXIOA6 to PCH RSMRST#_KBC(EC Delay 40ms) T6 >10ms PCH to KBC GPIO5E PCH_SUSCLK_KBC V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V. T7 >5ms KBC GPXIOA11 to PCH Not floating. AC_PRESENT Sense the power button status AC KBC_PWRBTN# 0ms<T8 <90ms 5V_S5 T4 3D3V_S5 T5 +5V_ALW & +3.3V_ALW need meet 0.7V difference +5V_ALW & +3.3V_ALW need meet 0.7V difference +5VA_PCH_VCC5REFSUS T6 T7 >16ms Press Power button 3D3V_AUX_KBC KBC GPIO20 to PCH PM_PWRBTN# Platform to KBC GPXIOD3 This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. KBC GPXIOA5 to PCH T9 >16ms PM_RSMRST# KBC GPXIOA5 to PCH T8 >10ms PCH to KBC GPIO5E AC PM_PWRBTN# PCH_SUSCLK_KBC AC PM_PWRBTN# T9 >5ms DC PCH_RSMRST# T10 T10 PCH to KBC GPIO8 PM_SLP_S4# T11 T11 PCH to KBC GPIO4 >30us PM_SLP_S3# PCH to KBC GPIO8 PM_SLP_S4# KBC GPIO23 to LAN PM_LAN_ENABLE PCH to KBC GPIO4 >30us PM_SLP_S3# KBC GPIO23 to LAN PM_LAN_ENABLE Enable by PM_SLP_S4# C V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V. 1D5V_S3 T12 DDR_VREF_S3(0.75V) T13 5V_S0 T14 3D3V_S0 T15 +5VS_PCH_VCC5REF Enable by PM_SLP_S4# +5V_RUN & +3.3V_RUN need meet 0.7V difference V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V. T16 1D5V_S3 T12 DDR_VREF_S3(0.75V) T13 5V_S0 T14 3D3V_S0 T15 +5VS_PCH_VCC5REF T16 1D5V_S0 T17 1D5V_S0 T17 1D8V_S0 T18 1D8V_S0 T18 0D75V_S0 T19 0D75V_S0 T19 1D8V_S0 & 1D5V_S3 power ready RUNPWROK 1D8V_S0 & 1D5V_S3 power ready T20 RUNPWROK 1D05V_VTT T21 T20 1D05V_VTT T21 TPS51219R PGOOD 1.05VTT_PWRGD(D85V_PWRGD) TPS51219R PGOOD T22 T23 0D85V_S0 0D85V_S0 T24 TPS51461RGER PGOOD TPS51461RGER PGOOD D85V_PWRGD SetVID CPU SVID BUS ACK 50us< T25 <2000us SetVID CPU SVID BUS VCC_CORE ACK 50us< T25 <2000us VCC_CORE VCC_GFXCORE VCC_GFXCORE T26 <5ms IMVP_PWRGD T26 VT1318MFQX PGOOD to system <5ms IMVP_PWRGD CLK_EXP_P This signal represents the Power Good for all the non-CORE and non-graphics power rails. T23 0D85V_S0 T24 D85V_PWRGD VT1318MFQX PGOOD to system CLK_EXP_P ALL_SYS_PWRGD=D85V_PWRGD T27 >99ms B T22 1.05VTT_PWRGD 0D85V_PWR(0D85V_S0) C +5V_RUN & +3.3V_RUN need meet 0.7V difference S0_PWR_GOOD D85V_PWRGD 2ms< KBC GPIOXA9 to PCH T28 >0us T29 <650ms This signal represents the Power Good for all the non-CORE and non-graphics power rails. ALL_SYS_PWRGD=D85V_PWRGD T27 >99ms S0_PWR_GOOD D85V_PWRGD PCH to CPU PM_DRAM_PWRGD 2ms< B KBC GPIOXA9 to PCH T28 >0us T29 <650ms PCH to CPU PM_DRAM_PWRGD T30 >1ms T31 >2ms 5ms< T32 <650ms 1D8V_S0 T30 >1ms T31 >2ms 5ms< T32 <650ms 1D8V_S0 PCH to CPU H_CPUPWRGD PCH to CPU H_CPUPWRGD T33 >0ms SYS_PWROK 1ms< PLT_RST# T35 <100ms T33 >0ms SYS_PWROK T34 >1ms+60us PCH to all system 1ms< PLT_RST# T36 <200us DMI T35 <100ms T34 >1ms+60us PCH to all system T36 <200us DMI 1D5V_VGA_S0(Discrete only) N13P Power-Up/Down Sequence 3D3V_S0 PCH GPIO54 output DGPU_PWR_EN#(Discrete only) 3D3V_VGA_S0(Discrete only) 3D3V_VGA_S0 above NCP3218 VIH 8209A_EN/DEM_VGA(Discrete only) A VGA_CORE(Discrete only) 1D5V_VGA_S0(Discrete only) A Ta >0ms Tb >0ms Tc >0ms 1D05V_VGA_S0(Discrete only) NCP3218 PGOOD <Core Design> DGPU_PWROK(Discrete only) Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. For power-down, reversing the ramp-up sequence is recommended. Title Power Sequence Size A1 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 1 Sheet 99 of 103 5 4 3 2 1 COLOSUSS POWER BLOCK DIAGRAM D D AC Adapter VT1318MFQX 5V_S5 RT8223M KBC_PWR_ON DC Battery DCBATOUT VIN VREG3 DC/DC (+V3ALW/+V5ALW) Charger BQ24738RGRR C VREG5 EN 5V_AUX_S5 3D3V_AUX_S5 3D3V_AUX_KBC VIN R2703 OR3J VIN U1701 CH715FGP VIN D85V_PWRGD PGOOD1 RTC_AUX_S5 SVID PGOOD2 SVID 17 IMVP_PWRGD 42~44 3D3V_S5 3D3V_S0 VIN PM_SLP_S3# QM3004M3 EN 36 C 1D5V_S3 5V_S5 5V_S0 VIN PM_SLP_S3# 1D5V_S0 VIN QM3004M3 PM_SLP_S3 QM3004M3 EN EN 36 36 41 5V_S5 RSMRST# VCC_GFXCORE VR_ON 27 40 PGOOD VCC_CORE DC/DC (CPU_CORE) (VGFX_CORE) DCBATOUT PM_SLP_S4# VDD RT8207MZQW 1.5/0.75V Vout VIN PGOOD 1D5V_S3 3D3V_S5 RUNPWROK VIN PM_SLP_S3# RT8068A 1.8V 1D8V_S0 RUNPWROK EN 47 S5 46 3D3V_S0 1D5V_S3 VTT PWR_0D75V_EN (PM_SLP_S3#) 8209A_EN/DEM_VGA 0D75V_S0 93 B DCBATOUT VLDOIN 3D3V_VGA_S0 DMP2130L DGPU_PWR_EN VIN B S3 46 VGA_CORE 5V_S5 NCP3218G EN/PSM PWRGD PWR_VGA_CORE_PGOOD DCBATOUT V5 VIN TPS51219R Vout 1.05V 1D05V_VTT (for CPU_VCCP) 1D05V_S0 (for PCH) 92 PWR_1D05V_1V_EN EN PGOOD 45 5V_S5 0D85V_EN 1D5V_VGA_S0 1D5V_VGA_EN (8209A_EN/DEM_VGA) VT385FCX 5V_S5 93 VIN 1D05V_S0 1D05V_VGA_S0 TPCC8065 1D5V_PGD V5DRV 0D85V_EN 93 EN TPS51461 VCCSA Vout PGOOD 48 0D85V_PWR D85V_PWRGD <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 3 2 Power Block Diagram Document Number Monday, December 26, 2011 Rev 1 Colossus Sheet 1 100 of 103 5 4 PCH SMBus Block Diagram 3 3D3V_S5 3D3V_S0 ‧ ‧ 2 1 KBC SMBus Block Diagram 3D3V_S5 ‧ 3D3V_S0 SRN10KJ-5-GP SRN2K2J-1-GP SRN2K2J-1-GP ‧ D SMBCLK SMBDATA 18 TouchPad Conn. DIMM 1 ‧ PCH_SMB_DATA ‧ ‧PCH_SMBCLK ‧ PCH_SMBDATA PCH_SMB_CLK SCL SDA PSDAT1 TPDATA PSCLK1 TPCLK ‧ ‧ TP_DATA TPDATA TP_CLK TPCLK D 27 14 3D3V_S5 3D3V_AUX_KBC SMBus Address:A0 ‧ 2N7002SPT ‧PCH_SMBCLK ‧ PCH_SMBDATA 3D3V_S0 3D3V_S5 SML1CLK SML1DATA ‧ ‧ ‧ DIMM 2 SRN2K2J-8-GP SRN4K7J-8-GP SDA 15 SMBus Address:A4 ‧ PCH_SML1CLK SCL Battery Conn. SRN33J-7-GP mSATA GPIO17/SCL1 BAT_SCL BAT_SCL0 CLK_SMB GPIO22/SDA1 BAT_SDA BAT_SDA0 DAT_SMB 27 SMBus address:16 SRN2K2J-1-GP PCH_SMBCLK PCH_SML1DATA SML0CLK SML0_CLK SML0DATA SML0_DATA 2N7002SPT PCH_SMBDATA ‧ ‧ SMB_DATA 103 KBC ENE KB9016QF PCH_SML0_CLK PCH_SML0_DATA 3D3V_S0 ‧ PCH SMB_CLK ‧ ‧ TouchPad SML1_CLK 69 To KBC SML1_DATA 27 BQ24725 27 SCL SDA SMBus address:12 27 SRN2K2J-1-GP C C 3D3V_S5 SDVO_CTRLCLK SDVO_CTRLDATA PCH_HDMI_CLK PCH_HDMI_DATA Level Shift DDC_CLK_HDMI DDC_DATA_HDMI ‧ 3D3V_S0 ‧ SRN2K2J-1-GP L_DDC_CLK L_DDC_DATA ‧ ‧ HP_CLK ‧ ‧ SMBC_THERM_NV SMBD_THERM_NV SRN2K2J-1-GP 86 VGA thermal sensor GPIO73/SCL2 SML1_CLK SCL GPIO74/SDA2 SML1_DATA SDA PCH 18 LCD_SMBCLK G-Sensor LCD_SMBDATA G_CLK CRT_DDC_CLK SCLK CRT_DDC_CLK G_DAT CRT_DDC_DATA Headphone 29 AMP HP_DATA SDATA CRT_DDC_DATA 79 SMBus address:xx B B DDC1CLK LCD_SMBCLK CLK DDC1DATA LCD_SMBDATA DATA LCD CONN 103 DDC2CLK DDC2DATA 103 3D3V_S0 VGA 5V_CRT_S0 ‧ ‧ 3D3V_S0 SRN2K2J-1-GP SRN10KJ-6-GP ‧ CRT_DDCCLK_CON CRT_DDCDATA_CON CRT CONN 5V_HDMI 2N7002DW-1-GP ‧ A A SRN1K5J-GP DDC2CLK DDC_CLK_HDMI DDC2DATA DDC_DATA_HDMI <Core Design> HDMI CONN Wistron Corporation 103 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: 5 4 3 2 SMBUS Block Diagram Document Number Sheet 1 Rev 1 Colossus Monday, December 26, 2011 101 of 103 5 4 3 2 Thermal Block Diagram 1 Audio Block Diagram D D DY DY PAGE28 DXP DY P2800_DXP PORTD_+R SPKR_R+ PORTD_-R SPKR_R- PORTD_+L SPKR_L+ PORTD_-L SPKR_L- MAIN SPEAKER P58 MMBT3904-3-GP SC2200P50V2KX-2GP UMA Thermal P2800 DXN P2800_DXN Codec 92HD91 Place near CPU PWM CORE OUT_R+ PORTF_R FSPK_R PORTF_L FSPK_L Speaker AMP TPA2012D2RTJR 2nd SPEAKER OUT_ROUT_L+ OUT_L- P58 MMBT3904-3-GP PAGE27 C KBC ENE9016 AD4 SYS_THRM TDR AD3 CPU_THRM TDL T8 OTZ THERM_SYS_SHDN# 2N7002 PURE_HW_SHUTDOWN# EN D IMVP_PWRGD S G Put under CPU(T8 HW shutdown) 3V/5V PORTB_L HP_OUT_L PORTB_R HP_OUT_R PGOD VR Head Phone AMP HPA00929RTJR PORTA_L HP OUT HPA_OUT_L HPA_OUT_R PORTA_R TP FAN_TACH1 FAN1_PWM PCH 5V_S0 PWM +VREFOUT_A THRMDC VGA P29 SMBC_THERM_NV SML1CLK PCH_SML1CLK I2CS_SCL DualMOS FAN_TACH1_C B MIC IN MIC_R0 THRMDA VREFOUT_A TP P29 MIC_L0 FANPWM0 FANFB0 PAGE18 C SML1DATA PCH_SML1DATA SMBD_THERM_NV I2CS_SDA DMIC_CLK/GPIO1 Digital MIC DMIC_CLK 86 DMIC_0/GPIO2 DMIC_DATA B P49 TACH FAN MONO_OUT MONO_OUT Woofer AMP TPA3111D1 Woofer WOOFER_WOOFER_+ P30 P29 A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Thermal/Audio Block Diagram Size A3 Date: 5 4 3 2 Document Number Rev 1 Colossus Monday, December 26, 2011 Sheet 1 102 of 103 4 3D3V_S0_MSATA 1 C10312 C10313 DY 2 2 2 DY SCD1U16V2KX-3GP 1 1 C10311 DY SC10U6D3V5KX-1GP 2 0R3J-0-U-GP C10310 SCD1U16V2KX-3GP C10309 SCD01U16V2KX-3GP DY SC10U6D3V5KX-1GP -1 1220 C10308 SCD1U10V2KX-5GP D 2 1 1 1 R10303 2 0R0603-PAD-1-GP 1 DY 1 2 2 1D5V_S0_MSATA R10304 1 1D5V_S0 3D3V_S0 3 2 5 D mSATA MSATA1 53 1D5V_S0_MSATA 3D3V_S0_MSATA NP1 1 1 2 DYC10306 SCD1U10V2KX-4GP 3 4 2 5 6 7 8 9 10 C C 11 12 13 14 15 16 17 18 19 20 21 22 17 SATA_RXP1 1 2 C10303 SATA_RXP1_C 23 17 SATA_RXN1 1 2 C10304 SATA_RXN1_C 25 17 SATA_TXN1 SCD01U16V2KX-3GP SCD01U16V2KX-3GP SCD01U16V2KX-3GP SCD01U16V2KX-3GP 1 2 C10302 SATA_TXN1_C 17 SATA_TXP1 1 PLT_RST# 5,21,27,31,32,36,65,71,82,83 24 C10305 1 2 26 2 C10301 SATA_TXP1_C 3D3V_S0_MSATA 27 SCD1U10V2KX-4GP 28 29 30 mSATA_PCH_SMBCLK R10302 1 32 mSATA_PCH_SMBDATA R10301 1 31 33 2 0R0402-PAD-1-GP 2 0R0402-PAD-1-GP PCH_SMBCLK 14,15,18 PCH_SMBDATA 14,15,18 34 35 36 3D3V_S0_MSATA B -1 1220 37 B 38 39 40 41 42 43 44 45 46 CLK_PCI_DEBUG 47 21,71 48 3D3V_S0_MSATA 49 50 51 22 mSATA_DET# 52 NP2 1 54 2 DYC10307 SCD1U10V2KX-4GP SKT-MINI52P-95-GP H= 5.2 mm 62.10043.E61 2ND = 62.10043.F81 677867-FM5 <Core Design> A 1st 2nd 3rd 4th Wistron Corporation 677867-FM5 677867-AM5 677867-BM5 677867-LM5 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5 4 A 3 2 Document Number mSATA Rev 1 Colossus W ednesday, January 04, 2012 Sheet 1 103 of 103
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