Design Optimization for Yield

Transcription

Does your first silicon arrive on life support?
Dale Pollek
dale@chipmd.com
(408) 725-9586
CEO/Founder ChipMD
Wescon, April 13, 2005
For more about ChipMD: http://www.chipmd.com
©2005, ChipMD, Inc., All rights reserved exclusively for Wescon 2005 attendees
No part to be duplicated without written permission from ChipMD, Inc.
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Our Lives Run on Microprocessors
Ò Computers, phones, switches, air traffic, …
Ò But we are literally running on...
5 MIPS in
each shoe
2
Ò What is DFY? Why need it?

DFY = Design For Yield
Ò What are key causes of Yield problems?
Which are “designer controllable”?
How can designers address them?

Ò Overview of a DFY enhanced design flow
Ò Optimization methods available today
Tradeoffs of each
How get best results in least time?

Ò Impact of DFY Success

Including example DFY success circuit
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Ò Yield Issues

Design
Layout & Tooling
Manufacturing & Test
Ò Costs are >> re-spin

Extra R&D & tooling
Revenue impact
TTM, TTV & MktShare
Yield
Semiconductor Yield
Sales $’s/chip
Volume Shipment
DFY
First
Silicon
Re-spin #2
Re-spin #1
Time to volume
Ò DFY affects 1st silicon

Each % worth $M’s
Yield is Money!
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Source: M. Rencher (EE Times 3/24/03)
Defining DFY and Design Yield
Ò DFY is well defined and explained

“Yields can be improved via design techniques”
Article by Mark Rencher March 24, 2003 in EE Times
Ò This article defines “parametric yield”

Where parametric yield is often what is thought of as
“design yield”, that is design’s capacity to quantify the
design as to what theoretical max yield can be attained
(assuming all other yield factors are zeroed out).
Specifically how designers can Design For Yield (DFY).
Ò A note to clear up “parametric” confusion in market

Use “design yield” because when some designers hear
“parametric”, they assume is process or fab issue even
though is something they can quantify and control.
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Who needs DFY?
Ò Digital SoC & ASIC

Library developers & IP providers
Critical paths & total chip verification
“All design is analog – some more so than others”
EDN Gabe Moretti 3/31/2005
Ò Memory design

Embedded IP needs 6+ sigma sense amps
Ò RF-A/MS circuits

Yield closely tied to process variations
Topology, operating conditions and use specific
Ò Every design comes down to being transistors

Plus resistors, capacitors, and “wires”, parasitics, …
This presentation focus is device level simulation DFY
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Sample Fabless User DFY Impact
Ò “Example Fabless” Wafer Cost

$110M/Qtr
Ò Fabless Market Value of product

Sales Value of $450M/Qtr
Profits were $24M (5.3%)
Wafer cost 24.4% of sales
Ò If improve yield by 10%

$11M Cost of wafers saved/Qtr
Net profits raised to 7.8% (~1.5X profit)
Ò If fab limited production & +10% yield

Sell an additional $45M/Qtr
Net profits raised to ~13.9% (>2.5X profit)
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Sources of DFY Problems
Ò 61% of New ICs/ASICs Require At Least One Re-Spin

Source: Aart de Geus, Chairman & CEO of Synopsys
Ò A few data points from Cadence
Source: Ping Chao, SVP and Chief Product Strategist
Analog’s Impact on Overall
Increasing Gate Capacity
100M
Design

75M
98%
50M
80%
25M
0
0.35µ
0.25µ
0.18µ
0.13µ
60%
<100nm
SoCs with Digital and Analog
50/50
80%
40%
60%
20%
40%
2%
20%
Transistors Area Effort
1998
2000
2002
2004
2006
Digital
Re-spins
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Analog
Key Causes DFY Must Address
Ò Global and local process variation (PV).
Ò How identify root cause of problems?
What is most significant cause?
What has least influence to reduce or avoid?

Ò What are the real worst cases?

Process and operating conditions
Ò How validate results before layout?

How reduce silicon used for design?
Ò Wide range of operating conditions.
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Design is Process Sensitive
Ò Need to design specific to the IC process
Design out global & local process variation impacts
Circuits require resizing for each process

%
Process migration
is not proportional
Need to
assess
impact
New IC Process
Second Source
Fab Line or
Process Drift
First Process
Fab Line Used
Process Parameter “x”
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Process distribution
“PV2”
%
Performance
PV’s Dominate & Overwhelm
Respective performances
“PV1”
“PV1”
”
2
V
P
“
3”
V
“P
“PVη”
? How many PV’s?
? How many perf’s?
? How deal with all?
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Typical Non-DFY Design Flow
Ò Simulate & iterate … and repeat
Set
Architecture
& Spec’s
Ò Yield not good enough, try again…
Define
Topologies &
Constraints
Simulate
Revise
Sizing
(& repeat)
Revise
Topology
Analyze
“Redesign By Autopsy”
RBA
Silicon Debug
Layout &
Parasitic
Extraction
Is
Re-spin
< 2.5
Simulate
(& repeat)
Analyze
Generate
Masks
To
Mfg
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DFY Design Flow Enhancements
Ò Sensitivity driven design diagnoses

Global and local process variations & design parameters
Diagnose results for all operating conditions
Parallel simulations & manage the data for future use
Extended diagnoses from simulation data
Ò Feasibility optimization

Ensure all critical devices meet constraints
Make sure topology works before optimizing it

Also called “Nominal Optimization”

Also called “Design Centering”

Validation or confirmation of yield being ready for tapeout

Ò Performance optimization
Ò Yield optimization
Ò Extended Monte Carlo
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Sensitivity Driven Examinations
Ò “…sensitivity-analysis-based tools are
the only way to account for yield loss
during front-end design”
Bozeman
Kaminska, Pultronics
Ò Isolate the causes of problems
Process,
operating condition or design
parameter related?
Ò Rank contribution with quantified data
Guide
the engineer to most important first
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Parameter Sensitivity
Ò Process parameter feedback to design
Ò Design parameter impacts
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Mismatch Isolation Diagnosis
Ò Identification of sensitive transistors
Ò Quantification of mismatch influence
P3
mCMRR
1.0
0.8
P1
0.6
0.4
P2
0.2
0.0
P1
P2
P3
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Feasibility Optimization
Ò Does the circuit perform as expected?
Ò Are all sizing constraints met?
Ò Validate function before performance
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Example Constraints
Examples Functional
Robustness
Electrical
saturation
∆Vds small
Geometric
same Ls
min area
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Constraints Impact on Robustness
Ò Comparison of two
automatically calculated
nominal sizings:
a) with consideration of sizing rules
b) neglected sizing rules
Gain
b)
b)
Gain
a)
a)
Sizing rules satisfied
Sizing rules violated
w1
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Nominal Optimization
Ò First step towards robust design considers

Operating parameters
Constraints
Ò Maximize the performance at nominal

What is “best performance”?
How deal with counter performances?
Ò Some tools can also optimize at “corners”
Ò But corners are not always the same

Process corners are not always worst case
Worst cases change with topology & sizing
Ò No replacement for yield optimization!

How know if not near a “cliff”?
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Yield Optimization
Ò What is design end goal?
Getting some chips to work well?
Having as many possible meet all specs?

Ò Create a robust design by considering
Constraints
Operating conditions
Process statistics

Ò How know all spec’s met for all PV’s?

Does optimization cover all operating conditions?
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Design Yield Improvement
pdf
Improve nominal
performance
pdf
Decrease sensitivity
spec.
performance
Or, do
pdf
both
spec.
perf.
spec.
perf.
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Monte Carlo Yield Confirmation
Ò Based on the process distribution,
simulate N ‘samples’ of the circuit.
Ò Count passing samples to find yield.
# of
Yield =
# of
+ # of
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Monte Carlo Analysis
Ò How many simulations are required to
predict yield > Ymin with 95% confidence?
Design (βwc)
2σ
3σ
Ymin
97.7%
99.87%
4σ
99.997%
N
150
3,000
100,000
based on N > 3/(1-Ymin)
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Monte Carlo-Analysis w/ Op Conds
operating parameter
T [°C]
Tmax
Spec: A0 > 80 dB
for all
Tmin < T < Tmax
A0(tox,T) < 80 dB
A0(tox,T) > 80 dB
Tmin
tox,min
Y = 45%
tox,max process parameter
tox [µm]
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operating parameter
T [°C]
Tmax
Spec: A0 > 80 dB
for all
Tmin < T < Tmax
A0(tox,T) < 80 dB
Tnom
A0(tox,T) > 80 dB
Tmin
tox,min
Yest = 100%
wrong
tox [µm]
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operating parameter
T [°C]
Tmax
Spec: A0 > 80 dB
for all
Tmin < T < Tmax
A0(tox,T) < 80 dB
A0(tox,T) > 80 dB
Tmin
tox,min
Yest = 92%
wrong
tox [µm]
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Monte Carlo-Analysis of A0 over tox at T = Tmax
operating parameter
Spec: A0 > 80 dB
T [°C]
for all
Tmax
Tmin < T < Tmax
A0(tox,T) < 80 dB
A0(tox,T) > 80 dB
Tmin
tox,min
Yest = 45%
correct
tox [µm]
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Worst-Case Point
Ò The worst-case point is the most
probable set of process parameters
where the performance violates the
specification.
Ò This point is found deterministically
using worst-case analysis with multidimensional sensitivity diagnoses.
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Worst-Case Analysis
Ò The distance between nominal and worstcase point is a measure of the robustness of
the circuit.
Ò Increasing the distance results in higher
yield.
WCD [σ]
0
1
2
3
4
Est. Yield [%]
50
84
97.7
99.87
99.997
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Yield Confirmation
Total
Total
Yield
Yield
Partial
Partial
Yields
Yields
Yield
Yieldestimate
estimate
95%
95%confidence
confidence
interval
interval
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Optimization Methodologies
Ò
Ò
Ò
Ò
Ò
Traditional engineer interactive
Monte Carlo based
Automatic block generators
Global optimizers
Deterministic optimization
Sensitivity driven
Multi-dimensional
Worst Case Distance (WCD) based
Automatic, user guided or both

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Traditional Design Approach
; Senior designers “know” best approaches
;
Do you want to hold more or longer design review
meetings?
; “Spot check” results using simulation
;
When do you know if run enough simulation?
[ Limited to bandwidth of senior staff
[ Usually still need to use silicon to confirm
[ Newer processes getting too complex
[
Especially in highly integrated SoC/ASIC
Ò There’s an old saying I like here:

Wisdom comes experience
Experience comes from making mistakes
Who can afford mistakes in silicon?
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Standard Monte Carlo Driven
; Delivers net end result
; Runs complete assessment
;
;
Covers all parts swept – if you swept enough conditions
Requires extra user analysis and interpretation
[ Consumes a lot of simulation
[
[
Does not assure running at correct worst case conditions
Computational limits to where use is reasonable
[ Not capable to isolate root causes
[
And does not provide quantified impacts of each
[ Does not provide design insight
Ò Proven long-standing and predictable

Useful for validation
But very limited for design use
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Extended Monte Carlo
ÒApplications:
Yield
estimation
Influence analysis (root cause analysis, contributor analysis)
Performance distributions
Means, standard deviations, correlations of performances
Margin distributions
Scatter plots
ÒFeatures
Operating
conditions considered
Global process variation and local variation (mismatch)
Simultaneous simulations over multiple LSF queues
Flexible data export
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Automatic Block Generators
; Quickly generates standard blocks
;
Why not just go with silicon proven IP “parts”?
[ Requires shift of methods to equations
[
Most have been “black box” approaches
[ Usually still need to use silicon to confirm
[ Limited to pre-tested topo’s
[
[
User adds topo’s are not silicon validated
Works okay on really small blocks
Ò Joe Costello said it best in EETimes March 4, 2005

“The problem, Costello noted, is that those large
IP blocks were very complicated to design, given
the need to account for process variations.”
Article by Richard Goering on the demise of Barcelona
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Global Optimizers
; Locates maximum performance only
; Uses standard simulator
[ Black box – ignores designer’s inputs
[
[
No user guiding nor designer insight feedback
No understanding how it derived result
[ Limited to nominal (& corners) process point
[
Not able to deal with local PV and mismatch
Frequently gets only 70% to 80% design yield
[
Throws out previous data & completely restarts
[
[ Requires a lot of simulation each time
Ò Usually gets the best “nominal” performance

Does not assure there are no cliffs nearby
Not able to do real true yield optimization
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Deterministic Optimization
; Speeds up entire design flow
;
;
Multi-dimensional optimization
Sensitivity diagnosis driven
; Uses standard simulator & models
; Surgically isolates and remedies problems
;
;
Provides great diagnoses and insight to designer
User can guide it and focus efforts on key design needs
[ Requires statistical device models
[
[
In order to do complete and true yield
Without statistical data still can do all but yield optimization
Ò Only approach that can realistically address today’s
designer device level DFY needs
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Monte Carlo vs. Worst Case Distance
# Simulations
10 Bil
High robust Circuits
100 Mio
Monte Carlo
analysis Gains in
efficiency
1 Mio
10.000
Worst-case
distances
100
2σ
3σ
4σ
5σ
6σ
Yield/
7σ Robustness
ÒMonte Carlo effort increases exponentially with robustness
ÒDeterministic WCD is only known reasonable effort
method for optimization of circuits over 3 σ (> 99.87%)
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Where Can DFY be Improved?
Ò Better access to statistical models
Improved
device model development
Initial & ongoing “QA” to match drifts, etc
Does not replace IP verification silicon
Ò Faster/parallel Simulation licensing
Maybe
also improve API’s on simulators?
Ò More cooperative teaming/partnering
No
one vendor/customer can do it all
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Example DFY Success
On a 0.13um bandgap voltage reference circuit
Ò isQED paper by ST Microelectronics of Agrate Italy

Poster session presented by Carlo Roma 3/22/05
Other authors: Daglio, Sandre, Pasotti & Poles
Ò First pass silicon initially yielded ~48%

DesignMD diagnosis matched with this range of yield
Extended temperature requirements caused yield losses
Ò Sensitivity analysis prescribed problem areas

Isolated constraint & mismatch problems to remedy
Also did parameter reduction to speed-up analysis
Ò Topology verification diagnosed yield <82%

Maximum design yield was not high enough
Ò After topology change design yield ~93%

Optimization automated and sped up flow
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Impacts of Yield Optimization
Partial yields of performances in typical design flow
Sample circuit: Cascode amplifier migration to 0.13um and 90nm processes
6.0
99.997%
0%
Total
Yield
4.0
2.0
0.0
98%
82.9%
Yield
99.99%
Yield
Nominal
Yield Opt.
-2.0
50%
2%
-4.0
Initial
Gain
Slewrate
Transit frequency
Power
Phase margin
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Yield Y
Worst-Case-Distance βw
8.0
Financial ROI of DFY
∅ Saving-Potential p.a.
1. Company wide
yield improvement
today
With DFY
>+5%
> 300 M €
2. Company wide
reduction of
time-to-market
today
With DFY
>-5%
> 300 M €
3. Reduction of
development effort
today
With DFY
> - 20%
> 14 M €
4. Minimize risk
of redesigns
today
With DFY
> - 50 % > 30 M €
Source: Infineon, Bosch (EkompaSS03)
Total > 644 M €
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Keys to Optimize 1st Silicon Yield
Ò Provide designer insight to

Impacts of process
Key dependencies
Ò Enable user guidance & interaction
Ò Increase productivity of designers
Ò Use standard existing design flow

Simulators, design tools and models
Ò Optimize performance & yield

Maximize all performances
For all process variations
Over all operating conditions
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Who does Not Need DFY?
Ò Very low volume
Like when producing one satellite
But how about robustness?

Ò Older IC process tech’s
Mismatch a problem since pre-IC days
Guard bands give up too much performance

Ò If you buy chips not wafers

What about foundry underlying costs?
Ò Is anyone here not affected by yield?
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DFY Delivers
Design Complexity Management
Parameter
& performance sensitivities
Performance Optimization
Covers
full process spread
Includes worst case conditions
Deterministic algorithm
Yield Optimization
Time
to market & volume shipments
Maximize parametric yield
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DFY = Better Results Sooner
Ò Maximize Yield Prior to Layout
Ò For more details on DesignMD:

http://www.chipmd.com/content/products.htm
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