Building transmission system with errors detection

Digital Communication
Laboratories
P. Bakowski
bako@ieee.org
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DigiCom Labs
There are 5 labs related to the digital communication
1. Study of the parameters of metal cables including: characteristic
impendance, attenuation and basic data rate
2. Study of a digital transmission system with error detection and
correction
3. Study of line codes with base-band (part 1) and analogue
modulation (part 2)
4. Study of a QPSK modulation and communication system based on
SIMULINK model
5. Study of CRC code and communication system based on SIMULINK
model
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L2: transmission systems
The following lab is based on the usage of MODICOM
boards 3/1 – transmitter and 3/2 -receiver.
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L2: MODICOM 3/1
Transmitter includes Function
Generator with:
Two adjustable-amplitude D.C. levels for use in
either SLOW (1 b/s) or FAST (240 kb/s) mode
Two synchronized adjustable-amplitude
sineways (1kHz/2 kHz) for use in FAST mode.
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L2: MODICOM 3/1
2 sampled values - each with
16 kHz sampling rate
Analog channel multiplexer and sample/hold amplifier
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L2: MODICOM 3/1
7 bits data sample
data serial
output
Analog to Digital converter, error check code generator,
shift register and switched faults generator.
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L2: MODICOM 3/1
error check code generator
and 2-bit switch
00: OFF (7 data bits)
01: EVEN parity bit (6 data bits)
10: ODD parity bit (6 data bits)
11: HAMMING code (4 data bits)
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L2: MODICOM 3/1
error check code generator
and 2-bit switch
00: OFF (7 data bits)
01: EVEN parity bit (6 data bits)
10: ODD parity bit (6 data bits)
11: HAMMING code (4 data bits)
4 switched
faults:
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switch 1 – D6 always 0 (before ADC)
switch 2 – D6 always 1 after check
switch 3 – D5 always seen by check as 1,
even if the data sent is 0
switch 4 – effects the transmitter SYNC code
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L2: MODICOM 3/1
Pseudo-random code for frame
synchronization
7 bits
7 bits
frame
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L2: MODICOM 3/2
RX DATA
INPUT
parallel bus to
error detection correction unit
shift register and data latch
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L2: MODICOM 3/2
error detection/correction logic
HAMMING check
bits: (C2,C1,C0)
parity bit: C0
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00: OFF (7 data bits)
01: EVEN parity bit (6 data bits)
10: ODD parity bit (6 data bits)
11: HAMMING code (4 data bits)
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L2: MODICOM 3/2
RX data
input
clock regenerator
(fundamental frequency)
from data stream
RX clock
input
RX frame
synchronization
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L2: MODICOM 3/1 to 3/2 transmission
frame
clock
data
Three synchronization modes:
1. data + clock + frame synchronization
2. data + frame synchronization
3. data only
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L2: MODICOM 3/1 to 3/2 transmission
OFF
MODE 1
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TX CLOCK => RX CLOCK
TX SYNC => RX SYNC
TX DATA => RX DATA
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L2: MODICOM 3/1 to 3/2 transmission
Frame synchronisation code generation & detection
pseudorandom
generator
ON
ON
MODE 2
TX CLOCK => RX CLOCK
TX DATA => RX DATA
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L2: MODICOM 3/1 to 3/2 transmission
Frame synchronisation code generation & detection
ON
TX DATA => RX DATA
MODE 3
ON
clock
regeneration
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L2: MODICOM 3/1 to 3/2 transmission
Communication modes:
The system samples two analogue inputs with 16 kHz rate
and generates the 15-bit frames: 2*7 bits per sample plus
frame synchronization bit (16000 frames per second)
Depending on the error detection/correction mode:
1. All 7 bits of a sample are sent as data
2. 6 MS bits are data are sent as data plus one parity bit
3. 4 MS bits of data are coded with Hamming code on 7 bits
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L2: MODICOM 3/1 to 3/2 transmission
Errors injection:
The error bits may be generated before the data coding
(parity or Hamming) D => C, or after the data coding.
Depending on the state of the 2-bit error switch we have:
switch 1 – D6 always 0 (before ADC)
switch 2 – D6 always 1 after check code generation
switch 3 – D5 always seen by check as 1, even if the data
sent is 0
switch 4 – effects the transmitter SYNC code
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L2: MODICOM 3/1 to 3/2 transmission
Functional errors:
At the receiving end we may induce several functional
defaults:
switch 1 – PLL default (false clock)
switch 2 – default of frame synchronization
switch 3 – default of Hamming code detector and corrector
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L2: experimental study
In MODE 1 (data, clock and sync):
With FAST mode show on the oscilloscope the transmitted
and the received signals with different amplitudes.
Use the continuous signals (DC) to determine the dynamics
of AD converters.
With SLOW mode analyse the operation of the transmitter
and the receiver. Look for synchronisation bit the values of
transmitted samples/frames.
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L2: experimental study
In MODE 2 (data and clock only):
With FAST mode analyse the transmitted and the received
signals with different input values.
Verify the state of frame synchronization counter - switch ON.
What is the result when the switch is OFF ?
With SLOW mode analyse the frame synchronisation at the
emission end and at the reception end.
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L2: experimental study
In MODE 3 (data only):
Only FAST mode is possible (clock must be regenerated
dynamically from a long stream of bits)
1. Tune the clock regenerator by adjusting the TRIM knob in
order to see that the frame synchronisation bit stays on for all
values of input data.
2. Verify the transmission for
different amplitudes of sin signal.
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L2: experimental study
Study of error detection (parity) and error correction
(Hamming) codes:
Without errors:
1. In mode 2 and SLOW analyse the operation of EVEN and
ODD parity bits
2. In mode 2 and SLOW analyse the operation of HAMMING
code for D6-D3 data values and the corresponding C6-C0
codes.
3. In mode 2 and FAST verify the operation of all system with
HAMMING code.
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L2: experimental study
With transmitter errors:
1. In mode 3 and FAST analyse the operation without error
protection and SF2 set; the same test with parity bits !
2. In mode 3 , FAST, and with SF2 set, analyse the operation
with HAMMING code
3. In mode 2 and FAST, and SF1 set verify the operation of all
system without the error protection, with error detection, and
with HAMMING code.
4. The same as in point 3 with mode 2 and FAST, and SF3
set !
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L2: experimental study
With receiver faults:
1. In mode 3 and FAST analyse the operation without error
protection and SF1 set; the same test with parity bits !
2. In mode 2 , FAST, and with SF2 set, verify the operation of
all system without the error protection, with error detection,
and with HAMMING code.
3. In mode 2 and FAST, and SF3 set verify the operation of all
system without the error protection, with error detection, and
with HAMMING code.
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