Device Packaging

Advance Program and Registration on-line: www.imaps.org/devicepackaging
IMAPS International Conference and Exhibition on
Device Packaging
March 17 - 20, 2008
Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona - USA
in conjunction with the Global Business Council (GBC) Spring Conference
March 16 & 17, 2008 - www.imaps.org/gbc
Courtesy of FlipChip International, LLC
DEVICE PACKAGING PROGRAM OVERVIEW
General Chair:
Ted Tessier, FlipChip International, LLC
Technical Chairs:
James J.-Q. Lu, Rensselaer Polytechnic Institute
Christo Bojkov, MAXIM
Beth Keser, Freescale Semiconductor
Lou Nicholls, Amkor Technology
Monday, March 17
6 Professional Development Courses - 1/2 Day
8:00 am - Noon & 1:00 pm - 5:00 pm
Tuesday, March 18 - Thursday, March 20
Technical Sessions
Tuesday, March 18
Wafer Level Packaging Panel: 7:00 pm - 9:00 pm
Robert Dean, Auburn University
Ajay Malshe, University of Arkansas
Peter Tortorici, Medtronic Microelectronics Center
Steve Adamson, Asymtek
Corporate Sponsors:
Courtesy of Rensselaer Polytechnic Institute
Wednesday, March 19
Poster Session in Exhibit Hall: 1:30 pm - 2:55 pm
3D Panel: 7:00 pm - 8:00 pm
EXHIBITION
Tuesday, March 18
Wednesday, March 19
10:30 am - 7:00 pm
9:00 am - 3:00 pm
Presented by: International Microelectronics And Packaging Society (IMAPS)
Bringing Together the Entire Microelectronics Supply Chain!
Hotel Cut-off: February 12, 2008
Early Bird Registration Deadline: February 12, 2008
Program at a Glance
Sunday, March 16
GBC Registration: 6:00 pm
GBC Welcome Reception: 6:00 pm
Monday, March 17
Registration: 7:00 am - 6:00 pm
GBC Conference: 8:00 am - 5:00 pm
Professional Development Courses (1/2 Day)
8:00 am - Noon
PDC2
PDC1
Fundamentals of Packaging of MEMS
and Related Microsystems and
Nanomanufacturing
Instructor: Ajay Malshe, University of
Arkansas
Hermeticity Testing and “Near
Hermetic” Packaging Concepts
Instructor: Thomas Green, TJ Green
Associates LLC
PDC3
Package on Package (PoP) Applications, Requirements, Infrastructure and
Technologies
Instructor: Moody Dreiza, Amkor
Technology
Professional Development Courses (1/2 Day)
1:00 pm - 5:00 pm
PDC4
PDC5
PDC6
Packaging Issues & Solutions for
MEMS, MOEMS, and Nanoelectronics
Instructor: Ken Gilleo, ET-Trends LLC
Area Array Microelectronics Package
Reliability
Instructor: Amaneh Tasooji, Arizona
State University
Advances in 3D Integration and
Packaging
Instructor: James J.-Q. Lu, Rensselaer
Polytechnic Institute
Welcome Reception: 5:00 pm - 7:00 pm
Tuesday, March 18
Wednesday,
1 March 19
Thursday, March 20
6:00 am - 7:00 pm
Registration
6:00 am - 7:00 pm
Registration
6:00 am - 11:00 am
Registration
10:30 am - 7:00 pm
Exhibits Open
7:00 am - 11:30 am
Technical Sessions
WA1, WA2, WA3, WA4
7:00 am - 11:00 am
Technical Sessions
THA1, THA2
7:00 am - 11:00 am
Technical Sessions
TA1, TA2, TA3, TA4
10:30 am - 12:55 pm
Lunch Break In Exhibit Hall
9:00 am - 3:00 pm
Exhibits Open
11:30 am - 12:30 pm
Lunch In Exhibit Hall
(Food served from 11:30 am - 12:30 pm)
1:00 pm - 6:00 pm
Technical Sessions
TP1, TP2, TP3
6:00 pm - 7:00 pm
Reception In Exhibit Hall
7:00 pm - 9:00 pm
Wafer Level Packaging
Panel Discussion
1:30 pm - 2:55 pm
Poster Session In Exhibit Hall
2:30 pm - 6:15 pm
Technical Sessions
WP1, WP2, WP3, WP4
7:00 pm - 8:00 pm
3D Packaging
Panel Discussion
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Conference Overview
The Fourth Annual Device Packaging Conference (DPC2008) will be held in Scottsdale, Arizona, on March 17-20, 2008. It is an
international event sponsored and organized by the International Microelectronics And Packaging Society (IMAPS).
This year’s conference will feature technical sessions, panel discussions, a poster session, professional development courses
and a vendor exhibition and technology showcase. The conference provides a focused forum on the latest technological
developments in 5 topic areas related to microelectronic packaging: Flip Chip; Wafer Level/Chip Scale Packaging; 3-D
Packaging; MEMS; and Biomedical. Technical presentations in these 5 topic areas cover a full range of issues from new
developments and materials through manufacturing and reliability. The professional development courses offered are also
focused on these 5 topical areas of microelectronics and offer an additional valuable resource to attendees. The Global
Business Council (GBC) will co-locate its Spring Conference March 16-17, focusing on the business aspects of these technologies. There will be several networking receptions and gatherings throughout the week, including the opening reception,
meals, and other social events.
The conference is a major forum for the exchange of knowledge and provides numerous technical, social and networking
opportunities for meeting leading experts in these fields. The conference will attract a diverse group of people within industry
and academia. It provides a chance for educational interactions across many different functional groups and experience levels.
People who will benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, sales and marketing.
Organizing Committee
3D Packaging
Flip Chip
Wafer Level /
Chip Scale
MEMS
Biomedical
Technical Chairs:
James J.-Q. Lu, Rensselaer
Polytechnic Institute
Technical Chairs:
Beth Keser, Freescale
Semiconductor
Technical Chairs:
Beth Keser, Freescale
Semiconductor
Technical Chairs:
Robert Dean, Auburn
University
Technical Chairs:
Peter Tortorici, Medtronic
Microelectronics Center
Christo Bojkov, MAXIM
Lou Nicholls, Amkor
Technology Inc.
Ted Tessier, FlipChip
International
Ajay Malshe, University of
Arkansas
Steve Adamson,
Asymtek
Committee:
Christo Bojkov, MAXIM
Committee:
Christo Bojkov, MAXIM
Committee:
David Coe, UAH
Committee:
Mona Masghati, SIONEX
Corporation
Robert Hubbard, Lambda
Technologies, Inc.
Robert Hubbard, Lambda
Technologies, Inc.
Ron Foster, Axept
Committee:
Sitaram Arkalgud, SEMATECH
Flynn Carson, STATS
ChipPAC, Inc.
Kuan-Neng Chen, IBM T.J.
Watson Research Ctr.
Philip Garrou, Microelectronic
Consultants of NC
Morihiro Kada, ASET
Daniel Lu, Intel Corporation
Thorsten Matthias, EVGroup
Brian Grantham, U. S. Army
Chunho Kim, Intel Corporation
Chunho Kim, Intel
Corporation
Matt Perry, ENGENT, Inc.
Thorsten Teutsch, PacTech
Thorsten Teutsch, PacTech
Michael Toepper, Fraunhofer
IZM
Hong Yang, Applied Micro
Circuits Corporation
Michael Toepper, Fraunhofer
IZM
Hong Yang, Applied Micro
Circuits Corporation
Peter Ramm, Fraunhofer IZM
Leonard Schaper, University
of Arkansas
Paul Siblerud, Semitool, Inc.
Lee Smith, Amkor Technology
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Keith Warren, MEMS
Consultant
Vijay Varadan, University of
Arkansas
Preceding the Device Packaging Conference....
GBC Spring Conference
Addressing Cost and Performance-Driven Semiconductor Packaging
Challenges through the Supply Chain
March 16-17, 2008
Radisson Fort McDowell Resort and Casino
Please visit www.imaps.org/gbc to register for the GBC Conference.
Sunday, March 16
12:00 PM – GBC Golf Tournament*
(*Golf Outing is tentative. More information will be available on the GBC page on-line.)
We-Ko-Pa Golf Club (www.wekopa.com), Scottsdale/Fort McDowell, AZ
6:00 PM - 7:00 PM – Registration
6:00 PM – GBC Welcome Reception (Beverages and Appetizers)
Monday, March 17
7:00 AM - 6:00 PM – Registration
7:00 AM - 8:00 AM – Continental Breakfast
8:00 AM – Opening Remarks and Keynote
Howard Imhof, GBC Chair
Keynote Address: The 10th Anniversary Edition of the International Technology Roadmap for Semiconductors
Bill Bottoms, Chief Executive Officer, NanoNexus
9:30 AM - 12:00 Noon
Microelectronics Industry Overview
1:45 PM
Package Optimization for Cost Driven Applications
Lee Smith, Amkor Technology
9:30 AM
Packaging the Supply Chain
Jim Walker, Gartner/Dataquest
2:30 PM - Break
2:45 PM - 5:00 PM
Performance Driven Challenges
10:15 AM - Break
10:30 AM
The Role of Precious Metals in Electronics & the Semiconductor Supply
Chain - Past, Present, & Future
Conor Dullaghan, Metalor Technologies USA
2:45 PM
Common Platform Alliance for Semiconductor Packaging Technology
Scottie Ginn, IBM Systems and Technology Group
3:30 PM
Challenges for Adopting Standard IC Packaging Solutions for High
Reliability Medical Applications
Robert Erich, Medtronic Microelectronics Center
11:15 AM
How M&A Activities Are Affecting the Supply Chain in the Electronic
Packaging Industry
Loren Lancaster, Core Capital
12:00 PM - Lunch
4:15 PM
Future Packaging Needs for High Reliability Microelectronics
Mark Dimke, Rockwell Collins
1:00 PM - 2:30 PM
Cost Driven Challenges
5:00 PM - Closing Remarks and Adjourn
5:00 PM - 7:00 PM - Device Packaging Welcome Reception
(GBC Attendees Invited - Beverages and Appetizers)
1:00 PM
How Do Materials and Process Suppliers Enable Next-generation
Semiconductor Packaging While Addressing Ever Increasing Cost
Pressures?
Steven Corbett, Cookson Electronics
SAVE $100 WHEN YOU REGISTER FOR GBC AND DEVICE!
VISIT WWW.IMAPS.ORG/DEVICEPACKAGING FOR MORE INFORMATION.
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MONDAY, MARCH 17
7:00 am –
6:00 pm
7:00 am –
8:00 am
8:00 am –
Noon
10:15 am –
10:30 am
Noon –
1:00 pm
1:00 pm –
5:00 pm
Professional Development Courses (PDCs)
Registration
Continental Breakfast
Morning Professional Development Courses (PDCs)
PDC1 - Fundamentals of Packaging of MEMS and
Related Microsystems and Nanomanufacturing
Instructor: Ajay Malshe, University of Arkansas
PDC2 - Hermeticity Testing and “Near Hermetic”
Packaging Concepts
Instructor: Thomas Green, Microelectronics Packaging
Consultant, TJ Green Associates LLC
PDC3 – Package on Package (PoP)
Applications, Requirements, Infrastructure
and Technologies
Instructor: Moody Dreiza, Amkor Technology
Break
Lunch
Only provided for those attendees registered for both AM and PM PDCs
Afternoon Professional Development Courses (PDCs)
PDC6 - Advances in 3D Integration and
PDC5 - Area Array Microelectronics Package
PDC4 - Packaging Issues & Solutions for MEMS,
Packaging
Reliability
MOEMS, and Nanoelectronics
Instructor: James J.-Q. Lu, Rensselaer
Instructor: Amaneh Tasooji, Arizona State University
Instructor: Ken Gilleo, ET-Trends LLC
Polytechnic Institute
2:30 pm –
2:45 pm
5:00 pm –
7:00 pm
Break
Welcome Reception (Device Packaging)
Fundamentals of Packaging of MEMS and Related Microsystems and Nanomanufacturing (PDC1)
Course Leader: Ajay P. Malshe, University of Arkansas
Course Description:
Fabrication and application-specific packaging of micro electromechanical systems (MEMS) is a subject of immense interest. Their application-specific
packaging with other components is challenging and unlike IC packaging, has a different set of demands from releasing, dicing-to-interconnection at
chip-scale and manufacturing at wafer-level. This globally-taught course will address silicon and non-silicon micro fabrication processes and related
design details, and packaging of silicon and non-silicon MEMS and related microsystems. The course will use a range of novel applications to advocate
the use of various fabrication and packaging processes. The course will also introduce a new area on the horizon: “nano packaging - manufacturing.” In
the broader scope of the subject, for the 21st century packaging community, infusion of signals (electrical, optical, chemical, mechanical, etc.), domains
(hermetic, vacuum, fluidic, optical, etc.) and scales (nano-to-micro-macro) are of significant importance for designing and developing next generation
engineered micro and nano products as well as for adding value / functions to existing products. Particularly, key words, namely MEMS, micro systems
and nano technologies have captured attention of technology leaders. MEMS and related micro systems are typically divided into two application areas:
sensors and actuators. These are applied for a range of applications such as automotive, biomedical, optical, RF, etc. Examples of systems, devices
TM
and related application-specific packages are accelerometers, gyros, DMD , lab-on-a-chip, SMART drugs, etc. Further, with the major investment and
key advancements in nanotechnology, nano integrated MEMS and related micro devices and packages are of major importance to the next generation
engineered electronic systems.
Course Notes: (1) Chapter “Packaging of MEMS and MOEMS: Challenges and A Case Study” by Drs. Malshe and O’Conner, (2) copies of the
transparencies on MEMS and Nanomanufacturing, and (3) publication-“NSF-EC Workshop on Nanomanufacturing and Processing: A Summary Report,”
Malshe et al., SPIE International Symposium on Smart Materials, Nano-, and Micro-Smart Systems, Melbourne, Australia, December 2002.
Specific Topics Covered:
•
Introduction to MEMS and Related Microsystems
•
Fundamentals of silicon and other related micro fabrication techniques
•
Introduction to M4 in comparison to MEMS
•
Nontraditional micro fabrication processes, such as femtosecond laser and micro EDM processing
•
Introduction to applications of MEMS and related microsystems and application-specific packaging
•
System-on-a-chip vs. system-in-a-package: challenges and trade-offs for MEMS packaging
•
IC packaging vs. MEMS packaging: differences and similarities
•
Packaging and assembly of MEMS and related micro devices: role of die release, handling, dicing, attachment, interconnections, outgassing,
encapsulation, wafer-level packaging, etc., for application-specific MEMS and related microsystem packaging
•
Wafer-level and chip scale packaging of MEMS and related microsystems
•
Implementation of MEMS to RF, fluidics, sensors, and related applications
•
Manufacturing of related products and markets
•
Nanopackaging and Integration
•
Q & A Session
Who Should Attend?
The course is meant for industry and academic leaders and investors in science and engineering with interest in MEMS and related micro and nano
systems. Highly recommended for R&D scientists, engineers and managers involved in sensors, actuators, instrumentation and systems related to micro
and nano systems technology. Graduate students with special interest in the above areas will also find it useful.
Ajay P. Malshe (Ph.D., 1992) is the 21st Century Endowed Chair Professor of Materials, Manufacturing Processes and Integrated Systems at the Department of Mechanical
Engineering and adjunct-faculty of Electrical Engineering as well as Microelectronics and Photonics Program. He is Director of the Materials and Manufacturing Research
Laboratories (MMRL; a cluster of 5 laboratories). Malshe has multidisciplinary research programs in the field of MEMS and microelectronics packaging and integration,
nanomanufacturing and surface engineering for advanced machining. He has authored over one hundred twenty-five peer-reviewed publications, four book chapters, and
holds seven patents. His landmark scientific and engineering contributions are nano-particle composite coatings, particularly cubic boron nitride - titanium nitride composite
coating (cBN-TiN), electric discharge machining (electric pen lithography-EPL), wafer level chip scale packaging of MEMS and related microsystems, nano stamping of
quantum structures, nano-mechanical machining system-on-a-chip, chemo-mechanical as well as laser polishing of diamond films, femtosecond laser for chemically clean
nano and micro machining of difficult-to-machine materials. He has received sixteen awards for research, education and service achievements (1996-2006). The most recent
prestigious recognitions, Frost & Sullivan 2005 Technology Excellence Award and 2006 Top 25 Micro and Nano Innovations from R&D Magazine and Micro/Nano Newsletter
are due to his team’s invention contribution in the area of nanocomposite coating. He is a Fellow of Institute of Physics, London, UK and is listed in Lexington’s Who’s Who.
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He has graduated over twenty-five graduate students (PhD/MS), trained numerous post-doctoral fellows, and provided research experience to several undergraduate and high
school students. He has an extensive track record of global collaborations with academic institutions and companies. Prof. Malshe is the Chief Technology Officer (CTO) of
the two companies he has co-founded in the fields of nanomanufacturing (NanoMech LLC; www.nanomech.biz) and high-density Microsystems packaging (OmniPak LLC) in
the state of Arkansas. He is a member of professional societies such as ASEE, ASME, IEEE, IMAPS, MRS and SME and has arranged and chaired sessions and symposia in
the areas of his expertise.
Hermeticity Testing and “Near Hermetic” Packaging (PDC2)
Course Leader: Thomas J. Green, Microelectronics Packaging Consultant, TJ Green Associates LLC
Course Description:
Hermeticity of electronics packages and hermeticity test techniques continue to be of critical importance to the microelectronics packaging community.
Specifically, for MEMS, OLEDs, wafer scale packaging, optoelectronic devices, bio-medical implants and packaging for military and space. In contrast
to a hermetic cavity-style package "near hermetic" packages are being developed that rely on polymeric materials, such as LCP, to produce a package
with just enough moisture protection to survive in the intended end-use environment.
This course begins with an overview of hermetic sealing processes. The class will then examine the accepted leak test techniques as prescribed in Mil
Standard 883 Test Method 1014. This misunderstood test method is often a source of frustration. The basic science behind helium fine leak testing
(both the fixed and flexible methods) will be presented. Difficulties and limitations in fine leak testing of small volume packages is a major industry
concern, especially among the space community.
Recently techniques have been developed that measure both gross and fine leaks in the same pass. Optical Leak Test (OLT) is a method that employs
a laser interferometer to measure out of plane deflection on a lid surface in response to a changing pressure and, relates these measurements to an
equivalent helium leak rate. Cumulative Helium Leak Detection (CHD) is a variation on conventional leak detection that allows for gross and fine leak
testing in the same pass and the potential for helium leak detection at leak rates several orders of magnitude lower than that available with conventional
leak detection methods.
Packages made from polymeric materials as opposed to traditional hermetic seals (i.e., metal, glasses, ceramics) require a different approach from a
testing standpoint. The problem is now one of moisture diffusion through the barrier and package interfaces. A brief review of the techniques and
methods to evaluate a "non-hermetic" approach is presented.
In addition to a comprehensive set of course notes, each student receives a copy of “Hermeticity of Electronic Packages” by Hal Greenhouse (Noyce
Publications 2000) and a "Practical Guide to TM 1014" authored by the Instructor.
Who Should Attend?
This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for
sealing, leak testing and RGA results and for those responsible for evaluating package designs requiring hermetic or "near hermetic" packages.
Thomas J. Green is the Principal at TJ Green Associates LLC, a Veteran owned small business devoted to providing world class teaching and consulting services in
microelectronics packaging. As an independent consultant Tom's been responsible for numerous successful projects in the area of wirebond, die attach and package seal and
associated leak test. As an Adjunct Professor at the National Training Center for Microelectronics he designs curriculum and teaches industry short courses relating to
advanced microelectronics manufacturing processes. He has over twenty-five years of experience in the microelectronics industry at Lockheed Martin Astro Space and USAF
Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified
microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. He has conducted experiments and presented technical papers at NIST
and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. Tom is an active member of IMAPS and a Fellow of the
Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.
Package on Package (PoP) Applications, Requirements, Infrastructure and Technologies (PDC3)
Course Leader: Moody Dreiza, Amkor Technology
Course Description:
This course will take an in-depth view of the applications, market requirements, supply chain infrastructure and technologies associated with the BGA
package stacking platform commonly referred to as package on package (PoP).
This course will help you decide when and how PoP technology can provide system level semiconductor integration benefits; how you can evaluate and
select the optimum PoP technology for your applications by understanding the complex mix of cost, performance and business / logistic benefits PoP
provides; where industry standards, device floor-planning and supply chain infrastructures can reduce the total cost or time to market when
implementing a PoP solution; how the PoP platform aligns with industry roadmaps to meet the higher density challenges associated with next generation
device integration and system design requirements; and what the key PoP design related parameters are and how they relate to package sizing and
selection.
PoP Technologies and Infrastructure covered will include:
The top PoP which is typically a memory component using stacked die multi-chip package technology to integrate a combination of memory devices.
Associated JEDEC memory interface standards will be highlighted.
The bottom PoP which is typically a logic component using advanced high density thin core substrate technology with special design and material
properties to enable integration of a high density mobile processor device and support stacking of combination memory top package. Enabling
technologies, and JEDEC mechanical design guidelines will be summarized.
The PoP infrastructure - including SMT stacking, pre-stacking and joint industry studies for stacking and board level reliability testing will be presented.
A section of the course will review real world high volume PoP applications used in multimedia mobile handsets based on industry teardown reports.
Quantify the technical and business / logistic factors that make up the total cost of ownership benefits which has been major driver of broad industry
adoption of the PoP technology.
The course will explore the critical role industry infrastructure development and JEDEC standards have played in the high rates of PoP adoption in
mobile multimedia applications.
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Who Should Attend?
Engineers, Scientists and Managers involved with or interested in learning about applications, market requirements, supply chain infrastructure and
technologies associated with the BGA package stacking platform commonly referred to as package on package (PoP).
Moody Dreiza’s current responsibilities are in the field of product management associated with Amkor Technology’s stacked package (PoP) product line. Moody’s previous
experience includes four years in Amkor’s design center supporting CSP and PBGA design and design tool automation. Moody has earned a Bachelor’s degree in Mechanical
Engineering from the University of Manchester Institute of Science and Technology (UMIST) in Manchester, England.
Packaging Issues & Solutions for MEMS, MOEMS, and Nanoelectronics (PDC4)
Course Leader: Ken Gilleo, ET-Trends LLC
Course Description:
This new course provides an overview of MEMS (Micro-Electro-Mechanical Systems), MOEMS (aka Optical-MEMS) and Nanotechnology packaging
strategies and technologies. Topics include package designs, materials, and processes for these three related device technologies. MEMS and MOEMS
devices face considerable packaging challenges. Special packaging requirements will be covered in detail and a variety of options offered with a costreduction focus. Package types include metal, ceramic, wafer-level, non-hermetic plastic and near-hermetic injection molded cavity. Hermeticity
measurement, criteria, acceptable levels, and issues are discussed. In-package and on-chip “packaging agents,” such as getters, molecular coatings,
and volatile anti-stiction/lubricants, are included.
Packaging trends discussion encompasses cost-reduction with ceramic designs, hermetic capping to enable plastic overmolding, laser sealing,
microinjection plastic cavity types, and the 100% WLP (wafer-level package). MEMS-specific commercial packaging information is provided and several
successful case histories are described. Fluidic-MEMS, an important emerging area, is discussed including fluidic coupling and “pluggable” packaging.
Finally, requirements for future Nanotechnology devices will be predicted based on known properties of materials and the characteristics of experimental
devices. The case will be made for the adoption of MEMS packaging for future Nanoelectronic devices. Find out if packaging Nanoelectronics will be a
serious challenge or easier than expected - you may be surprised!
Who Should Attend?
Inventors, product developers, innovators, marketing personnel, analysts, equipment providers, and technologists in electronics, medical, biology,
BioMed, analytical field, optoelectronics, materials, telecom systems, and military.
Dr. Ken Gilleo is a chemist, inventor, IP specialist, expert witness, writer and consultant in materials, printed circuits, plastic packaging, assembly and emerging technologies
including MEMS, MOEMS and Nanotechnology. He developed getters, low cost plastic packages, adhesives and laser sealing for MEMS and MOEMS. He has produced over
500 articles, technical presentations and workshops and his 7th book, “MEMS/MOEMS Packaging” was published in late 2005. He has helped pioneer low-cost plastic
packaging for MEMS and worked on packaging designs, materials and processes.
Area Array Microelectronics Package Reliability (PDC5)
Course Leader: Amaneh Tasooji, Arizona State University
Course Description:
The objective of this course is to provide an overview on area array package reliability, analysis and tools and bestow awareness on critical factors
impacting microelectronics packaging reliability.
Area Array microelectronic packages with small pitch and large I/O count grid array are used in commercial and military applications such as in
aerospace, medical, telecommunication, transportation, etc. Reliability and risk assessment analysis of these widely used packages is a critical element
of product design and field support. Current practice in reliability focuses on thermal cycling of manufactured components and monitors the component
failure under the accelerated test conditions (ATC) representing the factory and OEM assembly, shipping and storage, and on/off environment of most
electronic products (user interface). Acceleration Factor (AF) is then determined using ATC data and the performance of the package under “use
condition;” hence, the package service reliability is predicted by extrapolation and application of AF. Statistical methods and life prediction methodologies
are used in conjunction with local/global elastic and/or inelastic stress/strain analysis in component reliability assessment.
This course briefly reviews Area Array design and discusses reliability approach, analysis and tools. Solder joint reliability is discussed in detail by
reviewing the published ball grid and column grid array (BGA/CGA) data, and evaluating the impact of various parameters (e.g., materials, design, and
processing parameters) on it. Deformation and failure mechanisms influencing reliability of solder joints are discussed in detail and current life prediction
models and failure modes such as brittle/ductile fracture, creep, fatigue, corrosion, and over-aging are discussed to further extend and reinforce the
intended learning. Solder joint microstructure and the Inter-Metallic Compounds (IMC) evolutions that may take place during thermal processing and/or
product application (isothermal and cyclic aging), and their impact on reliability are discussed by reviewing the Optical and Scanning Electron
Microscopy images and characterization data.
Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with
area array packages and general device assembly technologies.
Dr. Amaneh Tasooji has more than 23 years of industrial and academic experience in engineering, manufacturing, and e-business. She received her Ph.D. in Materials
Science and Engineering from Stanford University in 1982 and has a B.S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and
processing, component design, manufacturing, quality, and supply chain in many industries such as microelectronics, aerospace, and nuclear. She has had many technical
and leadership responsibilities while at Honeywell/AlliedSignal and has developed many materials behavior, deformation, and fracture models to improve life prediction and
design capabilities, thereby increasing product reliability. Dr. Tasooji is the recipient of many technical/engineering and leadership awards including ASTM Sam Tour Award
for distinguished contribution to research, development, and evaluation of corrosion testing and modeling. She holds a patent on “Adaptive Knowledge Management System
for Vehicle Trend Monitoring, Health Management and Preventive Maintenance,” and has technical licenses for computer software on “Predicting Stress Corrosion Cracking in
Nuclear Fuel Rods.” Dr. Tasooji has developed and delivered many graduate engineering courses (e.g., “Introduction to Micro-electronic Packaging,” “Overview of Materials
Science and Engineering for Microelectronics Packaging,” “Advanced Packaging Analysis and Design: Material Considerations,” and “Nuclear Materials”) and many
undergraduate courses (e.g., “Structure and Properties of Materials” and “Physical Metallurgy”) at Arizona State University. She has leveraged new technology and e-learning
concepts in developing web-based learning tools to be used in conjunction with face-to-face teaching, while emphasizing an Interactive Learning concept.
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Advances in 3D Integration and Packaging (PDC6)
Course Leader: Prof. James Jian-Qiang Lu, Rensselaer Polytechnic Institute
Course Description:
An overview of 3D integration and packaging will be presented, including motivation, key technologies and status towards commercialization. The major
motivations discussed include miniaturization of micro-systems; performance increase in speed and data bandwidth due to massive small-sized interchip interconnects; heterogeneous system integration of variety of technologies; and lower manufacturing cost for specific applications using particular
3D platforms.
In this course, 3D integration technologies are divided into 4 categories – transistor build-up, wafer-to-wafer stack, die-on-wafer assembly, and
packaging-based 3D. In transistor build-up 3D, active devices are built-up over an IC wafer. In wafer-to-wafer stack 3D, different systems are first
fabricated independently and then stacked and interconnected vertically. The die-on-wafer assembly is similar to a SoC approach, but with known-gooddies (KGDs) assembled on an IC wafer, then processed in wafer-level. In the last category, the ICs are packaged vertically in die-to-die, system-inpackaging (SiP) and package-on-package (PoP) fashions.
This course will discuss all these technologies, with emphasis on technology status and potential applications. The issues associated with each
technology category will be discussed, including integration architecture and design tools, yield and cost, thermal and mechanical constraints, and
manufacturing infrastructure. Finally, future directions into micro/nano/electro-opto/bio system hyper-integrations including MEMS will be presented,
showing 3D hyper-integration as a very promising emerging architecture for future computer, network, nanotech, and biotech.
Who Should Attend?
Engineers, managers and executives involved in future R&D investments, assembly and product development of electronic packaging, and wanting
fundamental understanding of 3D technologies, as well as the materials and equipment suppliers wanting to know about the existing and future 3D
integration technologies and options, will greatly benefit from this course.
James Jian-Qiang Lu received his Dr. rer. nat. (Ph.D.) degree from Technical University of Munich in December 1995, and is currently an Associate Professor in Electrical
Engineering at Rensselaer Polytechnic Institute (RPI), Troy, NY. At RPI, he has been leading the Interconnect Focus Center (IFC) flagship research program of 3D hyperintegration technology since 1999, and several other programs with focus on hyper-integration and micro-nano-bio interfaces for future chips. He has authored/co-authored
more than 160 publications in refereed journals, conferences or books, and given a number of invited presentations, seminars and short courses. Dr. Lu also served as
technical chair, workshop chair, session chair, panelist and panel moderator for many conferences. He is a senior member of IEEE (EDS & CPMT), a member of APS, MRS,
ECS, and a member of IMAPS National Technical Committee (Chair of 3D Packaging).
Welcome Reception
(Device Packaging Conference)
Monday, March 17th
5:00 pm - 7:00 pm
GBC Attendees are Invited!
Exhibition and Technology Showcase
Tuesday, March 18th
10:30 am - 7:00 pm
Wednesday, March 19th
9:00 am - 3:00 pm
Student Paper Competition for Flip Chip and Wafer Level/Chip Scale Packaging
sponsored by:
7
TUESDAY, MARCH 18
3D Packaging
6:00 am –
7:00 pm
6:15 am –
7:00 am
7:00 am –
11:00 am
7:00 am –
7:30 am
7:30 am –
8:00 am
8:00 am –
8:30 am
8:30 am –
9:00 am
9:00 am –
9:30 am
9:30 am –
10:00 am
10:00 am –
10:30 am
10:30 am –
11:00 am
Morning Technical Sessions
Flip Chip
BioMedical
MEMS
Wafer Level /
Chip Scale Packaging
Registration
Continental Breakfast
TA1:
3D Chip Packaging
Technology and
Applications
Chairs: Leonard Schaper,
University of Arkansas; Lee
Smith, Amkor Technology
Inc.
TA2:
Components, Packaging, and
Assembly in Biomedical
Applications
Chairs: Peter Tortorici,
Medtronic Microelectronics
Center; Steven J. Adamson,
Asymtek
TA3:
MEMS Processing
Technologies
Chairs: Donald W. Johnson,
MicroChem Corp; Keith
Warren, Independent MEMS
Consultant
TA4:
WL-CSP Board Level
Reliability I
Chairs: Pasi Nummila, NOKIA;
Kyle Baker, CMD
3D Integration Technologies
and Architectures for Portable
Applications
Volkan Ozguz, Irvine Sensors
Corporation
Electronic Packaging for Medical
Systems
Donald Hayes, MicroFab
Technologies, Inc.; Donald Hicks,
University of Texas at Dallas
A High Resolution Liftoff Patterning
Technique for Harsh Environment
Vapor Material Deposition.
Jordan Neysmith, Honggang Jiang,
Second Sight Medical Products Inc.
A Component Level Approach to
Medical Device Qualification
Dave Parkin, Medtronic, Inc.
Eutectic Metallurgies for MEMS
Applications
Shari Farrens, Sumant Sood, SUSS
MicroTec
Laser Tacking Ribbon Wire to
Battery Case in Packaging of an
Implantable Biomedical Device
Guangqiang Jiang, Yaomin Lin,
Alfred E. Mann Foundation for
Scientific Research
Silicon Package for MEMS and
Optical Devices
Akinori Shiraishi, Shinko Electric
Industries Co. Ltd.
Thermal Fatigue Properties and
Grain Boundary Character
Distribution of Lead-Free Sn-1.2Ag0.5Cu Solder Interconnects on WLP
Shinichi Terashima, Takayuki
Kobayashi, Masamoto Tanaka,
Kohei Tatsumi, Nippon Steel
Corporation
A Novel Re-passivation/RDL CSP
Technology for Minimizing Parasitic
Elements in ASIP (Application
Specific Integrated Passive)
Products
Phil Holland, Harry Gee, Umesh
Sharma, California Micro Devices
WLCSP : Challenges, Performances
and Trends.
Franck Dosseul, Christophe Serre,
Eric Bernier, ST Microelectronics
Water Penetration Study for a
Wireless 3D Electronic Patch
Jakob Janting, DELTA Danish
Electronics, Light & Acoustics
Application of Advanced
Photosensitive Etch Protection
Coating in TMAH Silicon Wet
Etching
J. Dalvi-Malhotra, X. F. Zhong, C.
Planje, K. Yess, Brewer Science, Inc
Mechanical Shock Robustness of
Different WLCSP Types
Mikael Johansson, Pasi Nummila,
Nokia Corporation
A New Corrosion-Free, Permanent
Epoxy Resist for MEMS and WLP
Applications
Donald Johnson, Wendy Dai,
MicroChem Corp; Pedro GTC Jorge,
DuPont Electronic Technologies;
Hidataka Uno, DuPont Kabushiki
Kaisha
Second Level Interconnect
Mechanical Robustness
Norman Owens, Freescale
Semiconductor; E. H. Wong, R.
Rajoo, S. K. W. Seah, C. S.
Selvanayagam, Institute of
Microelectronics; W.D. van Driel,
NXP Semiconductors; J. F. J. M.
Caers, X. J. Zhao, Philips Applied
Technologies; L. C. Tan, M. Leoni,
P. L. Eu, Freescale Semiconductor,
Inc.; Y.-S. Lai, C.-L. Yeh, Central
Labs, ASE, Inc.
Fine Pitch WLCSP Reliability for
Portable Electronic Devices
Eric Ouyang, Witoon Kittidacha,
Bharatwaj Ramakrishnan, Karntida
Vattananiyom, Elizabeth Neyman,
Spansion Inc.
High Performance Miniature
3D RF SiPs Combining Active
Silicon with a Silicon-based
Integrated Passive Device
Jean-Marc Yannou, Philippe
Suchet, Stephane Bellenger,
NXP Semiconductors
Flex Technology for Foldable
Medical Flip Chip Devices
Barbara Pahl, Thomas Loeher,
Technical University Berlin;
Hans Burkard, Josef Link,
Hightec MC AG; Anders E.
Petersen, Oticon A/S; Rolf
Aschenbrenner, Fraunhofer
Institute for Reliability and
Microintegration
Advances in Flip Chip Thermal
Compression Bonding Process
for SIP Device Packaging
Toru Mizuno, Philip Couts,
TDK Corporation
Flip Chip Track
begins on
Wednesday,
March 19.
Coffee Break In Foyer
Lead-free Rework of Packaged
Stacked CSP Components
Satyanarayan Iyer, Gurudutt
Chennagiri, SMART Modular
Technologies Inc.
Effect of Temperature on Carbon
Nanotube Field Effect Transistors
(CNTFETs) for Bio-sensors
Applications
Bashirul Polash, Hasina Huq, The
University of Texas-Pan American
Wafer Level Packaging; Chip
to Wafer Approach Using Flux
Less Soldering and Featuring
Hermetic Seal Capability
Gilbert Lecarpentier, SET
(Formerly SUSS Device
Bonder Division)
Equipment and Process
Solutions for Chip to Wafer
Stacking
Hannes Kostner, Datacon
Technology GmbH
Miniature Chemical and Biomolecular Sensors enabled by
Direct Write Micro-dispensing
Technology
David Wallace, Patrick Cooley,
Donald Hayes, MicroFab
Technologies, Inc.
Exhibition and Technology Showcase
10:30 am – 7:00 pm
Lunch Break In The Exhibit Hall: 10:30 am – 12:55 pm
(Food served from 11:30 am – 12:30 pm)
8
TUESDAY, MARCH 18
3D Packaging
Afternoon Technical Sessions
Flip Chip
BioMedical
MEMS
Wafer Level /
Chip Scale Packaging
TP3:
WL-CSP Board Level
Reliability II / Panel
Discussion
Chairs: Ted Tessier, Flip Chip
International, David Hayes,
Amkor Technology
1:00 pm –
6:00 pm
TP1:
Wafer-Level 3D
Integration and ThroughSi-Vias (TSVs) – I
Chairs: Peter Ramm,
Fraunhofer; Sitaram
Arkalgud, SEMATEC
TP2:
MEMS System Architecture &
Reliability
Chairs: Robert Dean, Auburn
University; Lee Levine,
Consultant - Process Solutions
Consulting
1:00 pm –
1:30 pm
Development of 3D High
Performance Memory
Robert Patti, Tezzaron
Semiconductor
A Variant of the First FullyDifferential Capacitive Sensor for
use in Scanning Probe Microscopy
Applications to Nano-Fabrication
Randall Peters, Sheng-Chiang
(John) Lee, Mercer University
Physics Department
A Packaging Solution to Reduce
Electrical Noise in MEMS Capacitive
Elements Resulting from
Environmental Mechanical
Vibrations
Robert Dean, Seong Kim, Chen
Chen, George Flowers, A. Scott,
Edward Hodel, Auburn University
Determining a Robust WLCSP
Mounting Process Using Six Sigma
Methodology
Dennis Lang, Fairchild
Semiconductor
Reliability of MEMS Vacuum
Packaging at Die or Wafer Level
Joel Collet, Stéphane Nicolas, Julien
Bon, Antoine Filipe, Stéphane
Renard, Tronics Microsystems
Hermetic Package Leak Testing ReVisited
Richard Kullberg, Robert Lowry,
Technical Affiliate, Oneida Research
Services, Inc.
Material Properties of an Epoxy
Based Wafer Applied Coating Using
A Novel Curative
David Zoba, Russel Stapleton, John
Hill, Lynn Yanyo, LORD Corporation
Low Expansion Substrates for Wafer
Level Packaging
Greg Rudd, Kalista Kusnadi,
Spectra-Mat, Inc.
Reliable MEMS Contact Through
Environment Control
Michael Dugger, David Asay,
James Ohlhausen, Seong Kim,
Sandia National Laboratories
Board Level Reliability Results for
Amkor’s 12x12 I/O WLCSPnl™
Rex Anderson, Robert Moody, Boyd
Rogers, Dan Mis, Amkor
Technology
1:30 pm –
2:00 pm
2:00 pm –
2:30 pm
2:30 pm –
3:00 pm
3:00 pm –
3:55 pm
4:00 pm –
4:30 pm
4:30 pm –
5:00 pm
5:00 pm –
5:30 pm
DRIE Achievements for TSV
Covering Via First and Via Last
Strategies
Michel Puech, Jean-Marc
Thevenoud, Nicolas Launay,
Matthieu Horgnies, Ketan
Patel, Xavier Guichenal, JeanMarc Gruffat, Alcatel Micro
Machining Systems
High Throughput Low CoO
Industrial Laser Drilling Tool
Aleksej Rodin, N.Brennan,
J.Callaghan, Xsil Ltd
Flip Chip Track
begins on
Wednesday,
March 19.
BioMedical Session
held on
Tuesday Morning,
March 18.
Cost-Effective Cu-TSV
Interconnects by EMC3D
Paul Siblerud, Semitool &
EMC-3D; Thorsten Matthias,
EVG; Hind Beaujon, Alcaltel;
Delphine Perrottet, XSil;
Jürgen Wolf, FhG; Mark
Scannell, Leti
Single Device Tracking – Cost
Benefit Analysis
Dave Huntley, KINESYS Software
Coffee Break In Exhibit Hall
High Rate Copper Filling Within
Through Silicon Vias for 3-D
Chip Stacking
Charles Sharbono, Rozalia
Beica, Tom Ritzdorf, Semitool
Inc.
MICROFAB DVF 200: A Fast,
Robust, Electrochemical
Process for Thru Silicon Vias
Applications
Thomas Richardson, Christian
Rietmann, Cai Wang, Pingping
Ye, Chen Wang, Yun Zhang,
Joe Abys, Cookson
Electronics, Enthone
Fabrication, Assembly, and
Evaluation of 10um Diameter
Cu/Sn and Solder Bump Bond
Arrays
Alan Huffman, Matthew Lueck,
John Lannon, Dorota Temple,
RTI International; Bill Sepp,
Technic, Inc.
A Comparison of Reliability
Behaviour of Different Solder Ball
Materials for WLCSP Products
Thomas Lange, Carsten Lutterloh,
Arne Kraemer, NXP
Semiconductors Germany GmbH
Title TBD
Luu Nuyen, National Semiconductor
Lead Free Wafer Level-CSP
Interconnects with Improved
Mechanical Performance
Anthony Curtis, Ronnie Yazzie,
Anna Hiner, Michael E. Johnson,
Guy Burgess, Ted Tessier, Flip Chip
International
5:30 pm –
6:00 pm
6:00 pm –
7:00 pm
Reception In The Exhibit Hall
7:00 pm –
9:00 pm
Wafer Level Packaging/Reliability Panel Discussion
WLCSP reliability has been a topic of considerable interest and discussion as the usage of this highly space efficient packaging option proliferates. We are fortunate to
have some of the most prominent WLCSP technology experts in the industry participating in this conference. This panel discussion will serve as a forum for the sharing of
WLCSP best known practices and reliability expectations of particular interest to DPC attendees that make, sell or use WLCSP technologies in their products.
9
WEDNESDAY, MARCH 19
3D Packaging
6:00 am 7:00 pm
6:15 am 7:00 am
7:00 am 11:30 am
7:00 am –
7:30 am
7:30 am –
8:00 am
8:00 am –
8:30 am
8:30 am –
9:00 am
Morning Technical Sessions
Flip Chip
BioMedical
10:30 am –
11:00 am
11:00 am –
11:30 am
Wafer Level /
Chip Scale Packaging
Registration
Continental Breakfast
WA1:
Wafer-Level 3D
Integration and ThroughSi-Vias (TSVs) – II
Chairs: Paul Siblerud,
Semitool; Christo Bojkov,
MAXIM
WA2:
Flip Chip Packaging
Performance
Chairs: Jon Aday, Amkor
Technology Inc.; Bob Hubbard,
Lambda Technologies, Inc.
WA3:
Polymer and Laminate MEMS
Chairs: Jordan Neysmith,
Second Sight Medical Products
Inc.; Richard C. Kullberg,
Asána Techne, LLC
WA4:
WL-CSP Bumping
Chairs: Rob Erich, Medtronic;
Rex Anderson, Amkor
Technology
Advanced Bonding Technology
For Wafer-Level 3D Integration
Bioh Kim, Thorsten Matthias,
Markus Wimplinger, Stefan
Pargfrieder, Paul Lindner, EV
Group
Thermal Process Induced
Wafer Misalignment in 3D
Integration
Sang Hwui Lee, Kuan-Neng
Chen, Douglas La Tulipe,
Albert Young, Jian-Qiang Lu,
Rensselaer Polytechnic Inst.
3D Integration Technologies for
Wireless Sensor Systems (eCUBES)
Peter Ramm, Fraunhofer IZM;
Maaike Taklo, Sintef; M.
Jürgen Wolf, Technical
University of Berlin
Copper Through Silicon Vias
(TSV): Physical Design and
Reliability
Sergey Savastiouk, ALLVIA,
Inc.; Ephraim Suhir, UCSC
CoreEZ™ Package Reliability with
Mixed Leaded and Lead Free Flip
Chip Interconnect
Deborah Schepis, David Alcoe,
Glenn Dearing, David King, Cheryl
Palomaki, Endicott Interconnect
Molded Flip Chip
Nokibul Islam, Miguel Jimarez,
Hansen Sy, BY Jung, JY Gim, YS
Jung, SC Choi, Lito Mendoza,
Amkor Technology, Inc.
Epoxy Siloxane Polymers for Micro
and Nano Fabrication Applications
Pei-I Wang, Dexian Ye, Toh-Ming
Lu, Ram Ghoshal, Rajat Ghoshal,
Rensselaer Polytechnic Inst.
C4NP – Solder Bumps for Flip Chip
and MicroBumps for 3D
Klaus Ruhmer, SUSS MicroTec,
Inc.; David Hawken, James Busby,
Russell Budd, David Danovitch, IBM
Study of Laser Assisted
Modifications in Liquid Crystal
Polymer (LCP) for Packaging of
MEMS Devices
Ajay Malshe, Ujjwala Darvemulla,
University of Arkansas
Optimization of the Dry Film
Lithography Process For Copper
Pillar Metallization Applications
Chester Balut, Pedro Jorge, DuPont
Company, Electronic Technologies
Hermetically Sealed Flip-Chip and
Column-Grid Array Packaging
Technology
Keith Sturcken, C. Hagerty, J.
Hughes, BAE SYSTEMS
Microfluidic Systems in PCB
Technology
Lienhard Pagel, Stefan Gassmann,
University of Rostock, Germany
Effect of Design Factors on Microvia Reliability of Flip Chip BGA
Polymeric Substrates
Dennis Leung, Xilinx; Guna
Selvaduray, San Jose State
University
Packaged Multi Sensor System for
Fisheries Research: New Test
Methods of Package
Karen Birkelund, Anders Hyldbård,
Erik Thomsen, Technical University
of Denmark - Department of Micro
and Nanotechnology
Process to Produce High Aspect
Ratio Electroplated Copper Pillars
on 300 mm Wafers
Chunwei Chen, S. Lee , B. Plass, G.
Pawlowski, AZ Electronic Materials;
W. Flack, A. Nguyen, Ultratech; T.
Ritzdorf, D. Ericksen, Semitool
ENIG Versus ENEPG Under Bump
Metallization for Leadfree WL-CSP
Solder Bumps - a Comparison of
Intermetallic Properties Using High
Speed Pull Test
Thorsten Teutsch, Axel Scheffler,
Hideo Mihara, Thomas Oppert, Elke
Zakel, Pac Tech USA
9:00 am –
3:00 pm
9:00 am –
10:00 am
10:00 am –
10:30 am
MEMS
BioMedical Session
held on
Tuesday Morning,
March 18.
Exhibition and Technology Showcase
9:00 am – 3:00 pm
Coffee Break In Exhibit Hall
Through-Silicon Via based 3D
IC Technology: Electrostatic
Simulations for Design
Methodology
Maxime Rousseau, Olivier
Rozeau, Gérald Cibrario, Gilles
Le Carval, Marie-Anne Jaud,
Patrick Leduc, CEALéti/Minatec, CNRS-LAAS &
STMicroelectronics
A Unique Dry Film Photoresist
System for TSV Formation and
Protection
Chester Balut, DuPont
Company, Electronic
Technologies; Colin Tsai,
DuPont Company, Taiwan
High Resolution DRIE Resist
for High Density Through
Silicon Vias
Harris Miller, Janice Collins,
MicroChem Corp.
Studies on the Thermal Cycling
Reliability of Cu Column/SnAg
Double-Bump Flip Chip Assemblies
on Organic Substrates for Fine Pitch
Applications
Ho-Young Son, Il-Ho Kim, JinHyoung Park, Soon-Bok Lee, Gi-Jo
Jung, Byung-Jin Park, Kyung-Wook
Paik, Korea Advanced Institute of
Science and Technology (KAIST)
Thermal Sub-modeling of Flip Chip
Ceramic Package Area Array
Interconnects
Mark Eblen, Kyocera America, Inc.;
Ronald Jensen, Honeywell
Aerospace Electronic Systems
Polymer MEMS Accelerometer
Integrated with Organic Electronics
Aditi Rane, Ramesh Ramadoss,
Robert Dean, Auburn University
Understanding The Wafer Bumping
Business Model: A Look at a New
Approach In Bumping Interconnect
and Packaging Solution
Rey Alvarado, J2 Design Services
LLC
Polymer MEMS/PCBMEMS and
Packaging for BioTag Systems in
the Environment
David Fries, Stan Ivanov, Heather
Broadbent, Pragnesh Bhanushali,
University of South Florida, College
of Marine Science
Innovative Photoresist Removal
Technology for Wafer Level
Packaging
Cass Shang, Mihaela Cernat, David
Maloney, Anthony Rardin, DuPont
EKC Technology
Application and Performance of nonsilicone Thermal Interface Materials
Murali Sethumadhavan, Joe Chun,
Rogers Corporation
Solder Paste Printing And Release
In Fine Pitch CSP Processes
Daniel Baldwin, Paul Houston,
Engent, Inc.
Lunch In Exhibit Hall: 11:30 am – 12:30 pm
Poster Session In Exhibit Hall: 1:30 pm – 2:55 pm
Effect of Intermetallic Compounds Growth of Component Side on Board Level Mechanical Reliability
Jae-Hoon Choi, Hyun-Jeong Ham, Yong-Hyun Kim, Dong-Chun Lee, Hui-Soek Kim, Samsung Elect.
Sn-Ag-Cu Solder for Portable and High Temperature Electronics Devices
Ganesh Iyer, Eric Ouyang, Witton Kittidacha, LK Suresh, Spansion Inc.
An Equivalent Power Plane Model with Frequency-Dependence and Fast Transient Simulation Method
Tadashi Ishikawa, Takayuki Watanabe, Hideki Asai, Shizuoka University
Hybrid Integrated Optical Circuits Utilizing Flip Chip Bonding
Robert Lee, Al Benzoni, Joel Paslaski, Pete Sercel, HOYA Corporation USA
High Performance Photoresist Removers Enable Through Silicon Vias
Jim Cullen, David Maloney, Pat Starrs, Anthony Rardin, Eric Finson, DuPont EKC Technology
Study On Composition And Morphology Of Au-Sn Solder Film Deposited By RF-Sputtering System
Dongjin Kim, D. H. Kim, J. W. Lee, G. B. Kim, H. K. Lee, T. Y. Lee, Hanbat National Univ.
Application of Photo-imageable Thick Film Technology on Zero-shrinkage LTCC Tapes
Hyo-Tae Kim, Jong-woo Lim, Eun-heay Lee, Thomas Jun, Myoung Lib Moon, Joong-hee Nam, Donghoon Yeo, Ungyu Paik, Jonghee Kim, Korea Institute of Ceramic Engineering and Technology
A Novel Wafer Level Packaging Process for CMOS Image Sensor Package
Chang-Hyun Lim, Samsung Electro-Mechanics Co., LTD.
10
WEDNESDAY, MARCH 19
Afternoon Technical Sessions
Flip Chip
2:30 pm –
6:15 pm
WP1:
3D Fabrication,
Assembly and Evaluation
Chairs: Phillip Garrou,
Microelectronic
Consultants of NC; James
J.-Q. Lu, Rensselaer
Polytechnic Institute
WP2:
Flip Chip Bumping and Bump
Characterization
Chairs: Thorsten Teutsch, Pac
Tech USA - Packaging
Technologies, Inc.; Lou
Nicholls, Amkor Technology,
Inc.
WP3:
MEMS Devices
Chairs: Tracy D. Hudson, U.S.
Army RDECOM AMRDEC; Ajay
Malshe, University of Arkansas
(HiDEC-MEEG)
2:30 pm –
3:00 pm
3D Technologies at CEA-Leti
Minatec
Léa Di Cioccio, D. Henry, P.
Leduc, A Mathewson, J. Brun,
B. Charlet, H. Moriceau, F.
Grossi, D Bordel, P. Gueguen,
P. Batude, P. Coudrain, J.M.
Fedeli, D. Van Thourout, C.
Seassal, N. Sillon, L. Clavelier,
G. Passemard, G. Poupon, M.
Scannell, CEA-LETI Minatec
Stacking Of Known Good
Rebuilt Wafers
Christian Val, 3D Plus
C4NP Technology: Present and
Future
Eric Perfecto, DY Shih, Bing Dang,
Kamalesh Srivastava, Luc Belanger,
IBM
A Proposal of Novel Micro OptoElectro-Mechanical Gyroscope Chip
Bo Zhang, MTE Kahn, Bohua Sun,
Cape Peninsula University of
Technology
Embedded Wafer Level Ball Grid
Array (eWLB)
Markus Brunnbauer, Thorsten
Meyer, Ralf Plieninger, Infineon
Technologies AG
A Novel Methodology for 3D
Integration Using Multilayer
Organics
George White, Sidharth
Dalmia, L. Carastro, V.
Sundaram, M. Swaminathan,
Jacket Micro Devices
Laser Dicing Technology for
Thin Silicon Wafers
Delphine Perrottet, Kali Dunne,
Billy Diggin, XSiL
Interfacial Reactions between Sn3.0Ag-0.5Cu Solder and Cu-Coated
PCB Coatings
Minerva Cruz, Guna Selvaduray, Six
Sigma
Development of a MEMS-based Kaband Phased Array for Passive
Electronically Steered Beam
Tracy Hudson, Janice Rock, Michael
Whitley, Andrew Jenkins, Michelle
Chaffin, U. S. Army RDECOM
AMRDEC
Scavenging Low Ambient RFSources for Microsystems
Tolgay Ungan, Leonhard Michael
Reindl, Department of Microsystems
Engineering-IMTEK
Thermal Performance Evaluation
and Optimization for Redistributed
Chip Package (RCP) Designs
Victor Adrian Chiriac, Beth Keser,
Larry Larsen, Lakshmi N.
Ramanathan, Duong Trung,
Freescale Semiconductor Inc.
Realization of System-in-Package
Modules by Embedding of Chips
Lars Boettcher, D. Manessis,
Alexander Neumann, A. Ostmann,
H. Reichl, Fraunhofer IZM Berlin
A MEMS-based Gas Sensor for the
Air Quality System Monitoring the
Automobile Indoor
Jung-Sik Kim, Si-Dong Kim, Jin-Ho
Yoon, Bum-Joon Kim, The
University of Seoul, Korea
Miniaturization by Component
Embedding Made Reliable and Cost
Effective
Thomas Gottwald, Ulrich Ockenfuss,
Schweizer Electronic AG
Investigating Defects in 3D
Packages Using 2D and 3D Xray Inspection
Evstatin Krastev, David
Bernard, Dage Precision
Industries, Inc.
Comparison of Thermal and Current
Effects for Electromigration Lifetime
Prediction for Sputtered Al/Ni(V)/CuUBM in Eutectic PbSn and Pb Free
Flip Chip Solder Joints
Mark Bachman, John Osenbach,
Dave Crouthamel (retired), Ron
Weachock, John Delucca, Frank
Baiocchi, LSI Corporation
Fundamentals of Electromigrations
in a Multiphase Material
Andre Lee, K.N. Subramanian, C.E.
Ho, Michigan State University
High Heat Flux Micro-Channel
Devices Using Liquid Metals for
Laser Diode Applications
Daniel Harris, Gary Wonacoot,
Robert Dean, Ashish Palkar, Auburn
University
A Stud-in-Via Interconnection for
Embedded Chip Scale Package:
Application to High Speed Memory
Chips
Li-Cheng Shen, EOL/ITRI
MEMS Acoustic Sensor with Direct
Spectral Output
Michael Kranz, Stanley Associates,
Inc.
Wafer Level Device Modification for
3D Embedded Die Applications
Ted Tessier, Anthony Curtis,
Michael E. Johnson, David
Lawhead, John Reche, Richard
Redburn, Flip Chip International
3:00 pm –
3:30 pm
3:30 pm –
4:00 pm
4:00 pm –
4:30 pm
4:30 pm –
4:45 pm
4:45 pm –
5:15 pm
5:15 pm –
5:45 pm
5:45 pm –
6:15 pm
7:00 pm –
8:00 pm
BioMedical
BioMedical Session
held on
Tuesday Morning,
March 18.
Ink Jet for Flip-Chip, 3D and WaferLevel Packaging
Donald Hayes, David Wallace, Mike
Boldman, Mike Grove, MicroFab
Technologies, Inc.
Alternative Nickel-based Surface
Finishes for
IC Substrate Applications in a Pbfree Environment
Hugh Roberts, Atotech USA Inc.;
Sven Lamprecht, Christian Sebald,
Atotech Deutschland GmbH
MEMS
Wafer Level /
Chip Scale Packaging
WP4:
Embedded Chip and Chips
First Technologies
Chairs: Bob Forman, Rohm and
Haas Electronic Materials;
Theodore G. Tessier, Flip Chip
International
3D Packaging
Coffee Break In Foyer
IR Thermal Microscopy for 3-D
Microelectronics Circuits
Tom Chung, R. Sandhu, B.
Poust, G. Pilkington, M.
Parlee, A. Noori, P. ChangChien, R. Tsai, A. Hirschberg,
Northrop Grumman Space
Technology
Market and Cost Analysis for
3D ICs
Eric Mounier, Jerome Baron,
Yole Developpement
Quantitative Analyses of
Electromigration Characteristics in
Pb-free Solder Bump and Cu Pillar
Bump Structures
Youngbae Park, Jang-Hee Lee, GiTae Lim, Byoung-Joon Kim ,YoungChang Joo, Seung-Taek Yang, MinSuk Suh, Qwan-Ho Chung, KwangYoo Byun , Kiwook Lee, Jaedong
Kim, Andong National University
Driving Advanced Packages
towards a Robust Reliable Design
Vijay Sarihan, Doug Mitchell, Beth
Keser, Freescale Semiconductor
3D Panel Discussion
Topics cover 3D technology platforms (SiP, PoP, Die-stack, Die-wafer, Wafer-to-wafer and Device-by-Device), unit processing technologies
and equipment/material capabilities, and future trends and technology drivers (applications and benefit).
Moderators: James J.-Q. Lu, Rensselaer Polytechnic Institute; Christo Bojkov, MAXIM
Opening Remarks: Dr. Phillip Garrou, Microelectronic Consultants of NC
11
THURSDAY, MARCH 20
3D Packaging
6:00 am –
11:00 am
6:15 am –
7:00 am
7:00 am –
11:00 am
7:00 am –
7:30 am
7:30 am –
8:00 am
8:00 am –
8:30 am
8:30 am –
9:00 am
9:00 am –
9:30 am
9:30 am –
10:00 am
10:00 am –
10:30 am
10:30 am –
11:00 am
Technical Sessions
Flip Chip
BioMedical
MEMS
Wafer Level /
Chip Scale Packaging
MEMS Track
held on
Tuesday,
March 18 and
Wednesday, March
19.
Wafer Level Track
held on
Tuesday,
March 18 and
Wednesday, March
19.
Registration
Continental Breakfast
THA1:
Analysis and
Applications of 3D
Integration
Chairs: Thorsten Matthias,
EVG; Flynn Carson,
STATS ChipPAC
THA2:
Flip Chip Packaging Materials
and Substrate Advances
Chairs: Beth Keser, Freescale
Semiconductor and Eric
Huenger, Rohm and Haas
Advanced CSP (ZyCSPTM)
based on 3-D LSI
Technologies for Sensor
Application and Beyond
Hirofumi Nakamura, Makoto
Motoyoshi, Kazutoshi
Kamibayashi, Manabu
Bonkohara, ZyCube Co., Ltd.
3D Stacking Device
Technology Using Wafer-toWafer Stacked Method
Nobuaki Miyakawa, Honda
Research Institute Japan Co.,
Ltd.
Enabling Technologies for 3D
Packaging of Optical Sensors
Juergen Leib, Michael
Toepper, Fraunhofer IZM;
Keith Cooper, Dietrich
Toennies, Katrin Weilermann,
Shari Farrens, SUSS MicroTec
Integrated System
Development for 3-D VLSI
Yang Liu, L. Schaper, S.
Burkett, A. Kamto,
I. U. Abhulimen, L. Cai, S.
Jacob, G. Jampana, University
of Arkansas
High-Density Microvia Technology
on Advanced Organic Substrate For
Next Generation Flip-Chip
Packaging
Venky Sundaram, Fuhan Liu, Hunter
Chan, Mahadevan Iyer, Rao
Tummala, Georgia Tech PRC; Hugh
Roberts, Sven Lamprecht, Atotech
Novel Electrically Conductive
Adhesives for Flip Chip Assembly
Interconnects
Myung Jin Yim, Yi Li, Kyung W.
Paik, C. P. Wong, Intel/Numonyx
Novel Concepts to Deliver High
Yield X3D-IC Packaging Based
on Wafer Scale Stacking
Sadeg Faris, Reveo, Inc.
Via Filling Applications for IC
Substrate and in Particular Flip Chip
BGA
Bernd Roelfs, David Baron, Atotech
Germany
Fabrication Effects on the Thermal
Behavior of a Flip Chip - Low
Temperature Cofired Ceramic
Package
Markus Norén, C. Hoffmann, W.
Salz, K. Aichholzer, EPCOS OHG
BioMedical Session
held on
Tuesday Morning,
March 18.
Underfill for Flip-Chip Packages in
the Future
Katsuyuki Mizuike, Tatsuya Ohori,
Makoto Shinohara, Nagase
ChemteX Corp.
The Next Generation in Substrate
Technology
R. Huemoeller, Amkor Technology
Coffee Break In Foyer
3-D Packaging and SiP CoDesign – the Business Case
for Standards
Ken Ball, Knowledge Based
Technical Consultancy Ltd.;
Georg Meyer-Berg, Infineon;
Alun Jones, TS2Micro;
Wolfgang Ackrodt, Bosch
Automotive; Donald Radley
Design, Fabrication, and
Testing of GSM/EDGE Mobile
Phone Module in RCP
Technology
George Leal, Robert Wenzel,
Trung Duong, George Leal,
Marc Mangrum, Beth Keser,
Doug Mitchell, Craig Amrine,
Chuck Egan, Phu Tran,
Freescale Semiconductor Inc.
Photoformable Thick Film Dielectric
Process Optimization for Reduced
Via Size
Doug Link, Starkey Laboratories,
Inc.; Mike Skurski, DuPont
Thank you to the Device Packaging Corporate Sponsors:
12
Device Packaging Exhibition and Technology Showcase
“An opportunity to talk to industry leaders”
Device Packaging 2008 will feature one collective Exhibition and Technology Showcase for vendors and suppliers who
support the many aspects of Device Packaging and each of the topical areas addressed during this Conference. This venue
features an ideal atmosphere for exhibiting companies to showcase their products and services to key decision making
professionals in the industry and for a large focused audience of attendees to engage these companies about the solutions
they need.
In addition to moving to a larger facility to accommodate more exhibitors, we have also enhanced the exhibit hall format this
year to encourage more interaction between the vendor companies and the attendees seeking information and solutions.
We have extended all breaks in the exhibit hall this year, including: a two and a half hour lunch break in the hall on
Tuesday; a one hour coffee break that afternoon; a one hour Tuesday evening reception; and lunch in the hall again
Wednesday, at 11:30 am, followed immediately by a poster session in the hall until 3:00 pm when exhibits close.
Full 8' by 10' exhibit booths will be on display. A list of exhibiting companies can be found on page 14 and the exhibit hall
floorplan can be found on page 15.
The exhibit floor has sold out again this year, making it the 3rd year in a row that this exhibition has quickly sold out. If you
have questions about exhibiting with IMAPS, or about getting signed up for the 2009 Device Packaging Conference, contact
Ann Bell at abell@imaps.org or 202-548-8717.
Exhibit Hours:
Tuesday - March 18
10:30 am - 7:00 pm
Refreshment Breaks, Lunch, and a Reception will be held in the Exhibit Hall.
Wednesday - March 19
9:00 am - 3:00 pm
Refreshment Breaks, Lunch and a Poster Session will be held in the Exhibit Hall.
For more information, visit:
www.imaps.org/devicepackaging or contact IMAPS at 202-548-4001
Exhibitors on the Device Packaging 2008 CD-ROM
IMAPS is offering Exhibiting Companies the opportunity to have an unlimited amount of product promotion information
on the Conference CD-ROM. Exhibitors must submit ONE pdf or word file, via e-mail, containing the information you want to appear to abell@imaps.org on or before March 15, 2008. Files must be sent to Ann Bell
(abell@imaps.org). Submissions must be as stated and arrive by the deadline. There is no charge for participation.
Conference CD-ROM
Conference Hotel
If you are unable to attend the Conference and would like a
copy of the CD-ROM of Presentations, you may purchase
a copy by using the registration form. Your copy will be
mailed to you after the event.
RADISSON FORT MCDOWELL RESORT & CASINO
10438 NORTH FORT MCDOWELL ROAD
SCOTTSDALE/FOUNTAIN HILLS, AZ 85264
PHONE: 480-789-5300 OR 800-333-3333
The cost is $200 for members; $300 for nonmembers,* plus
shipping and handling.
$209/night
On-line at: www.radisson.com/ftmcdowellaz. Promo. Code - IMAPS1
By Phone: please mention IMAPS-Device Packaging Conference
Reserve your copy on-line at www.imaps.org/
devicepackaging or call 202-548-4001.
Hotel Deadline: February 12, 2008
*includes a one-year IMAPS individual membership.
Rates and availability will not be guaranteed after the deadline.
13
Device Packaging Exhibition and Technology Showcase
Exhibiting Companies
(as of January 17, 2008)
The exhibit hall has sold out for the third straight year. The following 71 booths will be on display during Device Packaging
2008. Please visit the companies’ websites listed below for more information. A floorplan of this exhibit hall can be found
on page 15. If you have questions about exhibiting with IMAPS, or about getting signed up for the 2009 Device Packaging
Conference, contact Ann Bell at abell@imaps.org or 202-548-8717.
Company
AdTech Ceramics
www.adtechceramics.com
AI Technology
www.aitechnology.com
AkroMetrix, LLC
www.akrometrix.com
Amkor Technology, Inc.
www.amkor.com
Ansoft Corp.
www.ansoft.com
Antares Advanced Test Technologies
www.antares.com
Asymtek
www.asymtek.com
Atotech USA Inc.
www.atotechusa.com
AZ Electronics
www.az-em.com
Azimuth Electronics, Inc.
www.azimuth-electronics.com
Bennington Microtechnology Center
www.benningtonmicro.com
Brewer Science, Inc.
www.brewerscience.com
Chalman Technologies
www.cti-rep.com
Chip Supply, Inc.
www.chipsupply.com
CMC Interconnect
www.cmcinterconnect.com
Cyber Technologies USA
www.cybertechnologies.com
Datacon Technology GmbH
www.datacon.at
DuPont
www.dupont.com
Dyconex A.G.
www.dyconex.com
Endicott Interconnect Technologies, Inc.
www.endicottinterconnect.com
ESL ElectroScience
www.electroscience.com
EV Group
www.evgroup.com
F&K Delvotec, Inc,
www.fkdelvotecusa.com
Booth(s)
30
32
6
59
15
24
23
3
54
40
29
9
7-8
28
44
13
47
68-69
35
71
21
60
62
Company
FEI Company
www.feicompany.com
Gel-Pak/Quik-Pak
www.gelpak.com
Georgia Tech/Microsystems
Packaging Research Center
www.prc.gatech.edu/research/research.htm
GPD Global
www.gpd-global.com
HCM
www.hcm-france.com
HEI, Inc.
www.heii.com
Hesse & Knipps
www.hesse-knipps.com
Interconnect Systems, Inc.
www.isipkg.com
J Tech Distributors
www.jtechdist.com
JSR Micro, Inc.
www.jsrmicro.com
Lambda Technologies, Inc.
www.microcure.com
LINTEC Corporation
www.lintec-usa.com
Maxtek Components Corp.
www.maxtek.com
Micro Hybrid Dimensions, Inc.
www.micro-hybrid.com
MicroChem Corp.
www.microchem.com
MicroFab Technologies, Inc.
www.microfab.com
MJS Design
www.mjsdesigns.com
NAMICS
www.namics.co.jp
NEXX Systems, Inc.
www.nexxsystems.com
NTK Technologies, Inc.
www.ntktech.com
NuSil Technology
www.nusil.com
Oneida Research Services, Inc.
www.orsfr.com
Orthodyne
www.orthodyne.com
14
Booth(s)
65
39
14
58
18
57
1-2
49
5
4
56
41
51
36
16
46
45
38
48
64
50
34
26
Company
Pac Tech USA
www.pac-tech-usa.com
Palomar Technologies, Inc.
www.palomartechnologies.com
Photonics Spectra/
Laurin Publishing
www.photonics.com
Pure Technologies
www.puretechnologies.com
Reinhardt Microtech AG
www.reinhardt-microtech.ch
Reldan Metals, Inc.
www.reldanmetals.com
S.E.T.
Semitool, Inc.
www.semitool.com
Sikama International
www.sikama.com
Starfire Systems
www.starfiresystems.com
Stellar Microelectronics Inc.
www.stellarmicro.com
Surface Technology Systems, Ltd.
www.stsystems.com
SUSS Micro Tec
www.suss.com
Synergistic Technology Group, Inc.
TechSearch International
www.techsearchinc.com
Teledyne Microelectronics
www.teledynemicro.com
Ticona Engineering Polymers
www.ticona.com
Twilight Tech.
www.twilighttechnology.com
VLCSP Forum
www.vlcspforum.org
Weiss-Aug Co. Inc.
www.weiss-aug.com
West-Bond, Inc.
www.westbond.com
Zymet
www.zymet.com
Booth(s)
20
66
17
52
19
63
55
67
53
12
22
25
33
31
37
42
61
10
70
11
27
43
IMAPS 2008 Symposium - Call for Papers
Bringing Together the Entire Microelectronics Supply Chain!
Rhode Island Convention Center, Providence, Rhode Island
November 2-6, 2008
The 41st International Symposium on Microelectronics will be held at the Rhode Island Convention Center, Providence, Rhode Island – USA and is being
produced by the International Microelectronics And Packaging Society (IMAPS). The IMAPS Technical Committee seeks original papers that demonstrate
how new technologies and applications are expanding and redefining microelectronics “between the chip and the system.” The 41st Symposium on
Microelectronics will focus on the areas of Industry, Systems & Applications, Design, and Materials & Process. Abstracts should highlight the major
contributions of the work in each of these four areas of concentration. All abstracts submitted must represent original, previously unpublished work.
General Chair:
Larry Rexing, Heraeus Inc. - TFD
larry.rexing@heraeus.com
Technical Program Co-Chairs:
John Olenick
Ken Gilleo
ENrG Inc.
ET-Trends LLC
jolenick@enrg-inc.com
ken@et-trends.com
Planned Sessions Include:
Industry
Advanced Processes & Materials
♦ Biomedical
♦ 3D Packaging and High Density Substrates
♦ Telecom
♦ Electro-Static Protection
♦ Military Applications
♦ Photonic/Optoelectronic Packaging
♦ Consumer Electronics
♦ Underfill/Encapsulants and Adhesives
♦ Automotive Electronics
♦ Pb-Free Solder Materials, Processes, and Reliability
♦ Renewable Energy: Fuel Cells, Solar, Wind Generators
♦ Green Packaging / Compliance with RoHS
♦ Flip-Chip and Bumping: Processes, Reliability
Systems Packaging/Applications/Designs
♦ Packaging for Extreme Environments
♦ EMI/Signal Integrity/Electrical Modeling
♦ Package Reliability
♦ Thermal and Power Management
♦ Wirebonding and Stud Bumping
♦ Manufacturing, Outsourcing and Quality Assessment
♦ Microwave Communications
♦ Software and Firmware Applications
♦ Ceramic, Polymer, and Conductive Materials
♦ High Performance Interconnects and Boards
♦ Cu/Low-K
♦ Imaging Sensors
♦ LED Packaging
♦ Micro Packaging - MEMS and Nano Packaging
♦ Solid State Lighting
Translated Sessions (Invited Speakers Only)
♦ Emerging Technologies
♦ System Packaging
♦ Japanese (Japanese to English translation)
♦ Measurement Equipment
♦ Chinese (Chinese to English translation)
Poster Session
♦ Microwave and RF Applications
Outstanding papers that do not fit in planned or created sessions will
be considered for this interactive session.
Please send your 250-300 word abstract electronically only using the On-line submittal form at:
www.imaps.org/abstracts.htm
Abstract Cut-off Date: March 28, 2008
Notice of Acceptance: May 12, 2008
Final Manuscript Due: September 5, 2008
All Speakers are required to pay a reduced registration fee.
Cash Awards Offered: $2000 for Best Paper of Symposium; $500 for two Outstanding Papers of Symposium.
Accepted papers may be considered for publication in the IMAPS Journal of Microelectronics and Electronic Packaging.
If you need assistance with the on-line submission form, please contact Jackki Morris-Joyner (jmorris@imaps.org).
16
Upcoming
Events...Mark Your Calendar!
International Conference and Tabletop Exhibition on
Alternative Energy
Hotel Albuquerque Old Town
Albuquerque, New Mexico - USA
April 8 - 10, 2008
Visit www.imaps.org/energy for more information
IMAPS/ACerS 4th International Conference and Exhibition on
Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT)
Holiday Inn - City Centre
Munich, Germany
April 21 - 24, 2008
Visit www.cicmt.org for more information
Topical Workshop and Tabletop Exhibition on
Military, Aerospace, Space and Homeland Security (MASH):
Packaging Issues and Applications
The Conference Center at the Maritime Institute
Linthicum Heights (Baltimore), Maryland - USA
April 28 - 30, 2008
Visit www.imaps.org/mash for more information
Co-located with the ATW on Advanced Substrates - April 30 - May 1
Advanced Technology Workshop and Tabletop Exhibition on
Advanced Substrates and Next Generation Semiconductors
The Conference Center at the Maritime Institute
Linthicum Heights (Baltimore), Maryland - USA
April 30 - May 1, 2008
Visit www.imaps.org/substrates for more information
Co-located with MASH - April 28 - 30
International Conference and Tabletop Exhibition on
High Temperature Electronics (Hi-TEC)
Hotel Albuquerque Old Town
Albuquerque, New Mexico - USA
May 13 - 15, 2008
Visit www.imaps.org/hitec for more information
41st International Symposium on Microelectronics (IMAPS 2008)
Rhode Island Convention Center
Providence, Rhode Island - USA
November 2 - 6, 2008
Visit www.imaps2008.org for more information
17
iKNOW MICROELECTRONICS
IMAPS On-line Library of Searchable Technical Publications
IMAPS on-line library, iKnow Microelectronics,
provides a centralized, searchable database of the
technical papers and slides from IMAPS events and
publications offered by the Society.
iKnow Microelectronics currently contains more than 2,700 articles and publications
from symposia, conferences, workshops, web meetings and other publications from 2003
through 2008. IMAPS will continue to incrementally load additional historical publications
from 2002 and earlier throughout 2008.
iKnow Microelectronics contains the following publications in a Downloadable, CD-rom
and/or Printed format:
•
•
•
•
•
•
•
•
Journal of Microelectronics and Electronic Packaging (JMEP)
Advancing Microelectronics
IMAPS Symposium Proceedings
IMAPS Conference Proceedings
IMAPS Workshop Presentation Slides
Global Business Council Presentations
Podcasts (archived web meetings)
Reference Textbooks
Using iKnow’s Advanced Search Engine, you can locate papers by:
•
•
•
•
•
•
Keywords
Author
Primary Author Company
Event / Category
Year
Publication Format
Expand your knowledge and research abilities today!
Log-on to iKnow Microelectronics today at
www.imaps.org/imapsstore.
16
REGISTRATION FORM
REGISTER ON-LINE AT WWW.IMAPS.ORG/DEVICEPACKAGING
DEVICE PACKAGING CONFERENCE - MARCH 17 - 20, 2008
Member ID# _________________
‰ Dr. ‰ Mr. ‰ Ms.
First
Name________________________________M.I._____________Last
Company/Affiliation___________________________________________Job
Name_______________________________
Position___________________________
Address___________________________________________________________________________________________
City___________________________
Phone________________________
State______
Zip____________
Country____________________________________
Fax_________________________
Email_____________________________________
REGISTRATION FEES: EARLY REGISTRATION ENDS 2/12/08
PAYMENT
D EVICE C ONFERENCE F EES
Device Conference Fee:
$____________
Device & GBC Conference Fee:
$____________
Device Professional Course:
$____________
Device Additional Purchases:
$____________
Total Payment Due:
$____________
(On or before 2/12) (After 2/12)
‰Member (IMAPS)*
‰Non-Member*
‰Speaker* ‰Chair* ‰Chapter Officer*
‰Student*
‰Exhibits Only (Includes refreshments and food)
$650 $750
$750 $850
$400 $500
$275 $375
$25 $25
GBC & C OMBO F EES (R EGISTER FOR BOTH AND SAVE $100)
GBC & Device Packaging:
‰Member (IMAPS)*
$1075
$1375
‰Non-Member*
‰Speaker* ‰Chair* ‰Chapter Officer*
$825
‰Student*
$450
$100 savings already calculated in price above.
GBC Only:
‰Member (IMAPS)*
$525
‰Non-Member*
$725
$1225
$1525
$975
$650
$575
$775
*Includes one-year IMAPS individual membership or membership renewal
at no additional charge. Does not apply to corporate or affiliate memberships. Conference Fee includes an Abstract book, all meals listed and a CDROM of presentations. CD will be mailed 10 business days after the event.
DEVICE PROFESSIONAL DEVELOPMENT COURSES - 1/2 DAY
Monday, March 17: 8 am - Noon
‰Fundamentals of MEMS....PDC1
‰Hermeticity Testing....PDC2
‰Package on Package (PoP)....PDC3
Monday, March 17: 1 pm - 5 pm
‰MEMS, MOEMS, Nanoelectronics....PDC4
‰Area Array Microelectronics....PDC5
‰Advances in 3D Integration....PDC6
$375 $425
$475 $525
$375 $425
$375 $425
$375 $425
$375 $425
DEVICE ADDITIONAL PURCHASES
‰Guest/Family Member (meals only)
‰CD of Presentations (Member Rate)
‰CD of Presentations (Non-Member Rate)
‰Add to Ship in the US
‰Add to Ship Overseas
$150 $150
$200 $200
$300 $300
$7
$7
$25
$25
DEVICE EXHIBIT BOOTH (MARCH 18 - 19)
‰Member and Non-Member
SOLD OUT
HOUSING (Hotel Cut-off is February 12, 2008)
Radisson Fort McDowell Resort and Casino
10438 North Fort McDowell Road
Scottsdale/Fountain Hills, AZ 85264
Ph: 480-789-5300 or 800-333-3333
$209/Night
On-line at: www.radisson.com/ftmcdowellaz. Promotional Code - IMAPS1
By Phone: please mention IMAPS-Device Packaging Conference
DPC08
‰ Enclosed is a check payable in US funds to IMAPS
Charge my fees to:
‰ AMEX ‰ VISA ‰ MC ‰ Diners ‰ Discover
Card#______________________________ Exp.___________
Signature _________________________________________
Card billing address, if different from above: (required)
_______________________________________________________
_______________________________________________________
Email address required to receive confirmation of registration.
For Wire Transfer information call 202-548-4001.
Mail this form with payment to: IMAPS * 611 2nd Street, NE * Washington, DC
20002-4909. For credit card transactions, register on-line: www.imaps.org; or
register by phone with your credit card by calling 202-548-4001; Fax: 202-5486115. Additional information? E-mail: IMAPS@imaps.org, or visit our web
site: http://www.imaps.org. Cancellations will be refunded (less a $50
processing fee) only if written notice is postmarked on or before Friday,
February 29, 2008. No refunds will be issued after that date.
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