Sequential logic Sequential circuits Timing methodologies

Sequential logic
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Sequential circuits
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Timing methodologies
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cascading flip-flops for proper operation
clock skew
Basic registers
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simple circuits with feedback
latches
edge-triggered flip-flops
shift registers
simple counters
Hardware description languages and sequential logic
Autumn 2010
1
CSE370 - XIII - Sequential Logic
Circuits with feedback
 
How to control feedback?
 
what stops values from cycling around endlessly
X1
X2
•
•
•
Xn
Autumn 2010
switching
network
CSE370 - XIII - Sequential Logic
Z1
Z2
•
•
•
Zn
2
Simplest circuits with feedback
 
Two inverters form a static memory cell
 
will hold value as long as it has power applied
"1"
"stored value"
"0"
 
How to get a new value into the memory cell?
 
 
selectively break feedback path
load new value into cell
"remember"
"data"
"load"
Autumn 2010
"stored value"
3
CSE370 - XIII - Sequential Logic
Memory with cross-coupled gates
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Cross-coupled NOR gates
 
similar to inverter pair, with capability to force output to 0 (reset=1)
or 1 (set=1)
R
S
 
R
Q
S
Q'
Q
Cross-coupled NAND gates
 
similar to inverter pair, with capability to force output to 0 (reset=0)
or 1 (set=0)
S'
R'
Autumn 2010
Q
S'
R'
CSE370 - XIII - Sequential Logic
Q
Q'
4
Timing behavior
Reset
Hold
R
Q
S
Q'
Set
Reset
Set
Race
100
R
S
Q
\Q
Autumn 2010
5
CSE370 - XIII - Sequential Logic
State behavior or R-S latch
 
R
Q
S
Q'
Truth table of R-S latch behavior
S
0
0
1
1
R
0
1
0
1
Q
hold
0
1
unstable
Q Q'
0 1
Q Q'
1 0
Q Q'
0 0
Q Q'
1 1
Autumn 2010
CSE370 - XIII - Sequential Logic
6
Theoretical R-S latch behavior
 
State diagram
 
 
states: possible
SR=00
values of outputs SR=01
transitions: changes
based on inputs
R
Q
S
Q'
SR=10
Q Q'
0 1
SR=11
Q Q'
1 0
Q Q'
0 0
Q Q'
1 1
Autumn 2010
7
CSE370 - XIII - Sequential Logic
Theoretical R-S latch behavior
 
State diagram
 
 
states: possible
SR=00
values of outputs SR=01
transitions: changes
based on inputs
R
Q
S
Q'
SR=10
Q Q'
0 1
SR=11
SR=01
Q Q'
0 0
Q Q'
1 0
SR=00
SR=10
SR=11
Q Q'
1 1
Autumn 2010
CSE370 - XIII - Sequential Logic
8
Theoretical R-S latch behavior
 
State diagram
 
 
states: possible
SR=00
values of outputs SR=01
transitions: changes
based on inputs
R
Q
S
Q'
SR=10
SR=01
Q Q'
0 1
SR=01
Q Q'
1 0
SR=00
SR=10
SR=10
SR=11
Q Q'
0 0
SR=11
SR=11
SR=00
Q Q'
1 1
Autumn 2010
9
CSE370 - XIII - Sequential Logic
Theoretical R-S latch behavior
 
State diagram
 
 
states: possible
SR=00
values of outputs SR=01
transitions: changes
based on inputs
R
Q
S
Q'
SR=10
SR=01
Q Q'
0 1
SR=01
Q Q'
1 0
SR=00
SR=10
SR=10
SR=11
SR=11
SR=01
CSE370 - XIII - Sequential Logic
SR=11
SR=00
SR=11
SR=00
possible oscillation
between states 00 and 11
Autumn 2010
Q Q'
0 0
SR=10
Q Q'
1 1
10
Observed R-S latch behavior
R
Q
S
Q'
Very difficult to observe R-S latch in the 1-1 state
 
 
one of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0
 
 
 
a so-called "race condition"
or non-deterministic transition
SR=10
SR=00
SR=01
SR=01
Q Q'
0 1
SR=01
Q Q'
1 0
SR=00
SR=10
SR=10
SR=11
SR=11
Q Q'
0 0
SR=11
SR=00
SR=00
Autumn 2010
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CSE370 - XIII - Sequential Logic
R-S latch analysis
Break feedback path
 
S
0
0
0
0
1
1
1
1
R
Q
S
Q'
R
0
0
1
1
0
0
1
1
Autumn 2010
Q(t)
0
1
0
1
0
1
0
1
Q(t)
Q(t+Δ)
S
R
Q(t+Δ)
0
hold
1
0
reset
0
1
set
1
X not allowed
X
S
Q(t)
CSE370 - XIII - Sequential Logic
0
0
X
1
1
0
X
1
R
characteristic equation
Q(t+Δ) = S + R’ Q(t)
12
R-S latch using NAND gates
R’
Q'
R
0
0
1
1
0
0
1
1
R’
S’
Q
S’
S
0
0
0
0
1
1
1
1
Q(t)
S’
1
1
1
1
0
0
0
0
R’
1
1
0
0
1
1
0
0
Q(t)
0
1
0
1
0
1
0
1
Autumn 2010
Q(t+Δ)
0
1
0
0
1
1
X
X
S
hold
reset
Q(t)
0
0
1
0
set
X
1
X
1
R
not allowed
characteristic equation
Q(t+Δ) = S + R’ Q(t)
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CSE370 - XIII - Sequential Logic
Gated R-S latch
 
Control when R and S inputs matter
 
otherwise, the slightest
glitch on R or S while
enable is low could cause
change in stored value
R
R'
enable'
Q'
S'
Set
Q
S
100
Reset
S'
R'
enable'
Q
Q'
Autumn 2010
CSE370 - XIII - Sequential Logic
14
Clocks
 
Used to keep time
 
 
 
wait long enough for inputs (R' and S') to settle
then allow to have effect on value stored
Clocks are regular periodic signals
 
 
period (time between clock ticks)
duty-cycle (clock pulse width - expressed as % of period)
duty cycle (in this case, 50%)
period
Autumn 2010
CSE370 - XIII - Sequential Logic
15
Clocks (cont’d)
 
Controlling an R-S latch with a clock
 
 
 
R and S can’t change while clock is active
only have half of clock period for signal changes to propagate
signals must be stable for the other half of clock period
R’
R
Q
clock’
S’
Q’
S
stable changing stable changing stable
R’ and S’
clock’
Autumn 2010
CSE370 - XIII - Sequential Logic
16
Cascading latches
 
 
Connect output of one latch to input of another
How to stop changes from racing through chain?
 
 
 
need to be able to control flow of data from one latch to the next
move one latch per clock period
have to worry about logic between latches (arrows) that is too fast
R
R
Q’
R
Q’
S
S
Q
S
Q
clock
Autumn 2010
17
CSE370 - XIII - Sequential Logic
Master-slave structure
 
Break flow by alternating clocks (like an air-lock)
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use positive clock to latch inputs into one R-S latch
use negative clock to change outputs with another R-S latch
View pair as one basic unit
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master-slave flip-flop
twice as much logic
output changes a few gate delays after the falling edge of clock
but does not affect any cascaded flip-flops
slave stage
master stage
R
R
Q’
S
S
Q
P’
P
R
Q’
S
Q
CLK
Autumn 2010
CSE370 - XIII - Sequential Logic
18
D flip-flop
Make S and R complements of each other
 
 
 
eliminates 1s catching problem
can't just hold previous value
must have new value ready every clock period
 
 
 
value of D just before clock goes low is what is stored in flip-flop
can make R-S flip-flop by adding logic to make D = S + R’ Q
slave stage
master stage
D
R
Q’
S
Q
P’
P
R
Q’
Q’
S
Q
Q
CLK
10 gates
Autumn 2010
19
CSE370 - XIII - Sequential Logic
Edge-triggered flip-flops using gates
 
Only 6 gates
 
sensitive to inputs only near edge of clock signal (not while high)
D’
D
becomes D’ when
clock goes low
0
R
Q
Clk=1
Q’
S
becomes D when
clock goes low
Autumn 2010
4-5 gate delays
must respect setup and hold time
constraints to successfully
capture input
D Q
0
D
negative edge-triggered D
flip-flop (D-FF)
D’
CSE370 - XIII - Sequential Logic
characteristic equation
Q(t+1) = D
20
Edge-triggered flip-flops using transistors
 
Only 8 transistors
clk’
clk
clk’
D
Q
clk’
D
clk
Q
clk
D Q
Autumn 2010
clk
clk’
D Q
21
CSE370 - XIII - Sequential Logic
Edge-triggered flip-flops (cont’d)
 
Positive edge-triggered
 
 
inputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flops
 
inputs sampled on falling edge; outputs change after falling edge
100
D
CLK
Qpos
positive edge-triggered FF
Qpos’
Qneg
negative edge-triggered FF
Qneg’
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CSE370 - XIII - Sequential Logic
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Timing methodologies
 
Rules for interconnecting components and clocks
 
 
guarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory elements
 
we'll focus on systems with edge-triggered flip-flops
 
many custom integrated circuits focus on level-sensitive latches
 
 
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found in programmable logic devices such as our FPGA
they are much smaller (but need to be careful about timing)
Basic rules for correct timing:
 
 
(1) correct inputs, with respect to clock, are provided to the flip-flops
(2) no flip-flop changes state more than once per clocking event
Autumn 2010
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CSE370 - XIII - Sequential Logic
Timing methodologies (cont’d)
 
Definition of terms
 
 
 
Clock: periodic event, causes state of memory element to change
can be rising edge or falling edge or high level or low level
Setup time: minimum time before the clocking event by which the
input must be stable (Tsetup or Tsu)
Hold time: minimum time after the clocking event until which the
input must remain stable (Thold or Th)
Tsu Th
data
D Q
D Q
input
clock
there is a timing "window"
around the clocking event
during which the input must
remain stable and unchanged
in order to be recognized
Autumn 2010
clock
stable changing
data
clock
CSE370 - XIII - Sequential Logic
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Comparison of latches and flip-flops
D Q
CLK
D
positive
edge-triggered
flip-flop
CLK
Qedge
D Q
G
Qlatch
CLK
transparent
(level-sensitive)
latch
Autumn 2010
behavior is the same unless input changes
while the clock is high
CSE370 - XIII - Sequential Logic
25
Comparison of latches and flip-flops (cont’d)
Type
When inputs are sampled When output is valid
unclocked
latch
always
propagation delay from input change
level-sensitive
latch
clock high
(Tsu/Th around falling
edge of clock)
propagation delay from input change
or clock edge (whichever is later)
master-slave
flip-flop
clock hi-to-lo transition
(Tsu/Th around falling
edge of clock)
propagation delay from falling edge
of clock
negative
edge-triggered
flip-flop
clock hi-to-lo transition
(Tsu/Th around falling
edge of clock)
propagation delay from falling edge
of clock
Autumn 2010
CSE370 - XIII - Sequential Logic
26
Typical timing specifications
 
Positive edge-triggered D flip-flop
 
 
 
setup and hold times
minimum clock width
propagation delays (low to high, high to low, max and typical)
Tsu T h
1.8 0.5
ns ns
Tsu T h
1.8 0.5
ns ns
D
Tw
3.3
ns
Clk
Tw
3.3
ns
Tpdhl
1.1 ns
Tpdlh
3.6 ns
Q
all measurements are made from the clocking event (the rising edge of the clock)
Autumn 2010
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CSE370 - XIII - Sequential Logic
Cascading edge-triggered flip-flops
 
Shift register
 
 
 
new value goes into first stage
while previous value of first stage goes into second stage
consider setup/hold/propagation delays (prop must be > hold)
IN
D Q
Q0
D Q
Q1
OUT
CLK
100
IN
Q0
Q1
CLK
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CSE370 - XIII - Sequential Logic
28
Cascading edge-triggered flip-flops (cont’d)
 
Why this works
 
 
 
propagation delays exceed hold times
clock width constraint exceeds setup time
this guarantees following stage will latch current value before it
changes to new value
In
Tsu
1.8ns
Q0
Tsu
1.8ns
Tp
1.1-3.6ns
timing constraints
guarantee proper
operation of
cascaded components
Tp
1.1-3.6ns
Q1
assumes infinitely fast
distribution of the clock
CLK
Th
0.5ns
Autumn 2010
Th
0.5ns
29
CSE370 - XIII - Sequential Logic
Clock skew
 
When it doesn’t work
 
 
 
correct behavior assumes next state of all storage elements
determined by all storage elements at the same time
this is difficult in high-performance systems because time for clock
to arrive at flip-flop is comparable to delays through logic
effect of skew on cascaded flip-flops:
100
In
CLK1 is a delayed
version of CLK0
Q0
Q1
CLK0
CLK1
original state: IN = 0, Q0 = 1, Q1 = 1
expected next state: Q0 = 0, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0 (0 races through two FFs instead of one)
Autumn 2010
CSE370 - XIII - Sequential Logic
30
Summary of latches and flip-flops
 
Development of D-FF
 
level-sensitive used in custom integrated circuits
 
 
 
 
edge-triggered used in modern programmable logic devices
good choice for data storage register
Historically, JK-FF was popular but now never used
 
 
 
 
 
can be made with 8 switches
similar to RS but with 1-1 being used to toggle output
JK = 00 hold, 01 reset, 10 set, 11 toggle (complement state)
good in days of SSI (more complex input function: D = J Q’ + K’ Q )
can always be implemented using D-FF, if needed
Preset and clear inputs are highly desirable on flip-flops
 
used at start-up or to reset system to a known state
Autumn 2010
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31
Flip-flop features
 
Reset (set state to 0) – R
 
 
 
Preset or set (set state to 1) – S (or sometimes P)
 
 
 
 
Dnew = R' • D + S
Dnew = R' • D + R'S
(set-dominant)
(reset-dominant)
Selective input capability (input enable or load) – LD or EN
 
 
 
synchronous: Dnew = D + S (when next clock edge arrives)
asynchronous: doesn't wait for clock, quick but dangerous
Both reset and preset
 
 
synchronous: Dnew = R' • D (when next clock edge arrives)
asynchronous: doesn't wait for clock, quick but dangerous
multiplexor at input: Dnew = LD' • Q + LD • D
load may or may not override reset/set (usually R/S have priority)
Complementary outputs – Q and Q'
Autumn 2010
CSE370 - XIII - Sequential Logic
32