Hands on Training Program on “TCAD & Cadence
Transcription
Hands on Training Program on “TCAD & Cadence
Registration Form Using Cadence Hands on Training Program on “TCAD & Cadence for IC Design” RTL Design and Simulation Physical aware synthesis Synthesis and low power synthesis Using RTL Compiler Block and Top Level P&R Using SOC Encounter STA Using Cadence Timing Engine Organized by School of Electronics Engineering VLSI Division About the Program The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap. Last date for Registration Dr. Harish Kittur, VIT University Dr. R.Srinivasan, SSNCE Dr.Sakthivel.R, VIT University Ravi.S, VIT University Jagannadha Naidu, VIT University V.N.Ramakrishnan, VIT University P.Chitra, VIT University Coordinators Participants can send their registration to 3. Institution Name : 4. Phone & email : 5. Communication Address : 6. Accommodation : Y/N 7. DD Details : M/F e-mail: vnramakrishnan@vit.ac.in — 98 4095 4095 msravi@vit.ac.in — 97 9015 5650 Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 30. Faculty and industry persons : Rs. 4,500/Student and research scholars : Rs. 4,000/Hostel accommodation can be provided on request basis Topics to be addressed Mode of Payment Structure Creation, Simulation and Device Simulation Process Simulation Multi-gate Simulation Radiation effects study on devices and circuits : Prof. Harish Kittur Prof .V.N.Ramakrishnan Prof. Ravi.S Registration Fees 2. Gender : 07/04/2015 Target Audience Using TCAD : Important Date Resource Persons 8 - 11, April 2015 1. Name & Designation DD can be drawn in favour of “VIT University”Payable at Vellore. DD can be sent to V.N.Ramakrishnan, Asst. Professor SENSE/VLSI VIT University. Vellore – 632014. Place : Date : Signature