Hoon Park, Anping He, Marly Roncken, Xiaoyu Song References

Verifying Timing Constraints for Delay-Insensitive Circuits
Hoon Park, Anping He, Marly Roncken, Xiaoyu Song
Asynchronous Research Center, Maseeh College of Engineering and Computer Science
results
ch4
in_A
1
Storage
C4
four main steps in ARCtimer. ARCtimer is
used early in the design process to build a
Design Library of verified components for
use in any chip design.
References
[1] W. Mallon. Theories and Tools for the Design of Delay-Insensitive
Communicating Processes, Ph.D. thesis, University of Groningen, 2000.
[2] K. Desai, K. Stevens, J. O'Leary. Symbolic Verification of Timed
Asynchronous Hardware Protocols, In Proceedings ISVLSI, 2013.
[3] H. Park, A. He, M. Roncken, X. Song. Semi-modular delay model revisited
in context of relative timing, Electronics Letters (IET), Volume 51, Issue 4,
pages 332-334, 2015.
[4] H. Park, A. He, M. Roncken, X. Song, I. Sutherland. Modular Timing
Constraints for Delay-Insensitive Systems, to appear in Journal of Computer
Science and Technology (JCST), 2015.
inv
in_D
L
ckbuf
out_D
FF_D
1
L
buf_out_R1 out_R
D Q
FF
o
R
_
t
u
7
out_R
2
in_A
6
out
_R
and
in_A buf_in_A1
D Q
1
in_R
4
0
in_A
All other events are
sent to an error state
inv
Click Storage Protocol
ARCtimer is a framework to identify
The spiral in the figure shows the
D Q
FF
component network
internal timing constraints. Through
ARCtimer, we have identified timing
constraint patterns for the entire Click
circuit family. This flow can handle data as
well as non-deterministic internal choice.
out_R
1
out_A
out_A
ch2
GUI
xor_in xnor_out
in_R
3
out_A
Join
(add)
C3
ch5
and
out_A
1
1
in_A
in_ R
5
Circuit
ENV_out
ch3
0
functions
components
data types
xor_in xnor_out out_A
in_R
Protocol
Environment
in_R
Click Storage Circuit
Design: Fibonacci
Storage 1 Storage
C1
C2
ch1
buf_out_R2
self-timed circuits? The fundamental reason
is that only a limited class of circuits is truly
insensitive to delays in gates and wires.
The circuit is delay-insensitive only
if each handshake component faithfully
follows the protocols.
By carefully considering time locally
we can ignore time globally.
Timing Pattern Generation & Verification
ENV_in
Why does anyone verify timing in
Design Library
buf_in_A2
Chip Design
parkhoon@gmail.com
circuit Input
Gate level netlist
in_R
out_A
in_A
in_D
ch4
Parser
out_R
out_D
Storage C4
ch5
gate level netlist
Add checkpoints to
simplify STA code
and+
evaluate
timing constraints
NO
{in_R, out_A}
Output
Handshake
{in_A, out_R}
Component
Handshake events
({in_R}, {in_A})
({out_R}, {out_A})
Handshake protocol (P)
P = in_R; in_A; out_R; out_A; P
Step 2
Model
Checker
Click Storage Timing
STA and Repair
wire & gate
delays
STA
repair invalid timing
constraints
Step 1
timing
constraints
xor_in±
xnor_out± in_R±
ckbuf± out_A±
FF±
YES
chip
(pod)
FF±
(early)
inv±
(late)
ckbuf+
FF±
xor_in
ckbuf-
in_R±
and+
Step 3
xor_in+
xnor_out+
Timing
Patterns
Generalize to timing patterns
Step 4
Modular STA code
path-delay search
channel subroutines
subroutine calls
OK?
Generate timing constraints
from counterexample
Static
Timing
Analysis
and+
xor_inxnor_outckbuf-
in_R±
out_A±