IBM Lenovo G480 LA-7981p Free Laptop Schematic

Transcription

A
B
C
D
E
1
1
Compal Confidential
2
2
QIWG5/QIWG6 DIS M/B Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13X
2012-02-01
3
3
LA-7981P
REV:1.0
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/15
2012/07/11
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Cover Page
Size Document Number
Custom
Rev
1.0
LA-7981P
Date:
Wednesday, February 15, 2012
Sheet
E
1
of
60
A
B
C
D
Compal confidential
ZZZ
File Name : QIWG5/QIWG6
G5_DAZ@
G5_DA@
DAZ_PCB
DA_PCB
DAZ0N100101
ZZZ5
nVIDIA N13M-GE
DAZ_PCB
Intel
Ivy Bridge
DAZ0N200101
PCI-E x16
VRAM 128*16
DDR3*8
100MHz
2.7GT/s
Page34
CRT
Connector
DA80000Q010
G5_DA@
G5_DA@
DA_PCB
DA_PCB
DA400016P10
G5_DA@
DA400016Q10
DA_PCB
DA400018T10
ZZZ7
ZZZ6
ZZZ8
ZZZ9
ZZZ10
ZZZ11
G6_DA@
G6_DA@
G6_DA@
G6_DA@
G6_DA@
G6_DA@
DA_PCB
DA_PCB
DA_PCB
DA_PCB
DA_PCB
QIWG6
DA80000Q010
DA400016P10
DA400016Q10
DA400016R10
DA400016S10
DA_PCB
DA400018T10
BANK 0, 1, 2, 3
1
LS7981P CardReader/B
LS7982P USB/B
LS7983P PWR/B
LS7984P LED/B
LS7985P ODD/B
Page12-13
Up to 8GB
Dual Channel
DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
DDR3 1600MHz(1.5V)
DMI *4
FDI *8
Intel
Panther Point
LVDS Page33
Connector
AZALIA
2 channel speaker
Page41
Audio Codec
Conexant
CX20671-21Z
HM75 / HM76
Page41
FCBGA 989
25mm*25mm
USB3.0 *2(Left)
Card Reader
Reltek
LPC BUS
3
Arthros
Page42
AR8161(GLAN)
EC
AR8162(10/100)
ENE KB9012
Page43
Mini Card Slot
*1
Page36
SPIROM
BIOS Page14
uPD720202
Audio Jacks
BlueTooth Conn.
Page40
SATA *6
Page14-22
Renesas
Page41
Camera Conn.Page33
Page45
USB3.0
Int. MIC x1
2
USB2.0 *14
PCI-E x1 *6
Page43
3
RTS5178 for SDR50
SDXC/MMC
Page37
USB2.0 *2(Right)
Page38
RJ-45
Connector
Page 43;44
Touch Pad
Page43
USB2.0 *2(Left)
Int. KBD
Page43
Page45
SATA HDD
PCI-E(WLAN)
Thermal Sensor
Mini Card Slot *1
WLAN
LS7981P CardReader/B
LS7982P USB/B
LS7983P PWR/B
Page5-11
HDMI
Connector
PCI Express
QIWG5
ZZZ4
DDR3 SO-DIMM *2
Socket-rPGA988B
37.5mm*37.5mm
Page35
Option
ZZZ3
LA7981
G6_DAZ@
nVIDIA N13P-GL
2
ZZZ2
LA7981
Page23-32
1
ZZZ1
E
EMC1403
Page39
SATA ODD
Page36
Page40
(Port 0/Port 1 support SATA3)
Page40
4
4
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
A
B
C
D
Title
Block Diagram
Custom
Rev
1.0
LA-7981P
Date:
Sheet
E
2
of
60
A
B
C
Voltage Rails
D
BOARD ID Table
+5VS
+3VS
power
plane
+1.5VS
+V1.05S_VCCP
1
+1.5V
+5VALW
+VCC_CORE
+B
+VGA_CORE
+3VALW
+VCC_GFXCORE_AXG
+1.8VS
State
O
O
S3
O
O
O
X
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
O
O
X
X
O
X
X
X
X
X
X
UHCI0
UHCI1
EHCI1
X
USB3.0
Address
EC SM Bus1 address
EC SM Bus2 address
Device
Device
Smart Battery
0001 011X b
UHCI3
1001_101xb
UHCI4
EHCI2
PCH SM Bus address
3
Device
Address
1001 000Xb
DDR DIMM2
1001 010Xb
UHCI2
Address
Thermal Sensor F75303M
DDR DIMM0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI5
UHCI6
HIGH
HIGH
HIGH
ON
ON
ON
ON
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
Device
Address
1001 111Xb (0x9E)
1
Board ID / SKU ID Table for AD channel
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
3 External
USB Port
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
Porject
G-series
G-series
G-series
G-series
Y-series
Y-series
Y-series
Y-series
Phase
MP
PVT
DVT
EVT
EVT
DVT
PVT
MP
BOM Structure Table
BTO Item
2
BOM Structure
USB Port (Right Side CR-BD)
USB Port (Left Side) USB3.0
USB Port (Left Side) USB3.0
GPU:N13P-GL
GPU:N13M-GE
HDMI
Interna-Intel-USB3.0
External-NEC-USB3.0
Blue Tooth
Connector
45 LEVEL
10/100 LAN
GIGA LAN
LAN LDO Mode
LAN Switch mode
Cameara
For QIWG5 (14")
For QIWG6 (15")
Unpop
G5/G6/G9(Low/Mid END)
G9 High-END
G9
G5/G6/G9(Low/Mid END)
Camera
USB/B (Right Side USB-BD)
Mini Card(WLAN)
Card Reader
Blue Tooth
NV-GPU SM Bus address
Internal thermal sensor
Clock
HIGH
0
1
2
3
4
5
6
7
USB 2.0 Port
2
+VS
LOW
Board ID
USB Port Table
+V
HIGH
Vcc
Ra/Rc/Re
O
+VALW
S1(Power On Suspend)
+1.05VS
O
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
Full ON
PCB Revision
0.1
+0.75VS
S0
SIGNAL
STATE
Board ID
0
1
2
3
4
5
6
7
E
N13P@
N13M@
HDMI@
IU3@
EU3@
BT@
ME@
45@
8162@
GIGA@
LDO@
SWR@
CMOS@
14@
15@
@
nonBBH@
BBH@
G9 @
15_nonBBH@
3
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
4
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
KB9012
+3VALW
KB9012
+3VALW
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW
A
VGA
BATT
WLAN
KB9012 SODIMM WWAN
Thermal
Sensor
PCH
V
X
X
X
X
X
X
X
X
X
X
X
X
X
+3VS
V
+3VS
V
X
X
X
X
X
X
X
X
X
V
X
V
X
X
V
X
X
+3VS
+3VALW
+3VS
+3VS
X
V
+3VS
4
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
B
C
D
Title
Notes List
Size
B
Date:
Document Number
Rev
1.0
LA-7981P
Sheet
E
3
of
60
5
4
3
2
1
Hot plug detect for IFP link C
VGA and GDDR3 Voltage Rails
D
ACTIVE
(N13x GPIO)
Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
GPIO
I/O
GPIO0
OUT
-
GPU VID4
GPIO1
OUT
-
GPU VID3
GPIO2
OUT
H
Panel Back-Light brightness(PWM capable)
GPIO3
OUT
H
Panel Power Enable
GPIO4
OUT
H
Panel Back-Light On/Off (PWM)
GPIO5
OUT
-
GPU VID1
OUT
-
GPIO7
OUT
N/A
GPIO8
I/O
-
Thermal Catastrophic Over Temperature
GPIO9
OUT
-
Thermal Alert
GPIO10
OUT
-
Memory VREF Control
GPIO11
OUT
-
GPU VID2
GPU VID0
GPIO13
OUT
-
GPIO14
OUT
N/A
GPIO15
IN
GPIO16
OUT
NVCLK
/MCLK
Products
(W)
(W)
(MHz)
(V)
(A)
(W)
(A)
N13P-GL
64bit
1GB
GDDR3
TBD
TBD
TBD
TBD
TBD
TBD
TBD
AC Power Detect Input
IN
GPIO18
IN
Power Rail
Other
(W)
(A)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(3.3V)
Logical
Strapping Bit2
SUB_VENDOR
Logical
Strapping Bit1
Logical
Strapping Bit0
SLOT_CLK_CFG
PEX_PLL_EN_TERM
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
FB[1]
FB[0]
SMB_ALT_ADDR
VGA_DEVICE
USER[3]
USER[2]
USER[1]
Logical
Strapping Bit3
PCI_DEVID[4]
ROM_SI
+3VS_VGA
ROM_SO
+3VS_VGA
STRAP0
+3VS_VGA
STRAP1
+3VS_VGA
STRAP2
+3VS_VGA
PCI_DEVID[3]
PCI_DEVID[2]
PCI_DEVID[1]
PCI_DEVID[0]
STRAP3
+3VS_VGA
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
STRAP4
+3VS_VGA
PCIE_SPEED_
CHANGE_GEN3
PCIE_MAX_SPEED
DP_PLL_VDD33V
(10K pull low)
USER[0]
3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]
RESERVED
3GIO_PAD_CFG_ADR[0]
GPU VID5
C
N13P-GL
(28nm)
??
N13M-GE
(28nm)
???
Hot plug detect for IFP link C
FB Memory (GDDR3)
ROM_SO
ROM_SCLK
ROM_SI
STRAP2
STRAP1
STRAP0
PD 10K
PD 15K
PD 20K
PU 20K
PD 35K
PU 45K
PD 10K
PD 15K
PD 15K
PU 20K
PD 35K
PU 45K
PD 10K
PD 15K
PD 20K
PU 20K
PD 35K
PU 45K
N/A
N/A
Samsung
2500MHz
K4G10325FG-HC04
Hynix
2500MHz
H5GQ1H24BFR-T2C
Samsung
2500MHz
K4G20325FG-HC04
Hot Plug Detect for IFPE
IN
N/A
N13P-GL
N13M-GE
B
I/O and
PLLVDD
(1.05V)
+3VS_VGA
32Mx32
GPIO19
PCI Express I/O and
(1.05V)
PLLVDD
(6)
(1.8V)
D
GPU
GPIO17
FBVDDQ
(GPU+Mem)
(1.35V)
FBVDD
(1.35V)
NVVDD
Device ID
C
IN
Mem
(1,5)
Physical
Strapping pin
ROM_SCLK
GPIO6
GPIO12
GPU
(4)
Function Description
32Mx32
64Mx32
+3VS_VGA
B
Hynix
2500MHz
+VGA_CORE
H5GQ2H24MFR-T2C
64Mx32
PD 10K
PD 15K
PD 20K
PU 20K
PD 35K
PU 45K
tNVVDD >0
+1.5VS_VGA
X76
tFBVDDQ >0
+1.05VS_VGA
tPEX_VDD >0
1. all power rail ramp up time should be larger than 40us
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
A
A
Tpower-off <10ms
Compal Secret Data
2011/06/15
Issued Date
1.all GPU power rails should be turned off within 10ms
Deciphered Date
2012/07/11
5
4
3
2
Title
VGA Notes List
Custom
Rev
0.2
LA-7981P
Date:
Tuesday, February 14, 2012
Sheet
1
4
of
60
5
4
3
2
1
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
1
+V1.05S_VCCP
R1
24.9_0402_1%
D
B27
B25
A25
B24
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
<16>
<16>
<16>
<16>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B28
B26
A24
B23
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
<16>
<16>
<16>
<16>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
<16>
<16>
<16>
<16>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
J18
J17
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
H20
FDI_INT
<16> FDI_LSYNC0
<16> FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
C15
D15
eDP_AUX
eDP_AUX#
C17
F16
C16
G15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
<16> FDI_FSYNC0
<16> FDI_FSYNC1
1
<16>
B
EDP_COMP
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
eDP_HPD
eDP
2
R7
24.9_0402_1%
PCI EXPRESS* - GRAPHICS
+V1.05S_VCCP
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
Intel(R) FDI
C
<16>
<16>
<16>
<16>
DMI
D
2
JCPU1A
PEG_COMP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P0
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PCIE_CTX_GRX_C_N15
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PCIE_CTX_GRX_C_P15
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P0
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N0
<23>
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane #
socket pin map definition
CFG2
*
PCIE_CRX_GTX_P[0..15]
definition matches
0:Lane Reversed
<23>
C
PCIE_CTX_GRX_N[0..15]
<23>
PCIE_CTX_GRX_P[0..15]
<23>
B
TYCO_2013620-2_IVY BRIDGE
A
A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
5
4
3
2
PROCESSOR(1/7) DMI,FDI,PEG
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
5
of
60
5
4
3
2
1
JCPU1B
R10;R11 put on U4 side
SKTOCC#
+V1.05S_VCCP
H_CATERR#
1
T48
AL33
CATERR#
AN33
2
<19,42> H_PECI
R15
56_0402_5%
1
2
H_PROCHOT#
<42,48> H_PROCHOT#
H_PROCHOT#_R
AL32
AN32
<19> H_THRMTRIP#
THERMAL
R9
62_0402_5%
PECI
PROCHOT#
THERMTRIP#
BCLK
BCLK#
CLOCKS
AN34
PROC_SELECT#
A28
A27
CLK_CPU_DMI_R 0_0402_5%
CLK_CPU_DMII#_R 0_0402_5%
@
1
1
@
D
R10
2
2
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
R11
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
DDR3
MISC
C26
<19> H_SNB_IVB#
MISC
D
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
A16
A15
2
2
R12
R13
1 1K_0402_5%
1 1K_0402_5%
R8
H_DRAMRST#
AK1
A5
A4
SM_RCOMP0 2 R16
SM_RCOMP1 2 R17
SM_RCOMP2 2 R18
+V1.05S_VCCP
H_DRAMRST# <7>
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
DDR3 Compensation Signals
+V1.05S_VCCP
PRDY#
PREQ#
R22
1
<16> H_PM_SYNC
2
H_PM_SYNC_R
AM34
PM_SYNC
0_0402_5%
0_0402_5%1
R26
H_CPUPWRGD_R
2
2
<19> H_CPUPWRGD
V8
UNCOREPWRGOOD
SM_DRAMPWROK
1
100P_0402_50V8J
2
EMI Reserve
R29
1
2 PM_DRAM_PWRGD_R
130_0402_5%
R27
10K_0402_5%
1
@ C549
AP33
BUF_CPU_RST#
AR33
RESET#
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
XDP_PRDY#
XDP_PREQ#
AR26
AR27
AP30
XDP_TCK
XDP_TMS
XDP_TRST#
AR28
AP26
T97
T98
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TDI
XDP_TDO
AL35 XDP_DBRESET#
R28
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
R20
R21
R23
2
2
2
XDP_TCK
R24
XDP_TRST# R25
2
2
1 1K_0402_5%
2
@
1 51_0402_5%
1 51_0402_5%
1 51_0402_5%
PU/PD for JTAG signals
C
1 51_0402_5%
1 51_0402_5%
+3VS
T49
T90
T91
T92
T93
T94
T95
T96
+3VALW
Buffered reset to CPU
1
C33
0.1U_0402_16V4Z
TCK
TMS
TRST#
JTAG & BPM
@
PWR MANAGEMENT
C
AP29
AP27
+1.5V_CPU_VDDQ
2
+3VS
B
1
B
PM_SYS_PWRGD_BUF
74AHC1G09GW_TSSOP5
S
1
U2
BUFO_CPU_RST# 4
SN74LVC1G07DCKR_SC70-5
NC
Y
A
3V
1
2
PCH_PLTRST#
PCH_PLTRST# <18>
R35 @
0_0402_5%
2
Q1 @
2N7002H_SOT23-3
2
G
R34
43_0402_1%
1
2
BUF_CPU_RST#
3
1 2
3
<10> RUN_ON_CPU1.5VS3#
D
2
R32
75_0402_5%
@
R33
39_0402_5%
1
P
4
2
O
A
C34
0.1U_0402_16V4Z
P
B
1
2
3
<16> PM_DRAM_PWRGD
1
G
+3VS
1 R161
2
10K_0402_5%
1
2
5
U1
+V1.05S_VCCP
5
R30
200_0402_5%
G
1 R880@ 2
0_0402_5%
<16> SYS_PWROK
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PROCESSOR(2/7) PM,XDP,CLK
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
6
of
60
5
4
3
2
JCPU1C
1
JCPU1D
<13> DDR_B_D[0..63]
D
C
<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2
B
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AE10
AF10
V6
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
AB6
AA6
V9
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
AA5
AB5
V10
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
AB4
AA4
W9
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_CAS#
SA_RAS#
SA_WE#
AB3
AA3
W10
AK3
AL3
AG1
AH1
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
AH3
AG3
AG2
AH2
M_ODT0 <12>
M_ODT1 <12>
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
C4
G6
J3
M6
AL6
AM8
AR12
AM15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
<12>
<12>
DDR_A_MA[0..15] <12>
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2
AA10
AB8
AB9
<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
AE2
AD2
R9
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
AE1
AD1
R10
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
AB2
AA2
T9
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
DDR SYSTEM MEMORY B
<12> DDR_A_D[0..63]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AA1
AB1
T10
AD3
AE3
AD6
AE6
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
AE4
AD4
AD5
AE5
M_ODT2 <13>
M_ODT3 <13>
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
D
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
<13>
C
<13>
DDR_B_MA[0..15] <13>
B
+1.5V
R02
D
S
H_DRAMRST#
3
1
2
<6> H_DRAMRST#
1
R37
1K_0402_5%
R40
DDR3_DRAMRST#_R
R38
1K_0402_5%
2
1
DRAMRST_CNTRL
2 @
DRAMRST_CNTRL <10>
0_0402_5%
DDR3_DRAMRST# <12,13>
Q2
LBSS138LT1G_SOT-23-3
1
2
G
R39
4.99K_0402_1%
1
<15> DRAMRST_CNTRL_PCH
2
@ R36
0_0402_5%
1
2
A
A
DRAMRST_CNTRL
1
2
Eiffel used 0.01u
design used 0.047u
C35
0.047U 16V K X7R 0402 Module
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PROCESSOR(3/7) DDRIII
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
7
of
60
5
4
3
2
1
CFG Straps for Processor
1
CFG2
2
R41
1K_0402_1%
D
Interl request AH26 short GND
check on EVT phase
JCPU1E
+VCC_GFXCORE_AXG
2
+VCC_CORE
2
R252
49.9_0402_1%
PAD
AH27
AH26
1
R60
RSVD32
T13
1: Normal Operation; Lane #
socket pin map definition
CFG2
0_0402_5%
R02
*
L7
AG7
AE7
AK2
definition matches
0:Lane Reversed
CFG4
1
RSVD28
RSVD29
RSVD30
RSVD31
2 @
@
W8
R42
1K_0402_1%
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
Display Port Presence Strap
@
2 100_0402_1%
Need PWR add new circuit on 1.05V(refer CRB)
AJ31
AH31
AJ33
AH33
AJ26
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
2
2
VSS_VAL_SENSE
Check
1
R257
49.9_0402_1%
1
R255
49.9_0402_1%
INTEL 12/28 recommand
to add RC120, RC121, RC122, RC123
Please place as close as JCPU1
B
J20
B18
J15
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
C
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
RSVD5
VSS_AXG_VAL_SENSE
*
CFG4
RSVD24
RSVD25
RSVD27
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
AR35
AT34
AT33
AP35
AR34
CFG6
CFG5
1
R88 1
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
1
2 100_0402_1%
N13M@ R43
1K_0402_1%
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
RSVD51
RSVD52
B34
A33
A34
B35
C35
@ R44
1K_0402_1%
AJ32
AK32
2
@
T8
J16
H16
G16
2
R82 1
RSVD37
RSVD38
RSVD39
RSVD40
RESERVED
1
1
R253
49.9_0402_1%
C
VCC_DIE_SENSE
VSS_DIE_SENSE
PEG Static Lane Reversal - CFG2 is for the 16x
2
CFG4
CFG5
CFG6
CFG7
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG
CFG2
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
D
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
BCLK_ITP
BCLK_ITP#
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
CFG[6:5]
*10: x8, x8 - Device 1 function 1 enabled ; function 2
B
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AT2
AT1
AR1
CFG7
B1
1
KEY
AN35
AM35
@R45
@
R45
1K_0402_1%
2
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
A
PROCESSOR(4/7) RSVD,CFG
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
8
of
60
5
4
JCPU1F
3
POWER
2
1
+V1.05S_VCCP
+VCC_CORE
8.5A
A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
VCCIO40
J23
D
C
1
1
C99
0.1U_0402_10V6K
2
2
R46
75_0402_5%
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
0_0402_5%
0_0402_5%
R50
1 R47
1
1
2 43_0402_5%
2 R48 @
2 R49 @
2
1 130_0402_5%
VR_SVID_CLK series-resistors close to VR
VR_SVID_ALRT# <55>
VR_SVID_CLK <55>
VR_SVID_DAT <55>
+V1.05S_VCCP
0.1uF on power side
B
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
1
+VCC_CORE
Trace Impedance =27-33 ohm
Trace Length Matc < 25 mils
2
AJ35 VCCSENSE_R
AJ34 VSSSENSE_R
2 R52
2 R53
1
1
@ 0_0402_5%
@ 0_0402_5%
VCCSENSE <55>
VSSSENSE <55>
1
VCC_SENSE
VSS_SENSE
R51
100_0402_1%
VCCIO_SENSE
VSS_SENSE_VCCIO
B10
A10
VSSIO_SENSE_L
1 R66 @2
100_0402_1%
VCCIO_SENSE <52,53>
R74 2VSSIO_SENSE
1
10_0402_1%
@
R54
100_0402_1%
2
B
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
+V1.05S_VCCP
SVID
C
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
SENSE LINES
D
CORE SUPPLY
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
PEG AND DDR
QC=94A
DC=53A
R74 & R79 put together
VSSIO_SENSE_L <53>
+V1.05S_VCCP
R79
2
1
10_0402_1%
A
VSS_SENCE 100ohm +-1% pull-down to GND near processor
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
5
4
3
2
PROCESSOR(5/7) PWR,BYPASS
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
9
of
60
4
3
1
+1.5V_CPU_VDDQ
1
@ J1
2
0_0402_5%
R56
82K_0402_5%
DRAMRST_CNTRL
<7>
+V_DDR_REFA_R
+V_DDR_REFB_R
1
2
G
DRAMRST_CNTRL
D
S
R353
1K_0402_1%
@
2
G
S
Q9
R64
1K_0402_1%
@
D
SUSP#
1
0_0402_5% @
Q4
2N7002_SOT23
R885 R02
1
2
15K_0402_1%
R57
330K_0402_5%
@
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
1
2
+VCC_GFXCORE_AXG
C97
0.047U_0603_25V7K
1
S
2
G
2
Q7
@
2N7002_SOT23
1
S
2
G
3
2
R58
RUN_ON_CPU1.5VS3
D
R616
10_0402_1%
2
R59
2
<25,42,46,51,52,53,54>
1
0_0402_5% @
1
<42,46,53> CPU1.5V_S3_GATE
3
RUN_ON_CPU1.5VS3#
D
1
2
2
@ R667
100K_0402_5%
S
2 0_0402_5%~D
2 0_0402_5%~D
R671@
RUN_ON_CPU1.5VS3#
3
R03
Q6
DRAMRST_CNTRL
2
G
D
4
1
1
D
@
Q3
2N7002_SOT23
AP4800
Id=9.6A
R670@
1
1
1 2
U3
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
+VSB
+3VALW
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
@
C92
0.1U_0402_10V6K
1
2
1
3
1
<46,53,54> SUSP
D
@
R55
220_0402_5%
PAD-OPEN 4x4m
1
R668
3
@
2
1
1
2
+1.5V
2
2
5
1
2
2
1
1
1
+V_SM_VREF
C
1
1
@2
1 R61
0_0402_5%
2
R62 @
1K_0402_1%
2
2
SENSE
LINES
D
C98
0.1U_0402_10V6K
+V_DDR_REFA_R
+V_DDR_REFB_R
R78
1K_0402_1%
2
R63 @
1K_0402_1%
2
B4
D1
2
VREF
S
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
DDR3 -1.5V RAILS
+1.5V_CPU_VDDQ
+1.5V
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
2
1
2
1
2
1
2
2
1
2
+
C123
330U_2.5V_M
C96
0.1U_0402_10V6K
1
2
+VCCSA
2
1
2
1
2
1
2
B
1
+ C128 @
330U_D2_2.5VY_R9M
2
H23
+VCCSA_SENSE
<52> +3VS
MISC
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
A19
H_VCCSA_VID0
H_VCCSA_VID1
2
@
1
2
R68 0_0402_5%
<52>
<52>
R75
10K_0402_5%
H_VCCP_SEL
1
R77
R02
2 @
+3VALW
2
1
R76 @
10K_0402_5%
1
M27 +VCCSA
M26
L26
J26
J25
J24
H26
H25
C22
C24
C129 @
0.1U_0402_10V6K
1
2
2
1
SA RAIL
VCCSA_SENSE
1
C95
0.1U_0402_10V6K
1
2
10U
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
+1.5V_CPU_VDDQ
C396 @
0.1U_0402_10V6K
1
2
1
1
C122
10U_0603_6.3V6M
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
C121
10U_0603_6.3V6M
2
1
1
C127
10U_0603_6.3V6M
2
1
VCCPLL1
VCCPLL2
VCCPLL3
+V_SM_VREF_CNT
C120
10U_0603_6.3V6M
2
1
B6
A6
A2
AL1
C126
10U_0603_6.3V6M
1
C132
1U_0402_6.3V6K
2
@
C131
1U_0402_6.3V6K
1
C130
10U_0603_6.3V6M
2
@
C345
22U_0805_6.3V6M
1
C154
22U_0805_6.3V6M
@
+1.8VS_VCCPLL
SM_VREF
PMV45EN_SOT23-3
Q5 @
3
R67
1K_0402_1%
+V_SM_VREF should
have 20 mil trace width
C119
10U_0603_6.3V6M
1.5A
0_0805_5%
2
+1.5V_CPU_VDDQ
VSS_AXG_SENSE <55>
R626
10_0402_1%
C125
10U_0603_6.3V6M
10U
R69
1
AK35
AK34
C124
10U_0603_6.3V6M
+1.8VS
VAXG_SENSE
VSSAXG_SENSE
C118
10U_0603_6.3V6M
B
Q5-orignal part
AP2302GN-HF_SOT23-3
SB523020210 +1.5V
G
C
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
RUN_ON_CPU1.5VS3
R89 @
100_0402_1%
C117
10U_0603_6.3V6M
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
VCC_AXG_SENSE <55>
POWER
GRAPHICS
<6>
+VCC_GFXCORE_AXG JCPU1G
1.8V RAIL
RUN_ON_CPU1.5VS3#
Check
VCCP_PWRCTRL
<52>
0_0402_5%
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
A
2
Title
PROCESSOR(6/7) PWR
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
10
of
60
5
4
3
2
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
D
C
B
1
JCPU1I
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
D
C
B
A
A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
5
4
3
2
PROCESSOR(7/7) VSS
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
11
of
60
5
4
3
2
1
+1.5V
DDR_A_D2
DDR_A_D3
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
<7> DDR_CKE0_DIMMA
DDR_A_BS2
<7> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<7> M_CLK_DDR0
<7> M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
<7> DDR_A_BS0
DDR_A_MA10
DDR_A_BS0
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
<7> DDR_CS1_DIMMA#
DDR_A_MA13
DDR_CS1_DIMMA#
1
2
C
<7>
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_CS0_DIMMA#
M_ODT0 <7>
R72
1K_0402_1%
+VREF_CA
1
DDR_A_DM4
2
DDR_A_D38
DDR_A_D39
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
<7>
M_ODT1 <7>
DDR_A_D36
DDR_A_D37
Layout Note:
Place near DIMM
+1.5V
1
2
+1.5V
1
R73
1K_0402_1%
@
DDR_A_D44
DDR_A_D45
2
1
@
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
EVT Check
2
1
+
C149 @
220U_6.3V_M
B
2
DDR_A_DQS#5
DDR_A_DQS5
VDDQ(1.5V) =
DDR_A_D46
DDR_A_D47
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_A_D52
DDR_A_D53
Layout Note:
Place near DIMM
6*0603 10uf (PER CONNECTOR)
DDR_A_DM6
VTT(0.75V) =
DDR_A_D54
DDR_A_D55
3*0805 10uf
7/28 Update connect GND directly
4*0402 1uf
+0.75VS
VREF =
DDR_A_D60
DDR_A_D61
1*0402 0.1uf
DDR_A_DQS#7
DDR_A_DQS7
1*0402 0.1uf
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
1*0402 2.2uf
@
VDDSPD (3.3V)=
1*0402 2.2uf
1
2
@
1
2
1
2
1
2
Layout Note:
Place near DIMM
SMB_DATA_S3 <13,15,36>
SMB_CLK_S3 <13,15,36>
+0.75VS
A
0.65A@0.75V
206
FOX_AS0A626-U4SN-7F
ME@
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
1
C148
0.1U_0402_10V6K
G2
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
C147
0.1U_0402_10V6K
G1
DDR_CKE1_DIMMA
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
C146
0.1U_0402_10V6K
205
DDR_A_D30
DDR_A_D31
C153
1U_0402_6.3V6K
2
DDR_A_DQS#3
DDR_A_DQS3
C152
1U_0402_6.3V6K
2
1
R83
10K_0402_5%
1
C156
0.1U_0402_10V6K
+3VS
C155
2.2U_0603_6.3V4Z
A
DDR_A_D28
DDR_A_D29
C151
1U_0402_6.3V6K
DDR_A_D58
DDR_A_D59
1 R81
2
10K_0402_5%
DDR_A_D22
DDR_A_D23
C150
1U_0402_6.3V6K
DDR_A_DM7
DDR_A_DM2
C145
0.1U_0402_10V6K
DDR_A_D56
DDR_A_D57
DDR_A_D20
DDR_A_D21
C144
10U_0603_6.3V6M
DDR_A_D50
DDR_A_D51
<7,13>
C143
10U_0603_6.3V6M
DDR_A_DQS#6
DDR_A_DQS6
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
C142
10U_0603_6.3V6M
DDR_A_D48
DDR_A_D49
DDR_A_DM1
DDR3_DRAMRST#
C141
10U_0603_6.3V6M
DDR_A_D42
DDR_A_D43
DDR_A_D12
DDR_A_D13
C140
10U_0603_6.3V6M
DDR_A_DM5
D
DDR_A_D6
DDR_A_D7
C139
10U_0603_6.3V6M
DDR_A_D40
DDR_A_D41
<7> DDR_A_MA[0..15]
DDR_A_DQS#0
DDR_A_DQS0
C138
10U_0603_6.3V6M
DDR_A_D34
DDR_A_D35
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_A_D4
DDR_A_D5
C137
10U_0603_6.3V6M
B
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
<7> DDR_A_DQS#[0..7]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C136
2.2U_0603_6.3V4Z
DDR_A_DQS#4
DDR_A_DQS4
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C135
0.1U_0402_10V6K
DDR_A_D32
DDR_A_D33
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1
DDR_A_DM0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
2
1
2
2
C133
0.1U_0402_10V6K
2
1
DDR_A_D0
DDR_A_D1
DDR_A_D8
DDR_A_D9
C
<7> DDR_A_DQS[0..7]
JDIMM1
C134
2.2U_0603_6.3V4Z
R71
1K_0402_1%
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A
+VREF_DQ_DIMMA
1
D
+1.5V
3A@1.5V
1
1
+1.5V
R70
1K_0402_1%
2
+VREF_DQ_DIMMA
4
3
2
Title
DDRIII-SODIMM SLOT1
Custom
Date:
Rev
0.2
LA-7981P
Sheet
1
12
of
60
5
4
3
2
1
+1.5V
+1.5V
<7> DDR_B_DQS[0..7]
JDIMM2
1
1
DDR_B_DM0
1
2
C157
2
C158
2
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
R85
1K_0402_1%
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
For Arranale only +VREF_DQ_DIMMB
supply from a external 1.5V voltage divide
circuit.
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
<7> DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
<7> DDR_B_BS2
DDR_B_BS2
C
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<7> M_CLK_DDR2
<7> M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#2
<7> DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
<7> DDR_B_WE#
<7> DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
<7> DDR_CS3_DIMMB#
DDR_B_MA13
DDR_CS3_DIMMB#
C
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB#
M_ODT2 <7>
+1.5V
<7>
M_ODT3 <7>
+VREF_CB
DDR_B_D36
DDR_B_D37
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
0.65A@0.75V
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
B
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
Layout Note:
Place near DIMM
VTT(0.75V) =
3*0805 10uf
1*0402 0.1uf
4*0402 1uf
+0.75VS
1*0402 2.2uf
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
VDDSPD (3.3V)=
1*0402 0.1uf
@
1*0402 2.2uf
SMB_DATA_S3 <12,15,36>
SMB_CLK_S3 <12,15,36>
+0.75VS
@
1
2
1
2
1
2
1
2
A
Layout Note:
Place near DIMM
FOX_AS0A626-U8SN-7F
ME@
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
1
VDDQ(1.5V) =
DDR_B_D62
DDR_B_D63
SMB_DATA_S3
SMB_CLK_S3
1
C172
0.1U_0402_10V6K
DDR_B_DQS#5
DDR_B_DQS5
2
@
C171
0.1U_0402_10V6K
DDR_B_D44
DDR_B_D45
1
C170
0.1U_0402_10V6K
@
C169
0.1U_0402_10V6K
R87
1K_0402_1%
C168
2
+1.5V
C167
2
1
C166
DDR_B_D38
DDR_B_D39
(0.1uF_402_10V)*4
10U_0603_6.3V6M
DDR_B_DM4
(10uF_0603_6.3V)*8
10U_0603_6.3V6M
1
Layout Note:
Place near DIMM
R86
1K_0402_1%
10U_0603_6.3V6M
206
DDR_CKE3_DIMMB
C165
G2
DDR_B_D30
DDR_B_D31
C176
1U_0402_6.3V6K
G1
DDR_B_DQS#3
DDR_B_DQS3
C175
1U_0402_6.3V6K
2
205
DDR_B_D28
DDR_B_D29
C174
1U_0402_6.3V6K
2
1
C178
0.1U_0402_10V6K
1
C177
2.2U_0603_6.3V4Z
+3VS
A
DDR_B_D22
DDR_B_D23
C173
1U_0402_6.3V6K
DDR_B_D58
DDR_B_D59
1 R95
2
10K_0402_5%
1
2
R97
10K_0402_5%
<7>
DDR_B_DM2
10U_0603_6.3V6M
DDR_B_DM7
DDR_CKE3_DIMMB
DDR_B_D20
DDR_B_D21
C164
DDR_B_D56
DDR_B_D57
<7,12>
10U_0603_6.3V6M
DDR_B_D50
DDR_B_D51
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
10U_0603_6.3V6M
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DM1
DDR3_DRAMRST#
C163
DDR_B_D48
DDR_B_D49
D
DDR_B_D12
DDR_B_D13
10U_0603_6.3V6M
DDR_B_D42
DDR_B_D43
DDR_B_D6
DDR_B_D7
C162
DDR_B_DM5
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
<7> DDR_B_MA[0..15]
DDR_B_DQS#0
DDR_B_DQS0
C161
DDR_B_D40
DDR_B_D41
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
<7> DDR_B_DQS#[0..7]
DDR_B_D4
DDR_B_D5
10U_0603_6.3V6M
DDR_B_D34
DDR_B_D35
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C160
2.2U_0603_6.3V4Z
DDR_B_DQS#4
DDR_B_DQS4
B
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C159
0.1U_0402_10V6K
DDR_B_D32
DDR_B_D33
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1
DDR_B_D0
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
2
+VREF_DQ_DIMMB
D
<7> DDR_B_D[0..63]
+1.5V
R84
1K_0402_1%
1
1
3A@1.5V
2
+VREF_DQ_DIMMB
4
3
2
Title
DDRIII-SODIMM SLOT2
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
13
of
60
5
4
3
2
1
PCH_RTCX1
W=20mils
W=20mils
+RTCVCC
+RTCBATT
1
PCH_RTCX2
2
10M_0402_5%
R98
Y1
R99
1K_0402_5%
1
2
1
1
32.768KHZ_12.5PF_CM31532768DZFT
C179
1U_0603_10V4Z
C180
18P_0402_50V8J
CLRP1
SHORT PADS
2
1
2
1
1
2
2
C181
18P_0402_50V8J
2
D
D
CMOS
2
+3VS
*
C
@
HDA_SPKR
2 1K_0402_5%
HIGH= Enable ( No Reboot )
LOW= Disable (Default)
<41> HDA_SPKR
+3V_PCH
*
PCH_SRTCRST#
G22
SM_INTRUDER#
K22
PCH_INTVRMEN
C17
<42> ME_FLASH
R108
*
HDA_SYNC
1 1K_0402_5%
2
R107 1
This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Chief River platfrom
@
T10
HDA_RST#
K34
HDA_RST#
E34
HDA_SDIN0
HDA_SDOUT
PCH_GPIO33
1
J3
51_0402_5%
PCH_JTAG_TMS
H7
PCH_JTAG_TDI
K5
PCH_JTAG_TDO
H1
2
Q10
HDA_SYNC
1
SPI_CLK_PCH_R
2
SPI_SB_CS0#
R878
1M_0402_5%
HDA_SDOUT
@
R122
200_0402_5%
@
R123
200_0402_5%
T3
Y14
SPI_SB_CS1#
T1
0_0402_5%
SPI_SI
V4
SPI_SO_R
check with vender
+3V_PCH
1
@
R121
200_0402_5%
+3V_PCH
1
1
+3V_PCH
HDA_DOCK_EN# / GPIO33
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
Del Q10 check with codec
VDDIO using 3VALW
U3
LPC_FRAME#
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
JTAG_TMS
SATAICOMPO
SATAICOMPI
SATA3RBIAS
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SPI_MOSI
SATALED#
SATA0GP / GPIO21
SPI_MISO
SATA1GP / GPIO19
PANTHER-POINT_FCBGA989
SERIRQ
AM3
AM1
AP7
AP5
SATA_ITX_C_DRX_N0 0.01U_0402_25V7K 2
SATA_ITX_C_DRX_P0 0.01U_0402_25V7K 2
SERIRQ
@
R128
100_0402_1%
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2
1 C184
1 C185
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_DTX_C_IRX_N0 <40>
SATA_DTX_C_IRX_P0 <40>
SATA_ITX_DRX_N0 <40>
SATA_ITX_DRX_P0 <40>
HDD
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2
C
<40>
<40>
<40>
<40>
ODD
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
SATA_COMP
R111
37.4_0402_1% +1.05VS_VCC_SATA
1
2
SATA3_COMP
R113
49.9_0402_1%
1
2
Y11
Y10
AB12
AB13
AH1
RBIAS_SATA3
2
R115
750_0402_1%
+3VS
B
P3
SATALED#
2 R117
1
10K_0402_5%
+3VS
V14
PCH_GPIO21
2 R119
1
10K_0402_5%
+3VS
P1
BBS_BIT0_R
8MB SPI ROM FOR ME
& Non-share ROM.
+1.05VS_SATA3
1
2 R187
1
10K_0402_5%
R291
0_0402_5%
SPI_SB_CS1# 1
2
SPI_SO_R
1
2
U6
CS1#
SPI_SO1
SPI_WP#1
1
2
3
4
R188
33_0402_5%
+3VS
R199
SPI_HOLD#1 0_0402_5%
SPI_CLK1
1
2 SPI_CLK_PCH_R
SPI_SI1
1
2 SPI_SI
R196
33_0402_5%
16M W25Q16BVSSIG SOIC 8P
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
+3VS
R124
33_0402_5%
@
R266 1
2 SPI_WP#1
3.3K_0402_5%
R221 1
2 SPI_HOLD#1
3.3K_0402_5%
2 SPI_WP#
3.3K_0402_5%
R127 1
R124;c190 close to U4.T3 pin
R129 1
2
2
2
DPDG1.1
<42>
CAP on Conn, side
AM10
AM8
AP11
AP10
1
2
PCH_JTAG_TDI
2
@
R126
100_0402_1%
1
2
1
2
1
@
R125
100_0402_1%
PCH_JTAG_TMS
1 10K_0402_5%
2
V5
SPI_CLK_PCH_R
PCH_JTAG_TDO
EC and Mini card debug port
LPC_FRAME# <36,42>
R104
SPI_CS0#
SPI_CS1#
<36,42>
<36,42>
<36,42>
<36,42>
+3VS
E36
K36
AB8
AB10
AF3
AF1
JTAG_TCK
SPI_CLK
D36
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TDO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AD7
AD5
AH5
AH4
HDA_DOCK_RST# / GPIO13
JTAG_TDI
C38
A38
B37
C37
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3COMPI
R175 @
1
2
1
<41> HDA_SDOUT_AUDIO
3
S
<41> HDA_RST_AUDIO#
HDA_SYNC_R
HDA_RST#
HDA_SDO
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA3RCOMPO
HDA_BIT_CLK
G
<41> HDA_SYNC_AUDIO
B
HDA_SDIN1
HDA_SDIN3
PCH_JTAG_TCK
D
R112
33_0402_5%
1
2
R114
33_0402_5%
1
2
R116
33_0402_5%
1
2
R118
33_0402_5%
1
2
SPKR
HDA_SDIN2
C36
SERIRQ
HDA_SYNC
A34
A36
LDRQ0#
LDRQ1# / GPIO23
HDA_BCLK
C34
N32
+5VS
<41> HDA_BITCLK_AUDIO
INTVRMEN
HDA_SPKR
2 1K_0402_1%
2 R110
INTRUDER#
L34
10K_0402_5% 2 R264 @1
+3V_PCH
FWH4 / LFRAME#
SRTCRST#
N34
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
+3V_PCH
RTCRST#
HDA_SYNC
G34
R109
0_0402_5%
ME_FLASH 1
2
RTCX2
HDA_BIT_CLK
HDA_SDOUT
@ 1 1K_0402_5%
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
D20
HDA_SDIN0
<41> HDA_SDIN0
R106 2
PCH_RTCRST#
RTCX1
SPI
R105 1
C20
SATA 6G
C182
1U_0603_10V4Z
(INTVRMEN should always be pull high.)
PCH_RTCX2
SATA
1
A20
RTC
H：
： Integrated VRM enable
L：
： Integrated VRM disable
PCH_RTCX1
IHDA
INTVRMEN
*
2
U4A
CLRP3
SHORT PADS
C183
1U_0603_10V4Z
1
2
R103 20K_0402_5%
1
2
R100 20K_0402_5%
1
PCH_INTVRMEN
2
SM_INTRUDER#
2 330K_0402_5%
1
2 1M_0402_5%
R102 1
2
R101 1
1
JTAG
+RTCVCC
CLRP2
SHORT PADS
+RTCVCC
2 SPI_HOLD#
3.3K_0402_5%
C190
22P_0402_50V8J
@
U6 Rersver 4M+2M Solution
+3VS
C191
1
2
R130
0_0402_5%
SPI_SB_CS0# 1
2
SPI_SO_R
1
2
U5
CS#
SPI_SO_L
SPI_WP#
33_0402_5%
R131
1
2
3
4
0.1U_0402_16V4Z
R132
CS#
VCC 8
SPI_HOLD#
0_0402_5%
SO
HOLD# 7
SPI_CLK_PCH 1
6
2 SPI_CLK_PCH_R
WP#
SCLK
SPI_SI_R
1
2 SPI_SI
GND
SI 5
R133
32M W25Q32BVSSIG SOIC 8P
33_0402_5%
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
14
of
60
3
2
1
U4B
PERN2
PERP2
PETN2
PETP2
BG36
BJ36
AV34
AU34
PERN3
PERP3
PETN3
PETP3
D
USB3.0
<45> PCIE_PRX_DTX_N4
<45> PCIE_PRX_DTX_P4
<45> PCIE_PTX_C_DRX_N4
<45> PCIE_PTX_C_DRX_P4
C309
C308
EU3@
EU3@
1
1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
BF36
BE36
AY34
BB34
CAP on Conn, side
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
LAN
C
R153 1
R154 1
2 0_0402_5%
2 0_0402_5%
R151 1
R152
2
2 0_0402_5%
1 10K_0402_5%
<36> CLK_PCIE_WLAN1#
<36> CLK_PCIE_WLAN1
R149 1
R150 1
2 0_0402_5%
2 0_0402_5%
<36> CLKREQ_WLAN#
R156 1
R158 2
2 0_0402_5%
1 10K_0402_5%
<37> CLK_PCIE_LAN#
<37> CLK_PCIE_LAN
<37> CLKREQ_LAN#
+3V_PCH
WLAN
+3VS
USB3.0
<45> CLK_PCIE_USB30#
<45> CLK_PCIE_USB30
<45> CLKREQ_USB30#
+3V_PCH
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
CLKREQ_LAN#_R
CLK_PCIE_WLAN1#_R
CLK_PCIE_WLAN1_R
CLKREQ_WLAN#_R
PCH_GPIO20
R147
2
1 10K_0402_5%
R334
R330
1 EU3@
1 EU3@
2 0_0402_5%
2 0_0402_5%
CLK_USB30#
CLK_USB30
R326
R301
1 EU3@
2
2 0_0402_5%
1 10K_0402_5%
CLKREQ_USB30#_R
Y40
Y39
J2
AB49
AB47
M1
V10
Y37
Y36
A8
Y43
Y45
+3V_PCH
R165
2
1 10K_0402_5%
PCH_GPIO26
+3V_PCH
R168
2
1 10K_0402_5%
PCH_GPIO44
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
AA48
AA47
+3VS
PERN5
PERP5
PETN5
PETP5
L12
V45
V46
L14
SML0ALERT# / GPIO60
C9
PCH_SMBDATA
PCH_SML0CLK
SML0DATA
G12
PCH_SML0DATA
SML1ALERT# / PCHHOT# / GPIO74
C13
SML1CLK / GPIO58
E14
SML1CLK
M16
SML1DATA
SML1DATA / GPIO75
CL_CLK1
3
DRAMRST_CNTRL_PCH <7>
2 R139
1
1K_0402_5%
1 10K_0402_5%
PCH_HOT#
M7
SMB_CLK_S3 <12,13,36>
2.2K_0402_5%
1
2 R137
+3VS
1
2
R138
2.2K_0402_5%
4 SMB_DATA_S3
DIMM1
DIMM2
MINI CARD
SMB_DATA_S3 <12,13,36>
2N7002DW-T/R7_SOT363-6
Q60B
D
+3V_PCH
Q61A
2N7002DW-T/R7_SOT363-6
EC_SMB_CK2
6
1
+3V_PCH
PCH_HOT# <42>
2.2K_0402_5%
R141 2
1
+3V_PCH
+3VS
1
2
R142
2.2K_0402_5%
4
EC_SMB_CK2 <23,39,42>
VGA
EC
thermal sensor
EC_SMB_DA2
EC_SMB_DA2 <23,39,42>
2N7002DW-T/R7_SOT363-6
Q61B
+3V_PCH
+3V_PCH
CL_DATA1
CL_RST1#
T11
R143
10K_0402_5%
P10
R544
2.2K_0402_5%
R144
1
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
1
2
R135
2.2K_0402_5%
3
PEG_A_CLKRQ# / GPIO47
PCIECLKRQ0# / GPIO73
2.2K_0402_5%
R136 2
1
DRAMRST_CNTRL_PCH
A12
C8
SML0CLK
+3V_PCH
+3V_PCH
2 R140
PERN4
PERP4
PETN4
PETP4
BG40
BJ40
AY40
BB40
CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R
SMBDATA
2 R134
1
10K_0402_5%
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLKOUT_DP_N
CLKOUT_DP_P
AM12
AM13
CLKIN_DMI_N
CLKIN_DMI_P
BF18
BE18
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R155 1
R157 1
2
2
10K_0402_5%
10K_0402_5%
BJ30
BG30
CLKIN_DMI2#
CLKIN_DMI2
R159 1
R160 1
2
2
10K_0402_5%
10K_0402_5%
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R162 1
R163 1
2
2
10K_0402_5%
10K_0402_5%
AK7
AK5
CLK_BUF_PCIE_SATA# R164 1
CLK_BUF_PCIE_SATA R166 1
2
2
10K_0402_5%
10K_0402_5%
K45
CLK_BUF_ICH_14M
2
10K_0402_5%
H45
CLK_PCI_LPBACK
V47
V49
XTAL25_IN
XTAL25_OUT
Y47
XCLK_RCOMP
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N
CLKIN_SATA_P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
CLKIN_PCILOOPBACK
PCH_SML0CLK
CLK_PCIE_VGA#
CLK_PCIE_VGA
2 0_0402_5%
2 0_0402_5%
R545
2.2K_0402_5%
PCH_SML0DATA
CLK_CPU_DMI#
CLK_CPU_DMI
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLK_REQ_VGA# <23>
1 R145
2 10K_0402_5%
@
CLK_PCIE_VGA#_R R146 1
CLK_PCIE_VGA_R R148 1
0_0402_5%
2
AB37
AB38
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
M10 PEG_CLKREQ#_R
2
BE34
BF34
BB32
AY32
PCH_SMBCLK
2
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCH_GPI011
H14
1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
E12
1
1
1
SMBCLK
2
C194
C195
SMBALERT# / GPIO11
5
PERN1
PERP1
PETN1
PETP1
2
BG34
BJ34
AV32
AU32
1
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
SMBUS
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
Link
1
1
Controller
C192
C193
CLOCKS
WLAN
PCI-E*
LAN
Q60A
2N7002DW-T/R7_SOT363-6
6
1 SMB_CLK_S3
2
4
5
5
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>
C
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
R167 1
CLK_PCI_LPBACK <18>
B
B
XTAL25_IN
+3V_PCH
R170
1 10K_0402_5%
2
PCH_GPIO56
E6
V40
V42
+3V_PCH
+3V_PCH
R172
R174
2
2
110K_0402_5%
1 10K_0402_5%
PCH_GPIO45
PCH_GPIO46
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
XCLK_RCOMP
T13
CLKOUT_PCIE7N
CLKOUT_PCIE7P
K12
XTAL25_OUT
R171
90.9_0402_1%
1
2
1
2
R169 1M_0402_5%
+1.05VS_VCCDIFFCLKN
3
2
CLKOUT_PCIE6N
CLKOUT_PCIE6P
V38
V37
AK14
PCIE_CLK_8N AK13
PCIE_CLK_8P
XTAL25_IN
XTAL25_OUT
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
27M_SSC
FLEX CLOCKS
AB42
AB40
CLKOUTFLEX0 / GPIO64
K43
F47
C196
12P_0402_50V8J
OSC
NC
NC
OSC
4
1
Y2
1 25MHZ_10PF_7V25000014
1
R02
2
H47
LAN_48M
K49
PCH_GPIO67
1 R207 @2 22_0402_5%
C197
12P_0402_50V8J
2
PCH_LAN_48M
PCH_GPIO67 <19>
BIOS Request SKU ID
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PCH (2/9) PCIE, SMBUS, CLK
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
15
of
60
5
4
3
2
1
D
D
U4C
SYS_PWROK <6>
1
R180 @
100K_0402_1%
2
+3VS
<5>
<5>
<5>
<5>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<5>
<5>
<5>
<5>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<5>
<5>
<5>
<5>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
+1.05VS
BJ24
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%
1
R177
1
R178
C
BG25
BH21
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
R191
PCH_POK
1
APWROK
2
R02
@
1
0_0402_5% R302
<42> PCH_APWROK
+3V_PCH
@
2 R556
2
B
R02
1 200_0402_5%
R192 1 300_0402_5%
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
FDI_LSYNC0
C12
K3
P12
SUSACK#
SYS_RESET#
SYS_PWROK
PCH_POK
2
0_0402_5%
2
APWROK
L22
L10
PWROK
APWROK
DRAMPWROK
@
1
R193
<42> EC_RSMRST#
FDI_FSYNC0
FDI_LSYNC1
PM_DRAM_PWRGD B13
<6> PM_DRAM_PWRGD
+3VS
FDI_INT
AV12
DMI2RBIAS
@
0_0402_5%
AW16
FDI_FSYNC1
System Power Management
1
SYS_RST#
SYS_PWROK
PCH_PWROK1
R190
FDI_INT
DMI_IRCOMP
@
<42> PCH_PWROK
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
DSWVRMEN
SUSACK#
T72
AEPWROK can be connect to
PWROK if iAMT disable
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_FSYNC0
SUSACK# is only used on platform
that support the Deep Sx state.
2
10K_0402_5% R184
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
DMI_ZCOMP
4mil width and place
within 500mil of the PCH
+3VS
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
PCH_RSMRST#_R
2
0_0402_5%
C21
SUSWARN#
K16
RSMRST#
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUSWARN#/SUSPWRDNACK/GPIO30
SLP_S3#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
FDI_INT <5>
A18
DSWODVREN
E22
PCH_DPWROK
B9
WAKE#
FDI_FSYNC0
<5>
FDI_FSYNC1
<5>
FDI_LSYNC0
<5>
FDI_LSYNC1
<5>
R02 @1 R181
N3
R02 @
1 R185
2 0_0402_5%
1
2 10K_0402_5%
R186
PM_CLKRUN#
G8
SUS_STAT#
+RTCVCC
*
1
4 SYS_PWROK
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
2 0_0402_5% PCH_RSMRST#_R
1
@ R189 8.2K_0402_5%
2
2
N14
SUSCLK <42>
D10
PM_SLP_S5# <42>
H4
PM_SLP_S4# <42>
F4
R194
2
1 10K_0402_5%
SUSWARN#
R195
1
2 200K_0402_5%
AC_PRESENT_R
R197
2
1 10K_0402_5%
PCH_RSMRST#_R
<42> PBTN_OUT#
<42,49>
ACIN
D29 1
2
@
R02
PBTN_OUT#_R
2
0_0402_5%
AC_PRESENT_R
CH751H-40PT_SOD323-2
PCH_GPIO72
2 R200
1
10K_0402_5%
+3V_PCH
2 R201
1 RI#
10K_0402_5%
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
A10
BATLOW# / GPIO72
SLP_A#
G10
SLP_A#
T99
SLP_SUS#
G16
PM_SLP_SUS#
T71
AP14
H_PM_SYNC
K14
PCH_GPIO291
PMSYNCH
RI#
SLP_LAN# / GPIO29
R299 10K_0402_5%
1
PM_SLP_S3# <42>
PM_DRAM_PWRGD
1
R198
R183
330K_0402_5%
@
+3VS
PCIE_WAKE# <36,37,45>
+3V_PCH
T74
C
R179
330K_0402_5%
DSWODVREN - On Die DSW VR Enable
H：Enable
L：Disable
2
Y
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
1
B
BC24
BE20
BG18
BG20
2
A
2
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
FDI
1
5
PCH_PWROK
<5>
<5>
<5>
<5>
DMI
VGATE
P
<55>
G
3
U15
MC74VHC1G08DFT2G SC70 5P
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
Can be left NC
when IAMT is not
support on the
platfrom
B
H_PM_SYNC <6>
2
R261 @
10K_0402_5%
Can be left NC if no use
integrated LAN.
+3V_PCH
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PCH (3/9) DMI,FDI,PM,
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
16
of
60
5
4
3
2
1
U4D
C
L_DDC_CLK
L_DDC_DATA
T45
P39
L_CTRL_CLK
L_CTRL_DATA
2.2K_0402_5%1 R204
2.2K_0402_5%1 R205
2
2
CTRL_CLK
CTRL_DATA
2.37K_0402_1%
2 R206
1
LVDS_IBG
AF37
AF36
LVD_IBG
LVD_VBG
LVD_VREF
AE48
AE47
LVD_VREFH
LVD_VREFL
<33> LVDS_ACLK#
<33> LVDS_ACLK
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
<33> LVDS_A0#
<33> LVDS_A1#
<33> LVDS_A2#
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
<33> LVDS_A0
<33> LVDS_A1
<33> LVDS_A2
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
+3VS
R524
2.2K_0402_5%
<34> DAC_GRN
<34> DAC_RED
DAC_BLU
1 150_0402_1%
DAC_GRN
1 150_0402_1%
DAC_RED
1 150_0402_1%
R208 2
R209 2
R210 2
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
SDVO_CTRLCLK
SDVO_CTRLDATA
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
M47
M49
CRT_HSYNC
CRT_VSYNC
HDMI@ R202
2.2K_0402_5%
R203HDMI@
2.2K_0402_5%
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
P38 HDMICLK_NB
M39 HDMIDAT_NB
AT49
AT47
AT40
TMDS_B_HPD# <35>
AV42 TMDS_B_DATA2#_PCHHDMI@
AV40 TMDS_B_DATA2_PCH HDMI@
AV45 TMDS_B_DATA1#_PCHHDMI@
AV46 TMDS_B_DATA1_PCH HDMI@
AU48 TMDS_B_DATA0#_PCHHDMI@
AU47 TMDS_B_DATA0_PCH HDMI@
AV47 TMDS_B_CLK#_PCH HDMI@
HDMI@
AV49 TMDS_B_CLK_PCH
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
C200
C201
C202
C203
C204
C205
C206
C207
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
HDMI_TX2-_CK
HDMI_TX2+_CK
HDMI_TX1-_CK
HDMI_TX1+_CK
HDMI_TX0-_CK
HDMI_TX0+_CK
HDMI_CLK-_CK
HDMI_CLK+_CK
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
HDMI D2
HDMI
HDMI D1
HDMI D0
C
HDMI CLK
CAP move on Conn, side
P46
P42
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPD_CTRLCLK
DDPD_CTRLDATA
HDMICLK_NB <35>
HDMIDAT_NB <35>
M43
M36
B
2
R559
2.2K_0402_5%
2
B
1
1
<34> DAC_BLU
SDVO_STALLN
SDVO_STALLP
D
+3VS
1
L_BKLTCTL
T40
K47
AP43
AP45
1
P45
EDID_CLK
EDID_DATA
PCH_PWM
<33> EDID_CLK
<33> EDID_DATA
SDVO_TVCLKINN
SDVO_TVCLKINP
2
+3VS
L_BKLTEN
L_VDD_EN
2
2
<33>
EDID_CLK
EDID_DATA
J47
M45
Digital Display Interface
<33> PCH_ENBKL
<33> PCH_ENVDD
LVDS
R234
2.2K_0402_5%
2
R523
2.2K_0402_5%
CRT_DDC_CLK
CRT_DDC_DATA
<34> CRT_DDC_CLK
<34> CRT_DDC_DATA
CRT_DDC_CLK
CRT_DDC_DATA
1
<34> CRT_HSYNC
<34> CRT_VSYNC
CRT_IREF T43
T42
DAC_IREF
CRT_IRTN
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
2
R211
1K_0402_1%
CRT
D
1
1
+3VS
A
A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
5
4
3
2
PCH (4/9) LVDS,CRT,DP,HDMI
Size
B
Date:
Document Number
Rev
0.2
LA-7981P
Sheet
1
17
of
60
5
4
3
2
1
+3VS
U4E
RP2
8.2K_0804_8P4R_5%
R213
1
2 8.2K_0402_5%
PCH_GPIO5
R225
1
2 8.2K_0402_5%
PCH_WL_OFF#
R292
1
@
2 8.2K_0402_5%
PCH_GPIO51
R557
1
@
2 8.2K_0402_5%
PCH_GPIO53
R259
1
2 8.2K_0402_5%
DGPU_PWR_EN1
R212
1
2 8.2K_0402_5%
DGPU_HOLD_RST#_R
R214
1
2 8.2K_0402_5%
DGPU_HOLD_RST#_R
@
Boot BIOS Strap bit1 BBS1
<45> USB3_RX3_N
<45> USB3_RX4_N
Boot BIOS
Bit11 Bit10 Destination
GNT1#/
GPIO51
0
1
Reserved
1
0
Reserved
1
1
0
0
DGPU_PWR_EN_R
1
R319
*
SPI
<45> USB3_RX3_P
<45> USB3_RX4_P
<45> USB3_TX3_N
<45> USB3_TX4_N
(Default)
LPC
USB3_RX1_N
USB3_RX3_N
USB3_RX4_N
USB3_RX1_P
T1832
T1826
USB3_RX3_P
USB3_RX4_P
USB3_TX1_N
T1831
T1827
USB3_TX3_N
USB3_TX4_N
USB3_TX1_P
T1830
T1828
USB3_TX3_P
USB3_TX4_P
<45> USB3_TX3_P
<45> USB3_TX4_P
2 NVDD_PWR_EN
0_0402_5%
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
@
B
R215
@
1
R553 1
R692 1
R691 1
<23> DGPU_HOLD_RST#
<54> NVDD_PWR_EN
<23,25> DGPU_PWR_EN
GPIO55
PCH_WL_OFF#
B21
M20
AY16
BG46
TP21
TP22
TP23
TP24
PPT EDS DOC#474146
T1829
T1825
C
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
2 1K_0402_5%
@
@
@
Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default
PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#
R715 1
<40,42> ODD_DA#
@
K40
K38
H38
G38
2 0_0402_5% DGPU_HOLD_RST#_RC46
2 0_0402_5% DGPU_PWR_EN1
C44
2 0_0402_5% DGPU_PWR_EN_R
E40
<36> PCH_WL_OFF#
A16 swap overide Strap/Top-Block
Swap Override jumper
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
PCH_GPIO2
2 0_0402_5% ODD_DA#_R
PCH_GPIO4
PCH_GPIO5
<42>
PCH_PLTRST#
<6> PCH_PLTRST#
22_0402_5% 1
22_0402_5% 1
22_0402_5% 2
<15> CLK_PCI_LPBACK
<42> CLK_PCI_EC
<36> CLK_PCI_DB
@
2 R219
2 R220
1 R173
1 R222
2
0_0402_5%
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
G42
G40
C42
D44
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
C6
CLK_PCI_LPBACK_R H49
CLK_PCI_EC_R
H43
CLK_PCI_DB_R
J48
K42
H40
AY7
AV7
AU3
BG4
RSVD5
RSVD6
AT10
BC8
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD23
RSVD24
AV5
AV10
RSVD25
AT8
RSVD26
RSVD27
AY5
BA2
RSVD28
RSVD29
AT12
BF3
C
USB DEBUG=PORT1 AND PORT9
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
K10
PCI_PME#
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4
D47
E42
F46
*
RSVD1
RSVD2
RSVD3
RSVD4
D
USB
8.2K_0804_8P4R_5%
RP1
PCH_GPIO2
8
1
DGPU_PWR_EN_R
7
2
PCH_GPIO4
6
3
ODD_DA#_R
5
4
D
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
RSVD
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
1
2
3
4
PCI
8
7
6
5
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS#
C33
USBRBIAS
B33
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N5
USB20_P5
USB20_N5 <33>
USB20_P5 <33>
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N13
USB20_P13
USBRBIAS
<43>
<43>
<45>
<45>
<45>
<45>
USB20_N9 <44>
USB20_P9 <44>
USB20_N10 <36>
USB20_P10 <36>
USB20_N11 <43>
USB20_P11 <43>
USB20_N13 <40>
USB20_P13 <40>
R218 2
1
22.6_0402_1%
LEFT USB
(USB 3.0)
LEFT USB
USB Camera
RIGHT USB
WLAN
Bluetooth
R02
PLTRST#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
A14
K20
B17
C16
L16
A16
D14
C14
10K_1206_8P4R_5% RP3
USB_OC5#
4
USB_OC2#
3
USB_OC7#
2
1
USB_OC4# <44>
USB_OC1# <45>
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
SMIB
USB_OC7#
B
CARD READER
USB_OC0# Share with USB_OC4#
due to same power switch
Within 500 mils
PME#
(CR-B/D USB)
USB_OC4# <44>
SMIB
USB_OC1#
USB_OC4#
USB_OC3#
<45>
+3V_PCH
5
6
7
8
4
3
2
1
5
6
7
8
10K_1206_8P4R_5% RP4
R03
SMIB
G
4
1
B
2
Y
1
PLT_RST#
C208 @
1U_0402_6.3V4Z
5
2
5
1
2
<23,36,37,42,45>
A
P
3
A
U7@
4
2
A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
+3VS
R223
100K_0402_5%
1 R262
10K_0402_5%
PCH_PLTRST#
3
2
PCH (5/9) PCI, USB
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
18
of
60
2
1
R707
@
1
+3V_PCH
Weak internal pull-high
1 R235
PCH_GPIO68
A42
TACH1 / GPIO1
TACH5 / GPIO69
B41
PCH_GPIO69
H36
TACH2 / GPIO6
TACH6 / GPIO70
C41
PCH_GPIO70
+3VS
TACH7 / GPIO71
A40
PCH_GPIO71
1 R227
2 10K_0402_5%
PCH_GPIO1
1 R228
2 10K_0402_5%
PCH_GPIO6
EC_SCI#
E38
TACH3 / GPIO7
EC_SMI#
C10
GPIO8
<42> EC_SMI#
2 1K_0402_5% PCH_GPIO28
1 R229@ 2 10K_0402_5%
+3V_PCH
R230 2 1K_0402_5%
T7
C4
LAN_PHY_PW R_CTRL / GPIO12
PCH_GPIO27
2 10K_0402_5%
PU on power side
2 10K_0402_5%
EC_LID_OUT#
G2
GPIO15
R297 1
2 0_0402_5%
+3VS 1 R232@ 2 10K_0402_1%
1 R238
+3VS
2 10K_0402_5%
<36> BT_DISABLE
<40> ODD_EN
+3V_PCH
R02
PCH_GPIO16
A20GATE
U2
+3VS
D40
BT_DISABLE
T5
SCLOCK / GPIO22
ODD_EN
E8
GPIO24
PCH_GPIO27
E16
GPIO27
2 10K_0402_5%
PCH_GPIO28
P8
GPIO28
1 R242
2 10K_0402_5%
PCH_BT_ON#
K1
STP_PCI# / GPIO34
1 R243
2 10K_0402_5%
PCH_GPIO35
K4
GPIO35
2
2
R250 @
10K_0402_5%
PCH_GPIO36
+3VS
1
1
PCH_GPIO37
R881
10K_0402_5%
+3VS
+3V_PCH
10K_0402_5%1 R224
2
1
2
PCH_GPIO36
V8
SATA2GP / GPIO36
PCH_GPIO37
M5
SATA3GP / GPIO37
PCH_GPIO38
N2
SLOAD / GPIO38
P4
PCH_PECI_R
P5
KBRST#
PROCPW RGD
AY11
THRMTRIP#
AY10
INIT3_3V#
+3VS
GATEA20 <42>
AU16
@
1
2
0_0402_5% R237
H_PECI
<6,42>
KBRST#
<42>
H_CPUPWRGD
PCH_THRMTRIP#_R 1
R239
KBRST#
R226
2 10K_0402_5%
1
<6>
H_THRMTRIP#
2
390_0402_5%
H_THRMTRIP# <6>
C
T14
DF_TVS
AY1
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
TS_VSS4
AK10
PCH_THRMTRIP#_R <23>
INIT3_3V
This signal has weak internal PU,can't pull low
+1.8VS
DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
NC_1
P37
R247
1
2 10K_0402_5%
PCH_GPIO39
M3
SDATAOUT0 / GPIO39
R248
1
2 10K_0402_5%
PCH_GPIO48
V13
SDATAOUT1 / GPIO48
VSS_NCTF_15
BG2
R249
1
2 10K_0402_5%
PCH_GPIO49
V3
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16
BG48
R251
1
2 10K_0402_5%
PCH_GPIO57
D6
GPIO57
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
R216
2.2K_0402_5%
NV_CLE
2
Weak internal
PU,Do not pull low
1
R217 1K_0402_5%
H_SNB_IVB# <6>
CLOSE TO THE BRANCHING POINT
2
2
R547
10K_0402_5%
TACH0 / GPIO17
1
1
1
+3VS
SATA4GP / GPIO16
RCIN#
DGPU_PWROK_R
R241
<36,40> PCH_BT_ON#
+3VS
PECI
CPU/MISC
<46,54> DGPU_PWROK
C
R244 @
10K_0402_5%
D
R236
10K_0402_5%
PCH_GPIO12
GPIO
1 R231
+3VS
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable
@
R706
200K_0402_5%
2
<42> EC_SCI#
R02 1
1
10K_0402_5%
2
C40
2
+3VS
H：On-Die voltage regulator enable
L：On-Die PLL Voltage Regulator disable
R245
USB3.0 by PCH
USB3.0 by NEC
+3VS
TACH4 / GPIO68
2 10K_0402_5%
<42> EC_LID_OUT#
*
R704
1
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
@
0
1
BMBUSY# / GPIO0
1 R233
GPIO28
1
@
PCH_GPIO71
PCH_GPIO71
R705
200K_0402_5%
U4F
R240
14/15"
17"
EC_SMI#
2 10K_0402_5%
+3VS
*
0
1
1
D
@ R703
PCH_GPIO70
Function
2
PCH_GPIO69
2
@ R702
+3VS
PCH_GPIO70
1
HM76 by PCH
HM70 by PCH
1
0
1
10K_0402_5%
Function
2
PCH_GPIO69
+3VS
10K_0402_5%
2
+3VS
1
3
1
4
10K_0402_5%
5
VSS_NCTF_1
VSS_NCTF_19
BJ4
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
A46
VSS_NCTF_4
VSS_NCTF_22
BJ46
A5
VSS_NCTF_5
VSS_NCTF_23
BJ5
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
BIOS Request SKU ID
1
2
R246
@
10K_0402_5%
1
R711
@
10K_0402_5%
2
+3VS
PCH_GPIO38
1
2
R298
10K_0402_5%
1
R708
A
10K_0402_5%
2
PCH_GPIO67
PCH_GPIO67 <15>
NCTF
B
A4
B
PCH_GPIO38
PCH_GPIO67
Function
A
0
0
Optimus
0
1
Reserved
1
0
DIS
1
5
1
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
UMA
4
3
2
Title
PCH (6/9) GPIO, CPU, MISC
Custom
Rev
0.2
LA-7981P
Date:
Sheet
19
of
1
60
5
4
3
2
1
L1 Change to 1 ohm P/N
S RES 1/10W 1 +-1% 0603
+1.05VS
POWER
U4G
+3VS
PCH Power Rail Table
Refer to CPU EDS R1.5
10U
@ J2
2
+1.05VS
CRT
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
1mA
VCCADAC
U48
VSSADAC
U47
1mA VCCALVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
AN16
AN17
AN21
AN26
AN27
10U
AP21
C
+1.05VS_VCC_EXP
1
2
1
2
C225
1U_0402_6.3V6K
2
C224
1U_0402_6.3V6K
1
C223
1U_0402_6.3V6K
2
C222
1U_0402_6.3V6K
2
1
C221
10U_0603_6.3V6M
1
AP23
AP24
AP26
AT24
+3VS
R260 2
+3VS_VCCA3GBG
1
0_0603_5%
1
+VCCAFDI_VRM
VCCIO[15]
VCCIO[16]
VCCIO[17]
This pin can be left as no connect in
On-Die VR enabled mode (default).
VCCIO[19]
3711mA
BG6
AP17
+VCCP_VCCDMI
AU20
VCC3_3[6]
R295 2
Voltage Rail
2
V_PROC_IO
V5REF
1
Voltage
S0 Iccmax
Current (A)
1.05
0.001
5
0.001
D
0_0603_5%
AK37
+VCCTX_LVDS
1
AM38
V5REF_Sus
+1.8VS
L2
0.1UH_MLF1608DR10KT_10%_1608
2
1
AM37
1
AP37
2
C216
0.01U_0402_25V7K
2
C217
0.01U_0402_25V7K
2
5
0.001
Vcc3_3
3.3
0.228
VccADAC
3.3
0.001
VccADPLLA
1.05
0.075
VccADPLLB
1.05
0.075
VccCore
1.05
1.3
VccDMI
1.05
0.042
VccIO
1.05
3.709
VccASW
1.05
0.903
VccSPI
3.3
0.01
VccDSW
3.3
0.001
VccDFTERM
1.8
0.002
VccRTC
3.3
6 uA
3.3
0.065
0.1uH inductor, 200mA
1
AP36
+3VS_VCC3_3_6 2
V33
C218
22U_0805_6.3V6M
V34
2
1
0_0603_5%
1
VCC3_3[7]
VCCVRM[3]
C219
0.1U_0402_10V7K
AT16
+VCCAFDI_VRM
+VCCP_VCCDMI
VCCIO[22]
VCCIO[23]
VCCIO[24]
+V1.05S_VCCP
R258
VCCIO[21]
VCCIO[26]
+1.05VS_VCCDPLL_FDI
+VCCA_LVDS
VCCIO[20]
AN34
T50 +1.05VS_VCCAPLL_FDI
C395@
10U_0603_6.3V6M
VCCIO[18]
VCCIO[25]
AP16
2
1
C215
10U_0603_6.3V6M
R256
VCCDMI[1]
VCC3_3[3]
C227
0.1U_0402_10V7K
2
AK36
VCCAPLLEXP
AN33
BH29
2
1
C214
0.1U_0402_10V7K
+3VS
HVCMOS
This pin can be left as no connect in
On-Die VR enabled mode (default).
1
C213
0.01U_0402_25V7K
1_0603_1%
1
VCCIO[28]
DMI
BJ22
VCCVRM[2]
VccAFDIPLL
AT20
+VCCP_VCCDMI
2
1
+1.05VS
R294
20mA VCCCLKDMI
AB36 +1.05VS_VCC_DMI_CCI
2
1
C226
1U_0402_6.3V6K
VCCDFTERM[1]
AG16
190mAVCCDFTERM[2]
AG17
DFT / SPI
+VCCAPLLEXP
T47
VCCTX_LVDS[4]
VCCIO
+1.05VS_VCCDPLLEXPAN19
1 0_0603_5%
1
2
60mA VCCTX_LVDS[3]
R254 2
+VCCADAC
+3VS
LVDS
2
1
C212
1U_0402_6.3V6K
2
1
C211
1U_0402_6.3V6K
1
C210
1U_0402_6.3V6K
2
D
C209
10U_0603_6.3V6M
1
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
VCC CORE
+1.05VS_VCCCORE
1
PAD-OPEN 4x4m
+1.05VS
L1
2
1300mA
2
1
2
C
1
0_0603_5%
C220
1U_0402_6.3V6K
0_0603_5%
2
VccSus3_3
+VCCPNAND
+1.8VS
VccSusHDA
3.3 / 1.5
VccVRM
1.8 / 1.5
0.01
R293
VCCDFTERM[3]
AJ16
2
1
VCCDFTERM[4]
AJ17
1
0.167
0_0603_5%
C228
0.1U_0402_10V7K
2
+3VS
VccCLKDMI
1.05
0.075
VccSSC
1.05
0.095
R263
2
1
VCCIO[27]
0_0603_5%
B
VCCDMI[2]
R399
FDI
+1.05VS
20mA VCCSPI
V1
+3V_VCCPSPI
1
2
2
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.04
0_0402_5%
1
C230
1U_0402_6.3V6K
B
+VCCAFDI_VRM
+1.5VS
2
R265
1
0_0603_5%
+VCCAFDI_VRM
Intel recommand
stuff R265 and unstuff R266
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PCH (7/9) PWR
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
20
of
60
5
4
3
2
1
Have internal VRM
+3VS
+1.05VS
R268 @
0_0603_5%
2
1
+VCCACLK
10U
DCPSUSBYP
+3VS_VCC_CLKF33
T38
VCC3_3[5]
VCCIO[33]
BH23
VCCAPLLDMI2
AL29
VCCIO[14]
AL24
1
VCCSUS3_3[8]
AA21
2
2
AA24
C242
22U_0805_6.3V6M
2
C241
22U_0805_6.3V6M
+1.05VM_VCCASW
1
1
0_0805_5%
AA26
AA27
AA29
AA31
AC26
C
AC27
AC29
AC31
AD29
10UH_LB2012T100MR_20%
AD31
R300
0_0603_5%
W21
2
W23
W24
1
@
2
2
1
2
C253
1U_0402_6.3V6K
2
+
C187
22U_0805_6.3V6M
@
2
1
C252
220U_B2_2.5VM_R35
1
C251
1U_0402_6.3V6K
1
C186
22U_0805_6.3V6M
2
+1.05VS_VCCA_B_DPL
C250
220U_B2_2.5VM_R35
+
VCCASW[1]
VCCASW[2]
W26
W29
W31
W33
VCCIO[34]
1010mA
1mA V5REF_SUS
VCCASW[3]
VCCASW[4]
+VCCRTCEXT
N16
1
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
DCPSUS[4]
VCCSUS3_3[1]
Y49
+3V_PCH
+3V_VCCPUSB
2
1
+5VALW_PCH
T26
+3V_PCH
0_0603_5%
R273
+3V_VCCAUBG2
1
1
2
0_0603_5%
C238
0.1U_0402_10V7K
2
+1.05VS
R276
+1.05VS_VCCAUPLL
2
1
M26
+PCH_V5REF_SUS
AN23
+VCCA_USBSUS
C243 @1
2 1U_0402_6.3V6K
AN24
+3V_VCCPSUS
C316 @1
@
2 0.1U_0402_10V7K
P34
+PCH_V5REF_RUN
N20
+3V_VCCPSUS
T24
V23
V24
P24
1
+3V_PCH
R275
10_0402_5%
D1
1mA V5REF
VCCSUS3_3[2]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
VCC3_3[1]
VCC3_3[8]
VCCASW[16]
VCC3_3[4]
+3V_PCH
R278
VCCSUS3_3[3]
2
1
2
2
1
+3VS_VCCPCORE
W16
VCCVRM[4]
VCCIO[13]
2
C248
1U_0603_10V6K
+3VS
2
1
+3VS
DCPRTC
+PCH_V5REF_RUN
1
C249 0_0603_5%
0.1U_0402_10V7K
+3VS_VCCPPCI
2
R283
VCCASW[20]
+3VS
R282
T34
VCCASW[18]
VCC3_3[2]
C
D2
1
2
VCCASW[17]
VCCASW[19]
R279
10_0402_5%
1
0_0603_5%
C247
1U_0402_6.3V
C240
0.1U_0603_25V7K
+3VS
R281
AA16
+PCH_V5REF_SUS
1
+5VS
VCCIO[12]
+VCCAFDI_VRM
T23
2
VCCIO[5]
C258
0.1U_0402_10V7K
T29
0_0603_5%
1
2
C246
1U_0402_6.3V6K
+1.05VS_VCCA_A_DPL
2
2
1
C245
1U_0402_6.3V6K
2
@
L5
1
C244
1U_0402_6.3V6K
1
+1.05VS
VCCSUS3_3[10]
PCI/GPIO/LPC
AA19
R277
1
DCPSUS[3]
Clock and Miscellaneous
2
+1.05VS
VCCSUS3_3[9]
VCCSUS3_3[6]
@ C239
1U_0402_6.3V6K
D
2
+VCCSUS1
1
0_0603_5%
C236
0.1U_0402_10V7K
+VCCDPLL_CPY
1
USB
+VCCAPLL_CPY_PCH
R271
2
+1.05VS
2
R272
119mA VCCSUS3_3[7]
0_0603_5%
L6
1
2
10UH_LB2012T100MR_20%
1
VCCIO[32]
T27
T101
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
1
P28
+5VALW_PCH
R289
1
H：On-Die PLL voltage regulator enable
V12
P26
VCCIO[31]
+5VALW
R270
+1.05VS_VCCUSBCORE 2
1
1
0_0603_5%
C233
1U_0402_6.3V6K
2
2
C235 @
0.1U_0402_10V7K
+PCH_VCCDSW
VCCIO[30]
3mA
VCCDSW3_3
N26
1
1
T16
VCCIO[29]
1
C234
0.1U_0402_10V7K
VCCACLK
2
AD49
1
2
+1.05VS
+VCCPDSW
1
0_0603_5%
2
POWER
U4J
2
1
2
R269
C232
1U_0402_6.3V6K
2
D
+3V_PCH
1
C231
10U_0603_6.3V6M
1+3VS_VCC_CLKF33
1
0_0603_5%
2
R303
2
AJ2
+VCC3_3_2
2
1
1
1
0_0603_5%
C254
0.1U_0402_10V7K
+1.05VS_SATA3
+1.05VS
R285
0_0603_5%
AF13
2
C255
2 0.1U_0402_10V7K
1
AH13
2
+1.05VS_SATA3
AH14
1
0_0603_5%
C257
1U_0402_6.3V6K
2
B
R274
C256
1U_0402_6.3V6K
+1.05VS_VCCDIFFCLKN
2
+1.05VS_VCCA_B_DPL
BF47
+VCCDIFFCLK
+1.05VS_VCCDIFFCLKN
AF17
AF33
AF34
AG34
VCCIO[7]
VCCDIFFCLKN[1]
55mA
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
+1.05VS_SSCVCC
AG33
VCCSSC
R280
+1.05VS
2
1
0_0603_5%
1
2
C259
1U_0402_6.3V6K
2
1
2
+1.05VM_VCCSUS
T17
V19
0_0603_5%
+V_CPU_IO
1
2
1
2
1
2
80mA
B
AF14
AK1
+VCCSATAPLL
+VCCAFDI_VRM
T100
H：On-Die PLL voltage regulator enable
VCCVRM[1]
AF11
+VCCAFDI_VRM
+1.05VS_VCC_SATA
+1.05VS
R288
VCCIO[2]
95mA
AC16
VCCIO[3]
AC17
VCCIO[4]
AD17
+1.05VS_VCC_SATA
2
1
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
1 0_0603_5%
C261
1U_0402_6.3V6K
BJ8
+1.05VS
DCPSST
DCPSUS[1]
DCPSUS[2]
V_PROC_IO 1mA
+RTCVCC
VCCASW[22]
VCCASW[23]
VCCASW[21]
T21
V21
T19
+3V_PCH
R287
A22
2
1
2
1
2
C270
0.1U_0402_10V7K
1
C269
0.1U_0402_10V7K
@
C268
1U_0402_6.3V6K
C267
0.1U_0402_10V7K
2
A
+1.05VM_VCCSUS
2
1
C264 @
1U_0402_6.3V6K
V16
+V1.05S_VCCP
R286
2
1
C266
0.1U_0402_10V7K
@ R290
0_0603_5%
2
1
C262
1U_0402_6.3V6K
+VCCSST
1
C265
4.7U_0603_6.3V6K
+1.05VS
C263
0.1U_0402_10V7K
1
0_0603_5%
VCCADPLLB
VCCAPLLSATA
2
R284
+1.05VS
80mA
MISC
1
VCCIO[6]
VCCADPLLA
VCCRTC
HDA
0_0603_5%
BD47
SATA
1
CPU
2
RTC
+1.05VS
+1.05VS_VCCA_A_DPL
10mA VCCSUSHDA
P32
+VCCSUSHDA
1
@
2
1
0_0603_5%
C271
0.1U_0402_16V4Z
A
2
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PCH (8/9) PWR
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
21
of
60
5
4
3
2
1
U4I
D
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
U4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
C
B
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
D
C
B
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
PCH (9/9) VSS
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
22
of
60
5
4
3
2
1
+3VS_VGA
QV1B
3
4
EC_SMB_CK2 <15,39,42>
2N7002DW-T/R7_SOT363-6
2
C
VGA_SMB_DA2
QV1A
1
6
EC_SMB_DA2 <15,39,42>
2N7002DW-T/R7_SOT363-6
+3VS_VGA
+3VS_VGA
CV6
CV7
CV8
CV9
CV10
CV11
CV12
CV13
CV15
CV17
CV19
CV14
CV16
CV18
CV20
CV22
CV24
CV26
CV21
CV23
CV25
CV27
CV29
CV31
CV33
CV28
CV30
CV32
CV36
CV41
CV34
CV35
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
2 0.1U_0402_10V7K
N13P@
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P8
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N15
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
2
<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
Differential signal
1
Y
A
@
1
2
RV20
200_0402_1%
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
AJ26
AK26
PLT_RST_VGA#
PEX_TERMP
4
1
3
2
4
1
2
1
VGA_AC_DET <42,54>
DV3
2 RV17
DPRSLPVR_VGA
2 RV114
DPRSLPVR_VGA
<54>
AK9
AL10
AL9
GC6_EVENT#_R
1
RV49
1
VGA_EDID_CLK
2
10K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
DACA_HSYNC
DACA_VSYNC
DACA_VDD
DACA_VREF
DACA_RSET
VGA_EDID_DATA
AM9
AN9
1
RV4
VGA_CRT_DATA
AG10
AP9
AP8
+DACA_VDD
10K_0402_5%
2 RV107 1
1
RV10
1
RV11
1
RV12
1
RV13
1
RV1
1
RV2
VGA_CRT_CLK
I2CB_SCL
I2CB_SDA
OVERT#
VGA_GPIO12
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
C
VGA_CRT_CLK
VGA_CRT_DATA
R4
R5
I2CB_SCL
I2CB_SDA
R7
R6
VGA_EDID_CLK
VGA_EDID_DATA
R2
R3
VGA_SMB_CK2
VGA_SMB_DA2
T4
T3
+1.05VS_VGA
30 ohms @100MHz (ESR=0.05)
60mA
SP_PLLVDD
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
VID_PLLVDD
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_RST_N
PEX_TERMP
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN
AD8
AE8
AD7
45mA
H3
H2
XTALIN
XTAL_OUT
J4
H1
XTALOUT
XTALSSIN
N13P-GL-A1 MP
LV7
1
2
FBMA-10-100505-300T 0402
+PLLVDD
RV112 1
@
2
0_0402_5%
45mA
+SP_PLLVDD
1
2
1
Near GPU
2
B
Under GPU
RV27
10K_0402_5%
1
2
<54>
@
@
if GC6 is supported, stuff the BOM option to
pull high to 3.3vs system power, if not, stuff
the BOM option to pull high to NV3V3;
RV26
10K_0402_5%
RV22
2.49K_0402_1%
D
R03
2
RV18
100K_0402_5%
<54>
GPU_VID5
VGA_GPIO15 100K_0402_5% 1
VGA_GPIO16
0_0402_5% 1
2
3
UV2
GPU_VID0
RV3
PEX_WAKE_N
AJ12
AP29
QV7A
DMN66D0LDW-7 2N_SOT363-6
<54>
<54>
2
GPU_VID0
VGA_GPIO12
GPU_VID5
1
<18> DGPU_HOLD_RST#
B
QV7B
DMN66D0LDW-7 2N_SOT363-6
5
OVERT#
GC6_EVENT#_R
1
2
PLT_RST#
AL13
AK13
AK12
G
<18,36,37,42,45>
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#
P
1
5
@
RV105
10K_0402_5%
GPU_VID1
GPU_VID2
R03
DPRSLPVR_VGA
<19>
+3VS_VGA
DACA_RED
DACA_GREEN
DACA_BLUE
PLLVDD
AJ11
B
2
CV40
VGA_SMB_CK2
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15
GPU_VID1
GPU_VID2
@
RV113
RV208
10K_0402_5%
CV131
1
1
5
RV25
2.2K_0402_5%
VGA_GPIO3 0_0402_5% 1
<54>
<54>
22U_0805_6.3V6M
2
2
+3VS_VGA
RV24
2.2K_0402_5%
GPU_VID4
GPU_VID3
0.1U_0402_10V7K
+3VS_VGA
GPU_VID4
GPU_VID3
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
1
D
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
2
PCIE_CRX_GTX_P[0..15]
PCH_THRMTRIP#_R
Part 1 of 7
GPIO
PCIE_CRX_GTX_N[0..15]
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
DACs
<5> PCIE_CRX_GTX_P[0..15]
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
I2C
<5> PCIE_CRX_GTX_N[0..15]
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P[0..15]
CLK
<5> PCIE_CTX_GRX_P[0..15]
PCI EXPRESS
<5> PCIE_CTX_GRX_N[0..15]
N13P@
6
U65A
PCIE_CTX_GRX_N[0..15]
N13M@
Under GPU(below 150mils)
U65
1
2
G
RV30
10K_0402_5%
3
CLK_REQ_GPU#
@
2
0_0402_5%
NC
XTAL_OUT
27MHZ 16PF +-30PPM X3G027000FG1H-HX
R02
2
180ohms (ESR=0.2) Bead
2
CV38
15P_0402_50V8J
1
2
2
2
2
A
2
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
2
CV5
3
CV4
OSC
OSC
CV113
NC
1
@ RV32
10K_0402_5%
1
QV2
2N7002H 1N_SOT23-3
1
RV110
1
CV37
15P_0402_50V8J
1
1
S
1
<15> CLK_REQ_VGA#
XTALIN
1
0.1U_0402_10V7K
2
2
D
A
SA00004V050
1
0.1U_0402_10V7K
4
N13M-GE-B-A1
+SP_PLLVDD
2
LV1
BLM18PG330SN1D_0603
4.7U_0402_6.3V6M
YV1
1
R02 CV42
0.1U_0402_10V7K
150mA
1
CV112
+1.05VS_VGA
+3VS_VGA
22U_0805_6.3V6M
<18,25> DGPU_PWR_EN
1
2
RV23 10M_0402_5%
RV29 10K_0402_5%
2
1
4
3
2
Title
N13X-PCIE/DAC/GPIO
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
23
of
60
5
4
3
2
1
U65D
Part 4 of 7
B
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
D
VDD_SENSE
L4
VCCSENSE_VGA
VCCSENSE_VGA
GND_SENSE
L5
VSSSENSE_VGA
VSSSENSE_VGA <54>
<54>
trace width: 16mils
differential voltage sensing.
differential signal routing.
TEST
TESTMODE
AK11
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
AM10
AM11
AP12
AP11
AN11
TESTMODE
1
RV34
TV2
TV3
TV4
TV5
1
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
NC
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
10K_0402_5%
RV33
2
10K_0402_5%
C
2
C
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
LVDS/TMDS
D
AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
H6
H4
H5
H7
GENERAL
RV35
BUFRST_N
L2
CEC
L3
MULTI_STRAP_REF0_GND
J1
AG3
AG2
IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N
AK3
AK2
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
AB3
AB4
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
AF3
AF2
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
ROM_CS
ROM_SCLK
ROM_SI
ROM_SO
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
J2
J7
J6
J5
J3
THERMDP
THERMDN
K3
K4
ROM_SCLK <32>
ROM_SI
<32>
ROM_SO <32>
10K_0402_5%
1
2
1
2
RV230 N13P@ 10K_0402_5%
1
2
RV38 N13P@40.2K_0402_1%
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
+3VS_VGA
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
R02
3V3 on N13P-GL/ for CEC signal
<32>
<32>
<32>
<32>
<32>
B
Reserve 1MB SPI ROM FOR VBIOS ROM
+3VS_VGA
CV295
2
20mils
1
1
N13P@
0.1U_0402_16V4Z
@
ROM_CS
ROM_SO
@
UV15
1
2
3
4
CS#
DO
W P#
GND
@
VCC
HOLD#
CLK
DIO
8
7
6
5
MX25L1005AMC-12G SOP
A
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
5
4
3
2
Title
RV225
10K_0402_5%
2
RV229 @
10K_0402_5%
0_0402_5%
ROM_CS_R
2
ROM_SO_R
2
0_0402_5%
2
@ RV224
@RV224
1
1
@RV226
@
RV226
1
N13P-GL-A1 MP
ROM_HOLD#
@ RV228
ROM_SCLK_R 1
ROM_SI_R
1
@ RV227
0_0402_5%
ROM_SCLK
2
ROM_SI
2
0_0402_5%
A
N13X-LVDS/HDMI/DP/THM
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
24
of
60
3
U65E
FB_VSS_SENSE
+1.5VS_VGA
F2
DDR3
RV6
40.2Ohm
RV8
FB_CAL_x_PU_GND
42.2Ohm
RV9
FB_CAL_xTERM_GND
51.1Ohm
CALIBRATION PIN
FB_CAL_x_PD_VDDQ
F1
1
2
40.2_0402_1%
J27
1
2
42.2_0402_1%
H27
1
2
51.1_0402_1%
H25
CV51
1
2
CV52
D
10U_0603_6.3V6M
CV50
10U_0603_6.3V6M
CV49
10U_0603_6.3V6M
CV48
CV47
10U_0603_6.3V6M
1
2
1
+1.05VS_VGA
1
CV55
CV56
22U_0805_6.3V6M
CV53
4.7U_0603_6.3V6K
CV46
CV45
1U_0402_6.3V6K
CV44
CV43
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
2
2
LV2
N13M@
IFPA_IOVDD
IFPB_IOVDD
0_0603_5%
2
Place near balls
Place near GPU
+VDD33
AH8 +IFPAB_PLLVDD1
RV48 1
AJ8
RV40 2 10K_0402_5%
@
2 1K_0402_1%
AG8 +IFPAB_IOVDD 1
AG9
RV65 2 10K_0402_5%
AF7 +IFPC_PLLVDD 1
RV43 2
AF8
RV42 2 10K_0402_5%
@
1 1K_0402_1%
AF6 +IFPC_IOVDD 1
RV44 2 10K_0402_5%
AG7 +IFPD_PLLVDD 1
RV46 1
AN2
RV45 2 10K_0402_5%
@
2 1K_0402_1%
AG6 +IFPD_IOVDD 1
RV47 2 10K_0402_5%
AB8 +IFPEF_PLLVDD1
AD6
1
RV72 2 10K_0402_5%
RV50 2 1K_0402_1%
AC7
AC8
RV73 2 10K_0402_5%
1
2
1
2
1
2
RV5
2
1
1
1
2
1
2
1
CV66
+3VS_VGA
J8
K8
L8
M8
+1.05VS_VGA
LV2 N13P@
2
1
120mA
+PEX_PLLVDD
CV65
+PEX_PLLVDD
AG26
4.7U_0805_25V6-K
2
1
CV3
2
1
CV73
1
4.7U_0603_6.3V6K
+PEX_SVDD3V3
AG12
1U_0603_10V6K
VDD33_0
VDD33_1
VDD33_2
VDD33_3
RV138 1 N13M@ 2 0_0402_5%
0.1U_0402_10V7K
PEX_PLLVDD
+PEX_PLLHVDD
CV75
PEX_SVDD_3V3
AH12
CV74
PEX_PLL_HVDD
CV70
+3VS_VGA
IFPAB_PLLVDD
IFPAB_RSET
FB_VDDQ_SENSE
2
1
2
C
BLM18PG121SN1D_0603
120ohms @100MHz (ESR=0.18)
2
0_0603_5%
Place near balls
2
FB_VDDQ_SENSE
IFPC_PLLVDD
IFPC_RSET
FB_GND_SENSE
IFPC_IOVDD
Reserve for NV DG
+VDD33
FB_CAL_PD_VDDQ
IFPD_PLLVDD
IFPD_RSET
FB_CAL_PU_GND
IFPD_IOVDD
@
FB_CAL_TERM_GND
IFPEF_PLVDD
IFPEF_RSET
Place near balls
IFPE_IOVDD
IFPF_IOVDD
+IFPE_IOVDD1
1
1
2
2
CV304
0.1U_0402_10V7K
2 RV141 @1
10_0402_5%
@
2 RV142 1
10_0402_5%
2
1
2
CV293
4.7U_0603_6.3V6K
+1.5VS_VGA
1
2
1
CV303
0.1U_0402_10V7K
C
2
1
4.7U_0603_6.3V6K
rise 1.5v system source voltage to 1.55-1.57V
2
0.1U_0402_10V7K
2
2
1
22U_0805_6.3V6M
1
2
1
CV109
0.1U_0402_10V7K
2
CV286
1
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
1
0.1U_0402_10V7K
2
CV285
1
0.1U_0402_10V7K
2
CV284
1
0.1U_0402_10V7K
2
CV294
1
0.1U_0402_10V7K
2
CV287
CV292
1
0.1uF X7R 0402 * 8
0.1U_0402_10V7K
2
CV280
1
0.1U_0402_10V7K
2
CV279
1
0.1U_0402_10V7K
2
CV278
1
0.1U_0402_10V7K
2
CV277
1
0.1U_0402_10V7K
2
1U_0603_6.3V6M
CV268
1
1U_0603_6.3V6M
2
CV267
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1uF X7R 0402 * 2
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
CV54
CV272
1
1
22U_0805_6.3V6M
1
4.7uF X7R 0402 * 2
+1.05VS_VGA
AG19
AG21
AG22
AG24
AH21
AH25
1U_0402_6.3V6K
1
2
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
22U_0805_6.3V6M
1
2
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
POWER
@
2
CV271
10U_0603_6.3V6M
2
2
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
Near GPU
2000mA
Part 5 of 7
3.5A
CV270
10U_0603_6.3V6M
1
CV269
10U_0603_6.3V6M
+1.5VS_VGA
CV273
22U_0805_6.3V6M
D
10U_0603_6.3V6M
Near GPU
1
CV111
+1.5VS_VGA
2
1U_0402_6.3V6K
4
4.7U_0603_6.3V6K
5
@
R02
B
B
+3VS to +3VS_VGA
N13P-GL-A1 MP
+3VS
+3VS_VGA
J10
1
@
N13P@
1
2
2
JUMP_43X79
+5VALW
1
QV5
LP2301ALT1G_SOT23
3
1
1 2
2
D
QV6
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
2
Title
RV207 @
1DGPU_PWR_EN#
10K_0402_5%
S
2N7002_SOT23
A
Issued Date
2
G
@
1
2
0.1U_0402_10V7K
2
RV206
470_0603_5%
@
@ CV242
1
1
2
R1105
100K_0402_5%
1
3
Q128
2N7002_SOT23
CV241
S
2
G
0_0402_5%
RV205
1
2
10K_0402_5%
0.1U_0402_10V7K
2
1
1
@
D
3
<18,23> DGPU_PWR_EN
2
R1103
100K_0402_5%
DGPU_PWR_EN#
R1104
2
1
G
SUSP#
CV57
10U_0603_6.3V6M
D
S
<10,42,46,51,52,53,54>
R1109 @
0_0402_5%
2
1
A
N13X-POWER
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
25
of
60
5
4
3
2
1
U65F
C
B
A
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W 13
W 15
W 17
W 18
W 20
W 22
W 28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W 32
Part 7 of 7
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
U1
U2
U3
U4
U5
U6
U7
U8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
V1
V2
V3
V4
V5
V6
V7
V8
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
W2
W3
W4
W5
W7
W8
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
D
C
B
A
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
4
V17
V18
V20
V22
W 12
W 14
W 16
W 19
W 21
W 23
Y13
Y15
Y17
Y18
Y20
Y22
N13P-GL-A1 MP
Title
3
2
N13-VGA CORE, GND
N13P@
5
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
N13P@
N13P-GL-A1 MP
+VGA_CORE
U65G
+VGA_CORE
POWER
D
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND
Part 6 of 7
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
26
of
60
5
<28,29> FBA_D[0..63]
4
3
FBA_MA[15..0]
FBA_D[0..63]
2
<28,29>
FBC_D[0..63]
<30,31> FBC_D[0..63]
FBA_BA[2..0]
1
FBC_MA[15..0]
<28,29>
FBC_BA[2..0]
<30,31>
<30,31>
U65C
U65B
FBA_CAS# <28,29>
FBA_CS0#_H <29>
FBA_ODT_H
FBA_CKE_H
FBA_MA13
FBA_MA8
FBA_MA6
FBA_MA11
FBA_MA5
FBA_MA3
FBA_BA2
FBA_BA1
FBA_MA12
FBA_MA10
FBA_RAS#
FBA_ODT_H <29>
FBA_CKE_H <29>
FBA_RAS# <28,29>
R32
AC32
R28
AC28
+1.5VS_VGA
RV58
RV59
@
@
1
1
2 60.4_0402_1%
2 60.4_0402_1%
can be unstuff by default
R30
R31
AB31
AC31
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
<28>
<28>
<29>
<29>
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
+FB_PLLAVDD
Place close to BGA
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
FB_CLAMP
FB_DLL_AVDD
200mA
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
E1
K27
BLM18PG330SN1D_0603
1
2 +FB_PLLAVDD
LV3
FB_CLAMP
CV106
1
R02
RV66 N13M@ 10K_0402_5%
2
1
+FB_PLLAVDD
0.1U_0402_10V7K
2
Place close to ball
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FB_VREF
U27
H26
1
2
Place close to ball
1
2
+FB_PLLAVDD
1
2
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
E11
E3
A3
C9
F23
F27
C30
A24
FBC_DQS0
FBC_DQS1
FBC_DQS2
FBC_DQS3
FBC_DQS4
FBC_DQS5
FBC_DQS6
FBC_DQS7
D10
D5
C3
B9
E23
E28
B30
A23
FBC_DQS#0
FBC_DQS#1
FBC_DQS#2
FBC_DQS#3
FBC_DQS#4
FBC_DQS#5
FBC_DQS#6
FBC_DQS#7
D9
E4
B2
A9
D22
D28
A30
B23
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
A
<28,29> FBA_DQM[7..0]
<28,29> FBA_DQS[7..0]
<28,29> FBA_DQS#[7..0]
FBC_CS0#_L
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
FBC_CS0#_L
FBC_ODT_L
FBC_CKE_L
FBC_MA14
FBC_RST#
FBC_MA9
FBC_MA7
FBC_MA2
FBC_MA0
FBC_MA4
FBC_MA1
FBC_BA0
FBC_WE#
FBC_MA15
FBC_CAS#
FBC_CS0#_H
FBC_RST# <30,31>
D
FBC_WE# <30,31>
FBC_CAS# <30,31>
FBC_CS0#_H <31>
FBC_ODT_H
FBC_CKE_H
<31>
<31>
Mode D - Mirror Mode Mapping
DATA Bus
FBC_RAS#
<30,31>
Address
32..63
0..31
FBx_CMD0
CS0#_L
FBx_CMD1
FBB_CMD_RFU0
FBB_CMD_RFU1
C12
C20
+1.5VS_VGA
FBB_DEBUG0
FBB_DEBUG1
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
FBB_PLL_AVDD
RV60 1
RV61 1
G14
G20
@
@
2 60.4_0402_1%
2 60.4_0402_1%
can be unstuff by default
FBC_CLK0
FBC_CLK0#
FBC_CLK1
FBC_CLK1#
D12
E12
E20
F20
FBC_CLK0 <30>
FBC_CLK0# <30>
FBC_CLK1 <31>
FBC_CLK1# <31>
F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27
FBx_CMD2
ODT_L
FBx_CMD3
CKE_L
FBx_CMD4
A14
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE#
WE#
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
C
CAS#
FBx_CMD16
CS0#_H
FBx_CMD17
FBx_CMD18
ODT_H
FBx_CMD19
H17
+FB_PLLAVDD
1
2
Place close to ball
B
CKE_H
FBx_CMD20
A13
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
Place close to BGA
N13P@
N13P@
30ohms (ESR=0.01) Bead
P/N;SM010007W00
<30,31> FBC_DQM[7..0]
<30,31> FBC_DQS[7..0]
<30,31> FBC_DQS#[7..0]
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
<30>
FBC_ODT_L <30>
FBC_CKE_L <30>
FBC_ODT_H
FBC_CKE_H
FBC_MA13
FBC_MA8
FBC_MA6
FBC_MA11
FBC_MA5
FBC_MA3
FBC_BA2
FBC_BA1
FBC_MA12
FBC_MA10
FBC_RAS#
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
N13P-GL-A1 MP
N13P-GL-A1 MP
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
CV108
FBA_WE# <28,29>
+1.05VS_VGA
FBA_PLL_AVDD
FBA_DQS#0
M30
FBA_DQS#1
H30
FBA_DQS#2
E34
FBA_DQS#3
M34
FBA_DQS#4 AF30
FBA_DQS#5 AK31
FBA_DQS#6 AM34
FBA_DQS#7 AF32
FBA_RST# <28,29>
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
0.1U_0402_10V7K
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_ODT_L <28>
FBA_CKE_L <28>
CV39
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_ODT_L
FBA_CKE_L
FBA_MA14
FBA_RST#
FBA_MA9
FBA_MA7
FBA_MA2
FBA_MA0
FBA_MA4
FBA_MA1
FBA_BA0
FBA_WE#
FBA_MA15
FBA_CAS#
FBA_CS0#_H
CV110
M31
G31
E33
M33
AE31
AK30
AN33
AF33
FBA_DEBUG0
FBA_DEBUG1
FBA_CS0#_L <28>
22U_0805_6.3V6M
FBA_DQS0
FBA_DQS1
FBA_DQS2
FBA_DQS3
FBA_DQS4
FBA_DQS5
FBA_DQS6
FBA_DQS7
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_CMD_RFU0
FBA_CMD_RFU1
FBA_CS0#_L
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
CV107
P30
F31
F34
M32
AD31
AL29
AM32
AF34
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
1U_0402_6.3V6K
B
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
0.1U_0402_10V7K
C
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
MEMORY INTERFACE
A
D
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
MEMORY INTERFACE B
Part 3 of 7
Part 2 of 7
4
3
2
Title
N13X-MEM Interface
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
27
of
60
5
4
3
2
1
FBA_D[0..63]
Memory Partition A - Lower 32 bits
<27,29>
FBA_MA[15..0] <27,29>
FBA_BA[2..0] <27,29>
UV3
+1.5VS_VGA
+FBA_VREF0
1
D
FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15
RV79
2
1.1K_0402_1%
RV68
2
1.1K_0402_1%
1
CV118
0.01U_0402_25V7K
1
+FBA_VREF0
2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
FBA_BA0
FBA_BA1
FBA_BA2
M2
N8
M3
BA0
BA1
BA2
RV80
160_0402_1%
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
J7
K7
K9
CK
CK
CKE/CKE0
FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D4
FBA_D1
FBA_D7
FBA_D0
FBA_D6
FBA_D3
FBA_D5
FBA_D2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D29
FBA_D25
FBA_D28
FBA_D26
FBA_D31
FBA_D24
FBA_D30
FBA_D27
+FBA_VREF0
M8
H1
FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15
Group0 (IN3)
Group3 (BOT)
FBA_DQM[7..0] <27,29>
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D19
FBA_D20
FBA_D17
FBA_D21
FBA_D16
FBA_D23
FBA_D18
FBA_D22
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D10
FBA_D15
FBA_D8
FBA_D13
FBA_D9
FBA_D12
FBA_D11
FBA_D14
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
FBA_BA0
FBA_BA1
FBA_BA2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#
FBA_DQS2
FBA_DQS1
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBA_DQM2
FBA_DQM1
E7
D3
DML
DMU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
M2
N8
M3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
FBA_CLK0
J7
FBA_CLK0# K7
FBA_CKE_L K9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
CK
CK
CKE/CKE0
FBx_CMD2
F3
C7
DQSL
DQSU
FBA_DQM0
FBA_DQM3
E7
D3
DML
DMU
FBA_DQS#0 G3
FBA_DQS#3 B7
FBA_RST#
<27,29> FBA_RST#
T2
DQSL
DQSU
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
ODT/ODT0
CS/CS0
RAS
CAS
WE
FBA_DQS#2 G3
FBA_DQS#1 B7
FBA_RST#
DQSL
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
FBA_ODT_L
FBA_CKE_L
2
FBA_DQS0
FBA_DQS3
K1
L2
J3
K3
L3
RV67
10K_0402_5%
RV76
10K_0402_5%
2
RV69
243_0402_1%
96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
X76@
2
2011/06/15
Deciphered Date
2012/07/11
5
4
3
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE#
WE#
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
C
CAS#
CS0#_H
ODT_H
2
1
2
2
Title
1
CKE_H
FBx_CMD20
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
A13
B
CV158
1
@ CV144
1U_0402_6.3V6K
2
1
@ CV143
1U_0402_6.3V6K
1
CV142
1U_0402_6.3V6K
2
@ CV138
1U_0402_6.3V6K
1
@ CV155
0.1U_0402_10V7K
2
0.1U_0402_10V7K
CV135
CV137
1
@ CV157
2
1U_0402_6.3V6K
2
1
Compal Secret Data
Issued Date
1
1U_0402_6.3V6K
2
CV163
1
1U_0402_6.3V6K
2
@ CV136
CV132
CV164
2
1
1U_0402_6.3V6K
2
1
A14
FBx_CMD5
FBx_CMD19
UV4 SIDE
0.1U_0402_10V7K
2
1
0.1U_0402_10V7K
2
1
CV133
1U_0402_6.3V6K
2
1
CV160
1U_0402_6.3V6K
2
1
CV129
1U_0402_6.3V6K
2
1
CV134
1U_0402_6.3V6K
1
CV159
0.1U_0402_10V7K
2
0.1U_0402_10V7K
1
@ CV161
2
CV162
1
1U_0402_6.3V6K
2
CV123
1
1U_0402_6.3V6K
2
CV121
1
1U_0402_6.3V6K
2
CV120
1
1U_0402_6.3V6K
2
CV119
1
+1.5VS_VGA
A14
FBx_CMD18
96-BALL
SDRAM DDR3
X76@
UV3 SIDE
0.1U_0402_10V7K
A
0.1U_0402_10V7K
+1.5VS_VGA
CKE_L
FBx_CMD4
FBx_CMD17
1
1
2
2
1
RV77
243_0402_1%
ODT_L
FBx_CMD3
FBx_CMD16
B
RV78
10K_0402_5%
32..63
CS0#_L
FBx_CMD1
1
FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#
0..31
FBx_CMD0
Group1 (TOP)
2
<27>
<27>
<27,29>
<27,29>
<27,29>
<27,29>
DATA Bus
Address
1
FBA_CLK0#
<27,29>
CMD mapping mod Mode D
+1.5VS_VGA
BA0
BA1
BA2
FBA_DQS[7..0]
FBA_DQS#[7..0]
D
Group2 (IN1)
1
C
<27> FBA_CLK0
<27> FBA_CLK0#
<27> FBA_CKE_L
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
+1.5VS_VGA
2
FBA_CLK0
M8
H1
UV4
2
A
N13X-VRAM A Lower
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
28
of
60
5
4
3
2
1
Memory Partition A - Upper 32
bits
UV5
+1.5VS_VGA
1
+FBA_VREF1
FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15
RV70
D
2
1.1K_0402_1%
RV82
2
1
CV178
0.01U_0402_25V7K
1
+FBA_VREF1
1.1K_0402_1%
FBA_D[0..63]
2
FBA_BA0
FBA_BA1
FBA_BA2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D36
FBA_D34
FBA_D37
FBA_D35
FBA_D39
FBA_D32
FBA_D38
FBA_D33
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D45
FBA_D42
FBA_D46
FBA_D41
FBA_D47
FBA_D43
FBA_D44
FBA_D40
RV83
160_0402_1%
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
Group4 (IN1)
Group5 (TOP)
M8
H1
VREFCA
VREFDQ
FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14
FBA_MA15
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
FBA_BA0
FBA_BA1
FBA_BA2
M2
N8
M3
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#
FBA_DQS7
FBA_DQS6
F3
C7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBA_DQM7
FBA_DQM6
E7
D3
BA0
BA1
BA2
CK
CK
CKE/CKE0
FBA_CLK1
J7
FBA_CLK1# K7
FBA_CKE_H K9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D63
FBA_D58
FBA_D60
FBA_D59
FBA_D61
FBA_D56
FBA_D62
FBA_D57
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D55
FBA_D51
FBA_D54
FBA_D49
FBA_D52
FBA_D50
FBA_D53
FBA_D48
FBA_BA[2..0] <27,28>
Group7 (IN3)
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
FBA_DQS4
FBA_DQS5
F3
C7
FBA_DQM4
FBA_DQM5
E7
D3
FBA_DQS#4 G3
FBA_DQS#5 B7
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
FBA_CKE_H
RESET
L8
ZQ/ZQ0
FBA_RST#
RESET
L8
ZQ/ZQ0
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
RV85
243_0402_1%
B1
B9
D1
D8
E2
E8
F9
G1
G9
2
1
2
1
2
1
2
1
2
1
2
1
2
@ CV175
1
FBx_CMD2
ODT_L
FBx_CMD3
CKE_L
FBx_CMD4
A14
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE#
WE#
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
C
CAS#
CS0#_H
ODT_H
FBx_CMD19
@ CV168
1U_0402_6.3V6K
2
@ CV179
1
1U_0402_6.3V6K
2
CV172
1
1U_0402_6.3V6K
2
CV166
1
1U_0402_6.3V6K
2
@ CV170
CV165
CV302
CV291
CV301
CV177
2
1
1U_0402_6.3V6K
2
1
32..63
CS0#_L
FBx_CMD18
UV6 SIDE
0.1U_0402_10V7K
2
1
0.1U_0402_10V7K
2
1
CV298
1U_0402_6.3V6K
2
1
CV297
1U_0402_6.3V6K
2
1
CV300
1U_0402_6.3V6K
2
1
CV290
1U_0402_6.3V6K
2
1
CV299
0.1U_0402_10V7K
2
1
0.1U_0402_10V7K
2
1
1U_0402_6.3V6K
2
1
1U_0402_6.3V6K
CV296
CV174
CV145
1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
0..31
FBx_CMD17
96-BALL
SDRAM DDR3
X76@
+1.5VS_VGA
1U_0402_6.3V6K
2
1U_0402_6.3V6K
2
1
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
Address
FBx_CMD1
CV171
1U_0402_6.3V6K
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
<27,28>
FBx_CMD16
CV167
1U_0402_6.3V6K
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
UV5 SIDE
0.1U_0402_10V7K
0.1U_0402_10V7K
1
DQSL
DQSU
T2
96-BALL
SDRAM DDR3
X76@
+1.5VS_VGA
DML
DMU
@ CV180
1U_0402_6.3V6K
J1
L1
J9
L9
2
RV86
243_0402_1%
DQSL
DQSU
<27,28>
FBA_DQS#[7..0]
D
FBx_CMD0
1
T2
ODT/ODT0
CS/CS0
RAS
CAS
WE
FBA_DQS#7 G3
FBA_DQS#6 B7
1
1
RV87
10K_0402_5%
2
1
RV84
10K_0402_5%
2
B
FBA_RST#
<27,28> FBA_RST#
FBA_ODT_H
K1
L2
J3
K3
L3
@ CV169
0.1U_0402_10V7K
FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#
FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#
0.1U_0402_10V7K
<27>
<27>
<27,28>
<27,28>
<27,28>
@ CV173
FBA_CLK1#
2
C
<27,28>
FBA_DQS[7..0]
DATA Bus
Group6 (BOT)
+1.5VS_VGA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
FBA_DQM[7..0]
1
<27> FBA_CLK1
<27> FBA_CLK1#
<27> FBA_CKE_H
J7
K7
K9
+FBA_VREF1
+1.5VS_VGA
2
FBA_CLK1
VREFCA
VREFDQ
M2
N8
M3
FBA_MA[15..0] <27,28>
UV6
M8
H1
<27,28>
CKE_H
FBx_CMD20
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
A13
B
A
A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
4
3
2
Title
N13X-VRAM A Upper
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
1
29
of
60
5
4
3
2
1
FBC_D[0..63]
Memory Partition C - Lower 32 bits
<27,31>
FBC_MA[15..0] <27,31>
FBC_BA[2..0]
UV7
+FBB_VREF0
1
D
M8
H1
VREFCA
VREFDQ
FBC_MA0
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
FBC_BA0
FBC_BA1
FBC_BA2
M2
N8
M3
RV111
2
1.1K_0402_1%
RV115
2
1.1K_0402_1%
1
CV202
0.01U_0402_25V7K
1
+FBB_VREF0
2
RV89
160_0402_1%
FBC_CLK0
FBC_CLK0#
FBC_CKE_L
<27> FBC_CLK0
<27> FBC_CLK0#
<27> FBC_CKE_L
J7
K7
K9
E3
F7
F2
F8
H3
H8
G2
H7
FBC_D4
FBC_D3
FBC_D7
FBC_D0
FBC_D5
FBC_D1
FBC_D6
FBC_D2
+FBB_VREF0
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBC_D28
FBC_D27
FBC_D31
FBC_D25
FBC_D29
FBC_D24
FBC_D30
FBC_D26
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBC_ODT_L
FBC_CS0#_L
FBC_RAS#
FBC_CAS#
FBC_WE#
FBC_DQS2
FBC_DQS1
F3
C7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBC_DQM2
FBC_DQM1
E7
D3
Group0 (IN3)FBC_MA0
Group3
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
(BOT)FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15
+1.5VS_VGA
310mA
CK
CK
CKE/CKE0
FBC_BA0
FBC_BA1
FBC_BA2
M8
H1
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
FBC_CLK0
J7
FBC_CLK0# K7
FBC_CKE_L K9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBC_D16
FBC_D21
FBC_D18
FBC_D17
FBC_D20
FBC_D23
FBC_D19
FBC_D22
FBC_CLK0#
<27>
<27>
<27,31>
<27,31>
<27,31>
FBC_ODT_L
FBC_CS0#_L
FBC_RAS#
FBC_CAS#
FBC_WE#
FBC_ODT_L
FBC_CS0#_L
FBC_RAS#
FBC_CAS#
FBC_WE#
K1
L2
J3
K3
L3
FBC_DQS0
FBC_DQS3
F3
C7
FBC_DQM0
FBC_DQM3
E7
D3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBC_D8
FBC_D15
FBC_D11
FBC_D12
FBC_D9
FBC_D13
FBC_D10
FBC_D14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
Group2 (IN1)
FBC_RST#
<27,31> FBC_RST#
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DATA Bus
Address
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
FBC_ODT_L
RESET
L8
ZQ/ZQ0
FBC_RST#
DQSL
DQSU
T2
RESET
L8
ZQ/ZQ0
1
1
RV117
10K_0402_5%
RV116
10K_0402_5%
J1
L1
J9
L9
96-BALL
SDRAM DDR3
X76@
B1
B9
D1
D8
E2
E8
F9
G1
G9
2011/06/15
Deciphered Date
2012/07/11
5
4
2
1
2
CV204
1U_0402_6.3V6K
2
1
CV201
1U_0402_6.3V6K
2
1
CV200
1U_0402_6.3V6K
2
1
CV198
1U_0402_6.3V6K
1
CV187
0.1U_0402_10V7K
CV197
CV184
CV186
2
0.1U_0402_10V7K
2
1
Compal Secret Data
Issued Date
2
1
1U_0402_6.3V6K
2
1
1U_0402_6.3V6K
2
1
CV195
CV203
1
1U_0402_6.3V6K
2
CV192
1
A14
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE#
WE#
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
C
CAS#
CS0#_H
ODT_H
CKE_H
FBx_CMD20
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
A13
B
UV8 SIDE
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
1
@ CV194
2
1
@ CV185
1U_0402_6.3V6K
2
1
CV182
1U_0402_6.3V6K
2
1
@ CV181
1U_0402_6.3V6K
2
1
CV206
1U_0402_6.3V6K
CV205
CV189
1
@ CV190
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
1
@ CV188
2
1
1U_0402_6.3V6K
2
1
1U_0402_6.3V6K
CV199
1
1U_0402_6.3V6K
2
1U_0402_6.3V6K
1
@ CV183
2
@ CV191
1
+1.5VS_VGA
A14
FBx_CMD5
FBx_CMD19
96-BALL
SDRAM DDR3
X76@
UV7 SIDE
0.1U_0402_10V7K
A
0.1U_0402_10V7K
+1.5VS_VGA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
RV88
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
1U_0402_6.3V6K
2
2
RV90
243_0402_1%
B1
B9
D1
D8
E2
E8
F9
G1
G9
CKE_L
FBx_CMD4
FBx_CMD18
1
1
1
RV91
10K_0402_5%
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
ODT_L
FBx_CMD3
FBx_CMD17
B
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
FBx_CMD2
FBx_CMD16
2
DQSL
DQSU
FBC_DQS#2 G3
FBC_DQS#1 B7
DML
DMU
32..63
CS0#_L
FBx_CMD1
Group1 (TOP)
+1.5VS_VGA
BA0
BA1
BA2
0..31
FBx_CMD0
2
DML
DMU
T2
J1
L1
J9
L9
<27,31>
FBC_CKE_L
FBC_DQS#0 G3
FBC_DQS#3 B7
<27,31>
FBC_DQS#[7..0]
D
1
C
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
BA0
BA1
BA2
2
FBC_CLK0
<27,31>
FBC_DQS[7..0]
UV8
3
2
Title
1
CV193
+1.5VS_VGA
<27,31>
FBC_DQM[7..0]
2
A
N13X-VRAM C Lower
Custom
Date:
Rev
0.2
LA-7981P
Sheet
1
30
of
60
5
4
3
2
1
Memory Partition C - Upper 32 bits
FBC_D[0..63]
<27,30>
FBC_MA[15..0] <27,30>
UV9
FBC_MA0
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15
FBC_BA0
FBC_BA1
FBC_BA2
FBC_ODT_H
FBC_CS0#_H
FBC_RAS#
FBC_CAS#
FBC_WE#
DQSL
DQSU
FBC_DQM4
FBC_DQM5
E7
D3
DML
DMU
FBC_RST#
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBC_DQS7
FBC_DQS6
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBC_DQM7
FBC_DQM6
E7
D3
DML
DMU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
K1
L2
J3
K3
L3
FBC_DQS#7 G3
FBC_DQS#6 B7
FBC_RST#
RV123
243_0402_1%
2
RV128
243_0402_1%
DQSL
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
D7
C3
C8
C2
A7
A2
B8
A3
FBC_D54
FBC_D51
FBC_D55
FBC_D49
FBC_D52
FBC_D50
FBC_D53
FBC_D48
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
2
CV212
1U_0402_6.3V6K
CV223
CV210
@ CV222
2
1
1
2
1
2
2011/06/15
Deciphered Date
4
3
32..63
CS0#_L
FBx_CMD1
FBx_CMD2
ODT_L
FBx_CMD3
CKE_L
FBx_CMD4
A14
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE#
WE#
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
FBx_CMD16
C
CAS#
CS0#_H
FBx_CMD17
FBx_CMD18
ODT_H
FBx_CMD19
1
2
1
2
2012/07/11
5
0..31
FBx_CMD0
Group6 (BOT)
1
2
1
2
Compal Secret Data
Issued Date
1
1U_0402_6.3V6K
2
@ CV211
2
1
1U_0402_6.3V6K
2
1
1U_0402_6.3V6K
2
1
@ CV208
2
1
<27,30>
DATA Bus
Address
+1.5VS_VGA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
<27,30>
FBC_DQS#[7..0]
UV10 SIDE
0.1U_0402_10V7K
2
1
CV225
1U_0402_6.3V6K
2
1
@ CV228
1U_0402_6.3V6K
2
1
CV221
1U_0402_6.3V6K
2
1
CV220
1U_0402_6.3V6K
1
@ CV230
0.1U_0402_10V7K
2
CV207
1
0.1U_0402_10V7K
2
CV226
1
1U_0402_6.3V6K
2
CV233
1
1U_0402_6.3V6K
2
1U_0402_6.3V6K
1
0.1U_0402_10V7K
+1.5VS_VGA
CV213
CV209
@ CV227
2
1U_0402_6.3V6K
2
1
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
<27,30>
FBC_DQS[7..0]
D
Group7 (IN3)
96-BALL
SDRAM DDR3
X76@
UV9 SIDE
0.1U_0402_10V7K
0.1U_0402_10V7K
A
1
CK
CK
CKE/CKE0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
96-BALL
SDRAM DDR3
X76@
+1.5VS_VGA
BA0
BA1
BA2
FBC_ODT_H
FBC_CS0#_H
FBC_RAS#
FBC_CAS#
FBC_WE#
DQSL
DQSU
T2
M2
N8
M3
FBC_CLK1
J7
FBC_CLK1# K7
FBC_CKE_H K9
1
1
2
RV119
10K_0402_5%
2
RV118
10K_0402_5%
1
<27,30> FBC_RST#
ODT/ODT0
CS/CS0
RAS
CAS
WE
FBC_BA0
FBC_BA1
FBC_BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
1
FBC_CKE_H
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
F3
C7
Group5 (TOP)
+1.5VS_VGA
BA0
BA1
BA2
FBC_DQS4
FBC_DQS5
FBC_DQS#4 G3
FBC_DQS#5 B7
FBC_ODT_H
B
K1
L2
J3
K3
L3
FBC_D47
FBC_D43
FBC_D46
FBC_D42
FBC_D40
FBC_D45
FBC_D44
FBC_D41
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<27,30>
FBC_DQM[7..0]
2
Title
1
CKE_H
FBx_CMD20
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
A13
B
CV232
<27>
<27>
<27,30>
<27,30>
<27,30>
FBC_CLK1#
FBC_ODT_H
FBC_CS0#_H
FBC_RAS#
FBC_CAS#
FBC_WE#
J7
K7
K9
D7
C3
C8
C2
A7
A2
B8
A3
Group4 (IN1)
VREFCA
VREFDQ
CV218
1U_0402_6.3V6K
1
C
FBC_CLK1
FBC_CLK1#
FBC_CKE_H
<27> FBC_CLK1
<27> FBC_CLK1#
<27> FBC_CKE_H
RV129
160_0402_1%
M2
N8
M3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
FBC_MA0
FBC_MA1
FBC_MA2
FBC_MA3
FBC_MA4
FBC_MA5
FBC_MA6
FBC_MA7
FBC_MA8
FBC_MA9
FBC_MA10
FBC_MA11
FBC_MA12
FBC_MA13
FBC_MA14
FBC_MA15
M8
H1
CV217
1U_0402_6.3V6K
2
FBC_CLK1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
CV215
1U_0402_6.3V6K
2
2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
CV214
1U_0402_6.3V6K
RV127
1.1K_0402_1%
CV229
0.01U_0402_25V7K
1
+FBB_VREF1
1
VREFCA
VREFDQ
FBC_D60
FBC_D57
FBC_D63
FBC_D58
FBC_D61
FBC_D56
FBC_D62
FBC_D59
CV224
0.1U_0402_10V7K
2
1.1K_0402_1%
M8
H1
+FBB_VREF1
0.1U_0402_10V7K
RV120
FBC_BA[2..0]
UV10
FBC_D39
FBC_D33
FBC_D38
FBC_D32
FBC_D36
FBC_D35
FBC_D37
FBC_D34
@ CV231
1
D
+FBB_VREF1
2
+1.5VS_VGA
2
A
N13X-VRAM C Upper
Custom
Date:
Rev
0.2
LA-7981P
Sheet
1
31
of
60
5
4
3
2
2
RV122 X76@
20K_0402_1%
RV95 X76@
45.3K_0402_1%
RV96 X76@
45.3K_0402_1%
+3VS_VGA
PCI_DEVID[4]
SLOT_CLK_CFG
PEX_PLL_EN_TERM
+3VS_VGA
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
ROM_SO
+3VS_VGA
FB[1]
FB[0]
SMB_ALT_ADDR
VGA_DEVICE
STRAP0
+3VS_VGA
USER[3]
USER[2]
USER[1]
USER[0]
STRAP1
+3VS_VGA
STRAP2
+3VS_VGA
PCI_DEVID[3]
PCI_DEVID[2]
PCI_DEVID[1]
PCI_DEVID[0]
STRAP3
+3VS_VGA
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
STRAP4
+3VS_VGA
PCIE_SPEED_
CHANGE_GEN3
PCIE_MAX_SPEED
DP_PLL_VDD33V
RV124 X76@
4.99K_0402_1%
RV125 X76@
10K_0402_1%
10K
1001
0001
15K
1010
0010
20K
1011
0011
25K
1100
0100
30K
1101
0101
35K
1110
0110
45K
1111
0111
5K
ZZZ
RV96 X76@
Samsung
34.8K_0402_1%
SD034348280
2
2
2
3GIO_PAD_CFG_ADR[0]
D
S1GM@
X7634138L05
ZZZ
ZZZ
RV100 X76@
4.99K_0402_1%
0000
Hynix
H2GP@
X7634138L02
H1GM@
X7634138L06
ZZZ
ZZZ
C
1
ROM_SI
ROM_SO
ROM_SCLK
Samsung
2
1
1
RV102
30K_0402_1%
X76@
RV103 X76@
15K_0402_1%
S1GP@
X7634138L03
S512M@
X7634138L07
ZZZ
ZZZ
Hynix
4.99K_0402_1%
Frenq.
N13P-GL
900 MHz
N13P-GL
900 MHz
N13P-GL
900 MHz
N13P-GL
900 MHz
Memory Size
Memory Config
128M* 16* 8
2GB
128M* 16* 8
2GB
64M* 16* 8
1GB
64M* 16* 8
1GB
Samsung (2Gb)
K4W2G1646C-HC11
Hynix (2Gb)
H5TQ1G63DFR-11C
Samsung (1Gb)
K4W1G1646G-BC11
Hynix (1Gb)
H5TQ1G63DFR-11C
H1GP@
X7634138L04
Hynix
H512M@
X7634138L08
X76
For N13P-GL strap table
GPU
SUB_VENDOR
3GIO_PADCFG
XCLK_417
0
No VBIOS ROM
3GIO_PADCFG[3:0]
0
277MHz (Default)
1
BIOS ROM is present (Default)
1
Reserved
0110
Notebook Default
RV103 X76@
SD034499180
B
Samsung
FB_0_BAR_SIZE
SLOT_CLK_CFG
0
Reserved
0
GPU and MCH don't share a common reference clock
1
Reserved
1
GPU and MCH share a common reference clock (Default)
2
256MB (Default)
SMBUS_ALT_ADDR
VGA_DEVICE
3
Reserved
0
0x9E (Default)
0
3D Device (Class Code 302h)
1
0x9C (Multi-GPU usage)
1
VGA Device (Default)
1
RV101
20K_0402_1%
X76@
X76
2
2
<24>
ROM_SI
<24>
ROM_SO
<24> ROM_SCLK
1
1
RV99 X76@
30K_0402_1%
Samsung
S2GP@
X7634138L01
Hynix
RV98
4.99K_0402_1%
X76@
RESERVED
Pull-down to Gnd
1
1
1
1
1
ZZZ
C
3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]
Pull-up to
+3VS_VGA
1000
Resistor Values
+3VS_VGA
Logical
Strapping Bit0
ROM_SI
Power Rail
2
2
R02
RV97 X76@
10K_0402_1%
1
Logical
Strapping Bit3
Logical
Strapping Bit1
Logical
Strapping Bit2
SUB_VENDOR
1
1
RV121 X76@
20K_0402_1%
2
Physical
Strapping pin
ROM_SCLK
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
2
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
2
<24>
<24>
<24>
<24>
<24>
2
D
RV93 X76@
45.3K_0402_1%
1
1
RV92 X76@
45.3K_0402_1%
R02
RV94 X76@
10K_0402_1%
1
2
2
2
+3VS_VGA
strap0
strap1
strap2
R
PU 45K
R
PU 45K
R
PU 45K
R
PU 45K
R
PD 45K
R
PD 45K
R
PD 45K
R
PD 45K
R
PU 10K
R
PU 10K
R
PU 10K
R
PU 10K
strap3
strap4
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
ROM_SI
ROM_SO
R
PD 45K
R
PD 35K
R
PD 20K
R
PD 15K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
ROM_SCLK
R
PD 15K
R
PD 15K
R
PD 15K
R
PD 15K
USER Straps
B
User[3:0]
1000-1100
Customer defined
PEX_PLL_EN_TERM
For N13M-GE strap table
GPU
Frenq.
N13M-GE
900 MHz
N13M-GE
900 MHz
N13M-GE
900 MHz
N13M-GE
900 MHz
Memory Size
Memory Config
128M* 16* 4
1GB
128M* 16* 4
1GB
64M* 16* 4
512MB
64M* 16* 4
512MB
Samsung (2Gb)
K4W2G1646C-HC11
Hynix (2Gb)
H5TQ1G63DFR-11C
Samsung (1Gb)
K4W1G1646G-BC11
Hynix (1Gb)
H5TQ1G63DFR-11C
strap0
strap1
strap2
strap3
strap4
ROM_SI
ROM_SO
R
PU 10K
R
PD 10K
R
PU 10K
R
PD 10K
R
PD 10K
R
PU 10K
R
PU 10K
R
PD 10K
R
PU 10K
R
PU 10K
R
PD 10K
R
PU 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
0
Disable (Default)
1
Enable
ROM_SCLK
PCIE_MAX_SPEED
R
PD 10K
R
PD 10K
R
PD 10K
R
PD 10K
0
Limit to PCIE Gen1
1
PCIE Gen 2/3 Capable
A
A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
4
3
2
Title
N13X_MISC
Custom
Date:
Rev
0.2
LA-7981P
Sheet
1
32
of
60
5
4
3
2
1
LCD POWER CIRCUIT
+LCDVDD
CMOS Camera
+3VS
+5VALW
+3VS
W=60mils
D
1
R401
100K_0402_5%
CMOS@
Q83
PMV65XP_SOT23-3~D
C513
4.7U_0805_10V4Z
+3VALW
1
OUT
3
1
GND
IN
3
1
2
1
3
2
<17> PCH_ENVDD
1
1
Q80
PMV65XP_SOT23-3~D
2
R435CMOS@
150K_0402_5%
W=60mils
D
C515
0.1U_0402_16V4Z
G
Q79
2N7002_SOT23 S
S
2
G
2
+LCDVDD
L29
+LCDVDD_CONN
1
Q81 DTC124EK
DTC124EKAT146_SC59-3
1
2
2
FBMA-L11-201209-221LMA30T_0805
C516
@ R408
100K_0402_5%
2
4.7U_0805_10V4Z
1
1
2
2
C542 @
0.1U_0402_16V4Z
D
10U
1
2
C519 @
10U_0603_6.3V6M
4.7V
<42> CMOS_ON#
2
1
G
R403
220K_0402_5%
1
2
3
+3VS_CMOS
CMOS@ (20 MIL)
2
1
R296
1
CMOS@
0_0603_5%
C518
0.1U_0402_16V4Z R02
2
D
D
S
2
2
1
(20 MIL)
R400
150_0603_1%
R296 for CMOS shake issue reserve
C520 CMOS@
0.1U_0402_16V4Z
C517
0.1U_0402_16V4Z
VGA LCD/PANEL BD. Conn.
C
C
+LEDVDD
B+
C539
680P_0402_50V7K
@
+3VS
1
1
2
2
1 R813
2
0_0805_5%
C541
4.7U_0805_25V6-K
JLVDS1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
@
2 R717
R433
0_0402_5%
BKOFF#
1
<42>
1
DISPOFF#
DISPOFF#
2
D4 @
R716
10K_0402_5%
<17> PCH_PWM
R430 1
<42> EC_INVT_PWM
R431 1
INVT_PWM
2 0_0402_5%
@
<17> LVDS_ACLK
<17> LVDS_ACLK#
2 0_0402_5%
<17> LVDS_A2
<17> LVDS_A2#
<17> LVDS_A1
<17> LVDS_A1#
<17> LVDS_A0
<17> LVDS_A0#
<17> EDID_DATA
<17> EDID_CLK
2
B
4.7K_0402_5%
2
BKOFF#
@
1
<17> PCH_ENBKL
2 @
ENBKL
<42>
0_0402_5%
+3VS
1
2
R538
R02
680P_0402_50V7K
C540@
1
R438
100K_0402_1%
CMOS
+LCDVDD_CONN
(60 MIL)
+3VS
2
<18>
<18>
+3VS_CMOS
USB20_P5
USB20_N5
USB20_P5
USB20_N5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
G1
G2
G3
G4
B
ACES_88341-3001 ME@
A
A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
LVDS/CAMERA
5
4
3
Custom
Date:
2
Rev
0.2
LA-7981P
Sheet
1
33
of
60
A
B
C
+5VS
+5VS
3
D
3
3
BLUE
1
GREEN
1
2
E
+5VS
RED
1
2
2
@
D5
BAT54S-7-F_SOT23-3
@
D6
BAT54S-7-F_SOT23-3
@
D7
BAT54S-7-F_SOT23-3
1
1
CRT Connector
+CRT_VCC
+5VS
D10
F1
2
1
1
+CRT_VCC_F
2
1
RB491D_SC59-3
2
1
2
JCRT1
1
PAD
T66
2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
NC11
RED
CRT_DDC_DAT_CONN
GREEN
CLOSE TO CONN
JVGA_HS
BLUE
JVGA_VS
2
+CRT_VCC
CRT_DDC_CLK_CONN
R448
1
2
C528
1
100P_0402_50V8J
1
G
A
2
Y
FCM1608CF-121T03 0603
1
2
L33
CRT_HSYNC_1
4
JVGA_HS
3
U23
SN74AHCT1G125DCKR_SC70-5
1
2
R451
1
@
C530
10P_0402_50V8J
D8
JVGA_VS
@
3
I/O2
I/O4
6
JVGA_HS
2
GND
VDD
5
+5VS
1
I/O1
I/O3
4
CRT_DDC_DAT_CONN
2
1
1K_0402_5%
2
CRT_DDC_CLK_CONN
1
P
5
2
3
G
A
OE#
<17> CRT_VSYNC
2
EMI Request
+CRT_VCC
3
16
17
1
5
P
2
<17> CRT_HSYNC
C531
0.1U_0402_16V4Z
G
G
2
OE#
C529
0.1U_0402_16V4Z
1K_0402_5%
ME@
R432
0_0402_5%
2
1
1
R434
0_0402_5%
2
1
2
CONTE_80431-5K1-152
BLUE
R436
0_0402_5%
2
1
2
1
2
R437
0_0402_5%
2
1
2
1
W=40mils
C521
0.1U_0402_16V4Z
GREEN
10P_0402_50V8J
C527
1
RED
10P_0402_50V8J
C526
R446
150_0402_1%
2
2
R443
150_0402_1%
10P_0402_50V8J
C524
10P_0402_50V8J
C522
1
1
1
2
R445
150_0402_1%
10P_0402_50V8J
C523
<17> DAC_GRN
10P_0402_50V8J
C525
<17> DAC_RED
<17> DAC_BLU
1.1A_6V_SMD1812P110TF
FCM1608CF-121T03 0603
1
2
L30
FCM1608CF-121T03 0603
1
2
L31
FCM1608CF-121T03 0603
1
2
L32
CRT_VSYNC_1
4
Y
FCM1608CF-121T03 0603
1
2
L34
@ C532
10P_0402_50V8J
1
1
+CRT_VCC
+3VS
2
R457
2.2K_0402_5%
2
5
R456
2.2K_0402_5%
4
<17> CRT_DDC_DATA
3
1
2
Pull high at chipset/VGA side
AZC099-04S.R7G_SOT23-6
JVGA_VS
U24
SN74AHCT1G125DCKR_SC70-5
3
CRT_DDC_DAT_CONN
2
2N7002DW -T/R7_SOT363-6
Q62B
1
<17> CRT_DDC_CLK
6
2N7002DW -T/R7_SOT363-6
Q62A
4
@
C533
100P_0402_50V8J
1
2
CRT_DDC_CLK_CONN
1
@
C534
68P_0402_50V8K
2
Compal Secret Data
Issued Date
4
2011/06/15
Deciphered Date
2012/07/11
Title
A
B
C
D
CRT Connector
Size
Document Number
Custom
Date:
Rev
0.2
LA-7981P
Sheet
E
34
of
60
5
4
3
2
1
+5VS
+5VS
RB491D_SC59-3
D13 HDMI@
2
1+HDMI_5V
2
2
3
+3VS
R482 @
0_0805_5%
1
C543
HDMI@
0.1U_0402_16V4Z 2
D14 @
BAT54S-7-F_SOT23-3
2
2
3
D
TMDS_B_HPD#
S
<17> TMDS_B_HPD#
Q93
HDMI@
2N7002H_SOT23-3
1
R484 HDMI@
2.2K_0402_5%
1
HDMI@ R483
2.2K_0402_5%
R488
20K_0402_5%
HDMI@
1
JHDMI1ME@
HDMI_DET
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+5VS_HDMI
HDMIDAT_R
HDMICLK_R
HDMI_CLK-_CK R465 1 @
2 0_0402_5%
HDMI_CLK-_CONN
HDMI_CLK+_CKR464 1 @
HDMI_TX0-_CK R467 1 @
2 0_0402_5%
2 0_0402_5%
HDMI_CLK+_CONN
HDMI_TX0-_CONN
HDMI_TX0+_CK R466 1 @
2 0_0402_5%
2 0_0402_5%
HDMI_TX0+_CONN
HDMI_TX1-_CONN
2 0_0402_5%
2 0_0402_5%
HDMI_TX1+_CONN
HDMI_TX2-_CONN
2 0_0402_5%
HDMI_TX2+_CONN
<17> HDMI_CLK-_CK
<17> HDMI_CLK+_CK
C
<17> HDMI_TX0-_CK
<17> HDMI_TX0+_CK
+3VS
2
<17> HDMI_TX1-_CK
<17> HDMI_TX1+_CK
R783
0_0402_5%
@
D
2
1
G
2
R485
1M_0402_5%
HDMI@
1
D
W=40mils
+5VS_HDMI
F2
HDMI@
1.1A_6VDC_FUSE
1
2 +5VS_HDMI
1
1
<17> HDMI_TX2-_CK
<17> HDMI_TX2+_CK
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
C
SUYIN_100042GR019M23DZL
1
HDMI@
1
1
2
2
HDMI_CLK+_CONN
C982 1
2 0.1U_0402_16V4Z @
HDMI_CLK-_CK
4
4
3
3
HDMI_CLK-_CONN
C983 1
2 0.1U_0402_16V4Z @
HDMICLK_R
5
<17> HDMICLK_NB
6
L35
HDMI_CLK+_CK
WCM-2012HS-900T
B
<17> HDMIDAT_NB
4
HDMIDAT_R
3
L36
Q63B
HDMI@
2N7002DW-T/R7_SOT363-6
HDMI@
HDMI_TX0+_CK
1
1
2
2
HDMI_TX0+_CONN
C984 1
2 0.1U_0402_16V4Z @
HDMI_TX0-_CK
4
4
3
3
HDMI_TX0-_CONN
C985 1
2 0.1U_0402_16V4Z @
WCM-2012HS-900T
HDMIDAT_R
L37
1
1
2
2
HDMI_TX1+_CONN
C986 1
2 0.1U_0402_16V4Z @
HDMI_TX1-_CK
4
4
3
3
HDMI_TX1-_CONN
C987 1
2 0.1U_0402_16V4Z @
680 +-5% 8P4R
5
4
6
3
7
2
8
1
HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN
680 +-5% 8P4R
5
4
6
3
7
2
8
1
RP6 HDMI@
2
L38
B
+3VS
D
S
WCM-2012HS-900T
D11 @
PJDLC05_SOT23-3
SD309680080
S ROW RES 1/16W 680 +-5% 8P4R
RP5 HDMI@
HDMI@
HDMI_TX1+_CK
HDMICLK_R
3
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN
1
Q63A
HDMI@
2N7002DW-T/R7_SOT363-6
3
2
Pull up R for PCH OR VGA SIDE
2
G
Q95
HDMI@
2N7002H_SOT23-3
HDMI@
HDMI_TX2+_CK
1
1
2
2
HDMI_TX2+_CONN
C988 1
2 0.1U_0402_16V4Z @
HDMI_TX2-_CK
4
4
3
3
HDMI_TX2-_CONN
C989 1
2 0.1U_0402_16V4Z @
WCM-2012HS-900T
A
1
A
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
5
4
3
2
HDMI CONN
Size
B
Document Number
Rev
0.2
LA-7981P
Date: Tuesday, February 14, 2012
Sheet
1
35
of
60
A
B
C
D
E
Mini-Express Card for WLAN/WiMAX(Half)
1
1
+3VS_WLAN
+3VS_WLAN
Mini-Express Card(WLAN/WiMAX)
1
@
80mil
J6
1
2
+1.5VS_CONN
2
+1.5VS
C548@
4.7U_0603_6.3V6K
1
1
2
1
C547
0.1U_0402_16V4Z
1
@
+3VS
+3VALW
2
2
C544
0.1U_0402_16V4Z
2
C545 @
0.1U_0402_16V4Z
JUMP_43X79
R02
<19,40> PCH_BT_ON#
<19> BT_DISABLE
1
R892
1
R897
<16,37,45> PCIE_WAKE#
<40> BT_ACTIVE
@
2
0_0402_5% <15> CLKREQ_WLAN#
2
0_0402_5%
<15> CLK_PCIE_WLAN1#
<15> CLK_PCIE_WLAN1
0_0402_5%
PCIE_WAKE#1
@
2 R514
BT_ACTIVE 1 R497
2 @ 0_0402_5%
BT_DISABLE_R
PCI_RST#_R
CLK_PCI_DB
2
+3VS_WLAN
100_0402_1%
R505
1
2
1
2
R506
100_0402_1%
For EC to detect
debug card insert.
53
GND
54
GND
+1.5VS_CONN
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
@1 R498 R02
2 0_0402_5%
1 R499
@1 R500
2
2
R02
1 R501
2
1 R502
2
@ 0_0402_5%
0_0402_5%
@ 0_0402_5%
@ 0_0402_5%
PCH_WL_OFF# <18>
PLT_RST# <18,23,37,42,45>
+3VALW
+3VS
2
SMB_CLK_S3 <12,13,15>
SMB_DATA_S3 <12,13,15>
USB20_N10 <18>
USB20_P10 <18>
R503 2
R504 2
@
@
1 0_0402_5%
1 0_0402_5%
WLAN_LED#
NC
TAITW_PFPET0-AFGLBG1ZZ4N0
ME@
R507
100K_0402_5%
3
1
3
WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
<42,43> EC_TX
<42,43> EC_RX
JWLN1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB
R508
R509
R510
R511
R512
R513
1
1
1
1
1
1
@
@
@
@
@
@
2
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME# <14,42>
LPC_AD3 <14,42>
LPC_AD2 <14,42>
LPC_AD1 <14,42>
LPC_AD0 <14,42>
PLT_RST#
CLK_PCI_DB <18>
4
4
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
A
B
C
D
Title
Mini-Card/NEW Card/SIM
Size
Document Number
Rev
0.2
LA-7981P
Date:
Sheet
E
36
of
60
5
4
3
+LX
L77
2
2
2
1
2
2
+1.1_AVDDL_L
1
Note: Place Close to LAN chip
L39 DCR< 0.15 ohm
Rate current > 1A
2
1
2
C317
2
1
C980
1
SWR@
4.7U_0603_6.3V6K
Q105
PMV65XP_SOT23-3~D
G
R176
1
1U_0402_6.3V4Z
D
S
3
L78
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
+1.1_AVDDL
+1.1_DVDDL
1
2
1
2
C967
0_0402_5%
D
L74 SWR@
1
2 +LX
4.7UH_SIA4012-4R7M_20%
+LX_R
2
0.1U_0402_16V4Z
R1357
+1.1_DVDDL
1
10U_0603_6.3V6M
C937
2
C936
1
JUMP_43X79
0.1U_0402_16V4Z
1
Close together
@
J18
@ C935
1000P_0402_50V7K
Layout Notice : Place as close
chip as possible.
LAN_PWR_ON#
1
+3V_LAN
+3VALW
<42> LAN_PWR_ON#
2
1
2
D
10U
10K_0402_5%
C976
0.1U_0402_16V7K
1
Place close to Pin34
Close to
Pin40
Vendor recommand reseve the
PU resistor close LAN chip
+3V_LAN
8162@
<18,23,36,42,45>
PLT_RST#
R1367
SA000050E00_S IC AR8161-AL3A-R QFN 40P E-LAN CTRL
SA000052J10_S IC AR8162-AL3A-R QFN 40P E-LAN CTRL
+AVDDH_AVDD3.3
1
38
39
23
TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3
12
11
15
14
18
17
21
20
MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+
SMCLK
SMDATA
RBIAS
10
LAN_RBIAS
NC
TESTMODE
VDD33
Atheros
AR8151/AR8161
32
33
REFCLK_N
REFCLK_P
PLT_RST#
2
PERST#
PCIE_WAKE#_R
3
W AKE#
@
+3V_LAN
@
2 0_0402_5%
2 0_0402_5%
R521 1
25
26
2 4.7K_0402_5%
@
28
27
Vendor recommand reseve the
PU resistor close LAN chip
+3V_LAN
R520 1
LAN_XTALO
LAN_XTALI
@
2 4.7K_0402_5%
7
8
4
<15> CLKREQ_LAN#
Near
Pin13
Near
Pin19
Near
Pin31
1
2
1
2
0.1U_0402_16V4Z
2
C959
C958
1
1U_0402_6.3V4Z
C960
2
0.1U_0402_16V4Z
C957
1
0.1U_0402_16V4Z
C956
2
0.1U_0402_16V4Z
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL
1
LX
XTLO
XTLI
Place Close to PIN1
+3V_LAN
1
2
R1371 2.37K_0402_1%
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG/AVDDL
41
GND
+3V_LAN
40
+LX
+LX
@
R1372
1
+1.7_VDDCT
DVDDL/PPS
DVDDL_REG/DVDDL
24
37
+1.1_DVDDL
AVDDH/AVDD33
AVDDH
AVDDH_REG
16
22
9
+AVDDH_AVDD3.3
+2.7_AVDDH
+2.7_AVDDH
CLKREQ#
13
19
31
34
6
1
5
VDDCT/ISOLAN
B
C
Place Close to PIN1
30K_0402_5%
2
+3VS
1
2
1
2
1
2
@
1
2
B
10U
+2.7_AVDDH
C961
R1369 1
R1370 1
2
Place close to Pin16
<38>
<38>
<38>
<38>
<38>
<38>
<38>
<38>
C954
10U_0603_6.3V6M
<15> CLK_PCIE_LAN#
<15> CLK_PCIE_LAN
MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+
C953
10U_0603_6.3V6M
RX_P
C952
1U_0402_6.3V4Z
RX_N
35
C951
0.1U_0402_16V4Z
36
C950
1000P_0402_50V7K
1
2
ACTIVITY <38>
LAN_LINK# <38>
2 R65 R02 1
LDO@ 10K_0402_5%
1
1
AR8161-AL3A-R_QFN40_5X5
2
Near
Pin9
Near
Pin6
1
2
1
2
Near
Pin22
1
2
1
2
1U_0402_6.3V4Z
TX_P
<16,36,45> PCIE_WAKE#
<42> LAN_WAKE#
ACTIVITY
LAN_LINK#
LED_0
LED_1
LED_2
TX_N
C964
PCIE_PRX_C_DTX_P1 30
0.1U_0402_16V4Z
C965
PCIE_PRX_C_DTX_N1 29
2 0.1U_0402_16V7K
0.1U_0402_16V4Z
2 0.1U_0402_16V7K
C947 1
2
C963
C946 1
GIGA@
0.1U_0402_16V4Z
C962
1
Overclocking mode stick
1U_0402_6.3V4Z
U41
Place Close to Chip
C948
H --> Overclocking mode
L --> Not overclocking mode
C
2
0_0402_5%
AR8162-AL3A-R
1U_0402_6.3V4Z
U41
PLT_RST#
C949
2 4.7K_0402_5%
@
0.1U_0402_16V4Z
R525 1
+3V_LAN
Near
Pin37
LAN_XTALI
LAN_XTALO
Y6
A
3.3V : Enable switching regulator
0V
: Disable switching regulator
C968
15P_0402_50V8J
4
NC
1
OSC
OSC
3
NC
2
A
1 25MHZ_10PF_7V25000014
1
2
2
C969
15P_0402_50V8J
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
LAN-AR8151/8161
Custom
Date:
Rev
0.2
LA-7981P
Sheet
1
37
of
60
5
4
3
2
1
MDI3+
T2
MDI3-
@
2
C970
0.1U_0402_16V4Z
<37>
<37>
MDI3+
MDI3-
<37>
<37>
MDI2+
MDI2-
MDI3+
MDI3-
1
2
3
4
5
6
7
8
6
7
8
9
10
1
1
6
7
8
9
10
D
11
GND
@
2
MDI2+
MDI2-
8162@
1 R304
2 0_0402_5%
1 R305
2 0_0402_5%
1
2
R1374 75_0603_5%
8162@
R02
MDO3+
MDO3MCT3
16
15
14
13
12
11
10
9
TX+
TXCT
NC
NC
CT
RX+
RX-
MCT2
MDO2+
MDO2-
8162@
1
2
R1375 75_0603_5%
1 R306
2
1 R307
2
0_0402_5%
8162@ 0_0402_5%
S X'FORM_ HD-081-A LAN
GIGA@
5
4
3
2
1
5
4
3
2
1
RCLAMP3304N.TCT_SLP2626P10-10
D69 @
C972
0.1U_0402_16V4Z
TD+
TDCT
NC
NC
CT
RD+
RD-
D
R308 change to C 10P 50V 0603 Rev0.5
S CER CAP 10P 50V J NPO 0603
R308
C973
0_0603_5%
2
1 1
2
R02
MDI2-
T1
2
MDI2+
@
C974
0.1U_0402_16V4Z
<37>
<37>
MDI0+
MDI0-
<37>
<37>
MDI1+
MDI1-
MDI0+
MDI0-
1
2
3
4
5
6
7
8
1
Place Close to T2
MDI11
MDI1+
@
2
C975
0.1U_0402_16V4Z
MDI1+
MDI1-
10P_0603_50V
TD+
TDCT
NC
NC
CT
RD+
RD-
MDO0+
MDO0-
16
15
14
13
12
11
10
9
TX+
TXCT
NC
NC
CT
RX+
RX-
MCT0
1 R1376 2
75_0603_5%
MCT1
1 R1377 2
75_0603_5%
MDO1+
MDO1-
For GDTx1
DL1- Mount
DL2/DL3/DL4- NC
R308- 75 ohm
R1374/R1375/R1376/R1377- 0 ohm
6
7
8
9
10
S X'FORM_ HD-081-A LAN
GND
C
RCLAMP3304N.TCT_SLP2626P10-10
D68 @
LDO Mode: pop R1380;R596
SWR Mode: pop R1449;R1378
5
4
3
2
1
5
4
3
2
1
11
6
7
8
9
10
C
MCT3
MDI0-
<37> ACTIVITY
ACTIVITY
R1448
2
PR3+
MDO2-
5
PR3-
MDO1-
6
PR2-
MDO3+
7
PR4+
G2
14
MDO3-
8
PR4-
G1
13
1 510_0402_5%
11
12
@
C979
470P_0402_50V7K
@
@
@
B
Yellow LEDYellow LED+
Reserve for EMI go rural solution
SANTA_130452-D ME@
1
@
LSE-200NX3216TRLF_1206-2
4
2
PR2+
MDO2+
DL4
PR1-
3
1
2
2
MDO0MDO1+
DL3
PR1+
1
1
LSE-200NX3216TRLF_1206-2
Overclocking mode stick
MCT0
MDO0+
LSE-200NX3216TRLF_1206-2
B
Green LED+
2
R596 LDO@
0_0402_5%
2
MCT1
10
DL2
2 SWR@ 1 0_0402_5%
Green LED-
1
R1378
1 510_0402_5%
9
2
2 LDO@
2
C978 @
470P_0402_50V7K
R1380
1
1 +3V_LAN
2 SWR@ 1 510_0402_5%
DL1
<37> LAN_LINK#
R1449
1
MDI0+
Place Close to T1
LSE-200NX3216TRLF_1206-2
MCT2
JRJ1
+3V_LAN
2
A
A
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
5
4
3
2
LAN_Transformer
Size
B
Date:
Document Number
Rev
0.2
LA-7981P
Sheet
1
38
of
60
5
4
3
2
1
SMSC thermal sensor
placed near by VRAM
+3VS
2
C590
0.1U_0402_16V4Z
REMOTE2-
1
1
Q97
MMST3904-7-F_SOT323-3
2
E
REMOTE1-
1
VDD
SMCLK
10
EC_SMB_CK2
REMOTE1+
2
DP1
SMDATA
9
EC_SMB_DA2
REMOTE1-
3
DN1
ALERT#
8
REMOTE2+
4
DP2
THERM#
7
REMOTE2-
5
DN2
GND
6
EC_SMB_CK2 <15,23,42>
EC_SMB_DA2 <15,23,42>
Under WWAN
REMOTE2+
1
@
C589
100P_0402_50V8J
1
2
C
2
B
2
REMOTE1-
REMOTE2+
C588 @
2200P_0402_50V7K
R540
10K_0402_5%
@
U27
1
@
C586
100P_0402_50V8J
3
1
+3VS
1
2
D
1
REMOTE1+
C587
2200P_0402_50V7K
Close to DDR
REMOTE1+
Close U27
C
Q98 @
MMST3904-7-F_SOT323-3
2
B
2
E
3
D
REMOTE2-
EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
VGA_L
VGA_R
H4
HOLEA
H5
HOLEA
H_3P8
1
1
1
H_3P3
H6
HOLEA
R581
H_3P3
@
C591
10U_0603_6.3V6M
1
H8
HOLEA
H9
HOLEA
H10
HOLEA
H11
HOLEA
H12
HOLEA
H13
HOLEA
H14
HOLEA
H15
HOLEA
H_2P8
H_2P8
H_2P8
H_2P8
H_2P8
H_2P8
H_2P8
M/B 橢橢
B
H17
HOLEA
1
1
H_2P8
H16
HOLEA
1
1
1
1
1
1
1
2
3
4
G5
G6
1
1
2
3
4
5
6
1
1
<42> EC_TACH
0_0603_5%<42> EC_FAN_PWM
2
H7
HOLEA
M/B 橢橢橢
L
R
JFAN1
1
2
FD4
B
FAN1 Conn
+5VS
FD3
H_3P8
A
B
FD2
H_2P8
1
H_3P8
FD1
1
H3
HOLEA
C
1
H2
HOLEA
1
CPU
1
1
H1
HOLEA
1
Address 1001_101xb
C
H_3P0X4P0N H_3P0X4P0N
H_3P0N
D
ACES_85205-04001
ME@
E
2P8 * 9 pcd
10U
A
A
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
5
4
3
2
Fintek-Thermal IC/FAN/screw
Size
B
Document Number
Rev
0.2
LA-7981P
Sheet
1
39
of
60
A
B
C
D
E
F
G
H
SATA HDD Conn.
BT MODULE CONN
JHDD1
+3VALW
1
<14> SATA_ITX_DRX_P0
<14> SATA_ITX_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
<14> SATA_DTX_C_IRX_N0
<14> SATA_DTX_C_IRX_P0
C710 @
0.1U_0402_16V4Z
C596 1
C597 1
1
2
3
4
5
6
7
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
GND
RX+
RXGND
TXTX+
GND
2
1
R632 BT@
100K_0402_5%
1
2
<19,36> PCH_BT_ON#
1
C709 BT@
0.1U_0402_16V4Z
1
2
+3VS
+3VS_BT
R02
R583
0_0603_5%
1 2
1
+3VS
1
2
G
Q104
PMV65XP_SOT23-3~D
2
+5VS
@
0.1U_0402_16V4Z
C712
BT@
+5V_HDD
R02
JBT1
<18>
<18>
<36>
USB20_P13
USB20_N13
USB20_P13
USB20_N13
BTON_LED:NC
BT_ACTIVE
BT_ACTIVE
R550 0_0805_5%
1
2 +5V_HDD
30mils
D
S
3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
1
2
3
4
5 G1
6 G2
1
7
8
2
+3VS
10U
1
C598
1000P_0402_50V7K
2
1
C599
0.1U_0402_16V4Z
2
1
C600 @
1U_0603_10V4Z
2
1
C602
10U_0603_6.3V6M
2
@
C603
0.1U_0402_16V4Z
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
23
24
GND
GND
SUYIN_127043FB022G278ZR
ACES_87213-0600G
ME@
ODD Power Control
2
@
1
+5VALW
1
2
1
1
SATA ODD FFC Conn.
2
JP2
1
2
G
R552 @
10K_0402_5%
1
Q99 @
PMV65XP_SOT23-3~D
2
R675 @
100K_0402_5%
2
OUT
1
2
3
IN
GND
2
C604
0.1U_0402_16V4Z
2
<14> SATA_ITX_C_DRX_P2
<14> SATA_ITX_C_DRX_N2
<14> SATA_DTX_C_IRX_N2
<14> SATA_DTX_C_IRX_P2
1
1
1
<19> ODD_EN
FOR 15"
+5V_ODD
D
S
3
2
2
JUMP_43X79
+5VS
@ R568
10K_0402_5%
2
J9
SATA_ITX_C_DRX_P2
SATA_ITX_C_DRX_N2
15@ C605 1
15@ C606 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_ITX_DRX_P2_15
SATA_ITX_DRX_N2_15
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
15@ C618 1
15@ C617 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
1
R710
@
C608
10U_0603_6.3V6M
ODD_DA#
<18,42> ODD_DA#
C607 @
0.01U_0402_25V7K
1
R555 2
1
10K_0402_5%
+3VS
SATA_DTX_IRX_N2_15
SATA_DTX_IRX_P2_15
ODD_DETECT#
2
0_0402_5%
+5V_ODD
2 R554
R_ODD_DA#
R02
0_0402_5%
@
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
10U
ACES_87056-01001-001
Q100 @
ME@
Co-lay
3
3
FOR 14"
SATA ODD Conn.
JODD1
SATA_ITX_C_DRX_P2 14@ C616 1
SATA_ITX_C_DRX_N2 14@ C615 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_ITX_DRX_P2_14
SATA_ITX_DRX_N2_14
SATA_DTX_C_IRX_N2 14@ C614 1
SATA_DTX_C_IRX_P2 14@ C613 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_IRX_N2_14
SATA_DTX_IRX_P2_14
ODD_DETECT#
+5V_ODD
R_ODD_DA#
R02
1
2
3
4
5
6
7
GND
RX+
RXGND
TXTX+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
ME@
GND1
GND2
14
15
TYCO_2-1759838-8~D
4
4
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
A
B
C
D
E
F
Title
HDD/ODD/BT Connector
Custom
Date:
G
Rev
0.2
LA-7981P
Sheet
40
of
H
60
5
4
3
2
1
CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).
D
D
1
+3VS
HDA_RST_AUDIO#
+3VS
2
@
Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)
2
@
1
2
@
CX_GPIO0
BBH@2 R519
1 0_0402_5%
38
37
SPK_L2+
SPK_L1-
11
13
SPK_R2+
SPK_R1-
16
14
Internal SPEAKER
0.1U_0402_16V4Z
2
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
C595
4.7U_0603_6.3V6K
C628
0.1U_0402_16V4Z
C594
C632
C620
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
SENSE_A
PORTB_R
PORTB_L
B_BIAS
R458
SENSE_A
1
2 5.11K_0402_1%
R491 1
R494
1
2 20K_0402_1%
2 39.2K_0402_1%
SENSE_A
36
C_BIAS
PORTC_R
PORTC_L
GPIO0/EAPD#
GPIO1/SPK_MUTE#
DMIC_CLK
DMIC_1/2
NC
NC
NC
LEFT+
LEFTAVEE
FLY_P
FLY_N
RIGHT+
RIGHT-
R526
1
2K_0402_5%
1
0_0402_5%
2.2U_0603_6.3V4Z
2
+MICBIASB
100_0402_1%
EXT_MIC
4.7K_0402_5%
1
External MIC
MIC_INR
MIC_INL
Internal MIC
R481
R493
23
22
1
1
2
2
39_0402_5%
39_0402_5%
HP_OUTR <43>
HP_OUTL <43>
Headphone
Changed from 5.1ohm to 15ohm
for "zi zi"noise.
24
25
39
1
C635
2
1U_0603_10V4Z
1
2
1
Combo Jack detect (normal close)
33K_0402_5%
R693 1
2
EXT_MIC
1
2
G
2
3
S
+5VS
C787
1U_0402_6.3V6K
<43>
PLUG_IN
R182 47K_0402_5%
1
2
@
1
C630
CX_GPIO0
PC_BEEP
2
PC Beep
1
2
C619 0.1U_0402_16V4Z
PLUG_IN_R
R724
10K_0402_5%
PLUG_IN_R
R723
20K_0402_5%
D
S
Q85
2N7002_SOT23
2
G
@
2
0.1U_0402_16V4Z
1
R492
1
2
33_0402_5%
B
MIC_JD
1
2
D
Q75
1
2PC_BEEP1
C612 0.1U_0402_16V4Z
un-pop
EXT_MIC <43>
2.2U_0603_6.3V4Z
+MICBIASC
CX20671-21Z_QFN40_6X6
41
R700
2
R490 & R700 for App & Nokia combo ear phone
R517
2
2
GNDA
<14> HDA_SPKR
C
@
32
31
30
21
19
20
Port B
Port A
MIC_JD
PLUG_IN_R
+MICBIASB
C621 1
C622 1
35
34
33
+3VS
Please bypass caps very close to device.
PC_BEEP
2
0_0402_5%
2
Sense resistors must be
connected same power
that is used for VAUX_3.3
R490
GND
Short GND and GNDA on
GND1 & GND2 on layout
2
12
15
17
@
1
2
PORTA_R
PORTA_L
40
1
4.7U_0603_6.3V6K
C631
C638
29
3
7
2
18
27
28
26
LPWR_5.0
RPWR_5.0
CLASS-D_REF
2
1
1
0_0402_5% 1
R496 2
10
EAPD active low
0=power down ex AMP
1=power up ex AMP
ICH Beep
2
ESD Reserve
3
<43> CX_GPIO0
<42>
EAPD
<42> EC_MUTE#
BEEP#
2
2
@
1
HDA_SDOUT_AUDIO
2
1
C609
2 33_0402_5%
2
1
4.7U_0603_6.3V6K
5
8
6
4
PC_BEEP
<42>
1
C641 @
100P_0402_50V8J
+5VS
1
0.1U_0402_16V4Z
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
RESET#
2
AVDD_3.3
AVDD_5V
AVDD_HP
9
FILT_1.65
HDA_RST_AUDIO#
FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3
U25
@
1
C629
R495 1
2
1
0.1U_0402_16V4Z
<14> HDA_BITCLK_AUDIO
<14> HDA_SYNC_AUDIO
<14> HDA_SDIN0
<14> HDA_SDOUT_AUDIO
1
0.1U_0402_16V4Z
1
C626
2
<14> HDA_RST_AUDIO#
EC Beep
HDA_RST_AUDIO#
1
+5VS
10 mils
4.7U_0603_6.3V6K
C634
2
1
0.1U_0402_16V4Z
1
1U_0603_10V4Z
C623
1R528 @ 2 0_0402_5%
2
GND
1
22P_0402_50V8J
C578
1
22P_0402_50V8J
C577
2
HDA_BITCLK_AUDIO
@
AVDD_3.3 pinis output of
internal LDO. NOT connect
to external supply.
22P_0402_50V8J
C576
C625
2
1
0.1U_0402_16V4Z
2
1
4.7U_0603_6.3V6K
C592
1
0.1U_0402_16V4Z
C584
2
C
R516 @
1
1 R515
2
0_0402_5%
+LDO_OUT_3.3V
1
0_0402_5%
@
B
R351 @
4.7K_0402_5%
HDA_SDOUT_AUDIO
1U_0603_10V4Z
C585
2
@
0.1U_0402_16V4Z
2
1
2
C593
+3VALW
1
2
1
22P_0402_50V8J
C575
R527
+3VS
1
0.1U_0402_16V4Z
C581
C579
2
0.1U_0402_16V4Z
C582
1
4.7U_0603_6.3V6K
C583
2
4.7U_0603_6.3V6K
C580
+3VS
@
EMI
HDA_SYNC_AUDIO
1
@
R480
10K_0402_5%
2
Place colose to Codec chip
close to Codec
+MICBIASC
2
2
2
@
@
2
2
2011/06/15
Deciphered Date
4
3
2
2
3
1
2
3
4
GND1
GND2
A
ACES_88231-04001
@ D70
TVNST52302AB0 C/C SOT523
D71 @
TVNST52302AB0 C/C SOT523
2012/07/11
5
5
6
Compal Secret Data
Issued Date
2
1
2
3
MIC_INL
1
1
1
1
1
R02
1
220P_0402_50V7K
MIC_INR
GNDA
1
1
2
3
4
220P_0402_50V7K
C611
2 2.2U_0603_6.3V4Z
C640
0.1U_0402_16V4Z
WM-64PCY_2P
45@
C633 1
C636
0.1U_0402_16V4Z
1
2
JSPK1 ME@
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
C610
MIC1
FBMA-L11-160808-121LMT_0603
2
FBMA-L11-160808-121LMT_0603
2
FBMA-L11-160808-121LMT_0603
2
FBMA-L11-160808-121LMT_0603
2
wide 30MIL
2
A
1
1
1
1
220P_0402_50V7K
C624
R518
2.2K_0402_5%
L41
L42
L43
L46
220P_0402_50V7K
C627
1
SPK_R1SPK_R2+
SPK_L1SPK_L2+
Title
CX20671 Codec
Custom
Rev
0.2
LA-7981P
Sheet
1
41
of
60
+3VLP
C535
100P_0402_50V8J
2
@
2 47K_0402_5% KSO2
+3VALW
+3VS
R600
EC_SMB_CK1
2
2.2K_0402_5%
1
R604
R601
2.2K_0402_5%
R602
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
1
<43>
<43>
EC_SMB_CK2
EC_SMB_DA2
1
2
@
C666
100P_0402_50V8J
<48,49>
<48,49>
<15,23,39>
<15,23,39>
+3VS
1
2
R605
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<16>
<16>
<19>
<33>
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
CMOS_ON#
EC_SMI#
ODD_DA#
EC_INVT_PWM
EC_TACH
EC_PME#
EC_TX
EC_RX
PCH_PWROK
EC_FAN_PWM
<18,40> ODD_DA#
<33> EC_INVT_PWM
<39> EC_TACH
EC_TACH
10K_0402_5%
<36,43> EC_TX
<36,43> EC_RX
<16> PCH_PWROK
<39> EC_FAN_PWM
2
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
SUSCLK
EC_RTCX1
SUSCLK_R
2
1
0_0402_5%
122
123
67
EC_VDD/AVCC
1
C93
20P_0402_50V8
SUSCLK_R
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
SPI Flash ROM
GPIO
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
GPIO
GPI
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
ECAGND
EC_RTCX1
1
2
R120
@
10M_0402_5%
83
84
85
86
87
88
1
USB_ON#
INT#
PN : SA00004OB20
V18R
119
120
126
128
PCH_PWR_EN
2 R750
NTC_V_R
check
@
32.768KHZ_12.5PF_9H03200413
4
OSC
1
OSC
NC
2
C347
@
NC
18P_0402_50V8J
1
1
C367 @
18P_0402_50V8J
2
R03
1
10K_0402_5%
TP_CLK
PCH_PWR_EN
<46,48>
ENBKL
RST
CAPS_LED# <43>
PWR_LED# <43>
BATT_LOW_LED# <43>
SYSON
<45,46,51>
VR_ON
<55>
PM_SLP_S4# <16>
BATT_LOW_LED#
SYSON
BBH@ 2 4.7K_0402_5%
+3VALW
PCH_PWR_EN 2 R599
@1 100K_0402_1%
BATT_TEMP
R757
2
R738
1
BKOFF# <33>
PBTN_OUT# <16>
PCH_APWROK <16>
SA_PGOOD <52>
ACIN
EC_ON
124
1
C663
1
C664
1
R522
2
100P_0402_50V8J
2
100P_0402_50V8J
2
@ 4.7K_0402_5%
<33>
+3VLP
EC_RSMRST# <16>
EC_LID_OUT# <19>
EC_LID_OUT#
Turbo_V
H_PROCHOT#_EC
MAINPWON_R
BKOFF#
PBTN_OUT#
+V18R
R792 2
1
@
R669
1 0_0402_5%
2
43_0402_1%
@
KB9012A2 work around
R4945
47K_0402_5%
<55>
VR_HOT#
VR_HOT#
@
@
1
2
Turbo_V
<48>
PROCHOT <48>
MAINPWON <48,50>
0_0402_5%
0_0402_5%
1 R737
2
0_0402_5%
ACIN
<16,49>
EC_ON
<43,50>
ON/OFF
<43>
LID_SW# <43>
SUSP#
<10,25,46,51,52,53,54>
PCH_HOT# <15>
H_PECI
<6,19>
H_PROCHOT#
D
S
H_PROCHOT#_EC
2
G
Q37
2N7002H_SOT23-3
<6,48>
1
2
C493
47P_0402_50V8J
+3VALW
R606
10K_0402_5%
1
C667
4.7U_0805_10V4Z
R609
2
KB9012QF A3 LQFP 128P_14X14
@
2
1
0_0402_5%
SYSON
EC_PME#
1
Q102 @
2N7002_SOT23
3
1
2011/06/15
PCI_PME# <18>
+3VALW
2
Compal Secret Data
LAN_WAKE# <37>
2 R610
1
0_0402_5% @
EMC Request
Issued Date
Capsensor Board For best buy use
nonBBH@
2 4.7K_0402_5%
R591 1
LAN_PWR_ON# <37>
BATT_CHG_LED# <43>
BATT_CHG_LED#
CAPS_LED#
LID_SW#
SUSP#
PCH_HOT#_R
PECI_KB9012
GND1
GND2
R603 1
R598 1nonBBH@ 2 4.7K_0402_5%
TP_DATAR592 1
2 4.7K_0402_5%
BBH@
CPU1.5V_S3_GATE <10,46,53>
VGA_AC_DET <23,54>
ME_FLASH <14>
NTC_V
<48>
1 0_0402_5%
S IC KB9012QF A3 LQFP 128P KB CONTROLLER
9
10
+5VS +3VS +5VS +3VS
2
ACIN
110
112
114
115
116
117
118
JCAP1 ME@
ACES_50521-0084N-P01
1
1
RST
2
2
3
+3VS
3
EC_SMB_DA2
4
4
EC_SMB_CK2
5
5
6
6
INT#
7
7
8
+5VS
8
R04
R695
8.2K_0402_5%
R594
USB_ON# 1
@
Y5
1
2
10K_0402_5%
1 R593
2
EC_MUTE# <41>
USB_ON# <44,45>
EAPD <41>
TP_CLK
<43>
TP_DATA <43>
TP_CLK
TP_DATA
CPU1.5V_S3_GATE
VGA_AC_DET
100
101
102
103
104
105
106
107
108
BRDID
+3VALW
97
98
99
109
73
74
89
90
91
92
93
95
121
127
R694
100K_0402_1%
R588
10K_0402_5%
@
+5VALW
SPI Device Interface
Bus
MP
PVT
DVT
EVT
V
V
V
2
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00
EC_FAN_PWM
IMVP_IMON <55>
68
70
71
72
2
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
PS2 Interface
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
BATT_TEMP <48>
GPU_IMON <54>
1 0_0402_5%
<48,49>
ADP_I
BRDID
EC_MUTE#
2
2
R740
100K_0402_5%
9
22
33
96
111
125
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
1
<16>
77
78
79
80
NUM_LED#: NC
1
@ R608
10K_0402_5%
R611
3
2
@
C665
100P_0402_50V8J
2
1
KSO16
KSO17
max
+3VALW
1
R597 1
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
BATT_TEMP
VGA_IMVP_IMON 2 R758
3
2 47K_0402_5% KSO1
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
63
64
65
66
75
76
S
@
+3VS
VAD_BID
0 V
0.289
0.538
0.875
V
V
V
D
R595 1
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
<41>
<43>
<49>
V
V
V
typ
V AD_BID
0 V
0.250
0.503
0.819
2
G
+3VALW
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
BEEP#
NOVO#
ACOFF
min
1
KSI[0..7]
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
BEEP#
NOVO#
ACOFF
0.1U_0402_10V6K
C492
KSI[0..7]
PWM Output
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
21
23
26
27
1
KSO[0..15]
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
VAD_BID
0 V
8.2K +/- 5% 0.216
18K +/- 5%
0.436
33K +/- 5%
0.712
2
<43>
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
R695
0
0
1
2
3
U31
AGND/AGND
1
100K +/- 5%
Board ID
2
69
EC_SCI#
BATT_LEN#
KSO[0..15]
<43>
EC_RST#
EC_SCI#
BATT_LEN#
12
13
37
20
38
2
GND/GND
GND/GND
GND/GND
GND/GND
GND0
<19>
<48>
2
C661
0.1U_0402_16V4Z
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
10_0402_5%
<18> CLK_PCI_EC
<18,23,36,37,45> PLT_RST#
2
3.3V +/- 5%
Vcc
R694
+3VALW
+EC_VCCA
1
11
24
35
94
113
2
47K_0402_5%
<19>
GATEA20
<19>
KBRST#
<14>
SERIRQ
<14,36> LPC_FRAME#
<14,36> LPC_AD3
<14,36> LPC_AD2
<14,36> LPC_AD1
<14,36> LPC_AD0
2
1
C658
1000P_0402_50V7K
1
R590
+3VALW
1
2
1
22P_0402_50V8J @ R589
2
2
1
C657
1000P_0402_50V7K
2
@ C660
1000P_0402_50V7K
2
1
C655
0.1U_0402_16V4Z
C656
0.1U_0402_16V4Z
2 ECAGND
1
2
L45
FBM-11-160808-601-T_0603
+EC_VCCA
C659
1
C662
0.1U_0402_16V4Z
1
1
C654
0.1U_0402_16V4Z
+3VALW
C653
0.1U_0402_16V4Z
L44
FBM-11-160808-601-T_0603
1
2
1
2
1
+3VALW
Deciphered Date
2012/07/11
Title
BIOS & EC I/O Port
Size
Document Number
Custom
Date:
Rev
0.2
LA-7981P
Sheet
42
of
60
KSI[0..7]
KSI[0..7]
KSO[0..17]
<42>
KSO[0..17]
JKB1
<42>
KSO16
C693 1
2 @ 100P_0402_50V8J
KSO17
C692 1
2 @ 100P_0402_50V8J
KSO2
C668 1
2 @ 100P_0402_50V8J
KSO1
C669 1
2 @ 100P_0402_50V8J
KSO15
C670 1
2 @ 100P_0402_50V8J
KSO7
C671 1
2 @ 100P_0402_50V8J
KSO6
C672 1
2 @ 100P_0402_50V8J
KSI2
C673 1
2 @ 100P_0402_50V8J
KSO8
C674 1
2 @ 100P_0402_50V8J
KSO5
C675 1
2 @ 100P_0402_50V8J
KSO13
C676 1
2 @ 100P_0402_50V8J
KSI3
C677 1
2 @ 100P_0402_50V8J
KSO12
C678 1
2 @ 100P_0402_50V8J
KSO14
C679 1
2 @ 100P_0402_50V8J
KSO11
C680 1
2 @ 100P_0402_50V8J
KSI7
C681 1
2 @ 100P_0402_50V8J
KSO10
C682 1
2 @ 100P_0402_50V8J
KSI6
C683 1
2 @ 100P_0402_50V8J
KSO3
C684 1
2 @ 100P_0402_50V8J
KSI5
C685 1
2 @ 100P_0402_50V8J
KSO4
C686 1
2 @ 100P_0402_50V8J
KSI4
C687 1
2 @ 100P_0402_50V8J
KSI0
C688 1
2 @ 100P_0402_50V8J
KSO9
C689 1
2 @ 100P_0402_50V8J
KSO0
C690 1
2 @ 100P_0402_50V8J
KSI1
C691 1
2 @ 100P_0402_50V8J
<42>
<42>
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
KSO16
KSO17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
JP3
1
2
3
4
+3VALW
<36,42> EC_TX
<36,42> EC_RX
ME@
JKB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
26
25
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
GND
GND
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
32
ME@
GND2
GND1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88514-2401
ACES_88514-3001
1
2
3
4
ACES_85205-0400
ME@
+5VS
+3VLP
+5VALW
2
1
3
51_ON#
SHORT PADS
ON/OFFBTN#
2
1
NOVO_BTN#
3
ON/OFF
2
51_ON#
ON/OFF
1
R725
@
1
2
0_0402_5%
1
2
R722 @
0_0402_5%
G1
G2
<18> USB20_N11
<18> USB20_P11
5
6
+USB_VCCB
D24 @
PJSOT24C 3P C/A SOT-23
DAN202UT106_SC70-3
G9@
C734
220U_6.3V_M
SF000002Y00
1
+
2
1
2
2 R623
1 14@
300_0402_5%
1
2
GND
GND
ACES_51524-0160N-001
USB20_N1
1
USB20_P1
4
@
L57 @
1
2
4
3
2
USB20_N1_C
USB20_N11
1
3
USB20_P1_C
USB20_P11
4
1
2
4
3
2
USB20_N11_C
3
USB20_P11_C
LED2 14@
D
BATT_LOW_LED#
<42> BATT_LOW_LED#
3
2
2
G
Q106 @
2N7002_SOT23-3
<41> CX_GPIO0
+MICBIASB
G9@
C733
470P_0402_50V7K
+5VALW
L47
EC_ON
1
USB20_N1
USB20_P1
LED1 14@
PWR_LED#
<42> PWR_LED#
19-213A-T1D-CP2Q2HY-3T_WHITE
EC_ON
<18>
<18>
ME@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
<42>
51_ON# <47>
D23
@
DAN202UT106_SC70-3
<42,50>
1
2
3
EXT_MIC
4
PLUG_IN
5
6
2 R687
1 0_0402_5% USB20_N11_C 7
2 R683
1 0_0402_5% USB20_P11_C 8
9
CR_GND
G9@
10
2 R534
1 0_0402_5% USB20_N1_C 11
2 R533
1 0_0402_5% USB20_P1_C 12
G9@
13
14
2 R684@ 1 0_0402_5%
15
2 R685@ 1 0_0402_5%
16
R688
0_0402_5%
2
1
2 R686
1 0_0402_5%
17
18
<41> EXT_MIC
<41> PLUG_IN
1 0_0402_5%
E-T_7182K-F04N-00R
3
R720
@
1
2
0_0402_5%
2
NOVO#
1
2
3
4
2
NOVO#
1
1
6
5
<42>
ON/OFF
J11
1
NOVO_BTN#
ON/OFFBTN#
D26
R535 @
100K_0402_5%
3
R701
100K_0402_5%
4
2 R690
HP_OUTR
HP_OUTL
HP_OUTR
HP_OUTL
+3VS
1
2
3
4
1
@
2
1
2
SMT1-05_4P SW3
1
JPWRB1
ME@
R642
100K_0402_5%
R532@
100K_0402_5%
CR_GND
2 R689@ 1 0_0402_5%
2
2
+3VALW
+3VLP
JCR1
<41>
<41>
+3VALW
1
2
2 R764
1 14@
470_0402_5%
+3VALW
WCM-2012-900T_4P
WCM-2012-900T_4P
S
HT-191UD5_AMBER
R639 @
10K_0402_5%
LED5 14@
BATT_CHG_LED#
1
<42> BATT_CHG_LED#
1
2
2 R765
1 14@
300_0402_5%
+5VALW
LED6 14@
+5VS
2 R889
1 0_0402_5%
nonBBH@
+3VS
2 R890
BBH@
CAPS_LED#
<42> CAPS_LED#
1
2
2
R2
1 14@
300_0402_5%
+5VS
1 0_0402_5%
ME@
15@
2 R627
1
0_0402_5%
1
2
3
1
SW_L
5
6
5
6
4
TP_3
@
2 R619
1 14@ TP_1
0_0402_5%
R621
15_nonBBH@
0_0402_5%
2
1 TP_2
R622 14@
0_0402_5%
2
1
1
14@ C702
0.1U_0402_16V4Z
SW5 14@
SMT1-05_4P
4
2
3
1
TP_3
SW_R
1
2
@
1 R615
2
100K_0402_5%
OUTPUT
2
ACES_88058-060N
@ D15
PSOT24C_SOT23-3
SW4 14@
SMT1-05_4P
+VCC_LID
2
0_0402_5%
1
LID_SW#
3
<42>
2
U34 14@
2
LID_SW#
JLED1 ME@
GND
2
6
5
4
3
2
1
1
R614
1
2
C698 @
100P_0402_50V8J
3
@ C697
100P_0402_50V8J
6
5
4
3
2
1
TP_CLK
TP_DATA
TP_3
TP_2
TP_1
1
0.1U_0402_10V6K
C491
1
0.1U_0402_10V6K
C490
TP_CLK
TP_DATA
2
<42>
<42>
@
+3VALW
GND
GND
VDD
8
7
0.1U_0402_16V4Z
2
JTP1
C696
1
+5VALW
+3VALW
+5VS
C703 14@
10P_0402_50V8J
LID_SW#
PWR_LED#
BATT_LOW_LED#
BATT_CHG_LED#
CAPS_LED#
SW_R
SW_L
AH1806-W-7 SC59 3P
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
ACES_88058-120N
R624 15_nonBBH@
0_0402_5%
2
1 TP_1
R625 14@
0_0402_5%
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TP_2
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:
ROM/KBD/PWR/CR/LED/TP Conn.
Document Number
Rev
0.2
LA-7981P
Sheet
43
of
60
A
B
C
D
E
1
1
Right Ext.USB Conn.
2
2
JUSB3 ME@
+5VALW
C713 0.1U_0402_16V4Z
2
1
<42,45> USB_ON#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
C714
8
7
6
5
220U_6.3V_M
USB_OC4# <18>
G547I2P81U_MSOP8
1
6.3Φ * 5.9
SF000001500
+USB_VCCB
1
<18> USB20_N9
1
<18> USB20_P9
+
C715
470P_0402_50V7K
2
2
USB20_N9
4
4
USB20_P9
1
1
L66
C716
@ 1000P_0402_50V7K
2
USB20_N9
USB20_P9
R868 2
R869 2
@
@
1 0_0402_5%
1 0_0402_5%
USB20_N9_C
USB20_P9_C
2
R02
U36
1
2
3
4
W=80mils
3
+USB_VCCB
RIGHT USB PORT X1
8
7
GND
GND
6
5
4
3
2
1
6
5
4
3
2
1
ACES_88058-060N
3
3
USB20_N9_C
2
2
USB20_P9_C
1
+USB_VCCB
WCM-2012-900T_4P
D25 @
PJDLC05_SOT23-3
3
3
4
4
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
A
B
C
D
USB ext. ports
Size
B
Date:
Document Number
Rev
0.2
LA-7981P
Sheet
E
44
of
60
5
4
+1.5V to +1.05V Transfer
GND
1
1
2
1
2
2
@
1
1U3RXDN1
U3RXDN2 9 10
1
1U3RXDN2
U3RXDP1 8
9
2
2U3RXDP1
U3RXDP2 8
9
2
2U3RXDP2
U3TXDN1 7
7
4
4U3TXDN1
U3TXDN2 7
7
4
4U3TXDN2
U3TXDP1 6
6
5
5U3TXDP1
U3TXDP2 6
6
5
5U3TXDP2
3
3
3
3
2
2
U2DN1
2
1
YSCLAMP0524P_SLP2510P8-10-9
1
3
4
GND
VDD
I/O1
I/O3
Intel_PCH_USB2.0
<18>
USB20_N3
<18>
USB20_P3
GND
R766
0_0603_5%
EU3@
RT9701-PB_SOT23-5
U32
EU3@
1
2
G
D
PCIE_WAKE#_USB3
4
5
7
8
Q125 EU3@
SSM3K7002FU_SC70-3
R02
EU3@
1 R747
2
430K_0402_5%
C837 EU3@
1000P_0402_50V7K
PLT_RST#_USB3
47
PCIE_WAKE#_USB3 48
CLKREQ_USB3
10
<18>
1
SMIB
+3V
R770
@
U2DP2
U3RXDP2
46
EU3@
EU3@
1 R1172
2 300K_0402_5%
11
1
2
1
2
D67 EU3@
1SS355TE-17_SOD323-2
1
R03
SMIB_R
1 R267
2
2
+3V
+3V
U3TXDP2_R C844 1
2 EU3@ .1U_0402_16V7K U3TXDP2_L
38
45
U3TXDN2_R C846 1
U2DN2_R
R774 2
2 EU3@ .1U_0402_16V7K U3TXDN2_L
EU3@ 1
0_0402_5%
U2DN2_L
44
40
U2DP2_R
U3RXDP2_R
R776 2
R772 2
EU3@ 1 0_0402_5%
EU3@ 1 0_0402_5%
U2DP2_L
U3RXDP2_L
41
U3RXDN2_R
R763 2
EU3@ 1 0_0402_5%
U3RXDN2_L
U2DN2_L
1
U2DP2_L
4
1
PONRSTB
SPISCK
SPICSB
SPISI
SPISO
USB3_XT1 24
USB3_XT2 23
U3TXDN1
U2DM1
U2DP1
U3RXDP1
U3RXDN1
IC(L)
1
2
Y7
C836 EU3@
1000P_0402_50V7K
C897 EU3@
12P_0402_50V8J
1
2
+3V
8
7
SPI_CLK_USB
6
USB_SO_SPI_SI 5
EU3@ 1
VCC
HOLD#
SCK
SI
CS#
SO
WP#
GND
1
2
3
4
<42,44> USB_ON#
U3TXDN1_R
U2DN1_R
C845 EU3@ 1
R759 2 EU3@
2 .1U_0402_16V7K U3TXDN1_L
U2DN1_L
1 0_0402_5%
<18>
USB20_N2
35
31
U2DP1_R
U3RXDP1_R
R754 2 EU3@
R760 2 EU3@
1 0_0402_5%
1 0_0402_5%
U2DP1_L
U3RXDP1_L
<18>
USB20_P2
32
U3RXDN1_R
R762 2 EU3@
1 0_0402_5%
U3RXDN1_L
R1152 EU3@
1
2
26
3
R566
U35
1
2
3
4
1
2
0_0402_5%
R02
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
2
1
1
4
R570
1
2
0_0402_5%
1
2
U2DN2
D
2
U3RXDN2
3
U3RXDP2
+USB3_VCCA
W=80mils
JUSB2
U3TXDP2
U3TXDN2
U2DP2
U2DN2
U3RXDP2
2
4
L53
3
U3RXDN2
2
U3TXDN2
3
U3TXDP2
2
U2DN1
3
U2DP1
LP2
C
9
1
8
3
7
2
6
4
5
SSTX+
VBUS
SSTXD+
GND
10
DGND
11
SSRX+
GND
12
GND
GND
13
SSRXGND
TAITW_PUBAU1-09FNLSCNN4H0
ME@
R741 1
IU3@
0_0402_5%
WCM-2012-900T_4P
U2DN1_L
1
U2DP1_L
4
1
2
4
3
L51
B
1 R564@ 2
0_0402_5%
<18> USB3_RX3_N
2
<18> USB3_RX3_P
2
IU3@
1 U3RXDN1_L
0_0402_5%
WCM-2012-900T_4P
U3RXDP1_L
1
R739 IU3@
0_0402_5%
1
4
1
2
4
3
<18> USB3_TX3_N
1
<18> USB3_TX3_P
1
U3TXDP1_L
4
2
C847 IU3@
.1U_0402_16V7K
+USB3_VCCA
2
U3RXDN1
3
U3RXDP1
W=80mils
JUSB1
U3TXDP1
L50
C849 IU3@
.1U_0402_16V7K
U3TXDN1_L
1
2
USB_OC1# <18>
1 R561@ 2
0_0402_5%
U3TXDN1
U2DP1
1 R565@ 2
0_0402_5%
U2DN1
U3RXDP1
WCM-2012-900T_4P
1
2
4
3
U3RXDN1
2
U3TXDN1
3
U3TXDP1
9
1
8
3
7
2
6
4
5
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
LP1
GND
GND
GND
GND
10
11
12
13
TAITW_PUBAU1-09FNLSCNN4H0
ME@
L49
1 R546@ 2
0_0402_5%
Place TX AC coupling Cap (C843~C850). Close to connector
1 C735
A
470P_0402_50V7K
2
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
3
4
1 R563@ 2
0_0402_5%
0_0402_5%
IU3@ 1
2
R755
R773
W=80mils
8
7
6
5
+
C736
220U_6.3V_M
SF000002Y00 2
SPI_CS_USB#
USB_SI_SPI_SO
U2DP2
WCM-2012-900T_4P
Intel_PCH_USB3.0
+USB3_VCCA
R1176 EU3@
47K_0402_5%
4
4
L54
2A/Active Low
AT25F512AN-10SU-2.7_SO8~D
5
2
2 .1U_0402_16V7K U3TXDP1_L
1.6K_0402_1%
1
R1175 EU3@
10K_0402_5%
U53
EU3@
1
1
2
1
U3TXDP2_L
2
2
2
R1177 EU3@
10K_0402_5%
A
C895 EU3@
.1U_0402_16V K
4
1
C898 EU3@
15P_0402_50V8J
2
I/O3
+5VALW
1 R638 @2
0_0402_5%
G547I2P81U_MSOP8
1
1
C848 IU3@
.1U_0402_16V7K
29
36
GND
2
I/O1
5
1 R562@ 2
0_0402_5%
RREF
C704
.1U_0402_16V7K
1
2
+3V
C850 IU3@
.1U_0402_16V7K
1
2 U3TXDN2_L
<18> USB3_TX4_P
EU3@
1
U3RXDP2_L
1
R714 IU3@
0_0402_5%
2 10K_0402_5%
2 10K_0402_5%
C843
+5VALW
+3V
2
2
24MHZ_12PF_X5H024000DC1H
1
R02
Q121 EU3@
SSM3K7002FU_SC70-3
IU3@
2
1 U3RXDN2_L
0_0402_5%
<18> USB3_TX4_N
49
S
CLKREQ_USB3
U2DN2
3
1 R636@ 2
0_0402_5%
U3TXDP1_R
1
R1180 EU3@
100_0402_5%
2
WCM-2012-900T_4P
R709
XT1
XT2
1
2
G
3
D
<15> CLKREQ_USB30#
1
2
1 R743@ 2
0_0402_5%
28
2
27
R745 EU3@
10K_0402_5%
VDD
4
3
L55
1 R721@ 2
0_0402_5%
Intel_PCH_USB2.0
SPI_CLK_USB 15
SPI_CS_USB# 14
USB_SO_SPI_SI 16
USB_SI_SPI_SO 13
1
GND
6
18
20
PPON2
PPON1
SMIB
R1161 EU3@
OCI2B 1
OCI1B 1
R1162 EU3@
17
19
OCI2B
OCI1B
U3TXDP1
EU3@
37
+3V
PERSTB
PEWAKEB
PECREQB
10K_0402_5%
+3V
B
25
3
U3TXDN2
U2DM2
PERXP
PERXN
UPD720202K8-701-BAA_QFN48_7X7
SMIB_R
0_0402_5%
2
C894 EU3@
1U_0603_10V6K
C832
1U_0402_6.3V6K
2
AVDD33
AVDD33
39
33
30
21
42
VDD10
VDD10
VDD10
VDD10
VDD10
9
43
34
6
VDD10
VDD33
22
PETXP
PETXN
U3RXDN2
PLT_RST#_USB3
1
<18> USB3_RX4_P
U3TXDP2
U2DP1
4
I/O4
1 R742@ 2
0_0402_5%
<18> USB3_RX4_N
PECLKP
PECLKN
1
2
<18,23,36,37,42> PLT_RST#
EU3@
1 C834 PCIE_PRX_C_DTX_P4
1 C835 PCIE_PRX_C_DTX_N4
EU3@
.1U_0402_16V7K2
2
.1U_0402_16V7K
3
S
1
<16,36,37> PCIE_WAKE#
1
2
<15> CLK_PCIE_USB30
<15> CLK_PCIE_USB30#
R1187 EU3@
10K_0402_5%
VDD33
12
2
C
VDD33
+3V
2
+5VALW
@
I/O2
WCM-2012-900T_4P
+3AVDD
Intel_PCH_USB3.0
VDD33
+3V
+1.05VDD
5
3
1 R728@ 2
0_0402_5%
R730
IU3@ 1
2
0_0402_5%
R640
IU3@ 1
2
0_0402_5%
1
+3V
VDD10
2
U2DP2
6
For EMI request
2
+1.05V
1
5
VIN
VOUT
VIN/CE VOUT
I/O4
2
<42,46,51> SYSON
D31
@
I/O2
U30 EU3@
0.2A
3
8
0.01U_0402_25V7K
EU3@
2
1
C827
1
0.1U_0402_16V7K
EU3@
C823
1
0.01U_0402_25V7K
EU3@
2
C825
2
1
0.1U_0402_16V7K
EU3@
1
Close to U32.25
10U_0603_6.3V6M
EU3@
C888
2
0.01U_0402_25V7K
EU3@
2
1
C813
2
1
0.01U_0402_25V7K
EU3@
2
C812
1
0.01U_0402_25V7K
EU3@
C811
1
0.01U_0402_25V7K
EU3@
C810
2
0.01U_0402_25V7K
EU3@
1
C809
2
0.1U_0402_16V7K
EU3@
1
C817
0.1U_0402_16V7K
EU3@
C816
1
L60 EU3@
1
2
FBMA-L11-201209-221LMA30T_0805
Close to U32.3
D22
D30
U3RXDN1 9 10
YSCLAMP0524P_SLP2510P8-10-9
+3AVDD
C821
2
1
0.01U_0402_25V7K
EU3@
C808
1
0.01U_0402_25V7K
EU3@
C806
2
0.01U_0402_25V7K
EU3@
1
C803
2
0.01U_0402_25V7K
EU3@
1
C800
2
0.01U_0402_25V7K
EU3@
C797
0.01U_0402_25V7K
EU3@
2
C798
0.1U_0402_16V7K
EU3@
2
1
+3V
10U_0603_6.3V6M
EU3@
+3V
1
+3V
2
+3VALW
1
8
C887
+3VALW to +3V Transfer
2
C805
2
1
0.1U_0402_16V7K
EU3@
Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025
1
2
C802
EU3@
R1151
32.4K_0402_1%
EU3@
APL5930KAI-TRG_SO8
D
1 R1149 2
10K_0402_1%
2
FB
C886 EU3@
10U_0603_6.3V6M
EN
POK
1
0.1U_0402_16V7K
EU3@
2
SYSON
8
2
1
7
R1150 5.1K_0402_1%
EU3@
C799
3
4
VOUT
VOUT
22U_0603_6.3V6M
EU3@
+5VALW
2
1
VCNTL
VIN
VIN
1
D27
@
C794
6
5
9
2
+1.05V
U52
EU3@
+1.5V
22U_0603_6.3V6M
EU3@
1
+5VALW
C796
EU3@
2
C863
1U_0603_10V6K
1
+1.5V
EU3@
C864
10U_0603_6.3V6M
+5VALW
3
+1.05VDD
2
Title
USB3.0/Left USB Ports
Custom
Date:
Rev
0.2
1
Sheet
45
of
60
A
B
C
E
+3VALW TO +3VALW(PCH AUX Power)
+5VALW TO +5VS
+3VALW TO +3VS
+3VALW
+3VS
U38
S
1
R647
470K_0402_1%
@
C782
10U_0603_6.3V6M
2 SUSP
G
Q108
2N7002_SOT23
@
R03
C726
0.01U_0603_50V7K
SUSP
S
R650
0_0402_5%
Q111
2N7002_SOT23
2
G
2
1
@
1
@
C780
1U_0603_10V4Z
C783
10U_0603_6.3V6M
2 @
R777 @
470_0603_5%
D
S
1
2
2
@
R778
47K_0402_5%
R03
C727
0.01U_0603_50V7K
2 PCH_PWR_EN#
G
Q118 @
2N7002_SOT23
1
D
S
@
Q120
2N7002_SOT23
2
G
R779 @
0_0402_5%
1
2
1
PCH_PWR_EN#
3
2
2
D
1
1
1
2
1
@
U40
8
1
7
2
6
3
5
+VSB
2
3
10U
S
15VS_GATE_R
82K_0402_5%
Q110
2N7002_SOT23
2
G
JUMP_43X118
R645
470_0603_5%
@
2
D
2
C725
1U_0603_10V4Z
D
1
1
5VS_GATE 2 R649
3
SUSP
S
2
1
C724
10U_0603_6.3V6M
+VSB
2 SUSP
G
Q107
2N7002_SOT23
@
1
2
R646
150K_0402_5%
1
1
1
D
+3V_PCH
1
3
+VSB
2
@
4
10U
1
1 2
1
10U
C723
10U_0603_6.3V6M
R644
470_0603_5%
@
PJ1
2
3
2
C722
1U_0603_10V4Z
3
10U
1
C721
10U_0603_6.3V6M
U39
8
1
7
2
6
3
5
4
2
4
2
1
1 2
1
C720
10U_0603_6.3V6M
1
+3VALW
8
1
7
2
6
3
5
1
+5VS
1 2
+5VALW
D
@
C781
0.1U_0603_25V7K
+1.5V to +1.5VS
+5VALW
2
1
2
1
C719
1U_0603_10V4Z
1
3
S
3
C728
2
G
Q124
2N7002_SOT23
S
2
C729
0.1U_0603_25V7K
+1.5V to +1.5VS_VGA Transfer
1
+1.5V
IN
300mil(7.2A)
3
1
2
1
2
R1110 @
100K_0402_5%
J12
@
2
1
3
1
1
JUMP_43X118
C856 @
10U_0603_6.3V6M
AO4430: Rdson: 5.5mohm @ VGS=10V
2
U49
AO4304L_SO8
10U
2
8
7
6
5
300mil(7.2A)
1
2
3
1
1
4
C852
10U_0603_6.3V6M
10U
+5VALW
C851
10U_0603_6.3V6M
10U
2
2
3
SYSON
+1.5VS_VGA
OUT
@ Q119
<42,45,51> SYSON
IN
GND
2
SUSP#
1.5VS_GATE
1
1
2
2
0.1U_0603_25V7K
S
D
PCH_PWR_EN
<42,48> PCH_PWR_EN
C853
10U_0603_6.3V6M
2
1
C854
0.1U_0402_16V4Z
2
2
10U
R1101 @
470_0603_5%
1
3
10,25,42,51,52,53,54>
SYSON#
OUT
Q117
@
R654
100K_0402_5%
1
0_0402_5%
2
2
1
SUSP
1
<10,53,54> SUSP
1
@
R653
100K_0402_5%
R652
220K_0402_5%
2 R651
D
2 SUSP
G
Q109
2N7002_SOT23
@
R781
100K_0402_5%
GND
Check
Q112
SUSP# 2
G
2N7002_SOT23
1
2
100K_0402_5%
R648
+5VALW
1
+5VALW
2
+RTCVCC
PCH_PWR_EN#
D
+3VALW
For Intel S3 Power Reduction.
R643
470_0603_5%
@
1
10U
R780
100K_0402_5%
2
2
1
C718
10U_0603_6.3V6M
1
2
1
C717
10U_0603_6.3V6M
3
<10,42,53>
1
CPU1.5V_S3_GATE
2
1 2
+1.5VS
1
1
1
0_0402_5%
SUSP
2
G
Q115
2N7002_SOT23
S
3
S
3
3
S
3
2
@ R91
D
2 SUSP
G
Q116
2N7002_SOT23
@
Q8
PMV65XP_SOT23-3~D
2
R658
22_0603_5%
D
2 SYSON#
G
Q114
2N7002_SOT23
@
+1.5V
1
1
1 2
1 2
1 2
3
S
D
2 SUSP
G
Q113
2N7002_SOT23
@
R659
470_0603_5%
@
G
D
R656
470_0603_5%
@
D
R655
470_0603_5%
@
+0.75VS
S
2
+1.05VS
1
+1.5V
1
+1.8VS
1
+VSB
2
2 R782
1
0_0402_5%
S
SUSP
D
S
2
G
1
R02
R784 @
0_0402_5%
1
@ Q127
2N7002_SOT23
C855
0.1U_0603_25V7K
2
2 R791 @1
0_0402_5%
SUSP
4
R1108
100K_0402_5%
@
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
B
DGPU_PWROK#
2 R789 @1
0_0402_5%
A
@
2 R790
1
0_0402_5%
2
G
S
1
DGPU_PWROK#
1
1
Q129
2N7002_SOT23
1
4
Q126
2N7002_SOT23
<54>
D
2
G
3
<19,54> DGPU_PWROK
DGPU_PWROK#
3
DGPU_PWROK#
R1106
0_0402_5%
2
1
D
2
2
10K_0402_5%
1
3
R1102
2
R1107
100K_0402_5%
C
D
Title
DC Interface
Size
Document Number
Custom
Date:
Rev
0.2
LA-7981P
Sheet
E
46
of
60
5
4
3
PF101
7A_24VDC_429007.WRML
1
2 APDIN1
PL101
SMB3025500YA_2P
1
2
1
2
PC104
1000P_0402_50V7K
1
2
D
VIN
2
Unpop for KB9012
1
PJ101
@ JUMP_43X39
1 1
2 2
PR119
68_1206_5%
3
1
@
VS
PC113
0.1U_0603_25V7K
2
1
@
2
2
1
2
PR124
22K_0402_1%
1
2
@
<43> 51_ON#
PC112
0.22U_0603_25V7K
1
51ON-2
PR123
@
100K_0402_1%
+3VLP
PR118
68_1206_5%
2
PR120
200_0603_5%
1
2
1
C
PQ104
TP0610K-T1-E3_SOT23-3
CHGRTCP
51ON-1
1
@ PD104
LL4148_LL34-2
2
1
BATT+
C
@
PD103
LL4148_LL34-2
2
1
PC103
100P_0402_50V8J
2
@ 4602-Q04C-09R 4P P2.5
JDCIN1
2
1
1
2
1
D
PC102
100P_0402_50V8J
3
2
PC101
1000P_0402_50V7K
3
APDIN
4
1
VIN
DC030006J00
4
2
51ON-3
@
@
2
@
@
1
RTCVREF
PR127
0_0402_5%
PR128
200_0603_5%
1
@ PU102
2
APL5156-33DI-TRL_SOT89-3
2
B
VOUT
2 CHGRTCIN
VIN
@
GND
@
PC114
10U_0603_6.3V6M 1
PC115
1U_0805_25V6K
B
2
1
3
1
3.3V
@
+CHGRTC
-
JRTC2
+
2
1
@ MAXEL_ML1220T10
PR131
560_0603_5%
1
2
PR132
560_0603_5%
1
2
PD109
RB751V-40_SOD323-2
2
1
1
2
+RTCBATT
RTCVREF
PD108
RB751V-40_SOD323-2
RTC Battery
A
A
Compal Secret Data
Issued Date
2010/01/25
2012/07/11
Deciphered Date
5
4
3
2
Title
PWR DCIN / Vin Detector /Pre-charge
Custom
C38-G series Chief River Schematic
Date:
Sheet
1
47
of
60
Rev
0.1
5
4
VMB2
PL201
SMB3025500YA_2P
1
2
BATT+
1
1
2
PC201
1000P_0402_50V7K
2
2
1
PR202
100_0402_1%
D
PC202
0.01U_0402_25V7K
ADP_I need to write Charge Options Register (0x12H)=> bit6=1
0: IOUT is the 20x current amplifier output <default @ POR>
1: IOUT is the 40x current amplifier output
JBATT2
EC_SMB_DA1 <42,49>
VL
+3VALW
1
2 PR232 1
0_0402_5%
2
1
1
@ PR231
0_0402_5%
PR230
2
1
@ PR233
2
MAINPWON <42,50>
2
47K_0402_1%
1
47K_0402_1%
Turbo_V
PR213 0_0402_5%
@
90W(DIS) : PR205=4.42K
PR210=27.4K
65W(UMA) : PR205=402(SD034020080)
PR210=5.11K
1
PR209
10K_0402_1%
PH201
100K_0402_1%_NCP15WF104F03RC
2
@ PR227
0_0402_5%
<42>
PR212
0_0402_5%
2
2
27.4K_0402_1%
1
ADP_OCP_2 1
<42>
1
+3VALW
PR210
5
C
2
Turbo_V_2
6
1
3
PROCHOT
OT2 RHYST2
NTC_V_2
OTP_N_002
7
G718TM1U_SOT23-8
2 ADP_OCP_1
G
S SSM3K7002FU_SC70-3
<42>
OT1 TMSNS2
8
NTC_V
4
GND RHYST1
2
3
VCC TMSNS1
OTP_N_003
2
PR208
1
1
PQ201
D
100K_0402_1%
<6,42,49> H_PROCHOT#
2
PR211
2
PU201
1
C
@
10K_0402_1%
+3VS
PC203
0.1U_0603_16V7K
2
1
PR206
12.7K_0402_1%
A/D
1
BATT_TEMP <42>
PR205
4.42K_0402_1%
1
2
PR204
10K_0402_5%
ADP_I
2
1
PR207
21.5K_0402_1%
+3VLP
<42,49>
TYCO_1775789-1
@
2
1
2
PR203
6.49K_0402_1%
For KB930 --> Keep PU201 circuit
(Vth = 1.25V)
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205, PR211,PQ201,PR208,PR212
PH1 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
EC_SMB_CK1 <42,49>
1
1
2
3
4
5
6
7
8
9
2
TYCO_1775789-1
@
1
2
3
4
5
6
7
GND
GND
1
EC_SMCA
EC_SMDA
2
1
PR201
100_0402_1%
D
1
2
3
4
5
6
7
8
9
2
VMB
PF201
12A_65V_451012MRL
1
2
JBATT1
1
2
3
4
5
6
7
GND
GND
3
+3VLP
B
B
S
VL
A
1
PR224
1K_0402_5%
2
PR228
S
PCH_PWR_EN
1
2
<50>
2
RTCVREF
0_0402_5%
PR225
10K_0402_1%
@
<42>
1
PR229
@
20_0402_5%1
D
3
SPOK
S
1
1
2
2
1
PR216
100K_0402_1%
PQ204
2N7002W-T/R7_SOT323-3
2
G
PC207
1U_0402_6.3V6K
3
2
PR226
100K_0402_1%
2
G
1
PR223
10K_0402_1%
2
1
2VREF_8205
<50>
1
1
1
1
PQ203
D 2N7002KW_SOT323-3
1
@ PR222
100K_0402_1%
+3VLP
2
PC206
0.1U_0603_25V7K
2
2
G
PU202A
LM393DG_SO8
PR220
22K_0402_1%
1
2
PC205
0.22U_0603_25V7K
1
-
PQ202
D 2N7002KW_SOT323-3
<49>
+VSBP
2
2
1
BATT_OUT
1
2
2
1
2
1
3
B+
3
O
PQ205
TP0610K-T1-E3_SOT23-3
PR215
100K_0402_1%
8
2
+
4
2
3
PR221
221K_0402_1%
+3VALW
PR214
100K_0402_1%
<BOM Structure>
PR218
10M_0402_5%
1
PR219
10K_0402_1%
1
2
+3VLP
P
PR217
768K_0402_1%
G
1
2
2
VMB2
PC204
0.01U_0402_25V7K
1
P2
+VSBP
+VSB
A
BATT_LEN#
Compal Secret Data
Issued Date
2010/01/25
2012/07/11
Deciphered Date
5
PJ201
@ JUMP_43X39
1 1
2 2
4
3
2
Title
PWR-BATTERY CONN/OTP
Custom
Date:
Sheet
1
48
of
60
Rev
0.1
5
4
3
2
1
B+
P3
P2
PQ301
AO4407A_SO8
PQ303
AO4407A_SO8
DISCHG_G
VIN
2
PD301
PHASE
19
HIDRV
18
BTST
17
5
6
7
8
4
PC313
BQ24727VCC1
PU301
SDA
BQ24727RGRR_VQFN20_3P5X3P5
2
PL302
10UH_PCMB104E-100MS_5.5A_20% PR320
0.01_1206_1%
PD303
REGN
16
4
2
1
2
1
3
2
1
BQ24727VDD
DL_CHG
PC320
0.1U_0603_25V7K
2
1
B
2
1
15
14
PR328
10_0603_5%
13
1
2
11
6.8_0603_5%
1 12
PR327
RB751V-40_SOD323-2
PC318
1U_0603_25V6K
2
BATT+
CHG
1
4
2
3
PR322
4.7_1206_5%
PR324
PC314
2.2_0603_5%
0.047U_0603_16V7M
1
2
2
1
BST_CHG
16251_SN
2
LODRV
SRP
1
DH_CHG
2
SRN
BM
PR326
100K_0402_1%
1U_0603_25V6K
LX_CHG
SA000051W00
C
SRP
SRN
PC317
10U_0805_25V6K
2
1
20
PACIN
PC316
10U_0805_25V6K
2
1
VCC
PQ310
AO4466L_SO8
21
1
ACN
TP
PR319
10_1206_5%
2
1
2
ACP
3
CMPIN
CMPOUT
<BOM Structure>
2
G
S
3
1
2N7002W -T/R7_SOT323-3
1
PC311
0.1U_0603_25V7K
2
1
2
D
PC319
680P_0603_50V7K
ILIM
1
1DISCHG_G-1
1
PQ309
P2
PQ312
AO4466L_SO8
SCL
10
PD302
1SS355_SOD323-2
2
PC310
0.1U_0603_25V7K
3
2
1
9
1
3
PR310
2
1
10K_0603_1%
2
5
6
7
8
<42,48> EC_SMB_CK1
PR306
200K_0402_1%
1
0.1U_0603_25V7K
IOUT
100P_0603_50V8
8
PR323
1
2
316K_0402_1%
PQ306
DTC115EUA_SC70-3
1
5
7
ACDET
<42,48> EC_SMB_DA1
+3VALW
2
2
3
S
PC312
1
2
PC323
0.1U_0603_25V7K
3
2
1
D
6
2N7002KW_SOT323-3
PQ313
2
G
BATT_OUT
ADP_I
@
64.9K_0603_1%
PR321
1
2ACOFF-12
10K_0402_5%
PC309
39.2K_0402_1%
1
@
PR325
0_0402_5%
<48>
PR309
2
<42,48>
2
2
PR313
@
@
1
2
4.7M_0603_1%
1
ACOK
PR315
10K_0402_5%
1
2
PR316
10K_0402_5%
1
2
2
1
390K_0603_1%
PR314
PR317
1
@ PR312
2
100K_0402_1%
@
VIN
1
ACOFF
<48>
1
<42>
1
S
2
PQ311
DTC115EUA_SC70-3
1
ACON
+3VALW
ACPRN
3
1
5
PR308
150K_0402_1%
2
P2-2
3
PQ307B
PR318
47K_0402_1%
1
2
PACIN
4
PACIN
PQ308
2N7002KW _SOT323-3
2
BATT_OUT
G
D
2N7002KDW-2N_SOT363-6
1
C
1 2
3
6
PQ307A
2N7002KDW -2N_SOT363-6
2
<50>
PR307
20K_0402_1%
4
DTC115EUA_SC70-3
PC308
GND
1
+3VALW
0.1U_0603_25V7K
1
P2-1
PR305
47K_0402_1%
1
2
1
ACP
PQ305
D
PR304
200K_0402_1%
1
2
ACN
2
8
7
6
5
4
1
2
3
2ACOFF-1
3
1SS355_SOD323-2
2
PC307
2200P_0402_50V7K
4
PC306
4.7U_0805_25V6-K
1
2
2
1
2
2
PC304
5600P_0402_25V7K
1
1
2
PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%
2
3
2
1
PR301
47K_0402_5%
1
DTA144EUA_SC70-3
B+
1
PC305
4.7U_0805_25V6-K
1
2
PL301
1UH_PCMB061H-1R0MS_7A_20%
PQ304
D
2
2
1
PR302
0.01_1206_1%
1
SH00000AA00
PC303
4.7U_0805_25V6-K
1
2
8
7
6
5
PC315
@ 10U_0805_25V6K
1
2
3
4
1
2
3
4
8
7
6
5
PC302
@ 10U_0805_25V6K
VIN
PQ302
AO4423L_SO8
B
0V
1
CHGVADJ
PC321
0.1U_0603_25V7K
2
4V
2
Vcell
1
CHGVADJ=(Vcell-4)/0.10627
4.2V
1.882V
4.35V
3.2935V
@
PC322
0.1U_0603_25V7K
BQ24727VDD
PR337
10K_0402_1%
1
2
PR336
10K_0402_1%
PR335
47K_0402_1%
<50>
PQ316
1
ACPRN
D
3
2
G
A
ACIN
<16,42>
PACIN
S
1
PR339
2
2
VCHLIM need over 95mV
2
IREF=0.254V~3.048V
2N7002KW_SOT323-3
IREF=1.016*Icharge
1
1
CC=0.25A~3A
12K_0402_1%
A
For disable pre-charge circuit.
2010/01/13
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
5
4
3
2
Title
CHARGER
Size
Document Number
Rev
0.1
Date:
Sheet
1
49
of
60
5
4
3
2
1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205
PJ402
2
+3VALW P
2
1
1
+3VALW
PC401
1U_0603_10V6K
@ JUMP_43X118
1
D
PJ403
2
+5VALW P
2
D
@
RT8205_B+
PJ401
PR403
20K_0402_1%
1
2
PR404
19.6K_0402_1%
1
2
+5VALW
21
UG_5V
PHASE1
20
LX_5V
LGATE2
LGATE1
19
LG_5V
PQ402
3
2
1
1
2
1
2
3
2
1
PC419
680P_0603_50V7K
PC421
4.7U_0805_10V6K
1
2
1
2
PC422
0.1U_0603_25V7K
Typ: 175mA
+5VALWP
1
+
4
TPC8A03-H_SO8
PC420
1U_0603_10V6K
2
1
2VREF_8205
5
4
2
PR410
4.7_1206_5%
5
6
7
8
PQ404
NC
RT8205EGQW _W QFN24_4X4
18
VIN
VREG5
17
EN
13
PL402
4.7UH_PCMB104E-4R7MS_5.5A_20%
1
2
VL
RT8205_B+
C
TPC8065-H_SO8
UGATE1
PHASE2
VFB=2.0V
5
6
7
8
PC410
0.1U_0603_25V7K
2
1
PC409
2200P_0402_50V7K
2
1
PC408
4.7U_0805_25V6-K
2
1
1
3
4
2
FB1
REF
FB2
PC407
4.7U_0805_25V6-K
2
1
ENTRIP1
ENTRIP2
5
6
UGATE2
<48>
1
3
ENTRIP2
6
PQ405A
2N7002KDW -2N_SOT363-6
PR413
0_0402_5%
2
1
PR408 PC413
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2
PQ405B
2N7002KDW -2N_SOT363-6
1
<42,48> MAINPWON
22
16
8
7
6
5
ENTRIP1
PR418
2.2K_0402_5%
2
1
23
BOOT1
SPOK
B+
B
For KB9012
PGOOD
BOOT2
PR411
499K_0402_1%
1
2
2
2
12
VREG3
4
PC415
150U_B2_6.3VM_R45M
PC418
680P_0603_50V7K
2
1
+
PQ403
AO4712_SO8
PR412
100K_0402_1%
1
LG_3V
1
2
3
+3VALWP
PR409
4.7_1206_5%
2
1
PL401
4.7UH +-20% PCMC063T-4R7MN 5.5A
1
2
4
24
GND
1
2
3
8
PR407
2 1
2 BST_3V 9
2.2_0603_5%
PC412
UG_3V 10
0.1U_0603_25V7K
LX_3V
11
1
<42,43> EC_ON
1
RT8205_B+
VO1
VO2
SKIPSEL
7
PR406
66.5K_0402_1%
2
ENTRIP1
4
TONSEL
P PAD
15
25
1
14
AO4466L_SO8
PU401
1
PQ401
2
PC411
4.7U_0805_10V6K
8
7
6
5
PC403
4.7U_0805_25V6-K
2
1
C
PR405
130K_0402_1%
1
2
ENTRIP2
+3VLP
1
1
PC406
2200P_0402_50V7K
2
1
2
@ JUMP_43X118
PC404
4.7U_0805_25V6-K
2
1
2
PR402
30K_0402_1%
1
2
1
Typ: 175mA
PC402
0.1U_0603_25V7K
2
1
PC405
0.1U_0603_25V7K
2
1
B+
PR401
13K_0402_1%
1
2
2
JUMP_43X118
PC417
150U_B2_6.3VM_R45M
2
B
+3.3VALWP OCP(min)=5.81A
+5VALWP OCP(min)=8.44A
PR414
100K_0402_1%
2
1
2
PQ408
DTC115EUA_SC70-3
3
@
A
3
@
PQ406
DTC115EUA_SC70-3
2
PC423
4.7U_0603_6.3V6M
EC_ON
2
PR416
100K_0402_1%
1
1
@
1
2
S
VS
A
<42,43>
D
2
G
2
1
PR417
40.2K_0402_1%
PR415
200K_0402_1%
2
1
1
ACPRN
PQ407
2N7002W-T/R7_SOT323-3
49>
3
1
VL
2010/01/25
Issued Date
For KB9012
@
5
Compal Secret Data
@
4
Deciphered Date
2012/07/11
3
2
Title
3VALWP/5VALWP
Size
Document Number
Custom
Date:
Sheet
1
50
of
60
Rev
0.1
A
B
C
D
1.5V_B+
PC505
2
1
2200P_0402_50V7K
PC504
2
1
0.1U_0402_25V6
B+
2
1UH_FDSD0412-H-1R0M-P3_3.3A_20%
PL502
3
2
1
4
PC503
10U_0805_25V6K
2
1
PQ501
TPC8065-H_SO8
PC502
10U_0805_25V6K
2
1
5
6
7
8
1
1
PGOOD
VBST
10
BST_1.5V
2
TRIP
DRVH
9
DH_1.5V
3
EN
SW
8
LX_1.5V
4
VFB
V5IN
7
DRVL
6
PR503
PC506
2.2_0603_5%
0.22U_0603_16V7K
1
2BST_1.5V-1 1
2
PL501
1UH_PCMC063T-1R0MN_11A_20%
1
2
TP
+5VALW
DL_1.5V
PQ502
11
PC508
1U_0603_10V6K
4
1
TPS51212DSCR_SON10_3X3
2
VFB=0.7V
TPC8A03-H_SO8
2
3
2
1
1
11.5K_0402_1%
+
PC507
220U_6.3V_M
+1.5VP OCP(min)=15.6A
2
PJ502
2
@
2
1
1
JUMP_43X118
PJ503
+1.5VP
2
@
2
PR508
10K_0402_1%
1
+1.5VP
1
2
RF
470K_0402_1%
PR507
1
5
1
PR5062
1
2
1
2
PC501 @
.1U_0402_16V7K
2
5
6
7
8
2
1
PR502
47K_0402_5%
<42,45,46> SYSON
PR501
0_0402_5%
1
2
1
1
PR505
PR504
4.7_1206_5%
PU501
100K_0402_1%
PC509
1000P_0603_50V7K
1
2
+1.5V
1
1
JUMP_43X118
2
2
3
3
1
2
PR512
1M_0402_5%
1
2
1
2
PC514
22U_0805_6.3VAM
2
SY8033BDBC_DFN10_3X3
PR510
20K_0402_1%
PC511
68P_0402_50V8J
2
1
FB=0.6Volt
1
6
+1.8VSP
PC513
22U_0805_6.3VAM
1
2
0_0402_5%
NC
TP
EN_1.8VSP
PC515 @
0.1U_0402_10V7K
2
11
PR511
1
7
<10,25,42,46,52,53,54> SUSP#
FB
2
EN
3
PJ504
+1.8VSP
2
2
@
1
+1.8VS
1
JUMP_43X118
1.8VSP max current=4A
1.8VSP_FB
1
SVIN
5
LX
1.8VSP_LX
1
8
2
1 2
PVIN
LX
PC512
PR509
680P_0603_50V7K 4.7_1206_5%
9
2
PC510
22U_0805_6.3VAM
PVIN
NC
JUMP_43X118
10
1
1.8VSP_VIN
1
PG
1
1
@
2
PL503
1UH_PH041H-1R0MS_3.8A_20%
1
2
4
PU502
PJ505
2
+5VALW
PR513
10K_0402_1%
4
2
4
Compal Secret Data
Issued Date
2010/01/25
Deciphered Date
2012/07/11
A
B
C
Title
PWR-+1.5VP/+1.8VSP
Custom
Date:
D
Sheet
51
of
60
Rev
0.1
4
3
+3VS
PR602
100K_0402_5%
1
H_VCCSA_VID1
13
11
+VCCSA_PHASE
PR606
PC603
0_0603_5%
0.22U_0603_16V7K
2+VCCSA_BT_1 1
2
PL601
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
1
PC605
22U_0805_6.3V6M
1
2
PGND
1
SW
TPS51461RGER_QFN24_4X4
VIN
VIN
24
7
+VCCSAP
@
@
PC604
1000P_0603_50V7K
@
@
TP
25
6
COMP
VREF
3
1
GND
JUMP_43X118
MODE
VIN
VOUT
+VCCSA_PWR_SRC
SLEW
+VCCSA_PWR_SRC
1
5
1
SW
2
@
C
2
8
1
SW
23
4
2
9
2
SW
PJ601
+3VALW
PR607
4.7_1206_5%
PGND
22
1
10
PC612
22U_0805_6.3V6M
1
2
+VCCSA_BT 1
PC611
22U_0805_6.3V6M
1
2
EN
12
PC610
2200P_0402_50V7K
2
1
14
BST
SW
21
2
+VCCSA
1
2
2
10U_0805_6.3V6M
PC616
10U_0805_6.3V6M
PC615
2
0.1U_0603_25V7K
PC614
1
2
2200P_0402_50V7K
PC613
1
1
D
PC609
22U_0805_6.3V6M
1
2
PGND
20
2
JUMP_43X118
+V1.05S_VCCP_PWRGOOD <53>
PC608
22U_0805_6.3V6M
1
2
19
V5FILT
V5DRV
PU601
@
<10>
PR605
0_0402_5%
1
2
+VCCSA_EN
PGOOD
PC602
2.2U_0603_10V7K
1
2
2
+VCCSAP
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
+VCCSA_VID0
+VCCSA_VID1
15
17
2
1
18
PC601
1U_0603_10V6K
PR604
10_0402_1%
2
1
16
+VCCSA_PWRGD
+5VALW
VID1
output voltage adjustable network
D
H_VCCSA_VID0
PJ602
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A
<10>
PR603
1K_0402_5%
2
1
VID0
<42> SA_PGOOD
1
PC607
0.1U_0402_10V7K
2
1
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
2
VID[1]
0
1
0
1
+VCCSA_PWRGD
VID [0]
0
0
1
1
2
PR601
1K_0402_5%
2
1
PC606
22U_0805_6.3V6M
1
2
5
C
@
PR608
2
1
33K_0402_5%
PC617
2
1
PR609
100_0402_5%
2
1
5
SW
VFB
V5IN
RF
DRVL
BST_+V1.05S_VCCPP
@
@
UG_+V1.05S_VCCPP
9
1
@
@
@
PL602
1UH_PCMC063T-1R0MN_11A_20%
1
2
3
2
1
10
@
8
SW_+V1.05S_VCCPP
7
+V1.05S_VCCPP_5V
6
LG_+V1.05S_VCCPP
@
TPC8A03-H_SO8
2
@
PC628
1000P_0603_50V7K
2
3
2
1
2
PR619
2
1000P_0402_50V7K
B
+V1.05S_VCCPP
PJ604
2
@
2
+V1.05S_VCCP
1
1
JUMP_43X118
@
PR618
@
1
PC623
4.7U_0805_25V6-K
+V1.05S_VCCPP
@
PC629
JUMP_43X118
PR617
4.7_1206_5%
@
2
B+
@
4
@
1
@
2
PC626
1U_0603_6.3V6M
1
PR616
470K_0402_1%
1
PQ602
11
TPS51212DSCR_SON10_3X3
@
2
+5VALW
1
4
RF_+V1.05S_VCCPP
EN
TP
2
@ @ PC625
0.1U_0402_16V7K
FB_+V1.05S_VCCPP
DRVH
1
@
3
VBST
TRIP
PC627
SUSP#
1
<10,25,42,46,51,53,54>
EN_+V1.05S_VCCPP
PGOOD
1
B
2
2
PR615
0_0402_5%
1
2
1
5
6
7
8
@
4
2
0.1U_0402_10V7K
PU602
TRIP_+V1.05S_VCCPP
PC624
0.22U_0603_16V7K
1
2
PR613
1
2
0_0603_5%
1
<53> +V1.05S_VCCP_PWRGOOD
PR614
1
2
66.5K_0402_1%
PC620
0.1U_0402_25V6
2
1
2
PQ601
TPC8037-H_SO8
PR612
100K_0402_5%
+VCCSA_SENSE <10>
PJ603
+V1.05S_VCCPP_B+
5
6
7
8
+3VS
PR611
0_0402_5%
2
1
1
1
2
2
PR610
5.1K_0402_1%
PC622
4.7U_0805_25V6-K
2
1
1
PC621
2200P_0402_50V7K
2
1
2
PC618
3300P_0402_50V7K
PC619
0.01U_0402_25V7K
1
2
0.22U_0402_10V6K
1
@
+
@
1
1.2K_0402_1%
PC631
150U_B2_6.3VM_R45M
2
PR620
0_0402_5%
2
1
4.32K_0402_1%
2
1
@
VCCIO_SENSE <9,53>
+3VS
@
VCCP_PWRCTRL = "High" ,
VCCP_PWRCTRL = "Low" ,
2
1
Vo = 1.05V (SNB)
Vo = 1V (IVB)
PR623
100K_0402_5%
1
D
@
@
S
1
2
PC630
.01U_0402_16V7K
1
2
2
G
3
PQ603
@
A
SSM3K7002FU_SC70-3
1
1
PR622
71.5K_0402_1%
2
2
@
PR621
10K_0402_1%
PR624
0_0402_5%
2
1
A
VCCP_PWRCTRL <10>
PR625
100K_0402_5%
@
Compal Secret Data
@
@
Issued Date
2010/01/25
Deciphered Date
2012/07/11
@
Title
PWR +VCCSAP/1.0
Size
C
Date:
5
4
3
2
Document Number
Sheet
1
52
of
60
Rev
0.1
5
4
3
2
1
1
1
+1.5V
PJ701
JUMP_43X118
@
D
2
2
D
PU701
@ PR719
7
3
VREF VCNTL
6
4
VOUT
NC
5
TP
9
+3VALW
PJ702
2
+0.75VSP
1
8
NC
@
1
+0.75VS
PJ703
2
2
1
1
JUMP_43X118
PJ704
2 2
1 1
@
+1.05VS_VCCPP
PC706
10U_0603_6.3V6M
2
1
1
1U_0603_10V6K
+0.75VSP
PC705
10U_0603_6.3V6M
2
1
2
PR704
2
JUMP_43X118
PC703
2
2
PC704
.1U_0402_16V7K
2
1
S
1
D
NC
GND
APL5336KAI-TRL_SOP8P8
2
G
PC701
0.1U_0402_10V7K
2
1
<10,46,54> SUSP
1
PR703
49.9K_0402_1%
1
2
3
PQ701
2N7002W -T/R7_SOT323-3
1K_0402_1%
<10,46,54> CPU1.5V_S3_GATE
PR702
1K_0402_1%
1
0_0402_5%
1
2
VIN
2
1
2
PC702
4.7U_0805_6.3V6K
1
@
+1.05VS
JUMP_43X118
PJ605 @
2
+1.05VS
C
2
2
1
+V1.05S_VCCP
1
JUMP_43X118
PJ606 @
2
1 1
C
JUMP_43X118
Ivy Bridge CPU ES2 Using
LX_1.05VS_VCCP
GSNS
DH
11
DL
10
DH_1.05VS_VCCP
1
3
TPS51219RTER_QFN16_3X3
PQ703
TPCA8057-H_PPAK56-8-5
2
DL_1.05VS_VCCP
1
2
1
2
10_0402_1%
@
1
PC713
1U_0603_10V6K
3
2
1
<BOM Structure>
2
PGND
+5VALW
2
10_0402_1% 0.01UF_0402_25V7K
2
9
8
7
TRIP
6
PR711
75K_0402_1%
2
1
PR714
1
2
5
PC712
PR716
1
GND
V5
COMP
VSNS
1
4
4
PC717
4.7U_0805_25V6-K
2
1
1
1
B+
B
+1.05VS_VCCPP
1
PC715
PR712
1000P_0603_50V7K 4.7_1206_5%
REFIN
PC719
4.7U_0805_25V6-K
2
1
TPCA8065-H_PPAK56-8-5 PL701
1.0UH +-20% PCMC104T-1R0MN 20A
PC709
330U_X_2VM_R6M
12
3
2
1
SW
5
2
2
2
JUMP_43X118
BST
EN
MODE
PGOOD
PAD
VREF
PC720
0.01UF_0402_25V7K
2
@
4
0_0402_5%
<9,52> VCCIO_SENSE
PC714
0.1U_0402_25V6
2
1
13
14
1
PQ702
2
1
12K_0402_1%
15
16
17
10.7K_0402_1%
PR707
2
1
2
1
PC710
0.1U_0603_25V7K
1
2
1
1
PR708
2
VSSIO_SENSE_L
<9,52>
PR717
PC708
0.1U_0402_25V6
2
1
B
PU702
5
PR713
2.2_0603_5%
BST_1.05VS_VCCP
1
2
PC718
2200P_0402_50V7K
2
1
100K_0402_1%
PJ705
1.05VS_B+
1
PR706
2
PR705
100K_0402_1%
2
1
2
PR715
0_0402_5%
1
2
<52> +V1.05S_VCCP_PW RGOOD
+1.05VS_VCCPP OCP(min)=20.75A
+3VS
PC707
.1U_0402_16V7K
1
PR709
2
1,52,54> SUSP#
@ 10K_0402_1%
PR710
60.4K_0402_1%
1
2
1
+
2
PC716
1000P_0402_50V7K
PR718
A
1
A
2
1
2
10_0402_1%
PC721
1000P_0402_50V7K
Compal Secret Data
2010/01/25
Issued Date
Deciphered Date
2012/07/11
5
4
3
2
Title
PWR +1.05VS_VCCPP/+0.75VSP
Size
Document Number
Custom
Date:
Sheet
1
53
of
60
Rev
0.1
A
B
C
D
2
2
1
PC804
10U_0805_25V6K
2
1
5
PC803
10U_0805_25V6K
3
2
1
1
PR809
10K_0402_1%
PR810
1_0402_1%
1
+
2
2
1
PR808
3.65K_0805_1%
2
1
2
+VGA_COREP
2
SNUB2_VGA
1
5
3
2
1
@4.7_1206_5%
4
V2N_VGA
3
<BOM
Structure>
2
1
+
PC808
330U_D2_2V_Y
3
PC802
2200P_0402_50V7K
2
1
PC801
0.1U_0402_25V6
2
1
1
2
<23>
<23>
GPU_VID0
<23>
5
3
2
1
@
PR807
2 @
VSUM-_VGA
VSUM+_VGA ISEN2_VGA
1
2
PC809
@680P_0402_50V7K
Under VGA Core
2
Near VGA Core
1
PC819
22U_0805_6.3V6M
2
1
PC820
47U_0805_4V6
2
1
PC821
22U_0805_6.3V6M
2
1
PC822
4.7U_0805_6.3V6K
PC833
4.7U_0805_6.3V6K
2
1
PC834
4.7U_0805_6.3V6K
2
1
PC835
4.7U_0805_6.3V6K
1
2
+VGA_B+
BOOT1_1_VGA
1
1
+VGA_CORE
3
JUMP_43X118
2
1
PC855
10U_0805_25V6K
2
1
4
PC856
0.22U_0603_10V7K
1
2
2
JUMP_43X118
PJ803
2
1
2
1
+VGA_COREP
3
2
1
PR827
2.2_0603_5%
2
1
PC854
10U_0805_25V6K
UGATE1_VGA
PC853
2200P_0402_50V7K
2
1
PC852
0.1U_0402_25V6
2
1
5
PQ804
PL804
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PHASE1_VGA
1
LF1_VGA
@
SNUB1_VGA
3
2
1
<BOM Structure>
4
+VGA_COREP
1
+
2
PC861
330U_D2_2V_Y
2
PC860
330U_D2_2V_Y
1
1
PR833
1_0402_1% +
2
2
1
V1N_VGA
3
<BOM
Structure>
PR832
10K_0402_1%
@4.7_1206_5%
2
VSUM-_VGA
VSUM+_VGA
ISEN1_VGA
1
2
Layout Note:
Place near Phase1 Choke
4
2
PR830
4
3
2
1
1
LGATE1_VGA
PR831
3.65K_0805_1%
2
1
1
5
5
PQ806
PQ805
VSUM-_VGA
4
PC865
@680P_0402_50V7K
PC866
0.1U_0402_16V7K
2
POP:PR815,PC803
PC832
4.7U_0805_6.3V6K
2
1
PC818
4.7U_0603_6.3V6M
PC846
@0.1U_0402_10V7K
PJ802
2
@
@
PH801
10K_0402_1%_TSM0A103F34D1RZ
PR837
1K_0402_1%
1
2
PC817
4.7U_0603_6.3V6M
2
1
PC831
4.7U_0603_6.3V6M
PC845
@0.1U_0402_10V7K
2
1
PC816
4.7U_0603_6.3V6M
2
1
PC830
4.7U_0603_6.3V6M
2
1
PC844
@0.1U_0402_10V7K
2
1
PC815
4.7U_0603_6.3V6M
2
1
PC829
4.7U_0603_6.3V6M
2
1
PC843
0.1U_0402_10V7K
2
1
PC814
4.7U_0603_6.3V6M
2
1
PC828
4.7U_0603_6.3V6M
2
1
PC842
0.1U_0402_10V7K
2
1
PC813
4.7U_0603_6.3V6M
2
1
PC827
4.7U_0603_6.3V6M
2
1
PC841
0.1U_0402_10V7K
2
1
PC812
4.7U_0603_6.3V6M
2
1
PC826
4.7U_0603_6.3V6M
2
1
PC840
0.1U_0402_10V7K
2
1
1
PC811
4.7U_0603_6.3V6M
2
1
2
1
1
2
@
2
<24>
PR828
2.61K_0402_1%
NTC_VGA
2
1
PR834
11K_0402_1%
2
1
PC859
0.033U_0603_25V7K
2
1
PC858
0.22U_0603_10V7K
2
1
1
PR826
@82.5_0402_5%
2
1
PC864
@0.01U_0402_25V7K
2
1
2
1
PC863
@330P_0402_50V7K
2
1
<42>
PC825
4.7U_0603_6.3V6M
2
1
2
VSSSENSE_VGA
GPU_IMON
PC839
0.1U_0402_10V7K
2
1
+5VS
1
2
@:PR806,PR812,PC823,PC848,PC849,PR832,
PC801,PC802,PQ801,PQ802,PQ803,PR804,
PC805,PC803,PR808,PR809,PR810,PC807,
PC804
4
For N13M-GE(15W without turbo)
2
PC862
1000P_0402_50V7K
VSUM_VGA_N001
2
PR836
10_0402_5%
1
2
1
LF2_VGA
PQ803
PC807
330U_D2_2V_Y
1
1
1
1
2
PC874
2
1
0.047U_0402_16V7-K
1
2
PR850
11.3K_0402_1%
+5VS
PC851
0.22U_0603_25V7K
PC850
1U_0603_10V6K
2
1
1
2
1
1
PR835
0_0402_5%
1
2
@ 0_0402_5%
2
1
2
PR866
0_0402_5%
VSUM+_VGA
PR825
10_0402_5%
PC857
330P_0402_50V7K
4
2
4
1
2
1
VDD_VGA
1
0_0402_5%
2
+VGA_B+
PR823
1_0402_5%
1
2
2
PR829
0_0402_5%
<24> VSSSENSE_VGA
+5VS
PC824
1U_0603_10V6K
PR819
PR821
VIN_VGA 1
PC849
0.22U_0402_10V6K
2
PR814
1
2
0_0402_5%
VCCP_VGA
VSUM-_VGA
<24> VCCSENSE_VGA
4
BOOT1_VGA
2
PR824
68.1K_0402_1%
1
PQ802
PC871
1U_0603_10V6K
IMON_VGA
ISEN1_VGA
+VGA_COREP
PL803
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PHASE2_VGA
VSEN_VGA
2
PR822
33K_0402_1%
UGATE2_VGA
ISL62883CHRTZ-T_TQFN40_5X5
For 15W one phase
ISEN2_VGA
2
4
PC805
0.22U_0603_10V7K
1
2
BOOT2_2_VGA
B+
2
40
39
38
37
36
35
34
33
32
31
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
@ PR865
0_0402_5%
2
1
@ PR815
0_0402_5%
2
+5VS
1
PC847
150P_0402_50V8J
PR820
1.15K_0402_1%
1
2
1
1
3
2FB2_VGA1
AGND
390P_0402_50V7K
PC838
100P_0402_50V8J
1
2
1
PR818
499_0402_1%
PC837
2FB1_VGA1
2
41
30
29
28
27
26
25
24
23
22
21
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
PC836
1000P_0402_50V7K
1
2
PR817
8.06K_0402_1%
2
1
PR816
@249K_0402_1%
1
2
PC823
22P_0402_50V8J
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
11
12
13
14
15
16
17
18
19
20
COMP_VGA
FB_VGA
2ISEN3_VGA
1
1
2
3
4
5
6
7
8
9
10
RTN_VGA
ISUM-_VGA
VW_VGA
PH802
1
BOOT2_VGA
1
1
1
+VGA_CORE
PC848
0.22U_0402_10V6K
PR871
1
PR804
2.2_0603_5%
2
1
+VGA_CORE
PU801
@
470K_0402_5%_TSM0B474J4702RE
2
1
2
4.02K_0402_1%
PR849 @
0_0402_5%
2
JUMP_43X118
<BOM Structure>
2
PR869
@
0_0402_5%
@
SUSP
PR812
100K_0402_5%
2
RBIAS_VGA
PSI#_VGA
1
2
LGATE2_VGA
2
@ PR870
100K_0402_5%
1
2
+3VS
0.1U_0603_25V7K
PR813
147K_0402_1%
2
1
2
<23,42> VGA_AC_DET
3
<23>
PR801
0_0402_5%
<19,46> DGPU_PWROK
1
1
1
CLK_ENABLE#_VGA
GPU_VID5
0.1U_0402_16V7K
PR811
1.91K_0402_1%
+3VS
2
G
2
@
DGPU_PWROK# <46>
SUSP <10,46,53>
PR847
0_0402_5%
1
2
@ PR806
1.91K_0402_1%
1
2
PJ801
PR851
0_0402_5%
1
2
N13P-GL:0.95V(VID5~0=101100)->NV by 2011.12.12
N13M-GE:0.875V(VID5~0=110010)->NV by 2011.11.3
S
PR843
0_0402_5%
1
2
PC806
DPRSLPVR_VGA
GPU_VID6
1
PR805
10K_0402_1%
1
2
+VGA_B+
PQ808
2N7002KW_SOT323-3
@
PQ801
PR842
0_0402_5%
1
2
1
PC869
10U_0805_10V6K 1U_0603_10V6K
2
G
2
2@ PR863 1
47K_0402_5%
2
D
GPU_VID1
<23>
2
+1.05VS_VGA
PQ809
2N7002KW_SOT323-3
GPU_VID2
1
1
1
S
PR841 @
0_0402_5%
DPRSLPVR_VGA
+3VS
SUSP
PR848
0_0402_5%
2
2
@
PR838
470_0603_1%
D
PR846
0_0402_5%
1
2
10K_0402_5%
2
PR862
GPU_VID0
1
<10,25,42,46,51,52,53>
SUSP#
1
10K_0402_5%
2
PR861
GPU_VID1
1
<10,25,42,46,51,52,53>
2
10K_0402_5%
2
PR860
GPU_VID2
1
<18> NVDD_PWR_EN
PC868
2
@ JUMP_43X118
PC870
1
2
PR802
147K_0402_1%
1
2VRON_VGA
PD809
1
2
RB751V-40_SOD323-2
@
1 PR803 2
@0_0402_5%
PR839
100K_0402_5%
1
2
GPU_VID3
<23>
10K_0402_5%
2
PR859
GPU_VID3
1
RB751V-40_SOD323-2 1
TPC8A03-H_SO8 PQ807
PR845
0_0402_5%
1
2
10K_0402_5%
2
PR858
GPU_VID4
1
<46> DGPU_PWROK#
<10,46,53> SUSP
PD808
PJ806
+1.05VS
1
2
3
PR840
20K_0402_1%
PR844
0_0402_5%
1
2
10K_0402_5%
2
PR857
1
@
2
10K_0402_5%
2
@
+1.05VS_VGA
8
7
6
5
1
10K_0402_5%
2
PR856
GPU_VID0
1
@
PC867
10U_0805_10V6K
1
10K_0402_5%
2
PR855
GPU_VID1
1
@
1
+1.05VS
+5VALW
GPU_VID4
10K_0402_5%
2
PR854
1
@
GPU_VID5
10K_0402_5%
2
PR864
GPU_VID3
1
@
GPU_VID2
10K_0402_5%
2
PR852
GPU_VID4
1
GPU_VID5
PR853
1
+3VS_VGA
PR816->120K(SD034120380)
PR820->1.69K(SD00000JB80)
PR822->22K(SD034220280)
PR837->866(SD034866080)
PC858->0.1uF(SE026104M80)
PC859->0.068uF(SE026683K80)
PR850->22.1K(SD034221280)
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2012/07/11
Title
PWR - VGA_COREP
Size
B
C
Document Number
Rev
0.1
C38 Chief River Schematic
Date:
A
D
Sheet
54
of
60
5
4
3
2
1
PC902
2
CSREFA
63.4K_0603_1%
806_0402_1%
PR955
2
DROOP
PC937
1
2
2
HG1
BST1
A
<42>
<56>
PC922
2
0.22U_0603_25V7K
SW1
<56>
CSP2A
1
Option for
2 phase CPU
PR935
0_0402_5%
1
3Phase: @
2Phase: install
2
CSP3
PR941
1 6.98K_0402_1%
2
CSP2
B
SWN2
<56>
SWN1
<56>
TSENSE
PR960 @
6.98K_0402_1%
PC932
1000P_0402_50V7K
PC931
1500p0.047U_0402_16V7K
3P:
2P: 1200p
CSSUM
PC934
2
1000P_0402_50V7K
CSREF
2 PC936
680P_0402_50V7K
PR9452
6.98K_0402_1%
1
PR961 @
6.98K_0402_1%
2
CSP1
<56>
PR946 1
CSREF
CSREF
PH902
100K_0402_1%_TSM0B104F4251RZ
1
PR949 2
130K_0603_1%
SWN1
1
PR951 2
130K_0603_1%
SWN2
PUT COLSE
TO VCORE
HOT SPOT
1 PR952 2NTC_PH201 1 PR953 2
75K_0402_1%
165K_0402_1%
PH903
2
1
220K_0402_5%_ERTJ0EV224J
A
IMVP_IMON
Issued Date
Compal Secret Data
2009/12/01
2012/07/11
Deciphered Date
4
PR928
0_0402_5%
PC924
2
.1U_0402_16V7K
5
Option for
1 phase GFX
6132_PWM
1
2Phase: @
1Phase: install
1
SW2
2
<56>
3P: 73.2K
2P: 41.2K
PR934 2
41.2K_0402_1%
TSENSE
CSCOMP
PUT COLSE
TO VCORE
Phase 1
Inductor
+5VS
SW1A
+5VS
<56>
<56>
PR931 2 BST1_1 1
1
2.2_0603_5%
PC927
0.047U_0402_16V7K
1
CSREF
1000P_0402_50V7K
3P: 806
2P: 1K
<56>
PR930 2
1
0_0402_5%
LG1
3P: 21K
2P: 12.4K
3P: 3.65K
2P: 9.53K
3P: 23.7K
2P: 24.9K
1K_0402_1%
LG2
6132P_VCCP
PC919
2
0.22U_0603_25V7K
PC920
1
2
2.2U_0603_10V7K
CSP1
CSP2
CSP3
3P: 2200p
2P: 3300p
24.9K_0402_1%
3P: 348
2P: 1.21K
2
2
2
PC933
1
PR950
1
1
8.06K_0402_1%
1
HG2
<56>
PR924 2 BST2_1 1
1
2.2_0603_5%
<56>
+5VS
1
PR943
PC929
2
1COMP_CPU1 2
1
6.04K_0402_1%
1500P_0402_50V7K
3P: 6.04K
2P: 4.32K
PR948
0.033U_0402_16V7K
PR944
PC930
1
2FB_CPU3 1
2
10_0402_1%
0.033U_0402_16V7K
PR947
FB_CPU2
1
2
CSCOMP
LG1A
BST2
PR921
PC918
2 BSTA1_11
2
2.2_0603_5%
0.22U_0603_25V7K
<56>
2
22P_0402_50V8J
PR942
PC928
1
2FB_CPU1 1
2
49.9_0402_1%
680P_0402_50V7K
1
HG1A
C
2
PC926
2
1
1 PR940 2
1K_0402_1%
3P: 330p
2P: 1000p
100K_0402_1%_TSM0B104F4251RZ
2
B
TRBST#
BSTA1
2
PC923
1000P_0402_50V7K
VSP
3P: 22p
2P: 10p
1
PR938
1
2
0_0402_5%
VSN
.1U_0402_16V7K
VCCSENSE
PR936
1
2
0_0402_5%
IMVP_IMON
1
2
PR939 12.4K_0402_1%
<9>
VGATE
2
VSSSENSE
1
<16>
<9>
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
TRBST#
FB_CPU
COMP_CPU
IMON
ILIM_CPU
DROOP
2
VR_HOT#
PH904
PUT COLSE
TO V_GT
HOT SPOT
6132_PWMA
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2
<42>
2P: 36K
1P: 26.1K
1
1
2
1
PR933
10K_0402_5%
PR918
1
2
26.1K_0402_1%
VCC
PWMA
VDDBP
BSTA
VRDYA
HGA
EN
SWA
SDIO
LGA
ALERT#
BST2
SCLK
HG2
VBOOT NCP6132AMNR2G_QFN60_7X7
SW2
ROSC
LG2
VRMP
PVCC
VRHOT#
PGND
VRDY
LG1
VSN
SW1
VSP
HG1
DIFF
BST1
PC935
1
2
1
2
1
PR932
@
75_0402_1%
<56>
1
6132_VCC
0.01U_0402_25V7K
+V1.05S_VCCP
<56>
.1U_0402_16V7K
PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
.1U_0402_16V7K
PR923
1
2
54.9_0402_1%
PR922 2
1
<9> VR_SVID_DAT
<9> VR_SVID_ALRT#
<9> VR_SVID_CLK
SWN1A
PU901
1
2.2U_0603_10V7K
2
PR920
3
VR_ON_CPU
1
2
4
<42>
VR_ON
PC917
0_0402_5%
VR_SVID_DAT1 5
VR_SVID_ALRT# 6
PR927
PR925
VR_SVID_CLK
7
0_0402_5%
95.3K_0402_1%
1
2 VBOOT
8
10K_0402_1%
ROSC_CPU
1 PR926 2VR_SVID_DAT1
1
2
9
VRMP
CPU_B+
1
2
10
VR_HOT#
11
PR929 1K_0402_1%
VGATE
12
13
PC921
14
+3VS
DIFF_CPU
15
130_0402_1%
1
2
.1U_0402_16V7K
PC916
CSREFA
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
PR919 2
1
2_0603_5%
PC915
1
2
+5VS
C
6.98K_0402_1%
2
PC914
1
2
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+V1.05S_VCCP
PR913
1
TSENSEA
1
DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA
PC912
1000P_0402_50V7K
CSP1A
PC910
0.047U_0402_16V7K
PC911
1000P_0402_50V7K
CSP2A
CSP1A
TSENSEA
2
1PR914
2
15.8K_0402_1%
CSCOMPA
2P: 21.5K
1P: 15.8K
CSSUMA
PR954
1
2
0_0402_5%
<10> VSS_AXG_SENSE
SWN1A
2
PR912 2
1
2200P_0402_50V7K
1
PR937
1
2
0_0402_5%
CSREFA
1000P_0402_50V7K
1
6.04K_0402_1%
PC906
1
2
DROOPA
2
2P: 1.65K
1P: 1K
PR910 10P_0402_50V8J PC909
2 COMPA1 1
2
1
<10> VCC_AXG_SENSE
1
1K_0402_1%
2
1K_0402_1%
CSCOMPA
PR915
2
1
PR906
220K_0402_5%_ERTJ0EV224J
NTC_PH203
200K_0402_1%
680P_0402_50V7K
PR909 2
1
PR907 1
2
165K_0402_1%
1
FBA2
1
2
10_0402_1%
PC908
1
2
200K_0402_1%
PC907
1
2
D
2
PR908
2
4700P_0402_25V7K
24.9K_0402_1%
2P: 24K
1P: 24.9K
10.7K_0402_1%
PC905
PUT COLSE
TO GT
Inductor
PH901
1
1.21K_0402_1%
2
2
1
1
FBA1
1
PR902 2
1
PC903
1
2
PR903
TRBSTA#
1
1
.1U_0402_16V7K
1 PR904 2
2
2 PC901
1
680P_0402_50V7K
PR905
1
2
75K_0402_1%
FBA3
10_0402_1%
PC904
1
2
PR901 2
1200P_0402_50V7K
1
D
1000P_0402_50V7K
PR915,PR946=200K(setting 113 degreeC)
PR915,PR946=8.25K(setting 93 degreeC)
3
2
Title
PWR-CPU_CORE
Custom
Date:
Sheet
1
55
of
60
Rev
0.1
5
4
3
2
1
1
4
2
3
<55>
D
3
2
PR957
4.7_1206_5%
PR958
1
CSREF
<55>
SWN1
<55>
<55>
LG2
4
3
2
1
10_0402_1%
V2N_CPU 2 PR959 1
10_0402_1%
SNUB_CPU2
2
PQ904
V1N_CPU2
1SNUB_CPU1
CSREF
SWN2
<55>
PC948
1
2
5
5
4
LG1
3
2
1
<55>
+VCC_CORE
PL903
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4
<BOM Structure>
SW2
PR956
4.7_1206_5%
PQ903
PC944
0.1U_0402_25V6
2
1
4
PC943
10U_0805_25V6K
2
1
PC942
10U_0805_25V6K
2
1
5
HG2
2
PC946
2200P_0402_25V7K
2
1
PC947
220U_25V_M
1
SW1
<55>
+
+VCC_CORE
PL902
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PQ902
CPU_B+
1
1
<55>
PL901
HCB4532KF-800T90_1812
1
2
3
2
1
D
CPU_B+
B+
PC941
2200P_0402_25V7K
2
1
4
HG1
3
2
1
<55>
PC940
0.1U_0402_25V6
2
1
PQ901
PC939
10U_0805_25V6K
2
1
5
PC938
10U_0805_25V6K
2
1
CPU_B+
2
680P_0603_50V7K
PC949
2
680P_0603_50V7K
C
C
QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A
DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A
PQ907
<55>
PC960
2200P_0402_25V7K
2
1
PC959
0.1U_0402_25V6
2
1
PC958
10U_0805_25V6K
2
1
5
PC957
10U_0805_25V6K
2
1
CPU_B+
B
B
4
HG1A
3
2
1
PL905
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
SW1A
1
4
<BOM Structure>
2
3
PR967
4.7_1206_5%
2
PQ909
SNUB_GFX1
4
LG1A
2
<BOM Structure>
1
3
2
1
55>
V1N_GFX
5
1
<55>
+VCC_GFXCORE_AXG
PR971 1
CSREFA
<55>
SWN1A
<55>
10_0402_1%
PC968
2
680P_0603_50V7K
A
A
QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
Compal Secret Data
Issued Date
2009/12/01
Deciphered Date
2012/07/11
Title
PWR-CPU_CORE
Size
C
Date:
5
4
3
2
Document Number
Sheet
1
56
of
60
Rev
0.1
5
4
3
+VCC_CORE
1
2
2
+VCC_CORE
1
PC1
10U_0805_6.3VAM
2
1
PC2
10U_0805_6.3VAM
2
1
PC3
10U_0805_6.3VAM
2
1
Below is 458544_CRV_PDDG_0.5 Table 5-8.
+VCC_GFXCORE_AXG
Socket Bottom
5 x 22 µF (0805)
5 x (0805) no-stuff
sites
Socket Top
7 x 22 µF (0805)
2 x (0805) no-stuff
sites
1
PC4
10U_0805_6.3VAM
2
PC5
10U_0805_6.3VAM
+VCC_GFXCORE_AXG
D
@
2
+VCC_CORE
1
2
1
2
1
2
1
2
1
2
1
2
1
2
PC19
22U_0805_6.3V6M
1
PC18
22U_0805_6.3V6M
2
@
PC11
10U_0805_6.3VAM
@
PC17
22U_0805_6.3V6M
2
1
PC10
10U_0805_6.3VAM
PC16
22U_0805_6.3V6M
2
1
PC9
10U_0805_6.3VAM
PC15
22U_0805_6.3V6M
2
1
PC8
10U_0805_6.3VAM
PC14
22U_0805_6.3V6M
2
1
PC7
10U_0805_6.3VAM
PC13
22U_0805_6.3V6M
2
1
PC6
10U_0805_6.3VAM
PC12
22U_0805_6.3V6M
1
@
+V1.05S_VCCP
2
1
2
@
PC56
22U_0805_6.3V6M
2
@
1
PC35
22U_0805_6.3V6M
1
@
PC55
22U_0805_6.3V6M
C
1
+
2 3
@
1
+
2 3
1
+
2 3
PC68
330U_D2_2VM_R9M
2
2
@
2
PC34
22U_0805_6.3V6M
1
2
1
1
PC67
330U_D2_2VM_R9M
2
<BOM Structure>
PC71
22U_0805_6.3V6M
2
2
PC54
22U_0805_6.3V6M
1
2
1
PC33
22U_0805_6.3V6M
2
@
PC70
22U_0805_6.3V6M
2
@
PC65
22U_0805_6.3V6M
2 3
2
PC53
22U_0805_6.3V6M
1
2
1
PC64
22U_0805_6.3V6M
+
1
PC66
330U_D2_2VM_R9M
2
@
PC69
22U_0805_6.3V6M
2
1
PC63
22U_0805_6.3V6M
2 3
1
PC60
330U_D2_2VM_R9M
1
2
1
PC62
22U_0805_6.3V6M
2 3
1
@
+
PC59
330U_D2_2VM_R6M
2
1
PC61
22U_0805_6.3V6M
+
PC58
330U_D2_2VM_R9M
2 3
PC57
330U_D2_2VM_R6M
C
1
@
1
2
PC32
22U_0805_6.3V6M
2
1
1
1
PC52
22U_0805_6.3V6M
PC48
22U_0805_6.3V6M
1
PC31
22U_0805_6.3V6M
2
@
2
2
PC51
22U_0805_6.3V6M
PC47
22U_0805_6.3V6M
+
1
1
1
2
PC30
22U_0805_6.3V6M
2
2
1
PC50
22U_0805_6.3V6M
PC46
22U_0805_6.3V6M
2
2
1
+V1.05S_VCCP
1
1
PC29
22U_0805_6.3V6M
2
2
1
1
PC49
22U_0805_6.3V6M
PC45
22U_0805_6.3V6M
2
1
2
@
PC28
22U_0805_6.3V6M
2
1
2
1
1
PC27
22U_0805_6.3V6M
PC44
22U_0805_6.3V6M
1
2
1
2
@
PC26
22U_0805_6.3V6M
2
1
2
1
PC43
22U_0805_6.3V6M
1
2
1
PC42
22U_0805_6.3V6M
2
1
PC41
22U_0805_6.3V6M
1
@
PC40
22U_0805_6.3V6M
2
PC24
22U_0805_6.3V6M
PC39
22U_0805_6.3V6M
2
1
PC23
22U_0805_6.3V6M
PC38
22U_0805_6.3V6M
2
1
PC22
22U_0805_6.3V6M
PC37
22U_0805_6.3V6M
2
1
PC21
22U_0805_6.3V6M
PC36
22U_0805_6.3V6M
2
1
PC20
22U_0805_6.3V6M
PC25
22U_0805_6.3V6M
1
1
D
@
<BOM Structure>
PC72
22U_0805_6.3V6M
+VCC_CORE
1
+
B
1
+
PC73
330U_D2_2VM_R9M
2 3
1
+
1
PC74
330U_D2_2VM_R9M
2 3
+
1
PC75@
330U_D2_2VM_R6M
2 3
+
PC76@
330U_D2_2VM_R6M
2 3
B
1
+
PC77
330U_D2_2VM_R6M
2 3
PC78
330U_D2_2VM_R9M
2 3
A
A
Compal Secret Data
2008/09/15
Issued Date
Deciphered Date
2012/07/11
5
4
3
2
Title
PWR - PROCESSOR DECOUPLING
Size
Document Number
Rev
0.1
Date:
Sheet
1
57
of
60
5
4
3
2
Version change list (P.I.R. List)
Item
1
D
2
3
4
1
Page 1 of 1
for PWR
Reason for change
PG#
add PR865 for ISL62883 one phase solution and
unpop for two phase solution.
P54
unpop PR315,PR316 for SMBus SPEC.
P49
delet PSI#_VGA for NV chip.
P54
change NTC_V pull high voltage from +3VLP to +3VALW
P48
Modify List
Date
Phase
2011.08.29 DVT
add PR865
unpop PR315,PR316
D
2011.08.29 DVT
2011.10.14 DVT2
5
6
7
8
C
C
9
10
11
12
13
14
B
B
15
16
17
A
A
2009/01/06
Issued Date
Compal Secret Data
Deciphered Date
2012/07/11
5
4
3
2
Title
PIR (PWR)
Custom
Date:
Sheet
1
58
of
60
Rev
0.1
5
4
3
2
1
COMPAL CONFIDENTIAL
3
3
3
10
V
B4
4
EC
PQ2
PCH_RSMRST#_R
A4
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_SUS#
B6
H_CPUPWRGD
PLT_RST#
SYSON
7
16
CPU
V
+1.5V
PU501
V
V
V
PU702
+V1.05S
PU602
+V1.05S_VCCP
SA_PGOOD
V
9
C
(DIS)
U38
+5VS
8b
8a
Q8
+1.5VS
PU701
+0.75VS
8a
B
(DIS)
U39
+3VS
13
VR_ON
SVID
DGPU_PWR_EN
PU601
+VCC_SA
B
13
DGPU_PWROK
8
SUSP#,SUSP
VGATE
12
6
SYSON#
14
11
V
ON/OFF
5
PBTN_OUT#
15
V
B7
SYS_PWROK
PM_DRAM_PWRGD
PCH
V
A5
EC_ON
V
51ON#
V V
B3
C
PCH_PWROK
V
V
V
+5VALW
V V
B2
B+
B7
V
B1
A5
V
+3VALW
V
PU401
+3V_PCH
+5V_PCH
B5
V
B+
10
V
PU301
A3
VV
V V
A2
V
BATT
MODE
BATT
VIN
V
A1
D
PCH_PWROK
AC
MODE
V
D
MODEL NAME: Power Sequence Block Diagram
LA-7981P
PCB NAME:
REVISION:
2011/07/13
DATE:
DGPU
SVID
PU901
+VCC_CORE
A
A
14 VGATE
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
Power sequence
Custom
Rev
0.2
LA-7981P
Date:
Sheet
1
59
of
60
5
4
3
2
Item
D
1
Page 1 of 2 for HW PIR
Reason for change
PG#
8
Modify List
Date
Phase
1
GPU 13M GPU Device loss (Pcie lan x8 issue)
Add R43
DVT
2
HDD no function
40
Add R550
DVT
3
10/100 lan no function & change to overclocking mode
37
ADD R1372 ; DEL R31
DVT
4
For DGPU_PWROK leakage issue.(Let timing +5VS > +3VS)
46
Change C726 from 0.1uF to 0.01uF
DVT
DVT
D
5
For S3 can't wake up
10
Change R56 from 15K to 4.7K
change R885 from 0 ohm to 15K
6
Can unstuff RV66 for N13P-GL & as NV DG
27
RV66 change to N13M@
DVT
7
GPU N13P-GL QS sample change strap
32
RV94 change from 45.3K to 10K
DVT
8
PCH 25Mhz for vender crystal test report change CL to 12pF
15
C196;C197
DVT
9
GPU 27Mhz for vender crystal test report change CL to 15pF
23
CV37;CV38
DVT
10
EC_LID_OUT# internal PD 20K, follow ORB change R230 from 10k to 1K
19
R230
DVT
11
For GPIO70;GPIO71
19
R705;R706 Change from 10K to 200K
DVT
12
for DVT board ID Change R695 from 33k to 18k
42
R695
DVT
13
LAN Surge test
27
T1;T2
DVT
14
Del ODD Power Control function component
40
R568;Q100;R675;C607;Q99
DVT
15
AO4430L(SB000007O10)EOL Change to AO4304 (SB00000RV00)
46
U49
DVT
16
Del (PCH AUX Power) Reserve component no use
46
C780;C781;C782;C783;R778;Q120;U40
DVT
17
PCH(U4) P/N Change from SA00004NQ30 to SA00004NQ80
14
U4
DVT
18
NV-GPU (U65)P/N change
N13P Keep SA000051A00
23
U65
DVT
19
EXT USB 3.0 IC PCIE_WAKE# ; CLKREQ_USB30# leakage on S4
45
Swap Q125;Q121 pin1 & pin3
DVT
20
No function
45
DEL R769
DVT
21
add LAN LDO mode function
ADD R65;R596;R1449;R1380
DVT
22
USB_OC0# Share with USB_OC4# due to same power switch
18
short USB_OC0#;USB_OC4# ; del R267
23
Add Capsensor B/D Conn. For best buy use
42
ADD JCAP1 Conn.
C
C
voltage level issue ( internal Pull High 20k )
fail change P/N from SP050006E00 to SP050006W00
B
B
N13M from SA00004V000 to SA00004V010
37;38
DVT
DVT
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
HW-PIR1
Custom
Date:
Rev
0.1
LA-7981P
Sheet
1
60
of
60
5
4
3
2
1
Item
Reason for change
PG#
24
L1 change to 1 ohm R
20
Modify List
Date
Phase
L1 change to R footprint
DVT
D
D
25
Reserve 0 ohm for CMOS Camera shake
33
add R296 0 ohm
DVT
26
Reserve 0 ohm for U49 MOS VGS 20V will burn out issue
46
add R784 0 ohm
DVT
27
For HDD +5VS Power plant del C601;
change C598 pin1 power name for good power plant
40
change from +5VS to +5V_HDD ;DEL C601
DVT
DVT
28
For Audio jack support APPLE and NOKIA function Reserve
29
For standard part cost down change 10uF 0805 type to 0603 type
43
add R684;R685;R688;R686 0ohm R
10,20
21,33
37,39
40,46
DVT
DVT
C124;C125;C126;C127;C130;C221;C215;C395;
C231;C519;C937;C953;C954;C591;C608;C602;
C720;C721;C723;C724;C782;C783;C717;C718;
C856;C852;C851;C853
DVT
C
C
change Crystal foot print follow standard parts from 5032 to 3225 package
30
31
change 0ohm to short-pad (R0402_0ohm)
32
Reserve BT_DISABLE (GPI022) for combo card(BT+WLAN)
33
U35;U36 Change footprint without thermal PAD type
34
PU 10K with 3V3 on N13P-GL/ for CEC signal
VGA_GPIO3;VGA_GPIO16
35
15;23;
37
7;8;
10;15
16;20;
33;36;
40;43
19
DVT
R40;R60;R77;R144;R190;R193;R198;R181;R185;
R265;R538;R498;R500;R583;R614
DVT
DVT
ADD R892;R897
DVT
U35;U36
DVT
RV230
DVT
RV113;RV114
DVT
CV42
DVT
43
LED2;LED5;LED6
DVT
DVT
44;45
24
change connect DPRSLPVR_VGA to PSI#_VGA
DVT
Y2;Y6;YV1
23;54
B
A
B
36
Fix VGA power on CLKREQ has drop (QV2 gate add 0.1uF)
37
LED5 和LED2 Location sawp ; Location name D9 change to LED6
38
For Lan surge fail add 0 ohm on MDO2-;MDO2+;MDO3-;MDO3+
38
R304;R305;R306;R307
39
Change UV2 PN from SA007080B90 to SA00000OH00
23
UV2
09/28
DVT
40
Change 2M BIOS ROM from SA00003FO00 to SA00003FO10
14
U6
09/29
DVT
U32
10/03
DVT
10/03
DVT
41
Correct PCIE_PRX_DTX_P4/N4 of U32 (SWAP)
42
Reserve +5VS to JCR1, add R689 ,R690
43
Update Power sheet of 1003 version
23
45
43
R689 (@),R690
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
A
10/04
47~58
2
Title
HW-PIR2
Custom
Date:
Rev
0.1
LA-7981P
Sheet
1
61
of
60
5
4
3
2
Item
Reason for change
44
CPU Symbol Update
PG#
Modify List
Date
Phase
5,6,7,
8,9,10,11
D
C
1
Location : Jcpu1
PVT
D
45
Change 10P 50V Cap from 1206 to 0603
38
Location : C973
PVT
46
S3 Reduction
53
Reserve PR719 for 0.75V
PVT
47
LAN CO-lay x1 GDT & 75ohm
38
Location : R308,R304,R305,R306,R307,DL1,DL2,DL3,DL4
PVT
48
R750 for Power request
42
Location :R750
PVT
49
JUSB3 From 4PIN TO 6 PIN FOR VOLTAGE DROP
44
Location : JUSB3
50
Add C535 100pF on +3VLP for ESD request - Pony
42
Location : C535
PVT
51
FOR TP POWER SOLUTION
42
Location : R598.R603
PVT2
52
FOR POWER REQUEST
42
Location : R738
PVT2
C
Location :
5
52
PVT
Change C from 0.22Uf to 0.11uF
23
C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,
C11,C12,C13,C14,C15,C16,C17,C18,C19,C20,
C21,C22,C23,C24,C25,C26,C27,C28,C29,C30,
C31,C32,
CV6,CV7,CV8,CV9,CV10,CV11,CV12,CV13,CV15,
CV17,CV19,CV14,CV16,CV18,CV20,CV22,CV24,
CV26,CV21,CV23,CV25,CV27,CV29,CV31,CV33,
CV28,CV30,CV32,CV36,CV41,CV34,CV35,
SVT
B
B
A
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
5
4
3
2
Title
HW-PIR2
Custom
Date:
Rev
0.1
LA-7981P
Sheet
1
62
of
60

IBM Lenovo G480 LA-7981p Free Laptop Schematic

Transcription

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