Center for Low Energy Systems Technology (LEAST)

Center for Low Energy Systems Technology (LEAST)
Alan Seabaugh, Hao Lu, Joerg Appenzeller 1, Suman Datta 2, Debdeep Jena 3,
Vijay Narayanan 2, and Bob Wallace 4
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USA 46556
1
Purdue University, 2Penn State, 3Cornell, and 4University of Texas at Dallas
Abstract: LEAST is a microelectronics research center
funded by the Semiconductor Research Corporation (SRC)
and DARPA to support the continued growth of the U.S.
semiconductor industry. The aim of the center is to
demonstrate transistor technologies that can outperform
CMOS at low voltage (less than 0.4 V) to enable systems
operating at dramatically lower power.
Steep transistors hinge on development of new electronic
materials and gate stacks. To advance steep transistors
LEAST was formed in 2013 and is now comprised of 28
faculty and 80-plus postdoctoral researchers and graduate
students at Purdue, Penn State, Carnegie Mellon, Cornell,
Georgia Tech, Illinois Institute of Technology, University
of Texas Dallas, University of California Santa Barbara,
University of California San Diego, University of
California Berkeley, and the University of Notre Dame.
Keywords: complex oxide, gallium nitride, steep
subthreshold swing, tunnel field-effect transistor, TFET,
transition metal dichalcogenide, TMD
Benchmarking of beyond CMOS devices has been a
constant emphasis within the SRC Nanoelectronic
Research Initiative and the SRC/DARPA Semiconductor
Technology Advanced Research Network (STARnet)
centers. These studies compare emerging research devices
with state-of-the-art CMOS [5, 6] and set device goals. The
TFET has emerged thus far as the leading option [6].
Introduction
Tunnel field-effect transistors (TFET) [1] can outperform
the metal oxide semiconductor MOSFET at supply
voltages less than 0.4 V [2]. This is because TFETs are not
limited to 60 mV/decade subthreshold swing as is the
MOSFET. To lower power and continue increases in
density, supply voltages must continue to be reduced as
shown in the ITRS projections of Figure 1 [3] and this
requires reduce subthreshold swing. Supply voltage must
decrease by approximately kT/q per year (26 mV/year) at
room temperature to maintain the trends of Moore’s law.
Realization of transistors that have a subthreshold swing of
less than 60 mV/decade, called “steep” transistors enables
system power reduction beyond the capabilities of CMOS.
In LEAST, the materials with the most promise for steep
transistors include two-dimensional (2D) crystals i.e.
graphene and the transition metal dichalcogenides [7-11],
III-nitrides [6], complex oxides [12], and ferroelectrics
[13]. Progress in these new technologies is measured by
successes in synthesis and growth [14], first-principles
material understanding [15-19], atomistic device modeling
of transistors, contact developments [20, 21], doping
techniques [22, 23], device development [24], SPICE
model deployment [25], and circuits/ architecture design
[26-28]. The center is also exploring microwave,
millimeter-wave, and analog applications [29].
While TFETs have been explored for nearly 10 years
experimental demonstrations of low subthreshold swing
indicate significant further improvements are needed [4].
TFETs are not the sole approach. Ferroelectric gates are
being developed to to provide voltage gain on the channel
surface potential. Current gain can also be used to provide
steep swing e.g. through impact ionization or via a
stimulated phase change.
Supply Voltage (V)
1
13a0811
ITRS projection
0.8
HP
0.6
LOP
CMOS
kT/q per year
0.4
Low voltage - steep transistors
0.2
0
2010
Tunnel Field-Effect Transistor
One embodiment is to use the gate of a metal oxide
semiconductor structure to control the interband tunneling
current across a degenerate p-n junction or heterojunction.
Two-dimensional channels like graphene or the transition
metal dichalcogenides are particularly well suited for
TFETs because of the symmetric band structure, the
superior electrostatic coupling of the gate to the atomicallythin channel, the full termination of surface dangling bonds,
and the application to flexible substrates. Since doping in
these materials is achieved by charge-transfer layers or
electrostatic gating, high doping densities, exceeding
1014 cm2, are achieved without the crystallographic
perturbation and strain caused by substitutional doping.
Energy band diagrams in the on and off states along with a
schematic cross section are shown in Figure 2.
2020
2030
Year
2040
2050
Figure 1. ITRS power supply projections for high
performance (HP), low operating power (LOP), and low
power (LP) technologies from the 2012 Process,
Integration, Devices, and Structures (PIDS) tables [3].
627
Figure 3. Analog benchmarking of the TFET vs. CMOS and
III-V transistors. Shown is transconductance per unit draincurrent vs. current per unit width.
Figure 2. Tunnel field-effect transistor based on twodimensional crystals: (a) energy band diagram in the on
state, (b) off state, and (c) schematic cross section.
The primary technical challenges to realize transistors of
this type include large-area single-crystal growth, doping
technology, surface preparation for nucleation of gate
dielectrics, gate stack development, ohmic contacts, and
complementary transistor processes. To achieve high
current drive it is desirable to develop heterojunction
technology to realize near-broken-gap band alignments at
the tunnel junction in all material systems.
(a)
Analog benchmarking of TFETs
While benchmarking of steep devices for digital
applications has advanced [5, 6], analog benchmarking has
received less attention. In the following, a first look at some
analog figures of merit are provided for the TFET. The
TFET used for comparison is an InAs homojunction p-i-n
TFET with a 20 nm double gate, simulated using an
atomistic device simulator [30]. The results were then fitted
to a universal SPICE model [25] including a capacitance
model which comprehends fringing capacitances and is
consistent with comprehensive capacitance models [29].
The first figure of merit shown is transconducance gm/ID vs.
drain current ID, Figure 3. Owing to the high output
resistance, the TFET has higher intrinsic voltage gain than
the MOSFET.
The CMOS models compared here are commercial foundry
device models operated at one-half VDD. Several III-V
transistors are also shown based on III-V technology
provided by two U.S. based companies. At low currents,
when the MOSFET is below threshold, the figure of merit
gm/ID should ideally approach q/kT or approximately 39.
(b)
Figure 4. Analog benchmark (a) Unity gain frequency per
unit power vs. current per unit width, (b) with log scale.
628
20nm InAs TFET
180nm CMOS
10
5
10
4
10
3
10
2
10
1
10
0
1.4
1.4
1.4
65nm CMOS
45nm CMOS
28nm CMOS
28nm FDSOI
130nm InP HBT
gm (µS/µm)
90nm CMOS
0.8
0.8
0.9
0.3
250nm InP HBT
500nm InP HBT
50nm InP HEMT
4
10
200nm InP HEMT
GaAs mHEMT
10
180 nm CMOS
90 nm CMOS
65 nm CMOS
45 nm CMOS
28 nm CMOS
28 nm FDSOI
20 nm TFET
150nm HBT
250nm HBT
500nm HBT
50nm HEMT
200nm HEMT
GaAs mHEMT
GaAs pHEMT
1.0
0.5
0.5
0.45
0.5
0.5
5.0
-1
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
ID (µA/µm)
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$(c)$
3
10
(a)$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$(b)$
GaAs pHEMT
A second figure of merit compares the unity gain frequency
fT per unit power vs. current/micron. This metric highlights
the low power limits of CMOS and again shows the
performance benefit of the TFET. Analog applications that
are opened by this technology are ultralow power
operational amplifiers and receivers, analog-to-digital
converters, low power rectifiers for energy scavenging, and
microwave/mm-wave detectors,
fT (GHz)
Figure 5. Simulated intrinsic small signal responses for the
technologies shown in Figures 3 and 4. (a) color legend,
(b) transconductance, (c) intrinsic voltage gain, and (d) current
gain cut-off frequency. The numbers on the curves are power
supply voltages. The TFET outperforms the MOSFET in voltageconstrained and power-constrained applications.
10
2
10
1
10
0
10
-1
10
-2
0.5
0.5
0.5
0.5
0.9
-3
(d)$
Acknowledgements
This work was supported in part by the Center for Low
Energy Systems Technology (LEAST) sponsored by
MARCO and DARPA. We thank Trond Ytterdal,
Norwegian Institute of Technology, for useful discussions
and for providing the CMOS SPICE simulations. The
authors also thank Bobby Brar, Teledyne Technologies,
and Tom Kazior, Marty Chumbes, and Shahed Reza,
Raytheon, for providing the III-V transistor simulations.
References
With the exception of references 1-3 and 30, these citations
highlight recent accomplishments in LEAST.
629
10
-2
10
-1
180 nm CMO
90 nm CMOS
65 nm CMOS
45 nm CMOS
28 nm CMOS
28 nm FDSO
20 nm TFET
150nm HBT
250nm HBT
500nm HBT
50nm HEMT
200nm HEM
GaAs mHEM
GaAs pHEM
0.8
1.0
5.0
InAs TFET 0.3
10
Conclusions
Silicon CMOS technology is reaching density limits set by
heat removal and the inability to lower supply voltage and
retain performance. TFETs outperform CMOS at low
voltage. The STARnet center LEAST is developing
approaches for steep subthreshold swing transistors
including the TFET to provide a technology to replace the
MOSFET in applications requiring energy efficiency.
1.4
1.4
1.4
0.8
0.45
10
0
10
1
ID (µA/µm)
10
2
10
3
10
4
1.
Seabaugh A. and Q. Zhang, “Low voltage tunnel
transistors for beyond-CMOS logic,” Proc. IEEE 98,
2095-2110 (2010).
2.
Avci, U. E., S. Hasan, D. E. Nikonov, R. Rios, K.
Kuhn, and I. A. Young, “Understanding the Feasibility
of Scaled III-V TFET for Logic by Bridging Atomistic
Simulations and Experimental Results,” 2012 VLSI
Symp. Technology, pp. 183–184.
3.
ITRS, International Technology Roadmap for
Semiconductors, PIDS 2012 and 2013 tables,
www.itrs.net/Links/2013ITRS/Home2013.htm.
4.
H. Lu and A. Seabaugh, “Tunnel Field-Effect
Transistors: State-of-the-Art,” IEEE J. Electron
Devices Soc., Vol. 2, no. 4, pp. 44–49, 2014.
5.
Nikonov, D. and I. Young, “Overview of BeyondCMOS Devices and a Uniform Methodology for their
Benchmarking,” Proc. IEEE, Vol.101, no.12, pp.
2498-2533, 2013.
6.
Nikonov, D. and I. Young, “Benchmarking of BeyondCMOS Exploratory Devices for Logic Integrated
Circuits”, IEEE J. Exploratory Solid-State Comput.
Devices and Circuits, submitted 2015.
7.
Das, S., A. Prakash, R. Salazar, and J. Appenzeller,
“Toward Low-Power Electronics: Tunneling
Phenomena in Transition Metal Dichalcogenides,”
ACS Nano, Vol. 8, no. 2, pp. 1681–1689, 2014.
8.
9.
19. Yan, Q., P. Rinke, A. Janotti, M. Scheffler, and C. G.
Van de Walle, “Effects of Strain on the Band Structure
of Group-III Nitrides,” Phys. Rev. B, Vol. 90, no. 12,
pp. 125118, 2014.
Fiori, G., F. Bonaccorso, G. Iannaccone, T. Palacios,
D. Neumaier, A. Seabaugh, S. K. Banerjee, and
L. Colombo, “Electronics Based on Two-Dimensional
Materials,” Nature Nanotech. 9, 768-799, 2014.
20. Das, S. and J. Appenzeller, “Where Does the Current
Flow in Two-Dimensional Layered Systems?” Nano
Lett. Vol. 13, pp. 3396–3402, 2013.
Barrera, S. C. de la, Q. Gao, and R. M. Feenstra,
“Theory of Graphene–Insulator–Graphene Tunnel
Junctions,” J. Vac. Sci. Technol. B, Vol. 32, no. 4, pp.
04E101, 2014.
21. McDonnell, S, R. Addou, C. Buie, R. M. Wallace, and
C. L. Hinkle, “Defect-Dominated Doping and Contact
Resistance in MoS2,” ACS Nano, Vol. 8, no. 3, pp.
2880–2888, 2014.
10. Ma, N. and D. Jena, “Interband Tunneling in TwoDimensional Crystal Semiconductors,” Appl. Phys.
Lett., Vol. 102, no. 13, pp. 132102, 2013.
22. Kiriya, D., M. Tosun, P. Zhao, J. S. Kang, and A.
Javey, “Air-Stable Surface Charge Transfer Doping of
MoS 2by Benzyl Viologen,” J. Am. Chem. Soc., Vol.
136, no. 22, pp. 7853–7856, 2014.
11. Li, M. O., D. Esseni, G. Snider, D. Jena, and H. G.
Xing, “Single particle transport in two-dimensional
heterojunction interlayer tunneling field effect
transistor,” J. Appl. Phys., Vol. 115, no. 7, p. 074508,
2014.
23. Xu,,H., S. Fathipour, E. Kinder, A. Seabaugh and S.
Fullerton-Shirey, “Reconfigurable Ion Gating in 2HMoTe2 Field-Effect Transistors using PEO:CsClO4
Solid Polymer Electrolyte,” ACS Nano, accepted.
12. Huefner, M., R. K. Ghosh, E. Freeman, N. Shukla, H.
Paik, D. G. Schlom, and S. Datta, “Hubbard Gap
Modulation in Vanadium Dioxide Nanoscale Tunnel
Junctions,” Nano Lett., Vol. 14, no. 11, pp. 6115–
6120, 2014.
24. Fathipour, S., N. Ma, W. S. Hwang, V. Protasenko, S.
Vishwanath, H. G. Xing, H. Xu, D. Jena, J.
Appenzeller, and A. Seabaugh, “Exfoliated multilayer
MoTe2 field-effect transistors,” Appl Phys Lett, Vol.
105, no. 19, pp. 192101–192101, 2014.
13. Khan, A. I., K. Chatterjee, B. Wang, S. Drapcho, L.
You, C. Serrao, S. R. Bakaul, R. Ramesh, and S.
Salahuddin, “Negative Capacitance in a Ferroelectric
Capacitor,” Nature Mat., available on line, Dec 2014.
25. Lu, H., D. Esseni, and A. Seabaugh, “Universal
analytic model for tunnel FET circuit simulation,”
Solid State Electronics, accepted (2015).
26. Swaminathan, K., E. Kultursay, V. Saripalli, V.
Narayanan, M. T. Kandemir, and S. Datta, “SteepSlope Devices: From Dark to Dim Silicon,” IEEE
Micro, Vol. 33, no. 5, pp. 50–59, 2013.
14. Lin, Y.-C., N. Lu, N. Perea-Lopez, J. Li, Z. Lin, X.
Peng, C. H. Lee, C. Sun, L. Calderin, P. N. Browning,
M. S. Bresnehan, M. J. Kim, T. S. Mayer, M.
Terrones, and J. A. Robinson, “Direct Synthesis of van
der Waals Solids,” ACS Nano, Vol. 8, no. 4, pp. 3715–
3723, 2014.
27. H. Liu, S. Datta, and V. Narayanan, “Steep Switching
Tunnel FET: A Promise to Extend the Energy Efficient
Roadmap for Post- CMOS Digital and Analog/RF
Applications,” IEEE Int. Symp. Low Power
Electronics and Design (ISLPED), pp. 145–150, 2013.
15. Gong, C., H. Zhang, W. Wang, L. Colombo, R. M.
Wallace, and K. Cho. “Band Alignment of TwoDimensional Transition Metal Dichalcogenides:
Application in Tunnel Field Effect Transistors,” Appl.
Phys. Lett., Vol. 103, no. 5, pp. 053513, 2013.
28. Sedighi, B., X. S. Hu, H. Liu, J. Nahas, and M.
Niemier, “Analog Circuit Design Using TunnelFETs,” IEEE Trans. Circuits-I, Vol. 62, no. 1, pp. 39–
48, 2015.
16. Gong, C, C. Huang, J. Miller, L. Cheng, Y. Hao, D.
Cobden, J. Kim, R. S. Ruoff, R. M. Wallace, K. Cho,
X. Xu, and Y. J. Chabal, “Metal Contacts on Physical
Vapor Deposited Monolayer MoS2,” ACS Nano, Vol.
7, no. 12, pp. 11350–11357, 2013.
29. Asbeck, P., K. Lee, and J. Min, “Projected
Performance of Heterostructure Tunneling FETs in
Low Power Microwave and mm-wave Applications,”
IEEE J. Electron Dev. Society, accepted (2015).
17. Gong, C., L. Colombo, R. M. Wallace, and K. Cho,
“The Unusual Mechanism of Partial Fermi Level
Pinning at Metal–MoS2 Interfaces,” Nano Lett., Vol.
14, no. 4, pp. 1714–1720, 2014.
30. Avci, U. E., R. Rios, K. Kuhn, and I. A. Young,
“Comparison of Performance, Switching Energy and
Process Variations for the TFET and MOSFET in
Logic,” Symp. VLSI Technology, pp. 124–125.
18. Lyons, J. L., A. Janotti, and C. G. Van de Walle,
“Effects of Carbon on the Electrical and Optical
Properties of InN, GaN, and AlN,” Phys Rev B, Vol.
89, no. 3, pp. 035204, 2014.
630